MT18VDDT3272A, 6472A, 12872A, 25672A Datasheet by Micron Technology Inc.

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OIJDIGEUUDBO

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

DDR SDRAM

UNBUFFERED DIMM

MT18VDDT3272A – 256MB

MT18VDDT6472A – 512MB

MT18VDDT12872A – 1GB

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/products/modules

Features

• 184-pin dual in-line memory module (DIMM)

• Fast data transfer rates: PC3200

• CAS Latency 3

• Utilizes 400 MT/s DDR SDRAM components

• Supports ECC error detection and correction

• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB

(128 Meg x 72)

•V

DD = VDDQ = +2.6V

•V

DDSPD = +2.3V to +3.6V

• 2.6V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/received

with data—i.e., source-synchronous data capture

• Differential clock inputs CK and CK#

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs (256MB), 7.8125µs (512MB, 1GB) maximum

average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Programmable READ CAS latency

•Gold edge contacts

Figure 1: 184-Pin DIMM (MO-206)

OPTIONS MARKING

•Package

184-pin DIMM (Standard) G

184-pin DIMM (Lead-free) Y

• Memory Clock/Speed, CAS Latency

5ns (200MHz), 400MT/s, CL = 3 -40B

•PCB

Standard 1.25in. (31.75mm)

1.25in. (31.75mm)

Table 1: Address Table

256MB 512MB 1GB

Refresh Count 4K 8K 8K

Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8)

Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11)

Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)

Bil

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

current revision codes. Example: MT18VDDT6472AG-40BB1.

Table 2: Part Numbers and Timing Parameters

PART NUMBER MODULE

DENSITY CONFIGURATION MODULE

BANDWIDTH MEMORY CLOCK/

DATA BIT RATE LATENCY

(CL - tRCD - tRP)

MT18VDDT3272AG-40B__ 256MB 32 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

MT18VDDT3272AY-40B__ 256MB 32 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

MT18VDDT6472AG-40B__ 512MB 64 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

MT18VDDT6472AY-40B__ 512MB 64 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

MT18VDDT12872AG-40B__ 1GB 128 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

MT18VDDT12872AY-40B__ 1GB 128 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3

gﬂﬂﬂﬂﬂﬂﬂﬂﬂg @Wwwu:

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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NOTE:

Pin 115 is No Connect for 256MB, or A12 for 512MB and 1GB.

Figure 2: Pin Locations: 184-PIN DIMM

Table 3: Pin Assignment

(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 24 DQ17 47 DQS8 70 VDD

2DQ025 DQS2 48 A0 71 NC

3VSS 26 VSS 49 CB2 72 DQ48

4DQ127 A9 50 VSS 73 DQ49

5DQS028 DQ18 51 CB3 74 VSS

6DQ229 A7 52 BA1 75 CK2#

7VDD 30 VDDQ 53 DQ32 76 CK2

8 DQ3 31 DQ19 54 VDDQ 77 VDDQ

9NC32 A5 55 DQ33 78 DQS6

10 NC 33 DQ24 56 DQS4 79 DQ50

11 VSS 34 VSS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 VSS 81 VSS

13 DQ9 36 DQS3 59 BA0 82 NC

14 DQS1 37 A4 60 DQ35 83 DQ56

15 VDDQ 38 VDD 61 DQ40 84 DQ57

16 CK1 39 DQ26 62 VDDQ 85 VDD

17 CK1# 40 DQ27 63 WE# 86 DQS7

18 VSS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 VSS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 VSS 89 VSS

21 CKE0 44 CB0 67 DQS5 90 NC

22 VDDQ 45 CB1 68 DQ42 91 SDA

23 DQ16 46 VDD 69 DQ43 92 SCL

Table 4: Pin Assignment

(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

VSS

116

VSS

139

VSS

162

DQ47

DQ4

117

DQ21

140

DM8 163 NC

DQ5

118

A11

141

A10

164

VDDQ

119

DM2

142

CB6

165

DQ52

DM0

120

VDD

143

VDDQ

166

DQ53

DQ6

121

DQ22 144 CB7

167

DQ7

122

145

VSS

168

VDD

100

VSS

123

DQ23 146 DQ36

169

DM6

101 NC

124

VSS

147

DQ37

170

DQ54

102 NC

125

148

VDD

171

DQ55

103

126

DQ28

149

DM4

172

VDDQ

104

VDDQ

127

DQ29

150

DQ38

173

105

DQ12

128

VDDQ

151

DQ39

174

DQ60

106

DQ13

129

DM3

152

VSS

175

DQ61

107

DM1

130

153

DQ44

176

VSS

108

VDD

131

DQ30

154

RAS#

177

DM7

109

DQ14

132

VSS

155

DQ45

178

DQ62

110

DQ15

133

DQ31

156

VDDQ

179

DQ63

111

CKE1

134

CB4

157

S0#

180

VDDQ

112

VDDQ

135

CB5

158

S1#

181

SA0

113

136

VDDQ

159

DM5

182

SA1

114

DQ20

137

CK0

160

VSS

183

SA2

115

NC/A12

138

CK0#

161

DQ46

184

VDDSPD

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1 PIN 52 PIN 53 PIN 92

Indicates a VDD or VDDQ pin Indicates a VSS pin

Front View

Back View

U1 U2 U3 U4 U5 U6 U7 U8 U9

U19

U10 U11 U12 U13 U14 U15 U16 U17 U18

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

16, 17, 75, 76, 137, 138 CK0, CK0#, CK1,

CK1#, CK2, CK2# Input Clock: CK, CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the

positive edge of CK,and negative edge of CK#. Output data

(DQs and DQS) is referenced to the crossings of CK and CK#.

21, 111 CKE0, CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates

the internal clock, input buffers and output drivers. Taking

CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operations (all device banks idle), or ACTIVE POWER-

DOWN (row ACTIVE in any device bank). CKE is synchronous

for POWER-DOWN entry and exit, and for SELF REFRESH entry.

CKE is asynchronous for SELF REFRESH exit and for disabling

the outputs. CKE must be maintained HIGH throughout read

and write accesses. Input buffers (excluding CK, CK# and CKE)

are disabled during POWER-DOWN. Input buffers (excluding

CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input

but will detect an LVCMOS LOW level after VDD is applied and

until CKE is first brought HIGH. After CKE has been brought

HIGH, it is an SSTL_2 input only.

157, 158 S0#, S1# Input Chip Selects: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when S# is registered HIGH. S# is considered part of

the command code.

52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

27, 29, 32, 37, 41, 43, 48,

115 (512MB, 1GB), 118, 122,

125, 130, 141

A0–A11

(256MB)

A0–A12

(512MB, 1GB)

Input Address Inputs: Provide the row address for ACTIVE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out

of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether

the PRECHARGE applies to one device bank (A10 LOW, device

bank selected by BA0, BA1) or all device banks (A10 HIGH).

The address inputs also provide the op-code during a MODE

during the LOAD MODE REGISTER command.

44, 45, 49, 51, 134, 135, 142,

144 CB0–CB7 Input/

Output Check bits.

5, 14, 25, 36, 47, 56, 67, 78,

86 DQS0–DQS8 Input/

Output Data Strobe: Output with READ data, input with WRITE data.

DQS is edge-aligned with READ data, centered in WRITE data.

Used to capture data.

97, 107, 119, 129, 140, 149,

159, 169, 177 DM0–DM8 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH

blocks WRITE operation. DM lines do not affect READ

operation.

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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2, 4, 6, 8, 12, 13, 19, 20, 23,

24, 28, 31, 33, 35, 39, 40, 53,

55, 57, 60, 61, 64, 68, 69, 72,

73, 79, 80, 83, 84, 87, 88, 94,

95, 98, 99, 105, 106, 109,

110, 114, 117, 121, 123, 126,

127, 131, 133, 146, 147, 150,

151, 153, 155, 161, 162, 165,

166, 170, 171, 174, 175, 178,

179

DQ0–DQ63 Input/

Output Data I/Os: Data bus.

92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

181,182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

91 SDA Input/

Output Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-

detect portion of the module.

REF Supply SSTL_2 reference voltage.

15, 22, 30, 54, 62, 77, 96,

104, 112, 128, 136, 143, 156,

164, 172, 180

VDDQ Supply DQ Power Supply: +2.6V ±0.1V.

7, 38, 46, 70, 85, 108, 120,

148, 168 VDD Supply Power Supply: +2.6V ±0.1V.

3, 11, 18, 26, 34, 42, 50, 58,

66, 74, 81, 89, 93, 100, 116,

124, 132, 139, 145, 152, 160,

176

VSS Supply Ground.

184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

9, 10, 71, 82, 90, 101, 102,

103, 113, 115 (256MB), 163,

167, 173

NC — No Connect: These pins should be left unconnected.

Table 5: Pin Descriptions (Continued)

Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

4% m: :J, ::::%::::%:::: :::: xxxxxxxx xxx xxxxxxxx xxxxxxxx ﬁx ::::%::::%::::%::::%:::: xxx xxx xxx xxx xxx L1 nunnnn www.mmronmm/number uide

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Figure 3: Functional Block Diagram

SA0

SERIAL PD

U19 SDA

SA1

SA2

BA0, BA1

A0-A11 (256MB)

A0-A12 (512MB,1GB)

RAS#

BA0, BA1: DDR SDRAMs

A0-A11: DDR SDRAMs

A0-A12: DDR SDRMs

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

WE#: DDR SDRAMs

CKE0: DDR SDRAMs U1, U3, U5, U7, U9, U11, U13, U15, U17

CKE1: DDR SDRAMs U2, U4, U6, U8, U10, U12, U14, U16, U18

CAS#

WE#

CKE0

CKE1

REF

DDR SDRAMs

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U13

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U17

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

S0#

SCL

U18

U16

S1#

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DQS0 DM4

DQS4

DM1

DQS1 DM5

DQS5

U12

DM CS# DQS

DM2

DQS2 DM6

DQS6

DM CS# DQS

U11 U8

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3 DM7

DQS7

DM CS# DQS

U10

DM CS# DQS

DM8

DQS8

U14

DM CS# DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DDQ

DDR SDRAMs

U4-U6,

U13-U15

CK0

CK0# U1-U3,

U16-U18

CK1

CK1#

U7-U12

CK2

CK2#

DDSPD

SPD/EEPROM

120

120 120

NOTE:

1. All resistor values are 22Ω unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the module part number guide at

www.micron.com/numberguide.

Standard modules use the following DDR SDRAM devices:

MT46V16M8TG (256MB); MT46V32M8TG (512MB); MT46V64M8TG (1GB)

Lead-free modules use the following DDR SDRAM devices:

MT46V16M8P (256MB); MT46V32M8P (512MB); MT46V64M8P (1GB)

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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General Description

The MT18VDDT3272A, MT18VDDT6472, and

MT18VDDT12872 are high-speed CMOS, dynamic

random-access, 256MB, 512MB, and 1GB memory

modules organized in x72 (ECC) configuration. DDR

SDRAM modules use internally configured quad-bank

DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. Double data

rate architecture is essentially a 2n-prefetch architec-

ture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or

write access for the DDR SDRAM module effectively

consists of a single 2n-bit wide, one-clock-cycle data

transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going

HIGH and CK# going LOW will be referred to as the

positive edge of CK. Commands (address and control

signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and out-

put data is referenced to both edges of DQS, as well as

to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed (BA0, BA1 select devices bank; A0–A11 select

device row for 256MB, A0–A12 select device row for

512MB and 1GB). The address bits registered coinci-

dent with the READ or WRITE command are used to

select the device bank and the starting device column

location for the burst access

DDR SDRAM modules provide for programmable

READ or WRITE burst lengths of 2, 4, or 8 locations. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more

information regarding DDR SDRAM operation, refer to

the 128Mb, 256Mb, or 512Mb DDR SDRAM compo-

nent data sheets.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for

use by the customer. System READ/WRITE operations

between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA (2:0), which provide eight unique

DIMM/EEPROM addresses. Write protect (WP) is tied

to ground on the module, permanently disabling hard-

ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of DDR SDRAM devices. This defi-

nition includes the selection of a burst length, a burst

type, a CAS latency and an operating mode, as shown

in Figure 4, Mode Register Definition Diagram, on

page 8. The mode register is programmed via the

MODE REGISTER SET command (with BA0 = 0 and

BA1 = 0) and will retain the stored information until it

is programmed again or the device loses power (except

for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

progress, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

Mode register bits A0–A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-

leaved), A4–A6 specify the CAS latency, and A7–A11

(256MB) or A7–A12 (512MB and 1GB) specify the oper-

ating mode.

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 4, Mode Register Definition

Diagram. The burst length determines the maximum

number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 2, 4,

or 8 locations are available for both the sequential and

the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four and by

A3–Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration; see Note 5 of Table 6, Burst Definition

Table, on page 9). The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. The programmed burst length

applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Table 6, Burst

Definition Table, on page 9.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,

CAS Latency Diagram, on page 9.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. Table 7,

CAS Latency (CL) Table, on page 9, indicates the oper-

ating frequencies at which each CAS latency setting

can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

10111213

* M14 and M13 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

Operating Mode

A10

A11

BA0

BA1

10111213

* M13 and M12 (BA1and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

512MB, 1GB Modules

256MB Module

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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NOTE:

1. For a burst length of two, A1-Ai select the two-data-ele-

ment block; A0 selects the first access within the block.

2. For a burst length of four, A2-Ai select the four-data-

element block; A0-A1 select the first access within the

block.

3. For a burst length of eight, A3-Ai select the eight-data-

element block; A0-A2 select the first access within the

block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

5. i = 9 (256MB, 512MB);

i = 9, 11 (1GB)

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7–A11 (for

256MB), or A7–A12 (512MB, 1GB) each set to zero, and

bits A0–A6 set to the desired values. A DLL reset is ini-

tiated by issuing a MODE REGISTER SET command

with bits A7 and A9–A11 (256MB), or A7 and A9–A12

(512MB, 1GB) each set to zero, bit A8 set to one, and

bits A0–A6 set to the desired values. Although not

required by the Micron device, JEDEC specifications

recommend when a LOAD MODE REGISTER com-

mand is issued to reset the DLL, it should always be

followed by a LOAD MODE REGISTER command to

select normal operating mode.

All other combinations of values for A7–A11

(256MB), or A7–A12 (512MB, 1GB) are reserved for

future use and/or test modes. Test modes and

Table 6: Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL TYPE =

INTERLEAVED

2A0

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7: CAS Latency (CL) Table

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHZ)

CL = 2 CL = 2.5 CL = 3

-40B 75 ≤ f ≤ 133 75 ≤ f ≤ 167 125 ≤ f ≤ 200

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

CK#

COMMAND

DQS

CL = 3

READ NOP NOP NOP

T0 T1 T2 T2n T3 T3n

ﬂ HHHHHHH mmnnumm

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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reserved states should not be used because unknown

operation or incompatibility with future versions may

result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in Figure6, Extended Mode Register

Definition Diagram, on page 10. The extended mode

TER command to the mode register (with BA0 = 1 and

BA1 = 0) and will retain the stored information until it

is programmed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these requirements could result in unspecified oper-

ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. E13 and E12 (256MB), or E14 and E13 (512MB, 1GB)

(BA1 and BA0) must be “0, 1” to select the Extended

Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

E1, E0

Operating Mode

A10

A11A12

BA1BA0

1011121314

E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

Operating Mode

A10

A11

BA1BA0

10111213

256MB Module

512MB, 1GB Modules

–

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Commands

Table 8, Commands Truth Table, and Table 9, DM

Operation Truth Table, provide a general reference of

available commands. For a more detailed description

of commands and operations, refer to the 128Mb,

256Mb, or 512Mb DDR SDRAM component data sheet.

NOTE:

1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address.

3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide column address; A10

HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–

BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12

(256MB, 512MB) provide the op-code to be written to the selected mode register.

Table 8: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) HXXX X 1

NO OPERATION (NOP) LHHH X 1

ACTIVE (Select bank and activate row) L L H H Bank/Row 2

READ (Select bank and column, and start READ burst) LHLHBank/Col 3

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LHHL X 4

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6, 7

LOAD MODE REGISTER LLLLOp-Code 8

Table 9: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION) DM DQS

WRITE Enable L Valid

WRITE Inhibit HX

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Voltage on VDD Supply

Relative to VSS . . . . . . . . . . . . . . . . . . . .-1V to +3.6V

Voltage on VDDQ Supply

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V

Operating Temperature

TA (ambient). . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C

Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.5 2.7 V 32, 36, 47

I/O Supply Voltage VDDQ 2.5 2.7 V 32, 36, 39,

I/O Reference Voltage VREF 0.49 ×

VDDQ0.51 ×

VDDQV6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V

(All other pins not under test = 0V)

Command/

Address, RAS#,

CAS#, WE# II

-36 36

µA 46

CKE, S# -18 18

CK, CK# -12 12

DM -4 4

OUTPUT LEAKAGE CURRENT

(DQ are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS IOZ -10 10 µA 46

OUTPUT LEVELS

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA 33, 34

IOL 16.8 – mA

Table 11: AC Input Operating Conditions

Notes: 1–5, 14, 48; notes appear pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 35

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 35

I/O Reference Voltage VREF(AC)0.49 × VDDQ0.51 × VDDQV 6

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 12: IDD Specifications and Conditions – 256MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

MAX

PARAMETER/CONDITION SYM -40B UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs changing

once every two clock cycles

IDD0a1,062 mA 21, 41

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD1a1,242 mA 21, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb27 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb450 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN);

CKE = LOW IDD3Pb225 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM and DQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3Nb450 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,242 mA 21, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,422 mA 21

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b2,160 mA 43

tREFC = 15.625µs IDD5Ab54 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b36 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN);

Address and control inputs change only during Active READ, or

WRITE commands

IDD7a3,222 mA 20, 42

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 13: IDD Specifications and Conditions – 512MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

MAX

PARAMETER/CONDITION SYM -40B UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0a1,251 mA 21, 41

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); Iout = 0mA; Address

and control inputs changing once per clock cycle

IDD1a1,566 mA 21, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb72 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb1,080 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN)

; CKE = LOW IDD3Pb720 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3Nb1,260 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,836 mA 21, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,791 mA 21

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,680 mA 43

tREFC = 7.8125µs IDD5Ab108 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b72 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN);

Address and control inputs change only during Active READ, or

WRITE commands

IDD7a4,266 mA 20, 42

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 14: IDD Specifications and Conditions – 1GB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

MAX

PARAMETER/CONDITION SYM -40B UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0a1,440 mA 21, 41

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD1a1,710 mA 21, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb90 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb990 mA 44

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN)

; CKE = LOW IDD3Pb810 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3Nb1,080 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,755 mA 21, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,800 mA 21

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b6,210 mA 43

tREFC = 7.8125µs IDD5Ab198 mA 24, 43

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard IDD6b90 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN);

Address and control inputs change only during Active READ, or

WRITE commands

IDD7a4,095 mA 20, 42

NOTE:

a: Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Value calculated reflects all module ranks in this operating condition.

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 15: Capacitance

Note: 11; notes appear on pages 19–21

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQ, DQS, DM CIO 810 pF

Input Capacitance: Command and Address CI1 36 54 pF

Input Capacitance: S#, CKE CI1 18 27 pF

Input Capacitance: CK, CK# CI2 12 18 pF

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 16: DDR SDRAM Component Electrical Characteristics and

Recommended AC Operating Conditions

Notes: 1–5, 8, 12–15, 29, 31; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

AC CHARACTERISTICS -40B

PARAMETER

SYMBOL

MIN MAX

UNITS NOTES

Access window of DQs from CK/CK# tAC -0.7 +0.7 ns

CK high-level width tCH 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 tCK 26

Clock cycle time CL = 3 tCK (3) 5 7.5 ns 40, 45

CL = 2.5 tCK (2.5) 613ns40, 45

CL = 2 tCK (2) 7.5 13 ns 40, 45

DQ and DM input hold time relative to DQS tDH 0.4 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.4 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 ns 27

Access window of DQS from CK/CK# tDQSCK -0.6 +0.6 ns

DQS input high pulse width tDQSH 0.35 tCK

DQS input low pulse width tDQSL 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access

tDQSQ 0.40 ns 22, 23

Write command to first DQS latching transition tDQSS 0.72 1.28 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 tCK

Half clock period tHP tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.70 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.70 ns 16, 37

Address and control input hold time (1 V/ns)

tIHF0.6 ns

Address and control input setup time (1 V/ns)

tISF0.6 ns

Address and control input hold time (0.5 V/ns)

tIHS0.6 ns 12

Address and control input setup time (0.5 V/ns)

tISS0.6 ns 12

Address and Control input pulse width (for each input) tIPW 2.2 ns

LOAD MODE REGISTER command cycle time

tMRD 2ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access

tQH tHP -tQHS ns 22, 23

Data hold skew factor tQHS 0.50 ns

ACTIVE to PRECHARGE command tRAS 40 70,000 ns 30

ACTIVE to READ with Auto precharge command tRAP 15 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 55 ns

AUTO REFRESH command period tRFC 70 ns 43

ACTIVE to READ or WRITE delay tRCD 15 ns

PRECHARGE command period tRP 15 ns

DQS read preamble tRPRE 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 tCK 38

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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ACTIVE bank a to ACTIVE bank b command tRRD 10 ns

DQS write preamble tWPRE 0.25 tCK

DQS write preamble setup time tWPRES 0ns18, 19

DQS write postamble tWPST 0.4 0.6 tCK 17

Write recovery time tWR 15 ns

Internal WRITE to READ command delay tWTR 2tCK

Data valid output window na tQH -tDQSQ ns 22

REFRESH to REFRESH command interval 256MB tREFC 140.6 µs 21

512MB,

1GB 70.3 µs

Average periodic refresh interval 256MB tREFI 15.6 µs 21

512MB,

1GB 7.8 µs

Terminating voltage delay to VDD tVTD 0ns

Exit SELF REFRESH to non-READ command tXSNR 75 ns

Exit SELF REFRESH to READ command tXSRD 200 tCK

Table 16: DDR SDRAM Component Electrical Characteristics and

Recommended AC Operating Conditions (Continued)

Notes: 1–5, 8, 12–15, 29, 31; notes appear on pages 19–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V

AC CHARACTERISTICS -40B

PARAMETER

SYMBOL

MIN MAX

UNITS NOTES

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fications are guaranteed for the specified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL(AC)

and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent upon output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 3 for -40B with the out-

puts open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.6V ±0.1V,

VDDQ = +2.6V ±0.1V, VREF = VSS, f = 200 MHz, TA=

25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting

the fact that they are matched in loading.

12. For slew rates less than 1V/ns and greater than or

equal to 0.5Vns. If slew rate is less than 0.5V/ns,

timing must be derated: tIS has an additional 50ps

per each 100mV/ns reduction in slew rate from

500mV/ns, while tIH has 0pF is unaffected. If slew

rate exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

15.

The output timing reference level, as measured at the

timing reference point indicated in Note 3, is V

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (HZ) or begins driving (LZ).

17.

The intent of the Don’t Care state after completion

of the postamble is the DQS-driven signal should

either be high, low, or high-Z and that any signal

transition within the input switching region must

follow valid input requirements. That is, if DQS

transitions high [above V

DC (MIN)] then it must

not transition low (below V

DC) prior to

DQSH

(MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

ple of tCK that meets the maximum absolute

value for tRAS.

21. The refresh period is 64ms. This equates to an

average refresh rate of 15.625µs (256MB) or

7.8125µs (512MB, 1GB). However, an AUTO

REFRESH command must be asserted at least

once every 140.6µs (256MB) or 70.3µs (512MB,

1GB); burst refreshing or posting by the DRAM

Output

OUT

)Reference

Point

Ω

30pF

“mum

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controller greater than eight refresh cycles is not

allowed.

22. The valid data window is derived by achieving

other specifications: tHP (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data valid window derates

in direct porportion to the clock duty cycle and a

practical data valid window can be derived. The

clock is allowed a maximum duty cycle variation

of 45/55. Functionality is uncertain when operat-

ing beyond a 45/55 ratio.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, VIL (AC)

or VIH (AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, VIL (DC)

or VIH (DC).

26. CK and CK# input slew rate must be ≥ 1V/ns (2V/

ns differentially).

27.

DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. DQ/DM/DQS

slew rates less than 0.5V/ns are not allowed. If slew

rate exceeds 4V/ns, functionality is uncertain.

28. VDD must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

30. tHP min is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK/ inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until tRAS(MIN) can be satis-

fied prior to the internal precharge command

being issued.

32.

Any positive glitch must be less than 1/3 of the

clock and not more than +400mV or 2.9V, which-

ever is less. Any negative glitch must be less than 1/

3 of the clock cycle and not exceed either -300mV

or 2.4V, whichever is more positive. However, the

DC average cannot be below 2.5V minimum.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 7,

Pull-Down Characteristics, on page 20.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure 7, Pull-Down Characteristics,

on page 20.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 8,

Pull-Up Characteristics, on page 20.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of

Figure 8, Pull-Up Characteristics, on page 20.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0V, and

at the same voltage and temperature.

Figure 7: Pull-Down Characteristics Figure 8: Pull-Up Characteristics

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f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10 percent, for device drain-to-source volt-

ages from 0.1V to 1.0 Volt.

34. The voltage levels used are derived from a mini-

mum VDD level and the referenced test load. In

practice, the voltage levels obtained from a prop-

erly terminated bus will provide significantly dif-

ferent voltage values.

35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. VIL undershoot:

VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the

pulse width can not be greater than 1/3 of the

cycle rate.

36. VDD and VDDQ must track each other.

37. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPST

(MAX) condition. tLZ (MIN) will prevail over

tDQSCK (MIN) + tRPRE (MAX) condition.

38. tRPST end point and tRPRE begin point are not

referenced to a specific voltage level but specify

when the device output is no longer driving

(tRPST), or begins driving (tRPRE).

39. During initialization, VDDQ, VTT, and VREF must

be equal to or less than VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0V, provided a minimum of

42Ω of series resistance is used between the VTT

supply and the input pin.

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As

such, future die may not reflect this option.

41. Random addressing changing and 50 percent of

data changing at every transfer.

42. Random addressing changing and 100 percent of

data changing at every transfer.

43. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

tREF later.

44. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

45. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

46. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

47. This is the DC voltage supplied at the DRAM and

is inclusive of all noise up to 20 MHz. Any noise

above 20MHz at the DRAM generated from any

source other than the DRAM istelf may not exceed

the DC voltage range of +2.6V ±0.1V.

48. When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or LOW.

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Initialization

To ensure device operation the DRAM must be ini-

tialized as described below:

1. Simultaneously apply power to VDD and VDDQ.

2. Apply VREF and then VTT power.

3. Assert and hold CKE at a LVCMOS logic low.

4. Provide stable CLOCK signals.

5. Wait at least 200µs.

6. Bring CKE high and provide at least one NOP or

DESELECT command. At this point the CKE input

changes from a LVCMOS input to a SSTL2 input

only and will remain a SSTL_2 input unless a

power cycle occurs.

7. Perform a PRECHARGE ALL command.

8. Wait at least tRP time, during this time NOPs or

DESELECT commands must be given.

9. Using the LMR command program the Extended

Mode Register (E0 = 0 to enable the DLL and E1 =

0 for normal drive or E1 = 1 for reduced drive, E2

through En must be set to 0; where n = most sig-

nificant bit).

10. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

11. Using the LMR command program the Mode Reg-

ister to set operating parameters and to reset the

DLL. Note at least 200 clock cycles are required

between a DLL reset and any READ command.

12. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

13. Issue a PRECHARGE ALL command.

14. Wait at least tRP time, only NOPs or DESELECT

commands are allowed.

15. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

16. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

17. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

18. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

19. Although not required by the Micron device,

JEDEC requires a LMR command to clear the DLL

bit (set M8 = 0). If a LMR command is issued the

same operating parameters should be utilized as

in step 11.

20. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

21. At this point the DRAM is ready for any valid com-

mand. Note 200 clock cycles are required between

step 11 (DLL Reset) and any READ command.

Figure 9: Initialization Flow Diagram

and V

Q Ramp

Apply V

REF

and V

CKE must be LVCMOS Low

Apply stable CLOCKs

Bring CKE High with a NOP command

Wait at least 200us

PRECHARGE ALL

Assert NOP or DESELECT for tRP time

Configure Extended Mode Register

Configure Load Mode Register and reset DLL

Assert NOP or DESELECT for tMRD time

PRECHARGE ALL

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRFC time

Optional LMR command to clear DLL bit

Assert NOP or DESELECT for tMRD time

DRAM is ready for any valid command

Step

Assert NOP or DESELECT commands for tRFC

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRP time

We“. — ~ Ambient Temperature =259 C

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Figure 10: Component Case Temperature vs. Air Flow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module.

2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered

memory modules. Case temperatures charted represent worst-case component locations on modules installed in the

internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard

for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test

chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

Tmax

- memory stress software

Tave

- 3D gaming software

Tave

- memory stress software

Minimum Air Flow

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (as

shown in Figure 11, Data Validity, and Figure 12, Defi-

nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Fig-

ure 13, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 11: Data Validity Figure 12: Definition of Start and Stop

Figure 13: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

4Q cron‘ HIGH LOW \ AA ‘ DH BUF OV0‘OVOVOVOVOVO'0'O'O'O'O'O'O'O'O'O'O'O‘O‘O'\ mom..oaiotototoxoxotototottﬁa320202020!"

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Figure 14: SPD EEPROM Timing Diagram

Table 17: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW

Table 18: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0V

IH or VIL 1START, Device Select, RW = ‘0’, Address

IH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ≥ 1 Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL ≤ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDDSPD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD + 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2mA

Table 20: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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Table 21: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

BYTE DESCRIPTION ENTRY (VERSION)

MT18VDDT3272A MT18VDDT6472A MT18VDDT12872A

0Number of SPD Bytes Used by Micron 128 80 80 80

1Total Number of Bytes in SPD Device 256 08 08 08

2Fundamental Memory Type SDRAM DDR 07 07 07

3Number of Row Addresses on

Assembly 12, 13 0C 0D 0D

4Number of Column Addresses on

Assembly 10, 11 0A 0A 0B

5Number of Physical Ranks on DIMM 2020202

6Module Data Width 72 48 48 48

7Module Data Width (Continued) 0000000

8Module Voltage Interface Levels SSTL 2.5V 04 04 04

9SDRAM Cycle Time, tCK

CAS Latency = 3 5ns (-40B) 50 50 50

10 SDRAM Access from Clock, tAC

CAS Latency = 3 0.7ns (-40B) 70 70 70

11 Module Configuration Type ECC 02 02 02

12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 80 82 82

13 SDRAM Device Width (Primary DDR

SDRAM) 8080808

14 Error-checking DDR SDRAM Data

Width 8080808

15 Minimum Clock Delay, Back-to-Back

Random Column Access 1 clock 01 01 01

16 Burst Lengths Supported 2, 4, 8 0E 0E 0E

17 Number of Banks on DDR SDRAM

Device 4040404

18 CAS Latencies Supported 3, 2.5, 2 1C 1C 1C

19 CS Latency 0010101

20 WE Latency 1020202

21 SDRAM Module Attributes Unbuffered/Diff.

Clock 20 20 20

22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0

23 SDRAM Cycle Time, tCK

(CAS Latency = 2.5) 6ns (for PC2700

system compatibility) 60 60 60

24 SDRAM Access from CK, tAC

(CAS Latency = 2.5) 0.7ns (for PC 2700

system compatibility) 70 70 70

25 SDRAM Cycle Time, tCK

(CAS Latency = 2) 7.5ns (for PC 2100

and PC 1600 system

compatibility)

75 75 75

26 SDRAM Access from CK, tAC

(CAS LATENCY = 2) 0.75ns (for PC 2100

and PC 1600 system

compatibility)

75 75 75

27 Minimum Row Precharge Time, tRP 15ns (-40B) 3C 3C 3C

28 Minimum Row Active to Row Active,

tRRD 10ns (-40B) 28 28 28

29 Minimum RAS# to CAS# Delay, tRCD 15ns (-40B) 3C 3C 3C

30 Minimum RAS# Pulse Width, tRAS 40ns (-40B) 28 28 28

256MB, 512MB, 1GB (x72, ECC, DR), PC3200

184-PIN DDR SDRAM UDIMM

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31 Module Rank Density 128MB, 256MB,

512MB 20 40 80

32 Address And Command Setup Time,

tIS 0.6ns (-40B) 60 60 60

33 Address And Command Hold Time,

tIH 0.6ns (-40B) 60 60 60

34 Data/ Data Mask Input Setup Time,

tDS 0.4ns (-40B) 40 40 40

35 Data/ Data Mask Input Hold Time,

tDH 0.4ns (-40B) 40 40 40

36-40 Reserved 00 00 00

41 Min Active Auto Refresh Time, tRC 55ns (-40B) 37 37 37

42 Minimum Auto Refresh to Active/

Auto Refresh Command Period, tRFC 70ns (-40B) 46 46 46

43 SDRAM Device Max Cycle Time,

tCKMAX

12ns (-40B) 30 30 30

44 SDRAM Device Max DQS-DQ Skew

Time, tDQSQ 0.4ns (-40B) 28 28 28

45 SDRAM Device Max Read Data Hold

Skew Factor, tQHS 0.5ns (-40B) 50 50 50

46 Reserved 00 00 00

47 DIMM Height 01 01 01

48–61 Reserved 00 00 00

62 SPD Revision Release 1.1 11 11 11

63 Checksum for Bytes 0-62 -40B 70 93 D4

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code 1-9 01-09 01-09 01-09

92 Identification Code (Continued) 0000000

93 Year of Manufacture in BCD Variable Data Variable Data Variable Data

94 Week of Manufacture in BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data

99-127

Manufacturer-Specific Data (RSVD) –––

Table 21: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

BYTE DESCRIPTION ENTRY (VERSION)

MT18VDDT3272A MT18VDDT6472A MT18VDDT12872A

452.com— EJDIIIIBIC‘IIﬂ x Ab» 4L ‘4 { ‘—_/67T @DIIIIIID:

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184-PIN DDR SDRAM UDIMM

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8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 15: 184-PIN DIMM Dimensions

NOTE:

All dimensions in inches (millimeters); or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete

power supply and temperature range for production

devices. Although considered final, these specifica-

tions are subject to change, as further product devel-

opment and data characterization sometimes occur.

1.256 (31.9)

1.244 (31.6)

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP. 0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

PIN 92

FRONT VIEW

BACK VIEW

0.054 (1.37)

0.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

PIN 184 PIN 93

0.150 (3.80) 0.150 (3.80)

TYP. 0.394 (10.00)

TYP.

0.157 (4.00)

MAX

PIN 1

0.035 (0.90) R

U10 U11 U12 U13 U15 U16 U17 U18

U1 U2 U3 U4 U6 U7 U8 U9

U19

U14

MAX

MIN

MT18VDDT3272A, 6472A, 12872A, 25672A Datasheet by Micron Technology Inc.

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