UCC21520 Datasheet by Texas Instruments

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UCC21520 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver

1 Features

• Universal: dual low-side, dual high-side or half-

bridge driver

• Operating temperature range –40 to +125°C

• Switching parameters:

– 19-ns typical propagation delay

– 10-ns minimum pulse width

– 5-ns maximum delay matching

– 6-ns maximum pulse-width distortion

• Common-mode transient immunity (CMTI) greater

than 100 V/ns

• Surge immunity up to 12.8 kV

• Isolation barrier life >40 years

• 4-A peak source, 6-A peak sink output

• TTL and CMOS compatible inputs

• 3-V to 18-V input VCCI range to interface with both

digital and analog controllers

• Up to 25-V VDD output drive supply

– 5-V and 8-V VDD UVLO options

• Programmable overlap and dead time

• Rejects input pulses and noise transients shorter

than 5 ns

• Fast disable for power sequencing

• Industry standard wide body SOIC-16 (DW)

package

• Safety-related certifications:

– 8000-VPK reinforced Isolation per DIN V VDE V

0884-11:2017-01

– 5.7-kVRMS isolation for 1 minute per UL 1577

– CSA certification per IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1 end

equipment standards

– CQC certification per GB4943.1-2011

2 Applications

• HEV and BEV battery chargers

• Isolated converters in DC-DC and AC-DC power

supplies

• Server, telecom, it and industrial infrastructures

• Motor drive and DC-to-AC solar inverters

• LED lighting

• Inductive heating

• Uninterruptible power supply (UPS)

3 Description

The UCC21520 and the UCC21520A are isolated

dual-channel gate drivers with 4-A source and 6-A

sink peak current. It is designed to drive power

MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz

with best-in-class propagation delay and pulse-width

distortion.

The input side is isolated from the two output

drivers by a 5.7-kVRMS reinforced isolation barrier,

with a minimum of 100-V/ns common-mode transient

immunity (CMTI). Internal functional isolation between

the two secondary-side drivers allows a working

voltage of up to 1500 VDC.

Every driver can be configured as two low-side

drivers, two high-side drivers, or a half-bridge driver

with programmable dead time (DT). A disable pin

shuts down both outputs simultaneously when it is set

high, and allows normal operation when left open or

grounded. As a fail-safe measure, primary-side logic

failures force both outputs low.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

UCC21520DW DW SOIC (16) 10.30 mm × 7.50 mm

UCC21520ADW DW SOIC (16) 10.30 mm × 7.50 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Driver

VDDB

OUTB

VSSB

UVLODEMODMOD

Driver

VDDA

OUTA

VSSA

UVLODEMODMOD

Functional Isolation

Reinforced Isolation

Disable,

UVLO

and

Deadtime

3,8

GND

INB

DIS

INA

VCCI

Functional Block Diagram

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

I TEXAS INSTRUMENTS

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................5

7.5 Power Ratings.............................................................5

7.6 Insulation Specifications............................................. 5

7.7 Safety-Related Certifications...................................... 6

7.8 Safety-Limiting Values................................................ 6

7.9 Electrical Characteristics.............................................7

7.10 Switching Characteristics..........................................8

7.11 Insulation Characteristics Curves..............................9

7.12 Typical Characteristics............................................10

8 Parameter Measurement Information.......................... 14

8.1 Propagation Delay and Pulse Width Distortion......... 14

8.2 Rising and Falling Time.............................................14

8.3 Input and Disable Response Time............................ 14

8.4 Programable Dead Time........................................... 15

8.5 Power-up UVLO Delay to OUTPUT..........................15

8.6 CMTI Testing.............................................................16

9 Detailed Description......................................................17

9.1 Overview................................................................... 17

9.2 Functional Block Diagram......................................... 17

9.3 Feature Description...................................................18

9.4 Device Functional Modes..........................................21

10 Application and Implementation................................ 22

10.1 Application Information........................................... 22

10.2 Typical Application.................................................. 23

11 Power Supply Recommendations..............................34

12 Layout...........................................................................35

12.1 Layout Guidelines................................................... 35

12.2 Layout Example...................................................... 36

13 Device and Documentation Support..........................38

13.1 Third-Party Products Disclaimer............................. 38

13.2 Documentation Support.......................................... 38

13.3 Certifications........................................................... 38

13.4 Receiving Notification of Documentation Updates..38

13.5 Support Resources................................................. 38

13.6 Trademarks............................................................. 38

13.7 Electrostatic Discharge Caution..............................38

13.8 Glossary..................................................................38

14 Mechanical, Packaging, and Orderable

Information.................................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (March 2020) to Revision E (December 2021) Page

• Updated Features .............................................................................................................................................. 1

• Changed tPWD in Switching Characteristics .......................................................................................................8

Changes from Revision C (December 2019) to Revision D (March 2020) Page

• Added cross reference to table note1 ................................................................................................................4

• Added VDDx power-up delay typ and max values ............................................................................................ 8

• Changed DT pin configuration recommendations ........................................................................................... 21

• Added update to bootstrap circuit recommendations....................................................................................... 24

• Added update to gate resistor selection recommendations .............................................................................25

• Added gate to source resistor recommendation .............................................................................................. 26

• Added update to Cboot selection recommendations ....................................................................................... 28

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5 Description (continued)

Each device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the

driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under

voltage lock-out (UVLO) protection.

With all these advanced features, the UCC21520 and the UCC21520A enable high efficiency, high power

density, and robustness in a wide variety of power applications.

6 Pin Configuration and Functions

Not to scale

1INA 16 VDDA

2INB 15 OUTA

3VCCI 14 VSSA

4GND 13 NC

5DISABLE 12 NC

6DT 11 VDDB

7NC 10 OUTB

8VCCI 9 VSSB

Figure 6-1. DW Package 16-Pin SOIC Top View

Table 6-1. Pin Functions

PIN TYPE(1) DESCRIPTION

NAME NO.

DISABLE 5 I

Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled

low internally if left open. It is recommended to tie this pin to ground if not used to achieve

better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when

connecting to a micro controller with distance.

DT 6 I

Programmable dead time function.

Tying DT to VCCI allows the outputs to overlap. Placing a 500-Ω to 500-kΩ resistor (RDT)

between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is

recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with RDT

to achieve better noise immunity. It is not recommended to leave DT floating.

GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.

INA 1 I

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB 2 I

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

NC 7 – No Internal connection.

NC 12 – No internal connection.

NC 13 – No internal connection.

OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT.

OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT.

VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.

VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL

capacitor located as close to the device as possible.

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Table 6-1. Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.

VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P = Power, G = Ground, I = Input, O = Output

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input bias pin supply voltage VCCI to GND –0.3 20 V

Driver bias supply VDDA-VSSA, VDDB-VSSB –0.3 30 V

Output signal voltage

OUTA to VSSA, OUTB to VSSB –0.3 VVDDA+0.3,

VVDDB+0.3 V

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns –2 VVDDA+0.3,

VVDDB+0.3 V

Input signal voltage INA, INB, DIS, DT to GND –0.3 VVCCI+0.3 V

INA, INB Transient for 50 ns –5 VVCCI +0.3 V

Channel to channel voltage VSSA-VSSB, VSSB-VSSA 1500 V

Junction temperature, TJ (2) –40 150 °C

Storage temperature, Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) To maintain the recommended operating conditions for TJ, see the Section 7.4.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VCCI VCCI Input supply voltage 3 18 V

VDDA,

VDDB Driver output bias supply UCC21520ADW – 5-V UVLO version 6.5 25 V

VDDA,

VDDB Driver output bias supply UCC21520DW – 8-V UVLO version 9.2 25 V

TAAmbient Temperature –40 125 °C

TJJunction Temperature –40 130 °C

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7.4 Thermal Information

THERMAL METRIC(1)

UCC21520,

UCC21520A UNIT

DW-16 (SOIC)

RθJA Junction-to-ambient thermal resistance 67.3 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 34.4 °C/W

RθJB Junction-to-board thermal resistance 32.1 °C/W

ψJT Junction-to-top characterization parameter 18.0 °C/W

ψJB Junction-to-board characterization parameter 31.6 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Application

Report.

7.5 Power Ratings

VALUE UNIT

PDPower dissipation by UCC21520 or UCC21520A

VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3

V, 3 MHz 50% duty cycle square wave 1-nF

load

1.05 W

PDI Power dissipation by transmitter side of

UCC21520 or UCC21520A

0.05 W

PDA, PDB Power dissipation by each driver side of

UCC21520 or UCC21520A

0.5 W

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT

CLR External clearance(1) Shortest pin-to-pin distance through air > 8 mm

CPG External creepage(1) Shortest pin-to-pin distance across the package surface > 8 mm

DTI Distance through insulation Minimum internal gap (internal clearance) of the double

insulation (2 × 10.5 µm) >21 µm

CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V

Material group According to IEC 60664-1 I

Overvoltage category per

IEC 60664-1

Rated mains voltage ≤ 600 VRMS I-IV

Rated mains voltage ≤ 1000 VRMS I-III

DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(2)

VIORM

Maximum repetitive peak

isolation voltage AC voltage (bipolar) 2121 VPK

VIOWM

Maximum working isolation

voltage

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB), test (see Figure 7-1)1500 VRMS

DC voltage 2121 VDC

VIOTM

Maximum transient isolation

voltage

VTEST = VIOTM, t = 60 sec (qualification)

VTEST = 1.2 × VIOTM, t = 1 s (100% production) 8000 VPK

VIOSM

Maximum surge isolation

voltage(3)

Test method per IEC 62368-1, 1.2/50 µs waveform,

VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 VPK

qpd Apparent charge(4)

Method a, After Input/Output safety test subgroup 2/3.

Vini = VIOTM, tini = 60s;

Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s

Method a, After environmental tests subgroup 1.

Vini = VIOTM, tini = 60s;

Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s

Method b1; At routine test (100% production) and

preconditioning (type test)

Vini = 1.2 × VIOTM; tini = 1s;

Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s

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7.6 Insulation Specifications (continued)

PARAMETER TEST CONDITIONS VALUE UNIT

CIO

Barrier capacitance, input to

output(5) VIO = 0.4 sin (2πft), f =1 MHz 1.2 pF

RIO

Isolation resistance, input to

output(5)

VIO = 500 V at TA = 25°C > 1012

ΩVIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011

VIO = 500 V at TS =150°C > 109

Pollution degree 2

Climatic category 40/125/21

UL 1577

VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),

VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production) 5700 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become

equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

7.7 Safety-Related Certifications

VDE CSA UL CQC

Certified according to DIN V VDE V

0884-11:2017-01,

and DIN EN 60950-1 (VDE 0805 Teil

1):2014-08

Certified according to IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1

Recognized under

UL 1577 Component

Recognition Program

Certified according to GB

4943.1-2011

Reinforced Insulation Maximum

Transient Isolation voltage, 8000

VPK;

Maximum Repetitive Peak Isolation

Voltage, 2121 VPK;

Maximum Surge Isolation Voltage,

8000 VPK

Reinforced insulation per CSA

60950-1-07+A1+A2 and IEC 60950-1 2nd

Ed.+A1+A2, 800 VRMS maximum working

voltage (pollution degree 2, material group I)

Reinforced insulation per CSA 62368-1-14

and IEC 62368-1 2nd Ed., 800 VRMS

maximum working voltage (pollution degree

2, material group I);

Basic insulation per CSA 61010-1-12+A1

and IEC 61010-1 3rd Ed., 600 VRMS

maximum working voltage (pollution degree

2, material group III);

2 MOPP (Means of Patient Protection) per

CSA 60601- 1:14 and IEC 60601-1 Ed.3+A1,

250 VRMS maximum working voltage

Single protection, 5700

VRMS

Reinforced Insulation,

Altitude ≤ 5000 m,

Tropical Climate 660 VRMS

maximum working voltage

Certification number: 40040142 Master contract number : 220991 File number: E181974 Certificate number:

CQC16001155011

7.8 Safety-Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT

Safety output supply

current

RθJA = 67.3°C/W, VDDA/B = 12 V, TA =

25°C, TJ = 150°C

See Figure 7-2.

DRIVER A,

DRIVER B 75 mA

RθJA = 67.3°C/W, VDDA/B = 25 V, TA =

25°C, TJ = 150°C

See Figure 7-2.

DRIVER A,

DRIVER B 36 mA

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7.8 Safety-Limiting Values (continued)

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER TEST CONDITIONS SIDE MIN TYP MAX UNIT

PSSafety supply power RθJA = 67.3°C/W, TA = 25°C, TJ = 150°C

See Figure 7-3.

INPUT 50

DRIVER A 900

DRIVER B 900

TOTAL 1850

TSSafety temperature(1) 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The

IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be

exceeded. These limits vary with the ambient temperature, TA.

The junction-to-air thermal resistance, RθJA, in the Section 7.4 table is that of a device installed on a high-K test board for leaded

surface-mount packages. Use these equations to calculate the value for each parameter:

TJ = TA + RθJA × P, where P is the power dissipated in the device.

TJ(max) = TS = TA + RθJA × PS , where TJ(max) is the maximum allowed junction temperature.

PS = IS × VI , where VI is the maximum input voltage.

7.9 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENTS

IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.5 2.0 mA

IVDDA,

IVDDB

VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 1.8 mA

IVCCI VCCI operating current (f = 500 kHz) current per channel,

COUT = 100 pF 2.0 mA

IVDDA,

IVDDB

VDDA and VDDB operating current (f = 500 kHz) current per channel,

COUT = 100 pF 2.5 mA

VCCI UVLO THRESHOLDS

VVCCI_ON Rising threshold 2.55 2.7 2.85 V

VVCCI_OFF Falling threshold VCCI_OFF 2.35 2.5 2.65 V

VVCCI_HYS Threshold hysteresis 0.2 V

UCC21520ADW VDD UVLO THRESHOLDS (5-V UVLO Version)

VVDDA_ON,

VVDDB_ON

Rising threshold VDDA_ON,

VDDB_ON 5.7 6.0 6.3 V

VVDDA_OFF,

VVDDB_OFF

Falling threshold VDDA_OFF,

VDDB_OFF 5.4 5.7 6 V

VVDDA_HYS,

VVDDB_HYS

Threshold hysteresis 0.3 V

UCC21520DW VDD UVLO THRESHOLDS (8-V UVLO Version)

VVDDA_ON,

VVDDB_ON

Rising threshold VDDA_ON,

VDDB_ON 8.3 8.7 9.2 V

VVDDA_OFF,

VVDDB_OFF

Falling threshold VDDA_OFF,

VDDB_OFF 7.8 8.2 8.7 V

VVDDA_HYS,

VVDDB_HYS

Threshold hysteresis 0.5 V

INA, INB AND DISABLE

VINAH, VINBH,

VDISH

Input high voltage 1.6 1.8 2 V

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7.9 Electrical Characteristics (continued)

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VINAL, VINBL,

VDISL

Input low voltage 0.8 1 1.2 V

VINA_HYS,

VINB_HYS,

VDIS_HYS

Input hysteresis 0.8 V

VINA, VINB

Negative transient, ref to GND, 50 ns

pulse

Not production tested, bench test

only –5 V

OUTPUT

IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f =

1 kHz, bench measurement 4 A

IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f =

1 kHz, bench measurement 6 A

ROHA, ROHB Output resistance at high state

IOUT = –10 mA, TA = 25°C, ROHA,

ROHB do not represent drive pull-up

performance. See tRISE in Section

7.10 and Section 9.3.4 for details.

5 Ω

ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω

VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 12 V, IOUT = –10

mA, TA = 25°C 11.95 V

VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 12 V, IOUT = 10

mA, TA = 25°C 5.5 mV

DEADTIME AND OVERLAP PROGRAMMING

Dead time

Pull DT pin to VCCI Overlap determined by INA INB -

DT pin is left open, min spec

characterized only, tested for

outliers

0 8 15 ns

RDT = 20 kΩ 160 200 240 ns

7.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tRISE Output rise time, 20% to 80%

measured points COUT = 1.8 nF 6 16 ns

tFALL Output fall time, 90% to 10%

measured points COUT = 1.8 nF 7 12 ns

tPWmin Minimum pulse width Output off for less than minimum,

COUT = 0 pF

20 ns

tPDHL Propagation delay from INx to OUTx

falling edges

14 19 30 ns

tPDLH Propagation delay from INx to OUTx

rising edges

14 19 30 ns

tPWD Pulse width distortion |tPDLH – tPDHL| 6 ns

tDM Propagation delays matching

between VOUTA, VOUTB f = 100 kHz 5 ns

tVDD+ to OUT VDDA, VDDB Power-up Delay Time:

UVLO Rise to OUTA, OUTB. See

Figure 8-6

INA or INB tied to VCCI

50 100 us

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I TEXAS INSTRUMENTS TA ‘ E‘“ — sway Mavngnne moo vm 25 _ OPemlmg 2m woo M a“ — mos m [a w pm am

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

|CMH|High-level common-mode transient

immunity

INA and INB both are tied to VCCI;

VCM=1500V; (See Section 8.6)100

V/ns

|CML|Low-level common-mode transient

immunity

INA and INB both are tied to GND;

VCM=1500V; (See Section 8.6)100

7.11 Insulation Characteristics Curves

Stress Voltage (VRMS)

Time to Fail (s)

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

1.E+1

1.E+2

1.E+3

1.E+4

1.E+5

1.E+6

1.E+7

1.E+8

1.E+9

1.E+10

1.E+11

Safety Margin Zone: 1800 VRMS, 254 Years

Operating Zone: 1500 VRMS, 135 Years

20%

87.5%

TDDB Line (<1 PPM Fail Rate)

Figure 7-1. Reinforced Isolation Capacitor Life Time Projection

Ambient Temperature (°C)

Safety Limiting Current per Channel (mA)

0 50 100 150 200

100

D001

IVDDA/B for VDD=12V

IVDDA/B for VDD=25V

Figure 7-2. Thermal Derating Curve for Safety-

Related Limiting Current (Current in Each Channel

with Both Channels Running Simultaneously)

Ambient Temperature (°C)

Safety Limiting Power (mW)

0 50 100 150 200

400

800

1200

1600

2000

D001

Figure 7-3. Thermal Derating Curve for Safety-

Related Limiting Power

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7.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

Frequency (kHz)

Current (mA)

0 800 1600 2400 3200 4000 4800 5600

D001

VDD=12v

VDD=25v

Figure 7-4. Per Channel Current Consumption vs

Frequency (No Load, VDD = 12 V or 25 V)

Frequency (kHz)

Current (mA)

0 500 1000 1500 2000 2500 3000

D001

VDD= 12V

VDD= 25V

Figure 7-5. Per Channel Current Consumption

(IVDDA/B) vs Frequency (1-nF Load, VDD = 12 V or

25 V)

Frequency (kHz)

Current (mA)

10 25 40 55 70 85 100

D001

VDD= 12V

VDD= 25V

Figure 7-6. Per Channel Current Consumption

(IVDDA/B) vs Frequency (10-nF Load, VDD = 12 V or

25 V)

Temperature (qC)

VDD Current (mA)

-40 -20 0 20 40 60 80 100 120 140 160

D001

50kHz

250kHz

500kHz

1MHz

Figure 7-7. Per Channel (IVDDA/B) Supply Current

Vs. Temperature (No Load, Different Switching

Frequencies)

Temperature (qC)

Current (mA)

-40 -20 0 20 40 60 80 100 120 140

0.4

0.8

1.2

1.6

D001

VDD= 12V

VDD= 25V

Figure 7-8. Per Channel (IVDDA/B) Quiescent Supply

Current vs Temperature (No Load, Input Low, No

Switching)

Temperature (qC)

Current (mA)

-40 -20 0 20 40 60 80 100 120 140

1.2

1.4

1.6

1.8

D001

VCCI= 3.3V

VCCI= 5V

Figure 7-9. IVCCI Quiescent Supply Current vs

Temperature (No Load, Input Low, No Switching)

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Load (nF)

Time (ns)

0 2 4 6 8 10

D001

tRISE

tFALL

Figure 7-10. Rising and Falling Times vs Load

(VDD = 12 V)

Temperature (qC)

Resistance (:)

-40 -20 0 20 40 60 80 100 120 140

D001

Output Pull-Up

Output Pull-Down

Figure 7-11. Output Resistance vs Temperature

Temperature (qC)

Propagation Delay (ns)

-40 -20 0 20 40 60 80 100 120 140

D001

Rising Edge (tPDLH)

Falling Edge (tPDHL)

Figure 7-12. Propagation Delay vs Temperature

VCCI (V)

Propagation Delay (ns)

3 6 9 12 15 18

D001

Rising Edge (tPDLH)

Falling Edge (tPDHL)

Figure 7-13. Propagation Delay vs VCCI

Temperature (qC)

Pulse Width Distortion (ns)

-40 -20 0 20 40 60 80 100 120 140

-5

-3

-1

D001

Figure 7-14. Pulse Width Distortion vs Temperature

VDDA/B (V)

Propagation Delay Matching (ns)

10 13 16 19 22 25

-5

-2.5

2.5

D001

Rising Edge

Falling Edge

Figure 7-15. Propagation Delay Matching (tDM) vs

VDD

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Temperature (qC)

Propagation Delay Matching (ns)

-40 -20 0 20 40 60 80 100 120 140

-5

-2.5

2.5

D001

Rising Edge

Falling Edge

Figure 7-16. Propagation Delay Matching (tDM) vs

Temperature

Temperature (qC)

Hysteresis (mV)

-40 -20 0 20 40 60 80 100 120 140

250

270

290

310

330

350

D001

Figure 7-17. VDD 5-V UVLO Hysteresis vs

Temperature

Temperature (qC)

UVLO Threshold (V)

-40 -20 0 20 40 60 80 100 120 140

5.5

6.5

D001

VVDD_ON

VVDD_OFF

Figure 7-18. VDD 5-V UVLO Threshold vs

Temperature

Temperature (qC)

Hysterisis (mV)

-40 -20 0 20 40 60 80 100 120 140

450

470

490

510

530

550

D001

Figure 7-19. VDD 8-V UVLO Hysteresis vs

Temperature

Temperature (qC)

UVLO Threshold (V)

-40 -20 0 20 40 60 80 100 120 140

D001

VVDDA_ON

VVDDA_OFF

Figure 7-20. VDD 8-V UVLO Threshold vs

Temperature

Temperature (qC)

IN/DIS Hysterisis (V)

-40 -20 0 20 40 60 80 100 120 140

700

740

780

820

860

900

D001

VCC=3.3V

VCC=5V

VCC=12V

Figure 7-21. IN/DIS Hysteresis vs Temperature

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Temperature (qC)

IN/DIS Low Threshold (V)

-40 -20 0 20 40 60 80 100 120 140

0.9

0.96

1.02

1.08

1.14

1.2

D001

VCC=3.3V

VCC= 5V

VCC=12V

Figure 7-22. IN/DIS Low Threshold

Temperature (qC)

IN/DIS High Threshold (V)

-40 -20 0 20 40 60 80 100 120 140

1.6

1.68

1.76

1.84

1.92

D001

VCC=3.3V

VCC= 5V

VCC=12V

Figure 7-23. IN/DIS High Threshold

Temperature (qC)

Dead Time (ns)

-40 -20 0 20 40 60 80 100 120 140

300

600

900

1200

1500

D001

RDT= 20k:

RDT= 100k:

Figure 7-24. Dead Time vs Temperature (with RDT =

20 kΩ and 100 kΩ)

Temperature (qC)

'DT (ns)

-40 -20 0 20 40 60 80 100 120 140

-50

-39

-28

-17

-6

D001

RDT= 20k:

RDT = 100k:

Figure 7-25. Dead Time Matching vs Temperature

(with RDT = 20 kΩ and 100 kΩ)

Time (ns)

Voltage (V)

0 100 200 300 400 500 600 700 800

-6

-2

D001

1 nF Load

10 nF Load

Figure 7-26. Typical Output Waveforms

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8 Parameter Measurement Information

8.1 Propagation Delay and Pulse Width Distortion

Figure 8-1 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the

propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and

disabling the dead time function by shorting the DT Pin to VCC.

INA/B

tPDLHA

OUTA

OUTB

tPDLHB

tDM

tPDHLB

tPDHLA

tPWDB = |tPDLHB t tPDHLB|

Figure 8-1. Overlapping Inputs, Dead Time Disabled

8.2 Rising and Falling Time

Figure 8-2 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how

short rising and falling times are achieved see Section 9.3.4.

20%

tRISE

80% 90%

10%

tFALL

Figure 8-2. Rising and Falling Time Criteria

8.3 Input and Disable Response Time

Figure 8-3 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low

ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more

information, see Section 9.4.1.

INA

DIS

OUTA

tPDHL

10% 10%

DIS Low

Response Time

tPDLH

DIS High

Response Time

90% 90%

10%

Figure 8-3. Disable Pin Timing

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8.4 Programable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (RDT) sets a dead-time interval. For

more details on dead time, refer to Section 9.4.2.

OUTB

INA

INB

10%

90%

Dead Time

(Set by RDT)

tPDHL

Dead Time

(Determined by Input signals if

longer than DT set by RDT)

90%

10%

tPDLH

tPDHL

OUTA

Figure 8-4. Dead-Time Switching Parameters

8.5 Power-up UVLO Delay to OUTPUT

Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising

edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40us) and tVDD+ to OUT for VDD UVLO

(typically 50us). It is recommended to consider proper margin before launching PWM signal after the driver's

VCCI and VDD bias supply is ready. Figure 8-5 and Figure 8-6 show the power-up UVLO delay timing diagram

for VCCI and VDD.

If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will

not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when

either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on

the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to

ensure safe operation during VCCI or VDD brownouts.

VCCI,

INx

VDDx

VVCCI_ON

OUTx

VVCCI_OFF

tVCCI+ to OUT

Figure 8-5. VCCI Power-up UVLO Delay

VCCI,

INx

VDDx VVDD_ON

OUTx

tVDD+ to OUT VVDD_OFF

Figure 8-6. VDDA/B Power-up UVLO Delay

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8.6 CMTI Testing

Figure 8-7 is a simplified diagram of the CMTI testing configuration.

11 VDDB

OUTB

VSSB

16 VDDA

OUTA

VSSA

Functional

Isolation

Reinforced Isolation

Input Logic

VCCI

DIS

GND

VCCI

INB

INA

OUTB

OUTA

VSS

Common Mode Surge

Generator

GND

VDDVCC

VCC

Figure 8-7. Simplified CMTI Testing Setup

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9 Detailed Description

9.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21520, UCC21520A are flexible dual gate drivers which can be configured to fit a variety of power

supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The

UCC21520, UCC21520A have many features that allow it to integrate well with control circuitry and protect the

gates it drives such as: resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock

out (UVLO) for both input and output voltages. The UCC21520 and the UCC21520A also hold its outputs low

when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and

TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its

respective input pins (INA and INB), allowing full and independent control of each of the outputs.

9.2 Functional Block Diagram

Driver

VDDB

OUTB

VSSB

UVLO

DEMODMOD

Driver

VDDA

OUTA

VSSA

UVLO

DEMODMOD

Functional Isolation

Reinforced Isolation

Deadtime

Control

3,8

GND

INB

DIS

INA

VCCI

200 k:

UVLO

VCCI

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9.3 Feature Description

9.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)

The UCC21520 and the UCC21520A have an internal undervoltage lock out (UVLO) protection feature on the

supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower

than VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected

output low, regardless of the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low

by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 9-1 ). In this

condition, the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output

through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower

NMOS device, typically around 1.5 V, when no bias power is available.

RHI_Z

VDD

RCLAMP

OUT

VSS

RCLAMP is activated

during UVLO

Output

Control

Figure 9-1. Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21520 and the UCC21520A also has an internal undervoltage lock out (UVLO)

protection feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And

a signal will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO

for VDD, there is hysteresis (VVCCI_HYS) to ensure stable operation.

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All versions of the UCC21520 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 9-1. UCC21520 and UCC21520A VCCI UVLO Feature Logic

CONDITION INPUTS OUTPUTS

INA INB OUTA OUTB

VCCI-GND < VVCCI_ON during device start up H L L L

VCCI-GND < VVCCI_ON during device start up L H L L

VCCI-GND < VVCCI_ON during device start up H H L L

VCCI-GND < VVCCI_ON during device start up L L L L

VCCI-GND < VVCCI_OFF after device start up H L L L

VCCI-GND < VVCCI_OFF after device start up L H L L

VCCI-GND < VVCCI_OFF after device start up H H L L

VCCI-GND < VVCCI_OFF after device start up L L L L

Table 9-2. UCC21520 and UCC21520A VDD UVLO Feature Logic

CONDITION INPUTS OUTPUTS

INA INB OUTA OUTB

VDD-VSS < VVDD_ON during device start up H L L L

VDD-VSS < VVDD_ON during device start up L H L L

VDD-VSS < VVDD_ON during device start up H H L L

VDD-VSS < VVDD_ON during device start up L L L L

VDD-VSS < VVDD_OFF after device start up H L L L

VDD-VSS < VVDD_OFF after device start up L H L L

VDD-VSS < VVDD_OFF after device start up H H L L

VDD-VSS < VVDD_OFF after device start up L L L L

9.3.2 Input and Output Logic Table

Table 9-3. INPUT/OUTPUT Logic Table(1)

Assume VCCI, VDDA, VDDB are powered up. See Section 9.3.1 for more information on UVLO operation modes.

INPUTS DISABLE OUTPUTS NOTE

INA INB OUTA OUTB

L L L or Left Open L L

If Dead Time function is used, output transitions occur after the

dead time expires. See Section 9.4.2

L H L or Left Open L H

H L L or Left Open H L

H H L or Left Open L L DT is left open or programmed with RDT

H H L or Left Open H H DT pin pulled to VCCI

Left Open Left Open L or Left Open L L -

X X H L L -

(1) "X" means L, H or left open.

9.3.3 Input Stage

The input pins (INA, INB, and DIS) of the UCC21520 and the UCC21520A are based on a TTL and CMOS

compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy

to drive with logic-level control signals (Such as those from 3.3-V micro-controllers), since the UCC21520 and

the UCC21520A have a typical high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary

little with temperature (see Figure 7-22,Figure 7-23). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise

immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin

low. These resistors are typically 200 kΩ (See Section 9.2). However, it is still recommended to ground an input

if it is not being used.

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Since the input side of the UCC21520 and the UCC21520A is isolated from the output drivers, the input signal

amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows

greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient

VDD for their chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a

voltage higher than VCCI.

9.3.4 Output Stage

The UCC21520 and the UCC21520A output stages feature a pull-up structure which delivers the highest peak-

source current when it is most needed, during the Miller plateau region of the power-switch turn on transition

(when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features

a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by

briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to

high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.

The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on

only for a brief instant when the output is changing states from low to high. Therefore the effective resistance

of the UCC21520 and the UCC21520A pull-up stage during this brief turn-on phase is much lower than what is

represented by the ROH parameter. Therefore, the value of ROH belies the fast nature of the UCC21520 and the

UCC21520A's turn-on time.

The pull-down structure in the UCC21520 and the UCC21520A is simply composed of an N-channel MOSFET.

The ROL parameter, which is also a DC measurement, is representative of the impedance of the pull-down

state in the device. Both outputs of the UCC21520 and the UCC21520A are capable of delivering 4-A peak

source and 6-A peak sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail

operation, thanks to the MOS-out stage which delivers very low drop-out.

VDD

OUT

VSS

Pull Up

Shoot-

Through

Prevention

Circuitry

Input

Signal

ROH

ROL

RNMOS

Figure 9-2. Output Stage

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9.3.5 Diode Structure in the UCC21520 and the UCC21520A

Figure 9-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21520 and the

UCC21520A. This provides a pictorial representation of the absolute maximum rating for the device.

INA

INB

DIS

20 V 20 V

GND

3,8

VCCI

30 V

VDDB

OUTB

OUTA

VSSA

VSSB

VDDA

Figure 9-3. ESD Structure

9.4 Device Functional Modes

9.4.1 Disable Pin

Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE

pin allows the UCC21520 and the UCC21520A to operate normally. The DISABLE response time is in the range

of 20 ns and quite responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and

necessary) when VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the

DISABLE pin is not used to achieve better noise immunity, and it is recommended to bypass using a ≈1-nF low

ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance.

9.4.2 Programmable Dead-Time (DT) Pin

The UCC21520 and the UCC21520A allow the user to adjust dead time (DT) in the following ways:

9.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.

9.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins

One can program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can

be determined from Equation 1, where RDT is in kΩ and tDT is in ns:

9.4.2.3

DT DT

t 10 R» ´

(1)

The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when

RDT=100kΩ. When using RDT> 5kΩ, it is recommended to parallel a ceramic capacitor, 2.2nF or above, close to

the chip with RDT to achieve better noise immunity and better dead time matching between two channels. It is

not recommended to leave the DT pin floating.

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An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead

time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.

If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent

shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead

time logic operating conditions are illustrated and explained in Figure 9-4:

INA

INB

OUTA

OUTB

A B C D E F

Figure 9-4. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,

when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it

immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

The UCC21520 or the UCC21520A effectively combines both isolation and buffer-drive functions. The flexible,

universal capability of the UCC21520 and the UCC21520A (with up to 18-V VCCI and 25-V VDDA/VDDB) allows

the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or

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SiC MOSFETs. With integrated components, advanced protection features (UVLO, dead time, and disable) and

optimized switching performance; the UCC21520 and the UCC21520A enable designers to build smaller, more

robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market.

10.2 Typical Application

The circuit in Figure 10-1 shows a reference design with the UCC21520 driving a typical half-bridge configuration

which could be used in several popular power converter topologies such as synchronous buck, synchronous

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

11 VDDB

OUTB

VSSB

16 VDDA

OUTA

VSSA

Functional

Isolation

Reinforced Isolation

Input Logic

CBOOT

CVDD

VSS

ROFF

RON

RGS

ROFF

RON

CIN

VDD

RBOOT

VDD

HV DC-Link

VCCI

DIS

GND

VCCI

INB

INA

RDT

RDIS

PCCVCC

CIN

RIN

Disable

VCC

PWM-A

PWM-B

Analog

Digital

RGS

CDT

•2.2nF

CDIS

Figure 10-1. Typical Application Schematic

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10.2.1 Design Requirements

Table 10-1 lists reference design parameters for the example application: UCC21520 driving 1200-V SiC-

MOSFETs in a high side-low side configuration.

Table 10-1. UCC21520 Design Requirements

PARAMETER VALUE UNITS

Power transistor C2M0080120D -

VCC 5.0 V

VDD 20 V

Input signal amplitude 3.3 V

Switching frequency (fs) 100 kHz

DC link voltage 800 V

10.2.2 Detailed Design Procedure

10.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an RIN in the range of 0 Ω to100 Ω and a CIN between 10 pF and 100 pF. In the

example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

10.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes

or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the

loss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage

is 800 VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good

margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.

When designing a bootstrap supply, it is recommended to use a bootstrap resistor, RBOOT. A bootstrap resistor,

is also used to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VDDA-VSSA

during each switching cycle.

Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET and UCC21520

may result in permanent damage to the device in certain cases.

The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode used. In the example, a

current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst

case peak current through DBoot is,

 



DD BDF

DBoot pk

Boot

V V 20V 2.5V

I 8A

R 2.2

(2)

where

• VBDF is the estimated bootstrap diode forward voltage drop at 8 A.

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10.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Section 9.3.4, the UCC21520 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:



§ ·



¨ ¸

 

DD BDF

NMOS OH ON GFET _Int

V V

I min 4A, R || R R R

(3)



§ ·

¨ ¸

 

NMOS OH ON GFET _Int

I min 4A, R || R R R

(4)

where

• RON: External turn-on resistance.

• RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.

• IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

In this example:



 

  : :  :  :

DD BDF

NMOS OH ON GFET _Int

V V 20V 0.8V

I 2.4A

R || R R R 1.47 || 5 2.2 4.6

(5)

 |

  : :  :  :

NMOS OH ON GFET _Int

V 20V

I 2.5A

R || R R R 1.47 || 5 2.2 4.6

(6)

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:



§ ·

 

¨ ¸

 

DD BDF GDF

OL OFF ON GFET _Int

V V V

I min 6A, R R || R R

(7)



§ ·



¨ ¸

 

DD GDF

OL OFF ON GFET _Int

V V

I min 6A, R R || R R

(8)

where

• ROFF: External turn-off resistance;

• VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is

an MSS1P4.

• IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated

value based on the gate drive loop resistance.

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I TEXAS INSTRUMENTS VG 20V 0.8V 0.75V D 5 IO A 0L oFF ON GFET \m I vD vG 20v70.75v A 0 0L OFF ON GFET \m Pena : vccl X Ivccw + VVDDA X IDDA + VVDDE X IDDE : 72mW GSW_ X DDX GXsw

In this example,

DD BDF GDF

OL OFF ON GFET _ Int

V V V 20V 0.8V 0.75V

I 3.6A

R R || R R 0.55 0 4.6



   

  :  :  :

(9)

DD GDF

OL OFF ON GFET _ Int

V V 20V-0.75V

I 3.7A

R R || R R 0.55 0 4.6



 |

  :  :  :

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the

power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close

to the parasitic ringing period.

Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including

transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing,

it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added

in the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx

voltages.

10.2.2.4 Gate to Source Resistor Selection

A gate to source resistor, RGS, is recommended to pull down the gate to the source voltage when the gate driver

output is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of dv/dt induced

turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically

sized between 5.1kΩ and 20kΩ, depending on the Vth and ratio of CGD to CGS of the power device.

10.2.2.5 Estimate Gate Driver Power Loss

The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21520 (PGD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in PG and not discussed in this section.

PGD is the key power loss which determines the thermal safety-related limits of the UCC21520, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well

as driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. Figure 7-4 shows the per output channel current consumption vs operating frequency

with no load. In this example, VVCCI = 5 V and VVDD = 20 V. The current on each power supply, with INA/INB

switching from 0 V to 3.3 V at 100 kHz is measured to be IVCCI = 2.5 mA, and IVDDA = IVDDB = 1.5 mA. Therefore,

the PGDQ can be calculated with

GDQ VCCI VCCI VDDA DDA VDDB DDB

P V I V I V I mW 72 u  u | u

(11)

The second component is switching operation loss, PGDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW,

can be estimated with

u u u

GSW DD G SW

P 2 V Q f

(12)

where

• QG is the gate charge of the power transistor.

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If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

u u u

GSW

P 2 20V 60nC 100kHz 240mW

(13)

QG represents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change

with different testing conditions. The UCC21520 gate driver loss on the output stage, PGDO, is part of PGSW.

PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC21520. If there are external turn-on and turn-off resistances, the total loss will be

distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the

pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,

however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two

scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

GSW OH NMOS OL

GDO

OH NMOS ON GFET _ Int OL OFF ON GFET _ Int

P R R R

P2 R R R R R R

|| || R R

§ ·

u 

¨ ¸

   

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520

gate driver loss can be estimated with:

GDO

240mW 5 ||1.47 0.55

P 30mW

2 5 ||1.47 2.2 4.6 0.55 0 4.6

§ ·

: : :

u  |

¨ ¸

: :  :  : :  :  :

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

 

ª º

u u u   u

« »

¬ ¼

³ ³

R _ Sys F _ Sys

T T

GDO SW DD OUTA/B OUTA/B

0 0

P 2 f 4A V V t dt 6A V t dt

(16)

where

• VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the

PGDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up

and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver

UCC21520, PGD, is:



GD GDQ GDO

P P P

(17)

which is equal to 102 mW in the design example.

10.2.2.6 Estimating Junction Temperature

The junction temperature (TJ) of the UCC21520 can be estimated with:

J C JT GD

T T P= + Y ´

(18)

where

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• TC is the UCC21520 case-top temperature measured with a thermocouple or some other instrument, and

• ΨJT is the Junction-to-top characterization parameter from the Section 7.4 table.

Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance

(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately

estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package

Thermal Metrics Application Report.

10.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC)

with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an

MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only

500 nF when a DC bias of 15 VDC is applied.

10.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for

this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

 

 

VDD

Total G

I @100kHz No Load 1.5mA

Q Q 60nC 75nC

f 100kHz

(19)

where

• QTotal: Total charge needed

• QG: Gate charge of the power transistor.

• IVDD: The channel self-current consumption with no load at 100kHz.

• fSW: The switching frequency of the gate driver

Therefore, the absolute minimum CBoot requirement is:

Total

Boot

VDDA

Q 75nC

C 150nF

V 0.5V

(20)

where

• ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

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Boot

C 1)

(21)

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not

drop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor

should be sized such that it can supply the initial charge to switch the power device, and then continuously

supply the gate driver quiescent current for the duration of the high-side on-time.

If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turn

off and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and high

dv/dt transients on the output of the driver and may result in permanent damage to the device.

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor

placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is

placed in parallel with CBoot to optimize the transient performance.

Note

Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and VBOOT could

stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during

initial CBOOT charging cycles, the bootstrap diode has highest reverse recovery current and losses.

10.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD

in Figure 10-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply

current for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for

CVDD. If the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic

capacitor, with a value over 10 µF, should be used in parallel with CVDD.

10.2.2.8 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor

is important for preventing shoot-through during dynamic switching.

The UCC21520 dead time specification in the electrical table is defined as the time interval from 90% of one

channel’s falling edge to 10% of the other channel’s rising edge (see Figure 8-4). This definition ensures that

the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.

However, this dead time setting may not reflect the dead time in the power converter system, since the dead

time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as

well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC21520:

 

  

Setting Req F_ Sys R _ Sys D on

DT DT T T T

(22)

where

• DTsetting: UCC21520 dead time setting in ns, DTSetting = 10 × RDT(in kΩ).

• DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough

margin, or ZVS requirement.

• TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.

• TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.

• TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

In the example, DTSetting is set to 250 ns.

It should be noted that the UCC21520 dead time setting is decided by the DT pin configuration (See Section

9.4.2), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to

parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with RDT to achieve better noise immunity.

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10.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example,

TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power

transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of

unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep

such ringing below the threshold. Below are a few examples of implementing negative gate drive bias.

Figure 10-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on

the isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.

The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for

a half-bridge configuration, and there will be steady state power consumption from RZ.

11 VDDB

OUTB

VSSB

16 VDDA

OUTA

VSSA

Functional

Isolation

Reinforced Isolation

Input Logic

CA1

ROFF

RON CIN

HV DC-Link

CA2

VZ = 5.1 V

25 V

Figure 10-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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Figure 10-3 shows another example which uses two supplies (or single-input-double-output power supply).

Power supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage.

The configuration for channel B is the same as channel A. This solution requires more power supplies than the

first example, however, it provides more flexibility when setting the positive and negative rail voltages.

11 VDDB

OUTB

VSSB

16 VDDA

OUTA

VSSA

Functional

Isolation

Reinforced Isolation

Input Logic

CA1

ROFF

RON CIN

HV DC-Link

CA2

VA+

VA-

Figure 10-3. Negative Bias with Two Iso-Bias Power Supplies

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The last example, shown in Figure 10-4, is a single power supply configuration and generates negative bias

through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply

and the bootstrap power supply can be used for the high side drive. This design requires the least cost and

design effort among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a

fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors favor this

solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits.

11 VDDB

OUTB

VSSB

16 VDDA

OUTA

VSSA

Functional

Isolation

Reinforced Isolation

Input Logic

CBOOT

CVDD

VSS

ROFF

RON

RGS

ROFF

RON

RGS

CIN

VDD

RBOOT

VDD

HV DC-Link

Figure 10-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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10.2.3 Application Curves

Figure 10-5 and Figure 10-6 shows the bench test waveforms for the design example shown in Figure 10-1

under these conditions: VCC = 5 V, VDD = 20 V, fSW = 100 kHz, VDC-Link = 0 V.

Channel 1 (Yellow): UCC21520 INA pin signal.

Channel 2 (Blue): UCC21520 INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In Figure 10-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on

the power transistor have a 250-ns dead time, shown in the measurement section of Figure 10-5. The dead-time

matching is less than 1 ns with the 250-ns dead-time setting.

Figure 10-6 shows a zoomed-in version of the waveform of Figure 10-5, with measurements for propagation

delay and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is

measured between the power transistors’ gate and source pins, and is not measured directly from the driver

OUTA and OUTB pins. Due to the split on and off resistors (Ron,Roff) and different sink and source currents,

different rising (16 ns) and falling time (9 ns) are observed in Figure 10-6.

Figure 10-5. Bench Test Waveform for INA/B and

OUTA/B

Figure 10-6. Zoomed-In bench-test waveform

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11 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21520 and the UCC21520A is between 3 V and 18

V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21520 one is using.

The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection

feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more

information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum

gate voltage of the power device being driven by the UCC21520 and the UCC21520A. The UCC21520 and the

UCC21520A have a recommended maximum VDDA/VDDB of 25 V.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional

≤100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount

of current drawn by the logic circuitry within the input side of the UCC21520 and the UCC21520A, this bypass

capacitor has a minimum recommended value of 100 nF.

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021 www.ti.com

Product Folder Links: UCC21520 UCC21520A

I TEXAS INSTRUMENTS

12 Layout

12.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520 and the

UCC21520A. Below are some key points.

Component Placement:

• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the

source of the top transistor and the source of the bottom transistor must be minimized.

• It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of

the UCC21520 or the UCC21520A.

• It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to

a µC with distance.

Grounding Considerations:

• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor

is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB

traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination

that may compromise the UCC21520’s and the UCC21520A’s isolation performance.

• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could

operate with a DC-link voltage up to 1500 VDC, one should try to increase the creepage distance of the PCB

layout between the high and low-side PCB traces.

Thermal Considerations:

• A large amount of power may be dissipated by the UCC21520 or the UCC21520A if the driving voltage is

high, the load is heavy, or the switching frequency is high (refer to Section 10.2.2.5 for more details). Proper

PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal

impedance (θJB).

• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority

on maximizing the connection to VSSA and VSSB (see Figure 12-2 and Figure 12-3). However, high voltage

PCB considerations mentioned above must be maintained.

• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind

that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

www.ti.com

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021

Product Folder Links: UCC21520 UCC21520A

I TEXAS INSTRUMENTS Input Filters FOB Cutout (Top Layer) FWM Inputs (Top Layer) VCCI Caps. (Top Layer) GND plane (Bot. La er) VDD Caps. ‘ W (Bot. Layer) Bootstrap Dlode L Layer) Transistor 0 Low Side Transistor .11.. Tr 2'»!

12.2 Layout Example

Figure 12-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 12-1. Layout Example

Figure 12-2 and Figure 12-3 shows top and bottom layer traces and copper.

Note

There are no PCB traces or copper between the primary and secondary side, which ensures isolation

performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 12-2. Top Layer Traces and Copper Figure 12-3. Bottom Layer Traces and Copper

Figure 12-4 and Figure 12-5 are 3D layout pictures with top view and bottom views.

Note

The location of the PCB cutout between the primary side and secondary sides, which ensures

isolation performance.

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021 www.ti.com

Product Folder Links: UCC21520 UCC21520A

l TEXAS INSTRUMENTS :01 n ﬂQ_Lﬁ .,[:::02 D U R_LB £13213

Figure 12-4. 3-D PCB Top View Figure 12-5. 3-D PCB Bottom View

www.ti.com

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021

Product Folder Links: UCC21520 UCC21520A

l TEXAS INSTRUMENTS

13 Device and Documentation Support

13.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

•Semiconductor and IC Package Thermal Metrics Application Report

•Isolation Glossary

13.3 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate

Number: 20160516-E181974,

VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance

CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate

Number:CQC16001155011

CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master

Contract Number:220991

13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.6 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021 www.ti.com

Product Folder Links: UCC21520 UCC21520A

TEXAS INSTRUMENTS Samples Sample: Sample: Samples

PACKAGE OPTION ADDENDUM

www.ti.com 21-Oct-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC21520ADW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520A

UCC21520ADWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520A

UCC21520DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520

UCC21520DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 UCC21520

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 21-Oct-2021

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC21520 :

•Automotive : UCC21520-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS ‘3‘ V.'

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jun-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC21520ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

UCC21520DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC21520ADWR SOIC DW 16 2000 356.0 356.0 35.0

UCC21520DWR SOIC DW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jun-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

UCC21520ADW DW SOIC 16 40 507 12.83 5080 6.6

UCC21520ADW DW SOIC 16 40 506.98 12.7 4826 6.6

UCC21520DW DW SOIC 16 40 507 12.83 5080 6.6

UCC21520DW DW SOIC 16 40 506.98 12.7 4826 6.6

Pack Materials-Page 3

www.ti.com

GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

SOIC - 2.65 mm max heightDW 16

SMALL OUTLINE INTEGRATED CIRCUIT

7.5 x 10.3, 1.27 mm pitch

4224780/A

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

NOTE 4

7.6

7.4

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

v¢\‘\‘\

www.ti.com

EXAMPLE BOARD LAYOUT

(9.75)

R0.05 TYP

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

16X (2)

16X (0.6)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

SYMM

SEE

DETAILS

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SEE

DETAILS

vm““‘+\‘\‘ maimémmﬁ A ﬁg % $ E A

www.ti.com

EXAMPLE STENCIL DESIGN

R0.05 TYP

16X (1.65)

16X (0.6)

14X (1.27)

(9.75)

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4221009/B 07/2016

SOIC - 2.65 mm max heightDW0016B

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

SYMM

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC21520 Datasheet by Texas Instruments

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