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STM32F412xE, STM32F412xG Datasheet by STMicroelectronics
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This is information on a product in full production.
December 2017 DocID028087 Rev 7 1/201
STM32F412xE STM32F412xG
Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash,
256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
Datasheet - production data
Features
•Dynamic Efficiency Line with BAM (Batch
Acquisition Mode)
•Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit,
125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
•Memories
– Up to 1 Mbyte of Flash memory
– 256 Kbyte of SRAM
– Flexible external static memory controller
with up to 16-bit data bus: SRAM, PSRAM,
NOR Flash memory
– Dual mode Quad-SPI interface
•LCD parallel interface, 8080/6800 modes
•Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
•Power consumption
– Run: 112 µA/MHz (peripheral off)
– Stop (Flash in Stop mode, fast wakeup
time): 50 µA Typ @ 25 °C; 75 µA max
@25 °C
– Stop (Flash in Deep power down mode,
slow wakeup time): down to 18 µA @
25 °C; 40 µA max @25 °C
– Standby: 2.4 µA @25 °C / 1.7 V without
RTC; 12 µA @85 °C @1.7 V
–V
BAT supply for RTC: 1 µA @25 °C
•1×12-bit, 2.4 MSPS ADC: up to 16 channels
•2x digital filters for sigma delta modulator,
4x PDM interfaces, stereo microphone support
•General-purpose DMA: 16-stream DMA
•Up to 17 timers: up to twelve 16-bit timers, two
32-bit timers up to 100 MHz each with up to
four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input, two
watchdog timers (independent and window),
one SysTick timer
•Debug mode
– Serial wire debug (SWD) & JTAG
–Cortex
-M4 Embedded Trace Macrocell™
•Up to 114 I/O ports with interrupt capability
– Up to 109 fast I/Os up to 100 MHz
– Up to 114 five V-tolerant I/Os
•Up to 17 communication interfaces
–Up to 4x I
2C interfaces (SMBus/PMBus)
– Up to 4 USARTs (2 x 12.5 Mbit/s,
2 x 6.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
full-duplex I2S interfaces
– SDIO interface (SD/MMC/eMMC)
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with PHY
– 2x CAN (2.0B Active)
•True random number generator
•CRC calculation unit
•96-bit unique ID
•RTC: subsecond accuracy, hardware calendar
•All packages are ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F412xE STM32F412CE, STM32F412RE, STM32F412VE,
STM32F412ZE
STM32F412xG STM32F412CG, STM32F412RG, STM32F412VG,
STM32F412ZG
WLCSP64
)%*$
UFQFPN48
(7x7 mm)
UFBGA100
(7x7mm)
UFBGA144
(10x10mm)
(3.623x3.651mm) LQFP100 (14x14mm)
LQFP144 (20x20mm)
LQFP64 (10x10mm)
www.st.com
Contents STM32F412xE/G
2/201 DocID028087 Rev 7
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 19
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
3.3 Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
3.8 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.20 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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5
3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 37
3.26 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38
3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.31 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 WLSCP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5 LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7 UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.8 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Contents STM32F412xE/G
4/201 DocID028087 Rev 7
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 85
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 86
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 86
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 115
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 121
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.24 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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STM32F412xE/G Contents
5
6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 164
6.3.27 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.1 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 192
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 193
B.2 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
B.3 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
List of tables STM32F412xE/G
6/201 DocID028087 Rev 7
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F412xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9. STM32F412xE/G pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 10. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 11. STM32F412xE/G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 12. STM32F412xE/G register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 17. Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 18. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 19. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 85
Table 20. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 86
Table 21. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 22. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 23. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V. . . 90
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 91
Table 26. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 92
Table 27. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 93
Table 28. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 94
Table 29. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 95
Table 30. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 96
Table 31. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 97
Table 32. Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 97
Table 33. Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 97
Table 34. Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 98
Table 35. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 98
Table 36. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 37. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 38. Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 39. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 40. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 41. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DocID028087 Rev 7 7/201
STM32F412xE/G List of tables
8
Table 42. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 43. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 45. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 46. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 47. SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 48. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 49. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 50. Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 51. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 52. EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 53. EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 54. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 55. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 56. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 57. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 58. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 59. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 60. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 61. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 62. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 63. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 64. FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 65. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 66. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 67. QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 68. QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 69. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 70. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 71. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 72. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 73. ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 74. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 75. ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 143
Table 78. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 80. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 81. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 82. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 83. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 84. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 85. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 153
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 88. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 89. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 155
Table 90. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 157
List of tables STM32F412xE/G
8/201 DocID028087 Rev 7
Table 91. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 157
Table 92. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 93. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 94. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 95. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 96. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 97. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 166
Table 98. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 99. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 100. WLCSP64 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 169
Table 101. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 102. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 103. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 104. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 105. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 106. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 185
Table 107. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 108. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 188
Table 109. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 110. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 111. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DocID028087 Rev 7 9/201
STM32F412xE/G List of figures
11
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. STM32F412xE/G block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. STM32F412xE/G WLCSP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. STM32F412xE/G UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. STM32F412xE/G LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. STM32F412xE/G LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. STM32F412xE/G LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. STM32F412xE/G UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. STM32F412xE/G UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 20. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 24. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 25. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 26. Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 31. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 35. FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 38. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 39. FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 41. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 42. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 43. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 44. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
List of figures STM32F412xE/G
10/201 DocID028087 Rev 7
Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 140
Figure 46. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 47. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 146
Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 147
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 151
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 153
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 54. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 55. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 57. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 58. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 59. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 62. WLCSP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 64. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 65. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 173
Figure 67. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 68. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 177
Figure 70. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 71. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 180
Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 74. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 77. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 80. UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 81. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 193
Figure 82. USB peripheral-only Full speed mode with direct connection
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 194
Figure 84. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 194
Figure 85. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 195
Figure 86. Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DocID028087 Rev 7 13/201
STM32F412xE/G Description
42
2 Description
STM32F412XE/G devices are based on the high-performance Arm® Cortex® -M4 32-bit
RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
STM32F412XE/G devices belong to the STM32 Dynamic Efficiency™ product line (with
products combining power efficiency, performance and integration) while adding a new
innovative feature called Batch Acquisition Mode (BAM) allowing even more power
consumption saving during data batching.
STM32F412XE/G devices incorporate high-speed embedded memories (up to 1 Mbyte of
Flash memory, 256 Kbytes of SRAM), and an extensive range of enhanced I/Os and
peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus
matrix.
All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers,
two PWM timers for motor control and two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces:
•Up to four I2Cs, including one I2C supporting Fast-Mode Plus
•Five SPIs
•Five I2Ss of which two are full duplex. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL, or via an external clock
to allow synchronization.
•Four USARTs
•An SDIO/MMC interface
•A USB 2.0 OTG full-speed interface
•Two CANs.
In addition, STM32F412xE/G devices embed advanced peripherals:
•A flexible static memory controller interface (FSMC)
•A Quad-SPI memory interface
•A digital filter for sigma modulator (DFSDM), two filters, up to four inputs, and support
of microphone MEMs.
STM32F412xE/G devices are offered in 7 packages ranging from 48 to 144 pins. The set of
available peripherals depends on the selected package.
The STM32F412xE/G operates in the -40 to +125 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving modes allows the design
of low-power applications.
Description STM32F412xE/G
14/201 DocID028087 Rev 7
These features make the STM32F412xE/G microcontrollers suitable for a wide range of
applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
•Mobile phone sensor hub
•Wearable devices
•Connected objects
•Wifi modules
DocID028087 Rev 7 15/201
STM32F412xE/G Description
42
Table 2. STM32F412xE/G features and peripheral counts
Peripherals STM32F412xE STM32F412xG
Flash memory (Kbyte) 512 1024
SRAM
(Kbyte) System 256
FSMC memory
controller(1) -1-1
Quad-SPI memory
interface -1-1
Timers
General-
purpose 10
Advanced-
control 2
Basic 2
Random number generator 1
Comm.
interfaces
SPI/ I2S 5/5 (2 full duplex)
I2C3
I2CFMP 1
USART 4(2) 44
(2) 4
SDIO/MMC 1
USB/OTG FS
Dual power rail
1
No
1
Yes
1
No
1
Yes
CAN 2
Number of digital Filters for
Sigma-delta modulator
Number of channels
2
3
2
4
2
3
2
4
LCD parallel interface
Data bus size - 8 16 - 8 16
GPIOs 36 50 81 114 36 50 81 114
12-bit ADC
Number of channels
1
10 16 10 16
Maximum CPU frequency 100 MHz
Operating voltage 1.7 to 3.6 V
Operating temperatures
Ambient temperatures: -40 to +85 °C / -40 to +105 °C/ -40 to +125 °C
Junction temperature: -40 to +130 °C
Package UFQ
FPN48
LQFP64
WLCSP64
UFBGA
100
LQFP100
UFBGA
144
LQFP144
UFQ
FPN48
LQFP64
WLCSP
64
UFBGA
100
LQFP100
UFBGA
144
LQFP144
1. The FSMC can also be used to interface most graphic LCD controllers.
2. Limited application for the USART3 since RX is not available for the UFQFPN48.
Description STM32F412xE/G
16/201 DocID028087 Rev 7
2.1 Compatibility with STM32F4 series
The STM32F412xE/G are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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STM32F412xE/G Description
42
Figure 2. Compatible board design for LQFP64 package
Figure 3. Compatible board design for LQFP144 package
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18/201 DocID028087 Rev 7
Figure 4. STM32F412xE/G block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
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DocID028087 Rev 7 19/201
STM32F412xE/G Functional overview
42
3 Functional overview
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The Arm Cortex-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm Cortex-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F412xE/G devices are compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F412xE/G.
Note: Cortex-M4 with FPU is binary compatible with Cortex-M3.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex-M4 with FPU processors. It balances the inherent performance
advantage of the Arm Cortex-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3 Batch Acquisition mode (BAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (flash and ART™ stopped) with the DMA using BAM followed by
some very short processing from flash allows to drastically reduce the power consumption
of the application. A dedicated application note (AN4515) describes how to implement the
STM32F412xE/G BAM to allow the best power efficiency.
Functional overview STM32F412xE/G
20/201 DocID028087 Rev 7
3.4 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5 Embedded Flash memory
The devices embed up to 1 Mbyte of Flash memory available for storing programs and data.
The Flash user area can be protected against reading by an entrusted code (Read
Protection, RDP) with different protection levels.
The flash user sectors can also be individually protected against write operation.
Furthermore the proprietary readout protection (PCROP) can also individually protect the
flash user sectors against D-bus read accesses.
(Additional information can be found in the product reference manual).
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.21: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6 One-time programmable bytes
A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can
be individually locked
(Additional information can be found in the product reference manual)
3.7 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
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STM32F412xE/G Functional overview
42
3.8 Embedded SRAM
All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states
3.9 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
3.10 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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22/201 DocID028087 Rev 7
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C and I2CFMP
•USART
•General-purpose, basic and advanced-control timers TIMx
•SD/SDIO/MMC/eMMC host interface
•Quad-SPI
•ADC
•Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter.
3.11 Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
•8-,16-bit data bus width
•Write FIFO
•Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.12 Quad-SPI memory interface (QUAD-SPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
DocID028087 Rev 7 23/201
STM32F412xE/G Functional overview
42
3.13 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the
Cortex-M4 with FPU.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.14 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.15 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
Functional overview STM32F412xE/G
24/201 DocID028087 Rev 7
3.16 Boot modes
At startup, boot pins are used to select one out of three boot options:
•Boot from user Flash memory
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.17 Power supply schemes
•VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
Note: The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.18.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
Table 3. Embedded bootloader interfaces
Package
USART1
PA9/
PA10
USART2
PD6/
PD5
USART3
PB11/
PB10
I2C1
PB6/
PB7
I2C2
PF0/
PF1
I2C3
PA8/
PB4
I2C
FMP1
PB14/
PB15
SPI1
PA4/
PA5/
PA6/
PA7
SPI3
PA15/
PC10/
PC11/
PC12
SPI4
PE11/
PE12/
PE13/
PE14
CAN2
PB5/
PB13
USB
PA11
/P12
UFQFPN48 Y - - Y - Y Y Y - - Y Y
WLCSP64 Y - - Y - Y Y Y Y - Y Y
LQFP64 Y - - Y - Y Y Y Y - Y Y
LQFP100Y Y - Y-YYYYYYY
LQFP144YYYYYYYYYYYY
UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y
UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y
DDUSB
DocID028087 Rev 7 25/201
STM32F412xE/G Functional overview
42
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
The following conditions VDDUSB must be respected:
– During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
– During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDUSB rising and falling time rate specifications must be respected.
– In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB is used, the associated GPIOs powered by VDDUSB are operating
between VDDUSB_MIN and VDDUSB_MAX.
– If USB is not used, the associated GPIOs powered by VDDUSB are operating
between VDD_MIN and VDD_MAX.
Figure 6. VDDUSB connected to an external independent power supply
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26/201 DocID028087 Rev 7
3.18 Power supply supervisor
3.18.1 Internal reset ON
This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.18.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should set the device in reset
mode when VDD is below 1.7 V. NRST should be connected to this external power supply
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
[J—
DocID028087 Rev 7 27/201
STM32F412xE/G Functional overview
42
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•The brownout reset (BOR) circuitry must be disabled.
•The embedded programmable voltage detector (PVD) is disabled.
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
3.19 Voltage regulator
The regulator has three operating modes:
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
3.19.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. The WLCSP64 is available in two versions, one with the regulator
internally enabled and one with the regulator internally disabled. On all other packages, the
regulator is always enabled.
Figure 7. Power supply supervisor interconnection with internal reset OFF(1)
1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages.
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Functional overview STM32F412xE/G
28/201 DocID028087 Rev 7
There are three power modes configured by software when the regulator is ON:
•MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
•Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the 100 pins and 144 pins
packages.
All packages have the regulator ON feature.
3.19.2 Regulator OFF
The regulator is disabled by holding BYPASS_REG pin high.
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The WLCSP64 is available in two versions, one with a fixed enabled
regulator and one with a fixed disabled regulator (see Table 4: Regulator ON/OFF and
internal power supply supervisor availability and Section 8: Part numbering). The regulator
OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
DocID028087 Rev 7 29/201
STM32F412xE/G Functional overview
42
Figure 8. Regulator OFF
The following conditions must be respected:
•VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
•Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
•If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
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Functional overview STM32F412xE/G
30/201 DocID028087 Rev 7
Figure 9. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
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STM32F412xE/G Functional overview
42
3.19.3 Regulator ON/OFF and internal reset ON/OFF availability
3.20 Real-time clock (RTC) and backup registers
The backup domain includes:
•The real-time clock (RTC)
•20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 byte of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
Table 4. Regulator ON/OFF and internal power supply supervisor availability
Package Regulator ON Regulator OFF Power supply
supervisor ON
Power supply
supervisor OFF
UFQFPN48 Yes No Yes No
WLCSP64 Yes No Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
WLCSP64
option P(1) No Yes Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
LQFP64 Yes No Yes No
LQFP100 Yes No Yes No
LQFP144 Yes No
Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
UFBGA100
Yes
BYPASS_REG set to
VSS
Yes
BYPASS_REG set to
VDD
UFBGA144
Yes
BYPASS_REG set to
VSS
Yes
BYPASS_REG set to
VDD
1. Refer to Section 8: Part numbering.
Functional overview STM32F412xE/G
32/201 DocID028087 Rev 7
or when the device wakes up from the Standby mode (see Section 3.21: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
VDD supply when present or from the VBAT pin.
3.21 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
To further reduce the power consumption, the Flash memory can be switched off
before entering in Sleep mode. Note that this requires a code execution from the RAM.
•Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
•Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp
event occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.22 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC and the backup registers.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal
DocID028087 Rev 7 33/201
STM32F412xE/G Functional overview
42
Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected
to VDD.
3.23 Timers and watchdogs
The devices embed two advanced-control timer, ten general-purpose timers, two basic
timers, two watchdog timers and one SysTick timer.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control and general-purpose timers.
Functional overview STM32F412xE/G
34/201 DocID028087 Rev 7
Table 5. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complemen-
tary output
Max.
interface
clock
(MHz)
Max.
timer
clock
(MHz)
Advance
d-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 100 10 0
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 50 100
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 50 100
TIM9 16-bit Up
Any
integer
between 1
and
65536
No 2 No 100 100
TIM10,
TIM11 16-bit Up
Any
integer
between 1
and
65536
No 1 No 100 100
TIM12 16-bit Up
Any
integer
between 1
and
65536
No 2 No 50 100
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and
65536
No 1 No 50 100
Basic
timers
TIM6,
TIM7 16-bit Up
Any
integer
between 1
and
65536
Yes 0 No 50 100
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STM32F412xE/G Functional overview
42
3.23.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator
multiplexed on 4 independent channels. They have complementary PWM outputs with
programmable inserted dead times. They can also be considered as complete general-
purpose timers. Their 4 independent channels can be used for:
•Input capture
•Output compare
•PWM generation (edge- or center-aligned modes)
•One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability
(0-100%).
The advanced-control timers can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.23.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F412xE/G
(see Table 5 for differences).
•TIM2, TIM3, TIM4, TIM5
The STM32F412xE/G devices include 4 full-featured general-purpose timers: TIM2.
TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs
TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in
conjunction with the other general-purpose timers and TIM1 advanced-control timer via
the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM output.
TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 4 hall-effect sensors.
•TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and
TIM12 have two independent channels for input capture/output compare, PWM or one-
pulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 full-
featured general-purpose timers or used as simple time bases.
3.23.3 Basic timer (TIM6, TIM7)
TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request
generation.
Functional overview STM32F412xE/G
36/201 DocID028087 Rev 7
3.23.4 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.23.5 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.23.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•A 24-bit downcounter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0
•Programmable clock source.
3.24 Inter-integrated circuit interface (I2C)
The devices feature up to four I2C bus interfaces which can operate in multimaster and
slave modes:
•One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to
400 kHz) modes and Fast-mode plus (up to 1 MHz).
•Three I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode
(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on
the complete solution, refer to the nearest STMicroelectronics sales office.
All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave)
and embed a hardware CRC generation/verification.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 6).
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks
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STM32F412xE/G Functional overview
42
3.25 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6).
These four interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. USART1 and USART6 interfaces are able to
communicate at speeds of up to 12.5 Mbit/s. USART2 and USART3 interfaces
communicate at up to 6.25 bit/s.
All USART interfaces provide hardware management of the CTS and RTS signals, Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can
be served by the DMA controller.
3.26 Serial peripheral interface (SPI)
The devices feature five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and
SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interfaces can be configured to operate in TI mode for communications in master
mode and slave mode.
Table 7. USART feature comparison
USART
name
Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud
rate in Mbit/s
(oversampling
by 16)
Max. baud
rate in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 6.25 12.5
APB2
(max.
100 MHz)
USART2 X X X X X X 3.12 6.25
APB1
(max.
50 MHz)
USART3
(1) X X X X X X 3.12 6.25
APB1
(max.
50 MHz)
USART6 X X X X X X 6.25 12.5
APB2
(max.
100 MHz)
1. The RX is not available for the UFQFPN48 package.
Functional overview STM32F412xE/G
38/201 DocID028087 Rev 7
3.27 Inter-integrated sound (I2S)
Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be
operated in master or slave mode, in simplex communication mode, and full duplex mode
for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution
as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz
are supported. When either or both of the I2S interfaces is/are configured in master mode,
the master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency.
All I2Sx interfaces can be served by the DMA controller.
3.28 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S applications. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
Different sources can be selected for the I2S master clock of the APB1 and the I2S master
clock of the APB2. This gives the flexibility to work with two different audio sampling
frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI
clocks or an external clock provided through a pin (external PLL or Codec output)
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
3.29 Digital filter for sigma-delta modulators (DFSDM)
The device embeds one DFSDM with 2 digital filters modules and 4 external input serial
channels (transceivers) or alternately 2 internal parallel inputs support.
The amount of filters defines the number of conversions which can be performed
simultaneously.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from microcontrollers
memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
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STM32F412xE/G Functional overview
42
The DFSDM peripheral supports:
•4 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0...20 MHz
•alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: device memory data streams (DMA)
•2 digital filter modules with adjustable digital signal processing:
–Sinc
x filter: filter order/type (1...5), oversampling ratio (up to 1...1024)
– integrator: oversampling ratio (1...256)
•up to 24-bit output data resolution, signed output data format
•automatic data offset correction (offset stored in register by user)
•continuous or single conversion
•start-of-conversion triggered by
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM1FLT0)
•analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1...3, oversampling ratio = 1...32
– input from digital output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
•short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1...256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
•break signal generation on analog watchdog event or on short circuit detector event
•extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
•DMA capability to read the final conversion data
•interrupts: end of conversion, overrun, analog watchdog, short circuit input serial
channel clock absence
•“regulator” or injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority.
Functional overview STM32F412xE/G
40/201 DocID028087 Rev 7
3.30 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.31 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 byte of SRAM are allocated for each CAN.
3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection
(BCD) can detect and identify the type of port, it is connected to (standard USB or charger).
The type of charging is also detected: Dedicated Charging Port (DCP), Charging
Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a
dedicated USB power rail allowing a different supply for the USB and for the rest of the chip.
For instance the chip can be powered with the minimum specified supply and the USB
running at the level defined by the standard. The major features are:
•Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•6 bidirectional endpoints
•12 host channels with periodic OUT support
•HNP/SNP/IP inside (no need for any external resistor)
•For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
•Link Power Management (LPM)
•Battery Charging Detection (BCD) supporting DCP, CDP and SDP
DocID028087 Rev 7 41/201
STM32F412xE/G Functional overview
42
3.33 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.34 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz.
3.35 Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.36 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN18 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.37 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
Functional overview STM32F412xE/G
42/201 DocID028087 Rev 7
3.38 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F412xE/G through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID028087 Rev 7 43/201
STM32F412xE/G Pinouts and pin description
73
4 Pinouts and pin description
4.1 WLSCP64 pinout description
Figure 11. STM32F412xE/G WLCSP64 pinout
1. The above figure shows the package bump side.
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Pinouts and pin description STM32F412xE/G
44/201 DocID028087 Rev 7
4.2 UFQFPN48 pinout description
Figure 12. STM32F412xE/G UFQFPN48 pinout
1. The above figure shows the package top view.
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DocID028087 Rev 7 45/201
STM32F412xE/G Pinouts and pin description
73
4.3 LQFP64 pinout description
Figure 13. STM32F412xE/G LQFP64 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F412xE/G
46/201 DocID028087 Rev 7
4.4 LQFP100 pinout description
Figure 14. STM32F412xE/G LQFP100 pinout
1. The above figure shows the package top view.
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DocID028087 Rev 7 47/201
STM32F412xE/G Pinouts and pin description
73
4.5 LQFP144 pinout description
Figure 15. STM32F412xE/G LQFP144 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F412xE/G
48/201 DocID028087 Rev 7
4.6 UFBGA100 pinout description
Figure 16. STM32F412xE/G UFBGA100 pinout
1. The above figure shows the package top view.
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DocID028087 Rev 7 49/201
STM32F412xE/G Pinouts and pin description
73
4.7 UFBGA144 pinout description
Figure 17. STM32F412xE/G UFBGA144 pinout
1. The above figure shows the package top view.
4.8 Pin definition
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Table 8. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input/ output pin
I/O structure
FT 5 V tolerant I/O
TC Standard 3.3 V I/O
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Pinouts and pin description STM32F412xE/G
50/201 DocID028087 Rev 7
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Table 8. Legend/abbreviations used in the pinout table (continued)
Name Abbreviation Definition
Table 9. STM32F412xE/G pin definition
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
---1B2A31 PE2 I/O FT -
TRACECLK,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
QUADSPI_BK1_IO2,
FSMC_A23,
EVENTOUT
-
---2A1A22 PE3 I/O FT - TRACED0, FSMC_A19,
EVENTOUT -
---3B1B23 PE4 I/O FT -
TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN3,
FSMC_A20,
EVENTOUT
-
---4C2B34 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO,
SPI5_MISO,
DFSDM1_CKIN3,
FSMC_A21,
EVENTOUT
-
---5D2B45 PE6 I/O FT -
TRACED3, TIM9_CH2,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
FSMC_A22,
EVENTOUT
-
1 1 B7 6 E2 C2 6 VBAT S - - - VBAT
2 2 B8 7 C1 A1 7 PC13 I/O FT (2)(3) EVENTOUT TAMP_1
33C88 D1 B1 8 PC14-
OSC32_IN I/O FT (2)(3)(4) EVENTOUT OSC32_IN
DocID028087 Rev 7 51/201
STM32F412xE/G Pinouts and pin description
73
44C79 E1 C1 9
PC15-
OSC32_
OUT
I/O FT (2)(4) EVENTOUT OSC32_
OUT
---- - C310 PF0 I/O FT - I2C2_SDA, FSMC_A0,
EVENTOUT -
---- - C411 PF1 I/O FT - I2C2_SCL, FSMC_A1,
EVENTOUT -
---- - D412 PF2 I/O FT - I2C2_SMBA, FSMC_A2,
EVENTOUT -
- - - - - E2 13 PF3 I/O FT - TIM5_CH1, FSMC_A3,
EVENTOUT -
- - - - - E3 14 PF4 I/O FT - TIM5_CH2, FSMC_A4,
EVENTOUT -
- - - - - E4 15 PF5 I/O FT - TIM5_CH3, FSMC_A5,
EVENTOUT -
- - - 10 F2 D2 16 VSS S - - - -
---11G2D317 VDD S - - - -
- - - - - F3 18 PF6 I/O FT -
TRACED0, TIM10_CH1,
QUADSPI_BK1_IO3,
EVENTOUT
-
- - - - - F2 19 PF7 I/O FT -
TRACED1, TIM11_CH1,
QUADSPI_BK1_IO2,
EVENTOUT
-
---- - G320 PF8 I/O FT -
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
-
---- - G221 PF9 I/O FT -
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
- - - - - G1 22 PF10 I/O FT - TIM1_ETR, TIM5_CH4,
EVENTOUT -
5 5 D8 12 F1 D1 23 PH0 -
OSC_IN I/O FT (4) EVENTOUT OSC_IN
6 6 E8 13 G1 E1 24 PH1 -
OSC_OUT I/O FT (4) EVENTOUT OSC_OUT
7 7 D7 14 H2 F1 25 NRST I/O RST - - NRST
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
52/201 DocID028087 Rev 7
- 8 D5 15 H1 H1 26 PC0 I/O FT - EVENTOUT ADC1_10,
WKUP2
- 9 F8 16 J2 H2 27 PC1 I/O FT - EVENTOUT ADC1_11,
WKUP3
-10E717 J3 H328 PC2 I/O FT -
SPI2_MISO,
I2S2ext_SD,
DFSDM1_CKOUT,
FSMC_NWE,
EVENTOUT
ADC1_12
-11D618K2 H429 PC3 I/O FT - SPI2_MOSI/I2S2_SD,
FSMC_A0, EVENTOUT ADC1_13
- - - 19 - - 30 VDD S - - - -
812G820 - - 31 VSSA/
VREF S- - - -
- - - - J1 J1 - VSSA S - - - -
----K1K1- VREF- S - - - -
913F7 - - - - VDDA/
VREF+ S- - - -
- - - 21 L1 L1 32 VREF+ S - - - -
- - - 22 M1 M1 33 VDDA S - - - -
10 14 E6 23 L2 J2 34 PA0 I/O FT -
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
EVENTOUT
ADC1_0,
WKUP1
11 15 G7 24 M2 K2 35 PA1 I/O FT -
TIM2_CH2, TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
QUADSPI_BK1_IO3,
EVENTOUT
ADC1_1
12 16 H8 25 K3 L2 36 PA2 I/O FT -
TIM2_CH3, TIM5_CH3,
TIM9_CH1, I2S2_CKIN,
USART2_TX,
FSMC_D4/FSMC_DA4,
EVENTOUT
ADC1_2
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 53/201
STM32F412xE/G Pinouts and pin description
73
13 17 F6 26 L3 M2 37 PA3 I/O FT -
TIM2_CH4, TIM5_CH4,
TIM9_CH2, I2S2_MCK,
USART2_RX,
FSMC_D5/FSMC_DA5,
EVENTOUT
ADC1_3
- 18 - 27 - G4 38 VSS S - - - -
----E3H5-
BYPASS_
REG IFT - - -
-19H728 - F4 39 VDD S - - - -
14 20 G6 29 M3 J3 40 PA4 I/O FT -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
DFSDM1_DATIN1,
FSMC_D6/FSMC_DA6,
EVENTOUT
ADC1_4
15 21 F5 30 K4 K3 41 PA5 I/O FT -
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
DFSDM1_CKIN1,
FSMC_D7/FSMC_DA7,
EVENTOUT
ADC1_5
16 22 H6 31 L4 L3 42 PA6 I/O FT -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO, I2S2_MCK,
TIM13_CH1,
QUADSPI_BK2_IO0,
SDIO_CMD,
EVENTOUT
ADC1_6
17 23 E5 32 M4 M3 43 PA7 I/O FT -
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
QUADSPI_BK2_IO1,
EVENTOUT
ADC1_7
-24E433K5 J4 44 PC4 I/O FT -
I2S1_MCK,
QUADSPI_BK2_IO2,
FSMC_NE4,
EVENTOUT
ADC1_14
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
54/201 DocID028087 Rev 7
-25G534L5 K445 PC5 I/O FT -
I2CFMP1_SMBA,
USART3_RX,
QUADSPI_BK2_IO3,
FSMC_NOE,
EVENTOUT
ADC1_15
18 26 H5 35 M5 L4 46 PB0 I/O FT -
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI5_SCK/I2S5_CK,
EVENTOUT
ADC1_8
19 27 F4 36 M6 M4 47 PB1 I/O FT -
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN0,
QUADSPI_CLK,
EVENTOUT
ADC1_9
20 28 G4 37 L6 J5 48 PB2 I/O FT -
DFSDM1_CKIN0,
QUADSPI_CLK,
EVENTOUT
BOOT1
- - - - - M5 49 PF11 I/O FT - TIM8_ETR, EVENTOUT -
- - - - - L5 50 PF12 I/O FT - TIM8_BKIN, FSMC_A6,
EVENTOUT -
---- - - 51 VSS S - - - -
---- - G552 VDD S - - - -
- - - - - K5 53 PF13 I/O FT - I2CFMP1_SMBA,
FSMC_A7, EVENTOUT -
---- - M654 PF14 I/O FT - I2CFMP1_SCL,
FSMC_A8, EVENTOUT -
- - - - - L6 55 PF15 I/O FT - I2CFMP1_SDA,
FSMC_A9, EVENTOUT -
- - - - - K6 56 PG0 I/O FT - CAN1_RX, FSMC_A10,
EVENTOUT -
---- - J657 PG1 I/O FT - CAN1_TX, FSMC_A11,
EVENTOUT -
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 55/201
STM32F412xE/G Pinouts and pin description
73
- - - 38 M7 M7 58 PE7 I/O FT -
TIM1_ETR,
DFSDM1_DATIN2,
QUADSPI_BK2_IO0,
FSMC_D4/FSMC_DA4,
EVENTOUT
-
- - - 39 L7 L7 59 PE8 I/O FT -
TIM1_CH1N,
DFSDM1_CKIN2,
QUADSPI_BK2_IO1,
FSMC_D5/FSMC_DA5,
EVENTOUT
-
- - - 40 M8 K7 60 PE9 I/O FT -
TIM1_CH1,
DFSDM1_CKOUT,
QUADSPI_BK2_IO2,
FSMC_D6/FSMC_DA6,
EVENTOUT
-
---- - - 61 VSS S - - - -
---- - G662 VDD S - - - -
- - - 41 L8 J7 63 PE10 I/O FT -
TIM1_CH2N,
QUADSPI_BK2_IO3,
FSMC_D7/FSMC_DA7,
EVENTOUT
-
- - - 42 M9 H8 64 PE11 I/O FT -
TIM1_CH2,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
FSMC_D8/FSMC_DA8,
EVENTOUT
-
- - - 43 L9 J8 65 PE12 I/O FT -
TIM1_CH3N,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
FSMC_D9/FSMC_DA9,
EVENTOUT
-
---44M10K866 PE13 I/O FT -
TIM1_CH3, SPI4_MISO,
SPI5_MISO,
FSMC_D10/FSMC_DA1
0, EVENTOUT
-
---45M11L867 PE14 I/O FT -
TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
FSMC_D11/FSMC_DA1
1, EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
56/201 DocID028087 Rev 7
---46M12M868 PE15 I/O FT -
TIM1_BKIN,
FSMC_D12/FSMC_DA1
2, EVENTOUT
-
21 29 H4 47 L10 M9 69 PB10 I/O FT -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
USART3_TX,
I2CFMP1_SCL,
SDIO_D7, EVENTOUT
-
- - - - K9 M10 70 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
I2S2_CKIN,
USART3_RX,
EVENTOUT
-
22 30 H3 48 L11 H7 71 VCAP_1 S - - - -
23 31 H2 49 F12 H6 - VSS S - - - -
24 32 H1 50 G12 G7 72 VDD S - - - -
25 33 G3 51 L12 M11 73 PB12 I/O FT -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
USART3_CK,
CAN2_RX,
DFSDM1_DATIN1,
FSMC_D13/FSMC_DA1
3, EVENTOUT
-
26 34 G2 52 K12 M12 74 PB13 I/O FT -
TIM1_CH1N,
I2CFMP1_SMBA,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
USART3_CTS,
CAN2_TX,
DFSDM1_CKIN1,
EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 57/201
STM32F412xE/G Pinouts and pin description
73
27 35 G1 53 K11 L11 75 PB14 I/O FT -
TIM1_CH2N,
TIM8_CH2N,
I2CFMP1_SDA,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
DFSDM1_DATIN2,
TIM12_CH1,
FSMC_D0/FSMC_DA0,
SDIO_D6, EVENTOUT
-
28 36 F2 54 K10 L12 76 PB15 I/O FT -
RTC_50Hz,
TIM1_CH3N,
TIM8_CH3N,
I2CFMP1_SCL,
SPI2_MOSI/I2S2_SD,
DFSDM1_CKIN2,
TIM12_CH2, SDIO_CK,
EVENTOUT
-
---55 - L977 PD8 I/O FT -
USART3_TX,
FSMC_D13/
FSMC_DA13,
EVENTOUT
-
- - - 56 K8 K9 78 PD9 I/O FT -
USART3_RX,
FSMC_D14/FSMC_DA1
4, EVENTOUT
-
---57J12J979 PD10 I/O FT -
USART3_CK,
FSMC_D15/FSMC_DA1
5, EVENTOUT
-
---58J11H980 PD11 I/O FT -
I2CFMP1_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
FSMC_A16,
EVENTOUT
-
- - - 59 J10 L10 81 PD12 I/O FT -
TIM4_CH1,
I2CFMP1_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
FSMC_A17,
EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
58/201 DocID028087 Rev 7
- - - 60 H12 K10 82 PD13 I/O FT -
TIM4_CH2,
I2CFMP1_SDA,
QUADSPI_BK1_IO3,
FSMC_A18,
EVENTOUT
-
---- - G883 VSS S - - - -
---- - F884 VDD S - - - -
- - - 61 H11 K11 85 PD14 I/O FT -
TIM4_CH3,
I2CFMP1_SCL,
FSMC_D0/FSMC_DA0,
EVENTOUT
-
- - - 62 H10 K12 86 PD15 I/O FT -
TIM4_CH4,
I2CFMP1_SDA,
FSMC_D1/FSMC_DA1,
EVENTOUT
-
---- - J1287 PG2 I/O FT - FSMC_A12,
EVENTOUT -
---- - J1188 PG3 I/O FT - FSMC_A13,
EVENTOUT -
---- - J1089 PG4 I/O FT - FSMC_A14,
EVENTOUT -
---- -H1290 PG5 I/O FT - FSMC_A15,
EVENTOUT -
---- - H1191 PG6 I/O FT - QUADSPI_BK1_NCS,
EVENTOUT -
---- -H1092 PG7 I/O FT - USART6_CK,
EVENTOUT -
- - - - - G11 93 PG8 I/O FT - USART6_RTS,
EVENTOUT -
---- - - 94 VSS S - - - -
---- - F10- VDD S -
- - - - - C11 95 VDDUSB S - - - -
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 59/201
STM32F412xE/G Pinouts and pin description
73
- 37F163E12G1296 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
I2CFMP1_SCL,
I2S2_MCK,
DFSDM1_CKIN3,
USART6_TX,
FSMC_D1/FSMC_DA1,
SDIO_D6, EVENTOUT
-
-38E164E11F1297 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
I2CFMP1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
USART6_RX,
DFSDM1_DATIN3,
SDIO_D7, EVENTOUT
-
-39F365E10F1198 PC8 I/O FT -
TIM3_CH3, TIM8_CH3,
USART6_CK,
QUADSPI_BK1_IO2,
SDIO_D0, EVENTOUT
-
-40E266D12E1199 PC9 I/O FT -
MCO_2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S2_CKIN,
QUADSPI_BK1_IO0,
SDIO_D1, EVENTOUT
-
29 41 E3 67 D11 E12 100 PA8 I/O FT -
MCO_1, TIM1_CH1,
I2C3_SCL,
USART1_CK,
USB_FS_SOF,
SDIO_D1, EVENTOUT
-
30 42 D1 68 D10 D12 101 PA9 I/O FT -
TIM1_CH2,
I2C3_SMBA,
USART1_TX,
USB_FS_VBUS,
SDIO_D2, EVENTOUT
-
31 43 D2 69 C12 D11 102 PA10 I/O FT -
TIM1_CH3,
SPI5_MOSI/I2S5_SD,
USART1_RX,
USB_FS_ID,
EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
60/201 DocID028087 Rev 7
32 44 D3 70 B12 C12 103 PA11 I/O FT -
TIM1_CH4, SPI4_MISO,
USART1_CTS,
USART6_TX,
CAN1_RX,
USB_FS_DM,
EVENTOUT
-
33 45 C1 71 A12 B12 104 PA12 I/O FT -
TIM1_ETR, SPI5_MISO,
USART1_RTS,
USART6_RX,
CAN1_TX,
USB_FS_DP,
EVENTOUT
-
34 46 C2 72 A11 A12 105 PA13 I/O FT - JTMS-SWDIO,
EVENTOUT -
- - - 73 C11 G9 106 VCAP_2 S - - - -
35 47 B1 74 F11 G10 107 VSS S - - - -
36 48 - 75 G11 - - VDD S - - - -
--A1- - F9108 VDD S - - - -
37 49 B2 76 A10 A11 109 PA14 I/O FT - JTCK-SWCLK,
EVENTOUT -
38 50 A2 77 A9 A10 110 PA15 I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART1_TX,
EVENTOUT
-
- 51 C3 78 B11 B11 111 PC10 I/O FT -
SPI3_SCK/I2S3_CK,
USART3_TX,
QUADSPI_BK1_IO1,
SDIO_D2, EVENTOUT
-
- 52 B3 79 C10 B10 112 PC11 I/O FT -
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
QUADSPI_BK2_NCS,
FSMC_D2/FSMC_DA2,
SDIO_D3, EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 61/201
STM32F412xE/G Pinouts and pin description
73
- 53 A3 80 B10 C10 113 PC12 I/O FT -
SPI3_MOSI/I2S3_SD,
USART3_CK,
FSMC_D3/FSMC_DA3,
SDIO_CK, EVENTOUT
-
- - - 81 C9 E10 114 PD0 I/O FT -
CAN1_RX,
FSMC_D2/FSMC_DA2,
EVENTOUT
-
- - - 82 B9 D10 115 PD1 I/O FT -
CAN1_TX,
FSMC_D3/FSMC_DA3,
EVENTOUT
-
-54A483C8 E9116 PD2 I/O FT -
TIM3_ETR,
FSMC_NWE,
SDIO_CMD,
EVENTOUT
-
- - - 84 B8 D9 117 PD3 I/O FT -
TRACED1,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
USART2_CTS,
QUADSPI_CLK,
FSMC_CLK,
EVENTOUT
-
- - - 85 B7 C9 118 PD4 I/O FT -
DFSDM1_CKIN0,
USART2_RTS,
FSMC_NOE,
EVENTOUT
-
- - - 86 A6 B9 119 PD5 I/O FT -
USART2_TX,
FSMC_NWE,
EVENTOUT
-
- - - - - E7 120 VSS S - - - -
---- - F7121 VDD S - - - -
- - - 87 B6 A8 122 PD6 I/O FT -
SPI3_MOSI/I2S3_SD,
DFSDM1_DATIN1,
USART2_RX,
FSMC_NWAIT,
EVENTOUT
-
- - - 88 A5 A9 123 PD7 I/O FT -
DFSDM1_CKIN1,
USART2_CK,
FSMC_NE1,
EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
62/201 DocID028087 Rev 7
---- - E8124 PG9 I/O FT -
USART6_RX,
QUADSPI_BK2_IO2,
FSMC_NE2,
EVENTOUT
-
---- - D8125PG10 I/O FT - FSMC_NE3,
EVENTOUT -
- - - - - C8 126 PG11 I/O FT - CAN2_RX, EVENTOUT -
---- - B8127PG12 I/O FT -
USART6_RTS,
CAN2_TX, FSMC_NE4,
EVENTOUT
-
---- - D7128PG13 I/O FT -
TRACED2,
USART6_CTS,
FSMC_A24,
EVENTOUT
-
---- - C7129PG14 I/O FT -
TRACED3,
USART6_TX,
QUADSPI_BK2_IO3,
FSMC_A25,
EVENTOUT
-
---- - -130 VSS S - - - -
---- - F6131 VDD S - - - -
---- - B7132PG15 I/O FT - USART6_CTS,
EVENTOUT -
39 55 A5 89 A8 A7 133 PB3 I/O FT -
JTDO-SWO,
TIM2_CH2,
I2CFMP1_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART1_RX,
I2C2_SDA, EVENTOUT
-
40 56 B4 90 A7 A6 134 PB4 I/O FT -
JTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD, I2C3_SDA,
SDIO_D0, EVENTOUT
-
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID028087 Rev 7 63/201
STM32F412xE/G Pinouts and pin description
73
41 57 C4 91 C5 B6 135 PB5 I/O FT -
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX, SDIO_D3,
EVENTOUT
-
42 58 B5 92 B5 C6 136 PB6 I/O FT -
TIM4_CH1, I2C1_SCL,
USART1_TX,
CAN2_TX,
QUADSPI_BK1_NCS,
SDIO_D0, EVENTOUT
-
43 59 A6 93 B4 D6 137 PB7 I/O FT -
TIM4_CH2, I2C1_SDA,
USART1_RX,
FSMC_NL, EVENTOUT
-
44 60 D4 94 A4 D5 138 BOOT0 I B - - VPP
45 61 C5 95 A3 C5 139 PB8 I/O FT -
TIM4_CH3,
TIM10_CH1, I2C1_SCL,
SPI5_MOSI/I2S5_SD,
CAN1_RX, I2C3_SDA,
SDIO_D4, EVENTOUT
-
46 62 B6 96 B3 B5 140 PB9 I/O FT -
TIM4_CH4,
TIM11_CH1, I2C1_SDA,
SPI2_NSS/I2S2_WS,
CAN1_TX, I2C2_SDA,
SDIO_D5, EVENTOUT
-
- - - 97 C3 A5 141 PE0 I/O FT -
TIM4_ETR,
FSMC_NBL0,
EVENTOUT
-
- - - 98 A2 A4 142 PE1 I/O FT - FSMC_NBL1,
EVENTOUT -
47 63 A7 99 D3 E6 - VSS S - - - -
- - C6 - H3 E5 143 PDR_ON I FT - - -
48 64 A8 100 C4 F5 144 VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP64
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F412xE/G
64/201 DocID028087 Rev 7
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F412xE/Greference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
Table 10. FSMC pin definition
Pins
FSMC
64 pins 100 pins 144 pins
LCD/NOR/PSR
AM/SRAM
NOR/PSRAM
Mux
PE2 A23 A23 - Yes Yes
PE3 A19 A19 - Yes Yes
PE4 A20 A20 - Yes Yes
PE5 A21 A21 - Yes Yes
PE6 A22 A22 - Yes Yes
PF0 A0 - - - Yes
PF1 A1 - - - Yes
PF2 A2 - - - Yes
PF3 A3 - - - Yes
PF4 A4 - - - Yes
PF5 A5 - - - Yes
PC2 NWE NWE Yes Yes Yes
PC3 A0 - Yes Yes Yes
PA2 D4 DA4 Yes Yes Yes
PA3 D5 DA5 Yes Yes Yes
PA4 D6 DA6 Yes Yes Yes
PA5 D7 DA7 Yes Yes Yes
PC4 NE4 NE4 Yes Yes Yes
PC5 NOE NOE Yes Yes Yes
PF12 A6 - - - Yes
PF13 A7 - - - Yes
PF14 A8 - - - Yes
PF15 A9 - - - Yes
PG0 A10 - - - Yes
PG1 A11 - - - Yes
PE7 D4 DA4 - Yes Yes
PE8 D5 DA5 - Yes Yes
PE9 D6 DA6 - Yes Yes
PE10 D7 DA7 - Yes Yes
DocID028087 Rev 7 65/201
STM32F412xE/G Pinouts and pin description
73
PE11 D8 DA8 - Yes Yes
PE12 D9 DA9 - Yes Yes
PE13 D10 DA10 - Yes Yes
PE14 D11 DA11 - Yes Yes
PE15 D12 DA12 - Yes Yes
PB12 D13 DA13 Yes Yes Yes
PB14 D0 DA0 Yes Yes Yes
PD8 D13 DA13 - - Yes
PD9 D14 DA14 - Yes Yes
PD10 D15 DA15 - Yes Yes
PD11 A16 A16 - Yes Yes
PD12 A17 A17 - Yes Yes
PD13 A18 A18 - Yes Yes
PD14 D0 DA0 - Yes Yes
PD15 D1 DA1 - Yes Yes
PG2 A12 - - - Yes
PG3 A13 - - - Yes
PG4 A14 - - - Yes
PG5 A15 - - - Yes
PC6 D1 DA1 Yes Yes Yes
PC11 D2 DA2 Yes Yes Yes
PC12 D3 DA3 Yes Yes Yes
PD0 D2 DA2 - Yes Yes
PD1 D3 DA3 - Yes Yes
PD2 NWE NWE Yes Yes Yes
PD3 CLK CLK - Yes Yes
PD4 NOE NOE - Yes Yes
PD5 NWE NEW - Yes Yes
PD6 NWAIT NWAIT - Yes Yes
PD7 NE1 NE1 - Yes Yes
PG9 NE2 NE2 - - Yes
PG10 NE3 NE3 - - Yes
PG12 A24 A24 - - Yes
Table 10. FSMC pin definition
Pins
FSMC
64 pins 100 pins 144 pins
LCD/NOR/PSR
AM/SRAM
NOR/PSRAM
Mux
STM32F412xE/G Pinouts and pin description
DocID028087 Rev 7 67/201
Table 11. STM32F412xE/G alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
Port A
PA0 - TIM2_CH1/
TIM2_ETR TIM5_CH1 TIM8_ETR - - - USART2_CTS - - - - EVENTOUT
PA1 - TIM2_CH2 TIM5_CH2 - - SPI4_MOSI/I
2S4_SD - USART2_RTS - QUADSPI_
BK1_IO3 - - EVENTOUT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - I2S2_CKIN - USART2_TX - - - FSMC_D4 EVENTOUT
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - I2S2_MCK - USART2_RX - - - FSMC_D5 EVENTOUT
PA4 - - - - - SPI1_NSS/I2
S1_WS
SPI3_NSS/
I2S3_WS USART2_CK DFSDM1_
DATIN1 - - FSMC_D6 EVENTOUT
PA5 - TIM2_CH1/
TIM2_ETR - TIM8_CH1N - SPI1_SCK/
I2S1_CK --
DFSDM1_
CKIN1 - - FSMC_D7 EVENTOUT
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO I2S2_MCK - - TIM13_
CH1
QUADSPI_
BK2_IO0 SDIO_CMD EVENTOUT
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I
2S1_SD ---
TIM14_
CH1
QUADSPI_
BK2_IO1 -EVENTOUT
PA8 MCO_1 TIM1_CH1 - - I2C3_SCL - - USART1_CK - - USB_FS_
SOF SDIO_D1 EVENTOUT
PA9 - TIM1_CH2 - - I2C3_
SMBA - - USART1_TX - - USB_FS_
VBUS SDIO_D2 EVENTOUT
PA10 - TIM1_CH3 - - - - SPI5_MOSI/
I2S5_SD USART1_RX - - USB_FS_ID - EVENTOUT
PA11 - TIM1_CH4 - - - - SPI4_MISO USART1_CTS USART6_
TX CAN1_RX USB_FS_DM - EVENTOUT
PA12 - TIM1_ETR - - - - SPI5_MISO USART1_RTS USART6_
RX CAN1_TX USB_FS_DP - EVENTOUT
PA13 JTMS-
SWDIO --- - - - - -- - -EVENTOUT
PA14 JTCK-
SWCLK --- - - - - -- - -EVENTOUT
PA15 JTDI TIM2_CH1/
TIM2_ETR -- -
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS USART1_TX - - - - EVENTOUT
Pinouts and pin description STM32F412xE/G
68/201 DocID028087 Rev 7
Port B
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - SPI5_SCK/
I2S5_CK --- - -EVENTOUT
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - SPI5_NSS/
I2S5_WS -DFSDM1_
DATIN0
QUADSPI_
CLK - - EVENTOUT
PB2 - - - - - - DFSDM1_
CKIN0 --
QUADSPI_
CLK - - EVENTOUT
PB3 JTDO-
SWO TIM2_CH2 I2CFMP1_
SDA
SPI1_SCK/I2
S1_CK
SPI3_SCK/
I2S3_CK USART1_RX - I2C2_SDA - - EVENTOUT
PB4 JTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO I2S3ext_
SD - I2C3_SDA - SDIO_D0 EVENTOUT
PB5 - - TIM3_CH2 - I2C1_SMBA SPI1_MOSI/I
2S1_SD
SPI3_MOSI/
I2S3_SD - - CAN2_RX - SDIO_D3 EVENTOUT
PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - CAN2_TX QUADSPI_
BK1_NCS SDIO_D0 EVENTOUT
PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - FSMC_NL EVENTOUT
PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - SPI5_MOSI/I2S
5_SD - CAN1_RX I2C3_SDA - SDIO_D4 EVENTOUT
PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/
I2S2_WS - - CAN1_TX I2C2_SDA - SDIO_D5 EVENTOUT
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK/
I2S2_CK I2S3_MCK USART3_TX - I2CFMP1_
SCL - SDIO_D7 EVENTOUT
PB11 - TIM2_CH4 - - I2C2_SDA I2S2_CKIN - USART3_RX - - - - EVENTOUT
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/
I2S2_WS
SPI4_NSS/
I2S4_WS
SPI3_SCK/
I2S3_CK
USART3_
CK CAN2_RX DFSDM1_
DATIN1
FSMC_D13/F
SMC_DA13 EVENTOUT
PB13 - TIM1_CH1N - - I2CFMP1_
SMBA
SPI2_SCK/
I2S2_CK
SPI4_SCK/
I2S4_CK -USART3_
CTS CAN2_TX DFSDM1_
CKIN1 -EVENTOUT
PB14 - TIM1_CH2N - TIM8_CH2N I2CFMP1_
SDA SPI2_MISO I2S2ext_SD USART3_
RTS
DFSDM1_
DATIN2 TIM12_CH1 FSMC_D0 SDIO_D6 EVENTOUT
PB15 RTC_
50Hz TIM1_CH3N - TIM8_CH3N I2CFMP1_
SCL
SPI2_MOSI/I
2S2_SD --
DFSDM1_
CKIN2 TIM12_CH2 - SDIO_CK EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
STM32F412xE/G Pinouts and pin description
DocID028087 Rev 7 69/201
Port C
PC0 - - - - - - - - - - - - EVENTOUT
PC1 - - - - - - - - - - - - EVENTOUT
PC2 - - - - - SPI2_MISO I2S2ext_SD - DFSDM1_
CKOUT - - FSMC_NWE EVENTOUT
PC3 - - - - - SPI2_MOSI/I
2S2_SD - - - - - FSMC_A0 EVENTOUT
PC4 - - - - - I2S1_MCK - - - - QUADSPI_
BK2_IO2 FSMC_NE4 EVENTOUT
PC5 - - - - I2CFMP1_
SMBA - - USART3_RX - - QUADSPI_
BK2_IO3 FSMC_NOE EVENTOUT
PC6 - - TIM3_CH1 TIM8_CH1 I2CFMP1_
SCL I2S2_MCK DFSDM1_
CKIN3 -USART6_
TX - FSMC_D1 SDIO_D6 EVENTOUT
PC7 - - TIM3_CH2 TIM8_CH2 I2CFMP1_
SDA
SPI2_SCK/
I2S2_CK I2S3_MCK - USART6_
RX -DFSDM1_
DATIN3 SDIO_D7 EVENTOUT
PC8 - - TIM3_CH3 TIM8_CH3 - - - - USART6_
CK
QUADSPI_
BK1_IO2 - SDIO_D0 EVENTOUT
PC9 MCO_2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN - - - QUADSPI_
BK1_IO0 - SDIO_D1 EVENTOUT
PC10 - - - - - - SPI3_SCK/
I2S3_CK USART3_TX - QUADSPI_
BK1_IO1 - SDIO_D2 EVENTOUT
PC11 - - - - - I2S3ext_SD SPI3_MISO USART3_RX - QUADSPI_
BK2_NCS FSMC_D2 SDIO_D3 EVENTOUT
PC12 - - - - - - SPI3_MOSI/
I2S3_SD USART3_CK - - FSMC_D3 SDIO_CK EVENTOUT
PC13 - - - - - - - - - - - - EVENTOUT
PC14 - - - - - - - - - - - - EVENTOUT
PC15 - - - - - - - - - - - - EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
Pinouts and pin description STM32F412xE/G
70/201 DocID028087 Rev 7
Port D
PD0 - - - - - - - - - CAN1_RX - FSMC_D2/FS
MC_DA2 EVENTOUT
PD1 - - - - - - - - - CAN1_TX - FSMC_D3/FS
MC_DA3 EVENTOUT
PD2 - - TIM3_ETR - - - - - - - FSMC_NWE SDIO_CMD EVENTOUT
PD3 TRACED1 - - - - SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN0
USART2_
CTS -QUADSPI_
CLK - FSMC_CLK EVENTOUT
PD4 - - - - - - DFSDM1_
CKIN0
USART2_
RTS - - - FSMC_NOE EVENTOUT
PD5 - - - - - - - USART2_TX - - - FSMC_NWE EVENTOUT
PD6 - - - - - SPI3_MOSI/I
2S3_SD
DFSDM1_
DATIN1 USART2_RX - - - FSMC_
NWAIT EVENTOUT
PD7 - - - - - - DFSDM1_
CKIN1 USART2_CK - - - FSMC_NE1 EVENTOUT
PD8 - - - - - - - USART3_TX - - - FSMC_D13/
FSMC_DA13 EVENTOUT
PD9 - - - - - - - USART3_RX - - - FSMC_D14/
FSMC_DA14 EVENTOUT
PD10 - - - - - - - USART3_CK - - - FSMC_D15/
FSMC_DA15 EVENTOUT
PD11 - - - - I2CFMP1_
SMBA --
USART3_
CTS -QUADSPI_
BK1_IO0 - FSMC_A16 EVENTOUT
PD12 - - TIM4_CH1 - I2CFMP1_
SCL
USART3_
RTS -QUADSPI_
BK1_IO1 - FSMC_A17 EVENTOUT
PD13 - - TIM4_CH2 - I2CFMP1_
SDA -- --
QUADSPI_
BK1_IO3 - FSMC_A18 EVENTOUT
PD14 - - TIM4_CH3 - I2CFMP1_
SCL -- ----
FSMC_D0/
FSMC_DA0 EVENTOUT
PD15 - - TIM4_CH4 - I2CFMP1_
SDA -- ----
FSMC_D1/
FSMC_DA1 EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
STM32F412xE/G Pinouts and pin description
DocID028087 Rev 7 71/201
Port E
PE0 - - TIM4_ETR - - - - - - - - FSMC_NBL0 EVENTOUT
PE1 - - - - - - - - - - - FSMC_NBL1 EVENTOUT
PE2 TRACECL
K--- -
SPI4_SCK/
I2S4_CK
SPI5_SCK/
I2S5_CK --
QUADSPI_
BK1_IO2 - FSMC_A23 EVENTOUT
PE3 TRACED0 - - - - - - - - - - FSMC_A19 EVENTOUT
PE4 TRACED1 - - - - SPI4_NSS/
I2S4_WS
SPI5_NSS/
I2S5_WS -DFSDM1_
DATIN3 - - FSMC_A20 EVENTOUT
PE5 TRACED2 - - TIM9_CH1 - SPI4_MISO SPI5_MISO - DFSDM1_
CKIN3 - - FSMC_A21 EVENTOUT
PE6 TRACED3 - - TIM9_CH2 - SPI4_MOSI/I
2S4_SD
SPI5_MOSI/
I2S5_SD - - - - FSMC_A22 EVENTOUT
PE7 - TIM1_ETR - - - - DFSDM1_
DATIN2 ---
QUADSPI_
BK2_IO0
FSMC_D4/
FSMC_DA4 EVENTOUT
PE8 - TIM1_CH1N - - - - DFSDM1_
CKIN2 ---
QUADSPI_
BK2_IO1
FSMC_D5/
FSMC_DA5 EVENTOUT
PE9 - TIM1_CH1 - - - - DFSDM1_
CKOUT ---
QUADSPI_
BK2_IO2
FSMC_D6/
FSMC_DA6 EVENTOUT
PE10 - TIM1_CH2N - - - - - - - - QUADSPI_
BK2_IO3
FSMC_D7/
FSMC_DA7 EVENTOUT
PE11 - TIM1_CH2 - - - SPI4_NSS/
I2S4_WS
SPI5_NSS/
I2S5_WS --- FSMC_D8/
FSMC_DA8 EVENTOUT
PE12 - TIM1_CH3N - - - SPI4_SCK/
I2S4_CK
SPI5_SCK/
I2S5_CK --- -
FSMC_D9/
FSMC_DA9 EVENTOUT
PE13 - TIM1_CH3 - - - SPI4_MISO SPI5_MISO - - - - FSMC_D10/
FSMC_DA10 EVENTOUT
PE14 - TIM1_CH4 - - - SPI4_MOSI/I
2S4_SD
SPI5_MOSI/
I2S5_SD --- -
FSMC_D11/
FSMC_DA11 EVENTOUT
PE15 - TIM1_BKIN - - - - - - - - - FSMC_D12/
FSMC_DA12 EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
Pinouts and pin description STM32F412xE/G
72/201 DocID028087 Rev 7
Port F
PF0 - - - - I2C2_SDA - - - - - - FSMC_A0 EVENTOUT
PF1 - - - - I2C2_SCL - - - - - - FSMC_A1 EVENTOUT
PF2 - - - - I2C2_SMBA - - - - - - FSMC_A2 EVENTOUT
PF3 - - TIM5_CH1 - - - - - - - - FSMC_A3 EVENTOUT
PF4 - - TIM5_CH2 - - - - - - - - FSMC_A4 EVENTOUT
PF5 - - TIM5_CH3 - - - - - - - - FSMC_A5 EVENTOUT
PF6 TRACED0 - - TIM10_CH1 - - - - - QUADSPI_
BK1_IO3 - - EVENTOUT
PF7 TRACED1 - - TIM11_CH1 - - - - - QUADSPI_
BK1_IO2 - - EVENTOUT
PF8 - - - - - - - - - TIM13_CH1 QUADSPI_
BK1_IO0 -EVENTOUT
PF9 - - - - - - - - - TIM14_CH1 QUADSPI_
BK1_IO1 -EVENTOUT
PF10 - TIM1_ETR TIM5_CH4 - - - - - - - - - EVENTOUT
PF11 - - - TIM8_ETR - - - - - - - - EVENTOUT
PF12 - - - TIM8_BKIN - - - - - - - FSMC_A6 EVENTOUT
PF13 - - - - I2CFMP1_
SMBA - - - - - - FSMC_A7 EVENTOUT
PF14 - - - - I2CFMP1_
SCL - - - - - - FSMC_A8 EVENTOUT
PF15 - - - - I2CFMP1_
SDA - - - - - - FSMC_A9 EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
STM32F412xE/G Pinouts and pin description
DocID028087 Rev 7 73/201
Port G
PG0 - - - - - - - - - CAN1_RX - FSMC_A10 EVENTOUT
PG1 - - - - - - - - - CAN1_TX - FSMC_A11 EVENTOUT
PG2 - - - - - - - - - - - FSMC_A12 EVENTOUT
PG3 - - - - - - - - - - - FSMC_A13 EVENTOUT
PG4 - - - - - - - - - - - FSMC_A14 EVENTOUT
PG5 - - - - - - - - - - - FSMC_A15 EVENTOUT
PG6 - - - - - - - - - - QUADSPI_
BK1_NCS -EVENTOUT
PG7 - - - - - - - - USART6_
CK ---EVENTOUT
PG8 - - - - - - - - USART6_
RTS ---EVENTOUT
PG9 - - - - - - - - USART6_
RX
QUADSPI_
BK2_IO2 - FSMC_NE2 EVENTOUT
PG10 - - - - - - - - - - - FSMC_NE3 EVENTOUT
PG11 - - - - - - - - - CAN2_RX - - EVENTOUT
PG12 - - - - - - - - USART6_
RTS CAN2_TX - FSMC_NE4 EVENTOUT
PG13 TRACED2 - - - - - - - USART6_
CTS - - FSMC_A24 EVENTOUT
PG14 TRACED3 - - - - - - - USART6_
TX
QUADSPI_
BK2_IO3 - FSMC_A25 EVENTOUT
PG15 - - - - - - - - USART6_
CTS ---EVENTOUT
Port H
PH0 - - - - - - - - - - - - EVENTOUT
PH1 - - - - - - - - - - - - EVENTOUT
Table 11. STM32F412xE/G alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
SYS_AF TIM1/
TIM2
TIM3/
TIM4/
TIM5
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/SPI3
/I2S3/SPI4/
I2S4/SPI5/I2S5
/DFSDM1
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/
USART6/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/CAN2
/TIM12/
TIM13/TIM14
/QUADSPI
DFSDM1/
QUADSPI/
FSMC
/OTG1_FS
FSMC /SDIO SYS_AF
Memory mapping STM32F412xE/G
74/201 DocID028087 Rev 7
5 Memory mapping
The memory map is shown in Figure 18.
Figure 18. Memory map
06Y9
0E\WH
EORFN
3HULSKHUDOV
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