STM32L431xx Datasheet by STMicroelectronics

Datasheet Feedback/Errors

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This is information on a product in full production.

May 2018 DS11453 Rev 3 1/208

STM32L431xx

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 256KB Flash, 64KB SRAM, analog, audio

Datasheet - production data

Features

•Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

– 200 nA in VBAT mode: supply for RTC and

32x32-bit backup registers

– 8 nA Shutdown mode (5 wakeup pins)

– 28 nA Standby mode (5 wakeup pins)

– 280 nA Standby mode with RTC

– 1.0 µA Stop 2 mode, 1.28 µA with RTC

– 84 µA/MHz run mode

– Batch acquisition mode (BAM)

– 4 µs wakeup from Stop mode

– Brown out reset (BOR)

– Interconnect matrix

•Core: Arm® 32-bit Cortex®-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait-state execution

from Flash memory, frequency up to 80 MHz,

MPU, 100DMIPS and DSP instructions

•Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

– 273.55 CoreMark® (3.42 CoreMark/MHz @

80 MHz)

•Energy benchmark

– 176.7 ULPBench® score

•Clock Sources

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator for RTC (LSE)

– Internal 16 MHz factory-trimmed RC (±1%)

– Internal low-power 32 kHz RC (±5%)

– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)

– Internal 48 MHz with clock recovery

– 2 PLLs for system clock, audio, ADC

•Up to 83 fast I/Os, most 5 V-tolerant

•RTC with HW calendar, alarms and calibration

•Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

•11x timers: 1x 16-bit advanced motor-control,

1x 32-bit and 2x 16-bit general purpose, 2x 16-

bit basic, 2x low-power 16-bit timers (available

in Stop mode), 2x watchdogs, SysTick timer

•Memories

– Up to 256 KB single bank Flash,

proprietary code readout protection

– 64 KB of SRAM including 16 KB with

hardware parity check

– Quad SPI memory interface

•Rich analog peripherals (independent supply)

– 1x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold

– 1x operational amplifier with built-in PGA

– 2x ultra-low-power comparators

•16x communication interfaces

– 1x SAI (serial audio interface)

–3x I2C FM+(1 Mbit/s), SMBus/PMBus

– 4x USARTs (ISO 7816, LIN, IrDA, modem)

– 1x LPUART (Stop 2 wake-up)

– 3x SPIs (and 1x Quad SPI)

– CAN (2.0B Active) and SDMMC interface

– SWPMI single wire protocol master I/F

– IRTIM (Infrared interface)

•14-channel DMA controller

•True random number generator

•CRC calculation unit, 96-bit unique ID

UFBGA100 (7×7)

LQFP64 (10x10)

UFBGA64 (5x5)

LQFP48 (7x7)

LQFP100 (14x14)

WLCSP64

UFQFPN32 (5x5)

WLCSP49UFQFPN48 (7x7)

www.st.com

STM32L431xx

2/208 DS11453 Rev 3

•Development support: serial wire debug

(SWD), JTAG, Embedded Trace Macrocell™

•All packages are ECOPACK2® compliant

Table 1. Device summary

Reference Part numbers

STM32L431xx STM32L431CC, STM32L431KC, STM32L431RC, STM32L431VC, STM32L431CB,

STM32L431KB, STM32L431RB

DS11453 Rev 3 3/208

STM32L431xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37

3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37

3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Contents STM32L431xx

4/208 DS11453 Rev 3

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.21 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.22.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.22.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 44

3.22.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.22.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 44

3.22.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.23 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 46

3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.25 Universal synchronous/asynchronous receiver transmitter (USART) . . . 48

3.26 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 49

3.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.28 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.29 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 51

3.30 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.31 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 52

3.32 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.33 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.34 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.34.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.34.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

DS11453 Rev 3 5/208

STM32L431xx Contents

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 89

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 89

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 137

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 138

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 151

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 156

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 164

Contents STM32L431xx

6/208 DS11453 Rev 3

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.5 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

7.6 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.7 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.8 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.9 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 204

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

DS11453 Rev 3 7/208

STM32L431xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L431xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18

Table 4. STM32L431xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6. STM32L431xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 12. STM32L431xx USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 15. STM32L431xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 16. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 17. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 18. STM32L431xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 81

Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 25. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 26. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 94

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 29. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 97

Table 30. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 31. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 32. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 99

Table 33. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 100

Table 34. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 35. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 36. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 37. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 38. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 39. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 40. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 42. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

List of tables STM32L431xx

8/208 DS11453 Rev 3

Table 43. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 44. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 45. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 46. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 47. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 48. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 49. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Table 50. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 51. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 52. PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 64. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 65. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 67. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 68. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 69. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 70. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 71. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 72. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 73. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 74. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 75. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 76. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 77. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 78. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 79. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 80. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 81. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 82. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 83. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 84. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 85. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 86. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 87. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 90. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 91. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 92. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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STM32L431xx List of tables

Table 93. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 181

Table 94. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 95. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 96. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 186

Table 97. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 98. WLCSP64 recommended PCB design rules (0.35 mm pitch) . . . . . . . . . . . . . . . . . . . . . 189

Table 99. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 100. WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193

Table 101. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 102. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 103. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 104. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 105. STM32L431xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 106. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

List of figures STM32L431xx

10/208 DS11453 Rev 3

List of figures

Figure 1. STM32L431xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 6. STM32L431Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 7. STM32L431Vx UFBGA100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 8. STM32L431Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 9. STM32L431Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 10. STM32L431Rx WLCSP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 11. STM32L431Cx WLCSP49 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 12. STM32L431Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13. STM32L431Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14. STM32L431Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 15. STM32L431xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 18. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 20. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 22. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 25. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 26. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 27. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 28. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 29. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 30. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 31. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 33. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 35. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 36. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 37. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 38. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 39. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 40. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 41. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 42. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 43. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 177

Figure 44. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 45. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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Figure 47. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 48. UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 183

Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 51. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 52. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 53. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 54. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 55. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 56. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 57. WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 58. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 59. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 60. WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 194

Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 63. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 64. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 65. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 66. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 67. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 68. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 69. UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 70. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

arm

Introduction STM32L431xx

12/208 DS11453 Rev 3

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L431xx microcontrollers.

This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx

reference manual (RM0394). The reference manual is available from the

STMicroelectronics website www.st.com.

For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical

Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11453 Rev 3 13/208

STM32L431xx Description

2 Description

The STM32L431xx devices are the ultra-low-power microcontrollers based on the high-

performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm® single-precision data-processing instructions and data types. It also implements a full

set of DSP instructions and a memory protection unit (MPU) which enhances application

security.

The STM32L431xx devices embed high-speed memories (Flash memory up to 256 Kbyte,

64 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and

an extensive range of enhanced I/Os and peripherals connected to two APB buses, two

AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L431xx devices embed several protection mechanisms for embedded Flash

memory and SRAM: readout protection, write protection, proprietary code readout

protection and Firewall.

The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,

two DAC channels, an internal voltage reference buffer, a low-power RTC, one general-

purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose

16-bit timers, and two 16-bit low-power timers.

In addition, up to 21 capacitive sensing channels are available.

They also feature standard and advanced communication interfaces.

•Three I2Cs

•Three SPIs

•Three USARTs and one Low-Power UART.

•One SAI (Serial Audio Interfaces)

•One SDMMC

•One CAN

•One SWPMI (Single Wire Protocol Master Interface)

The STM32L431xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C

(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-

power applications.

Some independent power supplies are supported: analog independent supply input for

ADC, DAC, OPAMP and comparators. A VBAT input allows to backup the RTC and backup

registers.

The STM32L431xx family offers nine packages from 32 to 100-pin packages.

Table 2. STM32L431xx family device features and peripheral counts

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

Flash memory 256KB 128KB 256KB 128KB 256KB 128KB 256KB

SRAM 64KB

Quad SPI Yes

Description STM32L431xx

14/208 DS11453 Rev 3

Timers

Advanced

control 1 (16-bit)

General

purpose

2 (16-bit)

1 (32-bit)

Basic 2 (16-bit)

Low -

power 2 (16-bit)

SysTick

timer 1

Watchdog

timers

(indepen

dent,

window)

Comm.

interfaces

SPI 3 2

I2C3 2

USART

LPUART

SAI 1

CAN 1

SDMMC Yes No

SWPMI Yes

RTC Yes

Tamper pins 3 2 2 1

Random generator Yes

GPIOs

Wakeup pins

38 or 39(1)

Capacitive sensing

Number of channels 21 12 6 3

12-bit ADC

Number of channels

12-bit DAC channels 2

Internal voltage

reference buffer Yes No

Analog comparator 2

Operational

amplifiers 1

Max. CPU frequency 80 MHz

Operating voltage 1.71 to 3.6 V

Table 2. STM32L431xx family device features and peripheral counts (continued)

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

DS11453 Rev 3 15/208

STM32L431xx Description

Operating

temperature

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

Packages LQFP100

UFBGA100

WLCSP64

LQFP64

UFBGA64

WLCSP49

LQFP48

UFQFPN48

UFQFPN32

1. For WLCSP49 package.

Table 2. STM32L431xx family device features and peripheral counts (continued)

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

Description STM32L431xx

16/208 DS11453 Rev 3

Figure 1. STM32L431xx block diagram

Note: AF: alternate function on I/O pins.

MSv39204V2

Flash

up to

256 KB

GPIO PORT A

AHB/APB2

EXT IT. WKUP

83 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage

regulator

3.3 to 1.2 V

VDD Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

DAC1

DAC2

TIM6

TIM7

TIM2

D-BUS

SRAM 48 KB

APB1 80 MHz (max)

SRAM 16 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PH[1:0],

PH[3]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT H

16b

TIM16 16b

1 channel,

1 compl. channel, BKIN as AF

OUT2

16b

32b 4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

16 external analog inputs

VREF+

USAR T 2MBps

Temperature sensor

@ VDDA

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

Touch sensing controller

7 Groups of

3 channels max as AF RC HSI

RC LSI

PLL 1&2

MSI

Quad SPI memory interface

D0[3:0],

D1[3:0],

CLK0,

CLK1

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

AHB1 80 MHz

CRC

APB2 80MHz

AHB2 80 MHz

FIREWALL

VREF Buffer

@ VDDA

@ VDD

VDD = 1.71 to 3.6 V

VSS

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

ITF

ADC1

HSI48

VDDA, VSSA

VDD, VSS, NRST

CRS CRS_SYNC

USART2 RX, TX, CK, CTS, RTS as AF

smcard

IrDA

USART3 RX, TX, CK, CTS, RTS as AF

smcard

IrDA

MOSI, MISO, SCK, NSS as AF

SPI2

MOSI, MISO, SCK, NSS as AF

SPI3

I2C1/SMBUS SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

I2C2/SMBUS

SCL, SDA, SMBA as AF

I2C3/SMBUS

FIFO

TX, RX as AF

bxCAN1

VOUT, VINM, VINP

OpAmp1

@VDDA

LPUART1 RX, TX, CTS, RTS as AF

SWPMI1 IO

RX, TX, SUSPEND as AF

LPTIM1 IN1, IN2, OUT, ETR as AF

LPTIM2 IN1, OUT, ETR as AF

DS11453 Rev 3 17/208

STM32L431xx Functional overview

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an Arm® core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L431xx family is compatible with all Arm® tools

and software.

Figure 1 shows the general block diagram of the STM32L431xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of

the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

Functional overview STM32L431xx

18/208 DS11453 Rev 3

3.4 Embedded Flash memory

STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for

storing programs and data in single bank architecture. The Flash memory contains 128

pages of 2 Kbyte.

Flexible protections can be configured thanks to option bytes:

•Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

•Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 2-Kbyte granularity.

•Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)

allows to select if the PCROP area is erased or not when the RDP protection is

changed from Level 1 to Level 0.

Table 3. Access status versus readout protection level and execution modes

Area Protection

level

User execution Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

Main

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased when RDP change from Level 1 to Level 0.

No No N/A(1)

2 Yes Yes N/A N/A N/A N/A

SRAM2

1 Yes Yes Yes(1) No No No(1)

2 Yes Yes Yes N/A N/A N/A

DS11453 Rev 3 19/208

STM32L431xx Functional overview

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

•single error detection and correction

•double error detection.

•The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two

blocks:

•48 Kbyte mapped at address 0x2000 0000 (SRAM1)

•16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2000 C000, offering a contiguous address

space with the SRAM1 (16 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.

These 16 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

•Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

•The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes

•Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

•Volatile data segment can be shared or not with the non-protected code

•Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

Functional overview STM32L431xx

20/208 DS11453 Rev 3

3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select

one of three boot options:

•Boot from user Flash

•Boot from system memory

•Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the

value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the

first flash memory location is not programmed and if the boot selection is configured to boot

from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART, I2C, SPI or CAN.

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

•VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and

the system analog such as reset, power management and internal clocks. It is provided

externally through VDD pins.

•VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA

voltage level is independent from the VDD voltage.

•VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted

to VDD.

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to Table 19: Voltage characteristics).

Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with

VDDIO1 = VDD.

DS11453 Rev 3 21/208

STM32L431xx Functional overview

Figure 2. Power supply overview

During power-up and power-down phases, the following power sequence requirements

must be respected:

•When VDD is below 1 V, other power supplies (VDDA) must remain below VDD +

300 mV.

•When VDD is above 1 V, all power supplies are independent.

During the power-down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the MCU remains below 1 mJ; this allows external decoupling

capacitors to be discharged with different time constants during the power- down transient

phase.

MSv39205V2

Low voltage detector

VDDA

VDDA domain

VSS

VDD

VBAT

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

VDD domain

I/O ring

VSSA

Reset block

Temp. sensor

PLL, HSI, MSI, HSI48

Standby circuitry

(Wakeup logic, IWDG)

Voltage regulator

VDDIO1

LSE crystal 32 K osc

BKP registers

RCC BDCR register

RTC

Backup domain

Core

Memories

Digital peripherals

VCORE domain

VCORE

,,,,,,,4, , ,,,,,,,,,,,,,,,,,,,,,,,,,

Functional overview STM32L431xx

22/208 DS11453 Rev 3

Figure 3. Power-up/down sequence

1. VDDX refers to VDDA.

3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes

except Shutdown and ensuring proper operation after power-on and during power down.

The device remains in reset mode when the monitored supply voltage VDD is below a

specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected

through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An

interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the

independent supply voltage VDDA with a fixed threshold in order to ensure that the

peripheral is in its functional supply range.

MSv47490V1

0.3

VBOR0

3.6

Operating modePower-on Power-down time

VDDX(1)

VDD

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD

DS11453 Rev 3 23/208

STM32L431xx Functional overview

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main

regulator (MR) and the low-power regulator (LPR).

•The MR is used in the Run and Sleep modes and in the Stop 0 mode.

•The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.

•Both regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing

zero consumption.

The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the Main Regulator that supplies the logic

(VCORE) can be adjusted according to the system’s maximum operating frequency.

There are two power consumption ranges:

•Range 1 with the CPU running at up to 80 MHz.

•Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

limited to 26 MHz.

The VCORE can be supplied by the low-power regulator, the main regulator being switched

off. The system is then in Low-power run mode.

•Low-power run mode with the CPU running at up to 2 MHz. Peripherals with

independent clock can be clocked by HSI16.

3.9.4 Low-power modes

The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best

compromise between low-power consumption, short startup time, available peripherals and

available wakeup sources.

Functional overview STM32L431xx

24/208 DS11453 Rev 3

Table 4. STM32L431xx modes overview

Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time

Run

MR range 1

Yes ON(4) ON Any

All

N/A

97 µA/MHz

N/A

MR range2 All except RNG 84 µA/MHz

LPRun LPR Yes ON(4) ON

Any

except

PLL

All except USB_FS, RNG N/A 94 µA/MHz to Range 1: 4 µs

to Range 2: 64 µs

Sleep

MR range 1

No ON(4) ON(5) Any

All Any interrupt or

event

28 µA/MHz

6 cycles

MR range2 All except RNG 26 µA/MHz

LPSleep LPR No ON(4) ON(5)

Any

except

PLL

All except USB_FS, RNG Any interrupt or

event 29 µA/MHz 6 cycles

Stop 0

MR Range 1

No OFF ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)(6)

LPUART1(6)

I2Cx (x=1...3)(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)(6)

LPUART1(6)

I2Cx (x=1...3)(7)

LPTIMx (x=1,2)

SWPMI1(8)

108 µA

2.4 µs in SRAM

4.1 µs in Flash

MR Range 2 108 µA

STM32L431xx Functional overview

DS11453 Rev 3 25/208

Stop 1 LPR No Off ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)(6)

LPUART1(6)

I2Cx (x=1...3)(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)(6)

LPUART1(6)

I2Cx (x=1...3)(7)

LPTIMx (x=1,2)

SWPMI1(8)

4.34 µA w/o RTC

4.63 µA w RTC

6.3 µs in SRAM

7.8 µs in Flash

Stop 2 LPR No Off ON LSE

LSI

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIM1

***

All other peripherals are

frozen.

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

I2C3(7)

LPUART1(6)

LPTIM1

1.3 µA w/o RTC

1.4 µA w/RTC

6.8 µs in SRAM

8.2 µs in Flash

Table 4. STM32L431xx modes overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time

Functional overview STM32L431xx

26/208 DS11453 Rev 3

Standby

LPR

Power

ed Off Off

SRAM

2 ON

LSE

LSI

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-down

Reset pin

5 I/Os (WKUPx)(9)

BOR, RTC, IWDG

0.20 µA w/o RTC

0.46 µA w/ RTC

12.2 µs

OFF

Power

Off

0.03 µA w/o RTC

0.29 µA w/ RTC

Shutdown OFF Power

ed Off Off

Power

Off

LSE

RTC

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-

down(10)

Reset pin

5 I/Os (WKUPx)(9)

RTC

0.01 µA w/o RTC

0.20 µA w/ RTC 262 µs

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. The SRAM1 and SRAM2 clocks can be gated on or off independently.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. SWPMI1 wakeup by resume from suspend.

9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Table 4. STM32L431xx modes overview (continued)

Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time

DS11453 Rev 3 27/208

STM32L431xx Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the

user to select one of the low-power modes described below:

•Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

•Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the low-

power run mode.

•Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still

running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator

remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI

up to 48 MHz or HSI16, depending on software configuration.

•Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off. The PLL, the

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention

mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

Functional overview STM32L431xx

28/208 DS11453 Rev 3

•Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,

the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup

domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin

event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic

wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

DS11453 Rev 3 29/208

STM32L431xx Functional overview

Table 5. Functionalities depending on the working mode(1)

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1 Stop 2 Standby Shutdown

VBAT

Wakeup capability

CPU Y - Y - - --------

Flash memory (up to

256 KB) O(2) O(2) O(2) O(2) ---------

SRAM1 (48 KB) Y Y(3) YY

(3) Y-Y------

SRAM2 (16 KB) Y Y(3) YY

(3) Y-Y-O

(4) ----

Quad SPI O O O O - --------

Backup Registers Y Y Y Y Y -Y-Y-Y-Y

Brown-out reset

(BOR) YYYYYYYYYY- --

Programmable

Voltage Detector

(PVD)

OOOOO

OOO- ----

Peripheral Voltage

Monitor (PVMx;

x=1,3,4)

OOOOO

OOO- ----

DMA OOOO-

--------

High Speed Internal

(HSI16) OOOO

(5) -(5) ------

Oscillator RC48 O O - - - --------

High Speed External

(HSE) OOOO-

--------

Low Speed Internal

(LSI) OOOOO

-O-O----

Low Speed External

(LSE) OOOOO

-O-O-O-O

Multi-Speed Internal

(MSI) OOOO-

--------

Clock Security

System (CSS) OOOO-

--------

Clock Security

System on LSE OOOOO

OOOOO- --

RTC / Auto wakeup O O O O O OOOOOOOO

Number of RTC

Tamper pins 33333O3O3O3O3

USARTx (x=1,2,3) O O O O O(6) O(6) -------

Functional overview STM32L431xx

30/208 DS11453 Rev 3

Low-power UART

(LPUART) OOOOO

(6) O(6) O(6) O(6) -----

I2Cx (x=1,2) O O O O O(7) O(7) -------

I2C3 OOOOO

(7) O(7) O(7) O(7) -----

SPIx (x=1,2,3) O O O O - --------

CAN OOOO-

--------

SDMMC1 O O O O - --------

SWPMI1 OOOO-

O- ------

SAIx (x=1) O O O O - --------

ADCx (x=1) O O O O - --------

DAC1 O O O O O --------

VREFBUF O O O O O --------

OPAMPx (x=1) O O O O O --------

COMPx (x=1,2) O O O O O OOO- ----

Temperature sensor O O O O - --------

Timers (TIMx) O O O O - --------

Low-power timer 1

(LPTIM1) OOOOO

OOO- ----

Low-power timer 2

(LPTIM2) OOOOO

O- ------

Independent

watchdog (IWDG) OOOOO

OOOOO- --

Window watchdog

(WWDG) OOOO-

--------

SysTick timer O O O O - --------

Touch sensing

controller (TSC) OOOO-

--------

Random number

generator (RNG) O(8) O(8) -----------

CRC calculation unit O O O O - --------

GPIOs OOOOO

OOO(9)

pins

(10)

(11)

pins

(10)

Table 5. Functionalities depending on the working mode(1) (continued)

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

Stop 0/1 Stop 2 Standby Shutdown

VBAT

Wakeup capability

DS11453 Rev 3 31/208

STM32L431xx Functional overview

3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.9.6 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external

supercapacitor, or from VDD when no external battery and an external supercapacitor are

present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-

tamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when VDD is not present.

An internal VBAT battery charging circuit is embedded and can be activated when VDD is

present.

Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events

do not exit it from VBAT operation.

3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run

and sleep, Stop 0, Stop 1 and Stop 2 modes.

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by

the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not

need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or

received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

Functional overview STM32L431xx

32/208 DS11453 Rev 3

Table 6. STM32L431xx peripherals interconnect matrix

Interconnect source Interconnect

destination Interconnect action

Run

Sleep

Low-power run

Low-power sleep

Stop 0 / Stop 1

Stop 2

TIMx

TIMx Timers synchronization or chaining Y Y Y Y - -

ADCx

DAC1 Conversion triggers Y Y Y Y - -

DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -

TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -

COMPx

TIM1

TIM2

Timer input channel, trigger, break from

analog signals comparison YYYY - -

LPTIMERx Low-power timer triggered by analog

signals comparison YYYYYY

(1)

ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -

RTC

TIM16 Timer input channel from RTC events Y Y Y Y - -

LPTIMERx Low-power timer triggered by RTC alarms

or tampers YYYYYY

(1)

All clocks sources (internal

and external)

TIM2

TIM15, 16

Clock source used as input channel for

RC measurement and trimming YYYY - -

CSS

CPU (hard fault)

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

TIM1

TIM15,16 Timer break Y Y Y Y - -

GPIO

TIMx External trigger Y Y Y Y - -

LPTIMERx External trigger Y Y Y Y Y Y

(1)

ADCx

DAC1 Conversion external trigger Y Y Y Y - -

1. LPTIM1 only.

DS11453 Rev 3 33/208

STM32L431xx Functional overview

3.11 Clocks and startup

The clock controller (see Figure 4) distributes the clocks coming from different oscillators to

the core and the peripherals. It also manages clock gating for low-power modes and

ensures clock robustness. It features:

•Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

•Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

•Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

•System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply

a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is

available in the system (LSE), the MSI frequency can be automatically trimmed by

hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency

at 80 MHz.

•RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be

used to drive the SDMMC or the RNG peripherals. This clock can be output on the

MCO.

•Auxiliary clock source: two ultralow-power clock sources that can be used to drive

the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

•Peripheral clock sources: Several peripherals (SDMMC, RNG, SAI, USARTs, I2Cs,

LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock.

Two PLLs, each having three independent outputs allowing the highest flexibility, can

generate independent clocks for the ADC, the SDMMC/RNG and the SAI.

•Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz

clock (MSI). The prescaler ratio and clock source can be changed by the application

program as soon as the code execution starts.

•Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI16 and a software

Functional overview STM32L431xx

34/208 DS11453 Rev 3

interrupt is generated if enabled. LSE failure can also be detected and generated an

interrupt.

•Clock-out capability:

–MCO: microcontroller clock output: it outputs one of the internal clocks for

external use by the application. Low frequency clocks (LSI, LSE) are available

down to Stop 1 low power state.

–LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes

down to Standby mode. LSE can also be output on LSCO in Shutdown mode.

LSCO is not available in VBAT mode.

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and

the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB

domains is 80 MHz.

LSE st HSE svsch MS‘ HS” 6 S S mam CLK mom CLK mm msmcm PLUEM2CLK PLLADC‘ CLK svscLK svsm

DS11453 Rev 3 35/208

STM32L431xx Functional overview

Figure 4. Clock tree

MSv39206V3

SYSCLK

MCO

LSCO

48 MHz clock to RNG, SDMMC

to ADC

to IWDG

to RTC

to PWR

HCLK

to AHB bus, core, memory and DMA

FCLK Cortex free running clock

to Cortex system timer

to APB1 peripherals

to APB2 peripherals

PCLK1

PCLK2

to SAI1

LSE

HSI16

SYSCLK to USARTx

x=2..3

to LPUART1

to I2Cx

x=1,2,3

to LPTIMx

x=1,2

SAI1_EXTCLK

to SWPMI

to TIMx

x=2,6,7

OSC32_OUT

OSC32_IN

MSI HSI16

HSE

HSI16

LSI

LSE

HSE

SYSCLK

HSE

MSI

HSI16

MSI

SYSCLK

LSE OSC

32.768 kHz /32

AHB PRESC

/ 1,2,..512

/ 8

APB1 PRESC

/ 1,2,4,8,16

x1 or x2

HSI16

SYSCLK

LSI

LSE

HSI16

APB2 PRESC

/ 1,2,4,8,16

to TIMx

x=1,15,16

x1 or x2

to USART1

LSE

HSI16

SYSCLK

/ M

MSI RC

100 kHz – 48 MHz

HSI RC

16 MHz

HSE OSC

4-48 MHz

Clock

detector

OSC_OUT

OSC_IN

/ 1→16

LSI RC 32 kHz

Clock

source

control

PLLSAI1CLK

PLL48M1CLK

PLLCLK

PLLSAI2CLK

PLL48M2CLK

PLLADC1CLK

HSI16

HSI RC

48 MHz

HSI48

CRS

PLL

PLLSAI1

VCO F

VCO

/ P

/ R

/ Q

/ P

/ Q

/ R

VCO F

VCO

PLLCLK

MSI

Functional overview STM32L431xx

36/208 DS11453 Rev 3

3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features

implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between

peripherals and memory as well as memory to memory. Data can be quickly moved by DMA

without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory

access requests from one or more peripherals. Each has an arbiter for handling the priority

between DMA requests.

The DMA supports:

•14 independently configurable channels (requests)

•Each channel is connected to dedicated hardware DMA requests, software trigger is

also supported on each channel. This configuration is done by software.

•Priorities between requests from channels of one DMA are software programmable (4

levels consisting of very high, high, medium, low) or hardware in case of equality

(request 1 has priority over request 2, etc.)

•Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•Support for circular buffer management

•3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

•Memory-to-memory transfer

•Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers

•Access to Flash, SRAM, APB and AHB peripherals as source and destination

•Programmable number of data to be transferred: up to 65536.

Table 7. DMA implementation

DMA features DMA1 DMA2

Number of regular channels 7 7

DS11453 Rev 3 37/208

STM32L431xx Functional overview

3.14 Interrupts and events

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M4.

The NVIC benefits are the following:

•Closely coupled NVIC gives low latency interrupt processing

•Interrupt entry vector table address passed directly to the core

•Allows early processing of interrupts

•Processing of late arriving higher priority interrupts

•Support for tail chaining

•Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 37 edge detector lines used to generate

interrupt/event requests and wake-up the system from Stop mode. Each external line can be

independently configured to select the trigger event (rising edge, falling edge, both) and can

be masked independently. A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up

to 83 GPIOs can be connected to the 16 external interrupt lines.

Functional overview STM32L431xx

38/208 DS11453 Rev 3

3.15 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the

following features:

•12-bit native resolution, with built-in calibration

•5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit

resolution)

•Up to 16 external channels.

•5 internal channels: internal reference voltage, temperature sensor, VBAT/3,

DAC1_OUT1 and DAC1_OUT2.

•One external reference pin is available on some package, allowing the input voltage

range to be independent from the power supply

•Single-ended and differential mode inputs

•Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

•Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups

of analog signals conversions can be programmed to differentiate background and

high-priority real-time conversions

– ADC supports multiple trigger inputs for synchronization with on-chip timers and

external signals

– Results stored into data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts

and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast

context switching

3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

DS11453 Rev 3 39/208

STM32L431xx Functional overview

3.15.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for

the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input

channel. The precise voltage of VREFINT is individually measured for each part by ST

during production test and stored in the system memory area. It is accessible in read-only

mode.

3.15.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage

using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than VDDA,

and thus outside the ADC input range, the VBAT pin is internally connected to a bridge

divider by 3. As a consequence, the converted digital value is one third the VBAT voltage.

3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage

signal outputs. The chosen design structure is composed of integrated resistor strings and

an amplifier in inverting configuration.

Table 8. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

TS_CAL2

TS ADC raw data acquired at a

temperature of 130 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75CA - 0x1FFF 75CB

Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

Functional overview STM32L431xx

40/208 DS11453 Rev 3

This digital interface supports the following features:

•Up to two DAC output channels

•8-bit or 12-bit output mode

•Buffer offset calibration (factory and user trimming)

•Left or right data alignment in 12-bit mode

•Synchronized update capability

•Noise-wave generation

•Triangular-wave generation

•Dual DAC channel independent or simultaneous conversions

•DMA capability for each channel

•External triggers for conversion

•Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected

to different DMA channels.

3.17 Voltage reference buffer (VREFBUF)

The STM32L431xx devices embed an voltage reference buffer which can be used as

voltage reference for ADCs, DAC and also as voltage reference for external components

through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

•2.048 V

•2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal

voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the

internal voltage reference buffer is not available.

Figure 5. Voltage reference buffer

MSv40197V1

VREFBUF

Low frequency

cut-off capacitor

DAC, ADC

Bandgap +

VDDA

100 nF

VREF+

DS11453 Rev 3 41/208

STM32L431xx Functional overview

3.18 Comparators (COMP)

The STM32L431xx devices embed two rail-to-rail comparators with programmable

reference voltage (internal or external), hysteresis and speed (low speed for low-power) and

with selectable output polarity.

The reference voltage can be one of the following:

•External I/O

•DAC output channels

•Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers

and can be also combined into a window comparator.

3.19 Operational amplifier (OPAMP)

The STM32L431xx embeds one operational amplifier with external or internal follower

routing and PGA capability.

The operational amplifier features:

•Low input bias current

•Low offset voltage

•Low-power mode

•Rail-to-rail input

3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing

functionality to any application. Capacitive sensing technology is able to detect finger

presence near an electrode which is protected from direct touch by a dielectric (glass,

plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is

measured using a proven implementation based on a surface charge transfer acquisition

principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware

library which is free to use and allows touch sensing functionality to be implemented reliably

in the end application.

Functional overview STM32L431xx

42/208 DS11453 Rev 3

The main features of the touch sensing controller are the following:

•Proven and robust surface charge transfer acquisition principle

•Supports up to 21 capacitive sensing channels

•Up to 3 capacitive sensing channels can be acquired in parallel offering a very good

response time

•Spread spectrum feature to improve system robustness in noisy environments

•Full hardware management of the charge transfer acquisition sequence

•Programmable charge transfer frequency

•Programmable sampling capacitor I/O pin

•Programmable channel I/O pin

•Programmable max count value to avoid long acquisition when a channel is faulty

•Dedicated end of acquisition and max count error flags with interrupt capability

•One sampling capacitor for up to 3 capacitive sensing channels to reduce the system

components

•Compatible with proximity, touchkey, linear and rotary touch sensor implementation

•Designed to operate with STMTouch touch sensing firmware library

Note: The number of capacitive sensing channels is dependent on the size of the packages and

subject to I/O availability.

3.21 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

3.22 Timers and watchdogs

The STM32L431xx includes one advanced control timers, up to five general-purpose timers,

two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table

below compares the features of the advanced control, general purpose and basic timers.

Table 10. Timer feature comparison

Timer type Timer Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complementary

outputs

Advanced

control TIM1 16-bit Up, down,

Up/down

Any integer

between 1

and 65536

Yes 4 3

General-

purpose TIM2 32-bit Up, down,

Up/down

Any integer

between 1

and 65536

Yes 4 No

General-

purpose TIM15 16-bit Up

Any integer

between 1

and 65536

Yes 2 1

DS11453 Rev 3 43/208

STM32L431xx Functional overview

3.22.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6

channels. They have complementary PWM outputs with programmable inserted dead-

times. They can also be seen as complete general-purpose timers. The 4 independent

channels can be used for:

•Input capture

•Output compare

•PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

•One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.22.2) using the same architecture, so the advanced-control timer can work

together with the TIMx timers via the Timer Link feature for synchronization or event

chaining.

General-

purpose TIM16 16-bit Up

Any integer

between 1

and 65536

Yes 1 1

Basic TIM6, TIM7 16-bit Up

Any integer

between 1

and 65536

Yes 0 No

Table 10. Timer feature comparison (continued)

Timer type Timer Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complementary

outputs

Functional overview STM32L431xx

44/208 DS11453 Rev 3

3.22.2 General-purpose timers (TIM2, TIM15, TIM16)

There are up to three synchronizable general-purpose timers embedded in the

STM32L431xx (see Table 10 for differences). Each general-purpose timer can be used to

generate PWM outputs, or act as a simple time base.

•TIM2

It is a full-featured general-purpose timer:

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.

This timer features 4 independent channels for input capture/output compare, PWM or

one-pulse mode output. It can work with the other general-purpose timers via the Timer

Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

It has independent DMA request generation and support quadrature encoder.

•TIM15 and 16

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 has 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode

output.

The timers can work together via the Timer Link feature for synchronization or event

chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.22.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as

generic 16-bit timebases.

3.22.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are

running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to

wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

DS11453 Rev 3 45/208

STM32L431xx Functional overview

This low-power timer supports the following features:

•16-bit up counter with 16-bit autoreload register

•16-bit compare register

•Configurable output: pulse, PWM

•Continuous/ one shot mode

•Selectable software/hardware input trigger

•Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

•Programmable digital glitch filter

•Encoder mode (LPTIM1 only)

3.22.5 Infrared interface (IRTIM)

The STM32L431xx includes one infrared interface (IRTIM). It can be used with an infrared

LED to perform remote control functions. It uses TIM15 and TIM16 output channels to

generate output signal waveforms on IR_OUT pin.

3.22.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC (LSI) and as it operates independently

from the main clock, it can operate in Stop and Standby modes. It can be used either as a

watchdog to reset the device when a problem occurs, or as a free running timer for

application timeout management. It is hardware or software configurable through the option

bytes. The counter can be frozen in debug mode.

3.22.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.22.8 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•A 24-bit down counter

•Autoreload capability

•Maskable system interrupt generation when the counter reaches 0.

•Programmable clock source

Functional overview STM32L431xx

46/208 DS11453 Rev 3

3.23 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:

•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

•Two programmable alarms.

•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy.

•Three anti-tamper detection pins with programmable filter.

•Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to

VBAT mode.

•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either

from the VDD supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data

when VDD power is not present. They are not reset by a system or power reset, or when the

device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

•A 32.768 kHz external crystal (LSE)

•An external resonator or oscillator (LSE)

•The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

•The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in

all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt

and wakeup the device from the low-power modes.

DS11453 Rev 3 47/208

STM32L431xx Functional overview

3.24 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 11: I2C implementation for the features

implementation.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•I2C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

•System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK

control

– Address resolution protocol (ARP) support

– SMBus alert

•Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility

•Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree.

•Wakeup from Stop mode on address match

•Programmable analog and digital noise filters

•1-byte buffer with DMA capability

Table 11. I2C implementation

I2C features(1)

1. X: supported

I2C1 I2C2 I2C3

Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X

Programmable analog and digital noise filters X X X

SMBus/PMBus hardware support X X X

Independent clock X X X

Wakeup from Stop 0 / Stop 1 mode on address match X X X

Wakeup from Stop 2 mode on address match - - X

Functional overview STM32L431xx

48/208 DS11453 Rev 3

3.25 Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32L431xx devices have three embedded universal synchronous receiver

transmitters (USART1, USART2 and USART3).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. They provide hardware management of the CTS and RTS

signals, and RS485 Driver Enable. They are able to communicate at speeds of up to

10Mbit/s.

USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and

SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx

(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake

up events from Stop mode are programmable and can be:

•Start bit detection

•Any received data frame

•A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 12. STM32L431xx USART/LPUART features

USART modes/features(1)

1. X = supported.

USART1 USART2 USART3 LPUART1

Hardware flow control for modem X X X X

Continuous communication using DMA X X X X

Multiprocessor communication X X X X

Synchronous mode X X X -

Smartcard mode X X X -

Single-wire half-duplex communication X X X X

IrDA SIR ENDEC block X X X -

LIN mode X X X -

Dual clock domain X X X X

Wakeup from Stop 0 / Stop 1 modes X X X X

Wakeup from Stop 2 mode - - - X

Receiver timeout interrupt X X X -

Modbus communication X X X -

Auto baud rate detection X (4 modes) -

Driver Enable X X X X

LPUART/USART data length 7, 8 and 9 bits

DS11453 Rev 3 49/208

STM32L431xx Functional overview

3.26 Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial

communication with minimum power consumption. It supports half duplex single wire

communication and modem operations (CTS/RTS). It allows multiprocessor

communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop

mode are programmable and can be:

•Start bit detection

•Any received data frame

•A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

LPUART interface can be served by the DMA controller.

Functional overview STM32L431xx

50/208 DS11453 Rev 3

3.27 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.28 Serial audio interfaces (SAI)

The device embeds 1 SAI. Refer to Table 13: SAI implementation for the features

implementation. The SAI bus interface handles communications between the

microcontroller and the serial audio protocol.

The SAI peripheral supports:

•Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

•8-word integrated FIFOs for each audio sub-block.

•Synchronous or asynchronous mode between the audio sub-blocks.

•Master or slave configuration independent for both audio sub-blocks.

•Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

•Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

•Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out.

•Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

•Number of bits by frame may be configurable.

•Frame synchronization active level configurable (offset, bit length, level).

•First active bit position in the slot is configurable.

•LSB first or MSB first for data transfer.

•Mute mode.

•Stereo/Mono audio frame capability.

•Communication clock strobing edge configurable (SCK).

•Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

•Interruption sources when enabled:

–Errors.

– FIFO requests.

•DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

DS11453 Rev 3 51/208

STM32L431xx Functional overview

3.29 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to

the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The

main features are:

•full-duplex communication mode

•automatic SWP bus state management (active, suspend, resume)

•configurable bitrate up to 2 Mbit/s

•automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

3.30 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

Table 13. SAI implementation

SAI features Support(1)

1. X: supported

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X

Stereo/Mono audio frame capability. X

16 slots X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X

FIFO Size X (8 Word)

SPDIF X

Functional overview STM32L431xx

52/208 DS11453 Rev 3

The CAN peripheral supports:

•Supports CAN protocol version 2.0 A, B Active

•Bit rates up to 1 Mbit/s

•Transmission

– Three transmit mailboxes

– Configurable transmit priority

•Reception

– Two receive FIFOs with three stages

– 14 Scalable filter banks

– Identifier list feature

– Configurable FIFO overrun

•Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

•Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

3.31 Secure digital input/output and MultiMediaCards Interface

(SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus

and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

The SDMMC features include the following:

•Full compliance with MultiMediaCard System Specification Version 4.2. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

•Full compatibility with previous versions of MultiMediaCards (forward compatibility)

•Full compliance with SD Memory Card Specifications Version 2.0

•Full compliance with SD I/O Card Specification Version 2.0: card support for two

different databus modes: 1-bit (default) and 4-bit

•Data transfer up to 48 MHz for the 8 bit mode

•Data write and read with DMA capability

3.32 Clock recovery system (CRS)

The STM32L431xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from LSE oscillator, from an external signal on CRS_SYNC

pin or generated by user software. For faster lock-in during startup it is also possible to

combine automatic trimming with manual trimming action.

DS11453 Rev 3 53/208

STM32L431xx Functional overview

3.33 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•Indirect mode: all the operations are performed using the QUADSPI registers

•Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

Quad SPI flash memories are accessed simultaneously.

The Quad SPI interface supports:

•Three functional modes: indirect, status-polling, and memory-mapped

•Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two

flash memories in parallel.

•SDR and DDR support

•Fully programmable opcode for both indirect and memory mapped mode

•Fully programmable frame format for both indirect and memory mapped mode

•Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

•Integrated FIFO for reception and transmission

•8, 16, and 32-bit data accesses are allowed

•DMA channel for indirect mode operations

•Programmable masking for external flash flag management

•Timeout management

•Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

Functional overview STM32L431xx

54/208 DS11453 Rev 3

3.34 Development support

3.34.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could

be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

3.34.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and

data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L431xx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then

formatted for display on the host computer that runs the debugger software. TPA hardware

is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

222 I 1 m I 2 m I 3 pas I A pas I 5 van I 5 P013 I 7 Pcwoscaz W I 3 P0503032 OUT I 9 vss I 10 we I 11 mesa W I 12 whose am I 13 LQFP100 ~st I 14 m I 15 Pm I 16 PC? I 17 PCS I 18 VSSA I 19 VREF I 20 mg. I 21 mm I 22 m I 23 m I 24 m I 25

DS11453 Rev 3 55/208

STM32L431xx Pinouts and pin description

4 Pinouts and pin description

Figure 6. STM32L431Vx LQFP100 pinout(1)

1. The above figure shows the package top view.

MSv39214V2

LQFP100

VSS

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

PC15-OSC32_OUT

VDD

PE5

VBAT

PC14-OSC32_IN

PE2

PE3

PE4

PE6

PC13

100

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PE8

PE11

PA6

PA7

PE9

PE12

PE15

PB0

PB1

PE13

PB10

VSS

PE7

PE10

PE14

PB11

VDD

PC9

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PA8

PC8

PA13

PA11

PA9

VDD

VSS

VDD

PA12

PA10

VDD

VSS

PB9

PB7

PB3

PE1

PE0

PB6

PD6

PD3

PB8

PH3/BOOT0

PD5

PD2

PC12

PB5

PB4

PD1

PC11

PA15

PD7

PD4

PD0

PC10

PA14

van I ‘ PC‘S I 2 PCM’OSCSQ w I 3 Pcwoscaz out I 4 we osc w I 5 PH‘rOSC out I s ”C“ ' E LQFP64

Pinouts and pin description STM32L431xx

56/208 DS11453 Rev 3

Figure 7. STM32L431Vx UFBGA100 ballout(1)

1. The above figure shows the package top view.

Figure 8. STM32L431Rx LQFP64 pinout(1)

1. The above figure shows the package top view.

MSv39213V2

PE3 PE1 PB8 PH3/BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

123456789101112

PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDD PA10

PC14-

OSC32_IN PE6 VSS PA9 PA8 PC9

PC15-

OSC32_OUT VBAT VSS PC8 PC7 PC6

PH0-OSC_IN VSS VSS VSS

PH1-

OSC_OUT VDD VDD VDD

PC0 NRST VDD PD15 PD14 PD13

VSSA PC1 PC2 PD12 PD11 PD10

VREF- PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13

VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12

VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

UFBGA100

MSv39212V2

LQFP64

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PB11

PA6

PA7

VSS

PB0

PB1

PB10

VDD

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

PH3/BOOT0

PB5

PC12

PB9

PB8

PB4

PC10

PB7

PB6

PA15

PB3

PD2

PC11

PA14

DS11453 Rev 3 57/208

STM32L431xx Pinouts and pin description

Figure 9. STM32L431Rx UFBGA64 ballout(1)

1. The above figure shows the package top view.

Figure 10. STM32L431Rx WLCSP64 pinout(1)

1. The above figure shows the package top view.

Figure 11. STM32L431Cx WLCSP49 pinout(1)

1. The above figure shows the package top view.

MSv39211V2

PC14-

OSC32_IN PC13 PB9 PB4 PB3 PA15 PA14 PA13

12345678

PC15-

OSC32_OUT VBAT PB8 PH3/BOOT0 PD2 PC11 PC10 PA12

PH0-OSC_IN VSS PB7 PB5 PC12 PA11

PH1-

OSC_OUT VDD PB6

NRST PC1 PC0

VSSA/VREF- PC2

PC3 PA0

VDDA/VREF+ PA1 PA4

PA3

PA2

PC4

PB1

PB0

VDD

VSS

PA7

PA6

PA5

VDD

VSS

PB11

PB10

PB15

PC7

PA8

PC5

PB2

PC6

VDD

VSS

PA10 PA9

PB12

PB13

PB14

PC8

PC9

MSv39210V2

VDD PA15 PC12 PD2 PB3 PB7 VSS VDD

12345678

VSS PA14 PC11 PB4 PB6 PB9 VBAT PC13

PA12 PA13 PC10 PB5 PH3/BOOT0 PC14-

OSC32_IN

PA9 PA10 PA11

PC7 PC9 PA8

PC6 PB15

PB14 PB13

VDD VSS PB11

PB12

PC8

PB1

PA6

PA5

PA4

PC0

PB10

PB2

PB0

PC5

PC4

VDD

PA1

PA0

PC2

PH1-

OSC_OUT

PA7

PA3

PA2

PC3

NRST

PB8 PC15-

OSC32_OUT

VSS

VDDA/VREF+

VSSA/VREF-

PC1

PH0-OSC_IN

MSv39209V2

VDD PA14 PB3 PB4 PH3/BOOT0 VSS VDD

1234567

VSS PA13 PA15 PB5 PB8 VBAT PC13

PA11 PA10 PA12 PB6 PB9

PA8 PA9 PB15

PB14 PB13 PB10

PB12 PB11

VDD VSS PB2

PA7

PB0

PA5

PA2

NRST

PB1

PA6

PA3

PB7

PA1

VDDA/VREF+

VSSA/VREF-

PH0-OSC_IN

PA4

PA0

PC3

PH1-

OSC_OUT

PC15-

OSC32_OUT

PC14-

OSC32_IN

VBAT I ‘ Pm: I 2 PCM’OSCE)? w l 3 PCIEVOSCSZ out I 4 we use w I 5 PHIVOSC out I s anr I 7 LQFP48

Pinouts and pin description STM32L431xx

58/208 DS11453 Rev 3

Figure 12. STM32L431Cx LQFP48 pinout(1)

1. The above figure shows the package top view.

Figure 13. STM32L431Cx UFQFPN48 pinout(1)

1. The above figure shows the package top view.

MSv39208V2

LQFP48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3/BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

MSv39207V2

UFQFPN48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3/BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

m . ‘ mom w . 2 pmosw out . NRSI I 4 WWW. . 5 UFQFF’N32 PAOrCK \N I 6

DS11453 Rev 3 59/208

STM32L431xx Pinouts and pin description

Figure 14. STM32L431Kx UFQFPN32 pinout(1)

1. The above figure shows the package top view.

MSv37605V2

UFQFPN32

VDD

PC14-OSC32_IN

PC15-OSC32_OUT

NRST

VDDA/VREF+

PA0/CK_IN

PA1

PA2

PA3

PA4

PA7

VSS

PA5

PA6

PB0

PB1

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

VSS

PH3/BOOT0

PB5

PA15

PB7

PB6

PB4

PB3

Table 14. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after

reset is the same as the actual pin name

Pin type

S Supply pin

I Input only pin

I/O Input / output pin

I/O structure

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

_f (1) I/O, Fm+ capable

_a (2) I/O, with Analog switch function supplied by VDDA

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

functions

Alternate

functions Functions selected through GPIOx_AFR registers

Additional

functions Functions directly selected/enabled through peripheral registers

1. The related I/O structures in Table 15 are: FT_f, FT_fa.

2. The related I/O structures in Table 15 are: FT_a, FT_fa, TT_a.

Pinouts and pin description STM32L431xx

60/208 DS11453 Rev 3

Table 15. STM32L431xx pin definitions

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

--- - - - - 1 B2 PE2 I/O FT -

TRACECK,

TSC_G7_IO1,

SAI1_MCLK_A,

EVENTOUT

--- - - - - 2 A1 PE3 I/O FT -

TRACED0,

TSC_G7_IO2,

SAI1_SD_B, EVENTOUT

--- - - - - 3 B1 PE4 I/O FT -

TRACED1,

TSC_G7_IO3,

SAI1_FS_A, EVENTOUT

--- - - - - 4 C2 PE5 I/O FT -

TRACED2,

TSC_G7_IO4,

SAI1_SCK_A,

EVENTOUT

--- - - - - 5 D2 PE6 I/O FT -TRACED3, SAI1_SD_A,

EVENTOUT

RTC_TAMP3,

WKUP3

- 1 1 B6 B7 1 B2 6 E2 VBAT S - - - -

- 2 2B7B82A2 7 C1 PC13 I/O FT

(1)

(2) EVENTOUT

RTC_TAMP1,

RTC_TS,

RTC_OUT,

WKUP2

2 3 3 C7 C8 3 A1 8 D1

PC14-

OSC32_I

N (PC14)

I/O FT

(1)

(2) EVENTOUT OSC32_IN

3 4 4 C6 C7 4 B1 9 E1

PC15-

OSC32_

OUT

(PC15)

I/O FT

(1)

(2) EVENTOUT OSC32_OUT

--- - - - -10F2 VSS S - - - -

--- - - - -11G2 VDD S - - - -

- 5 5D7D85C112 F1

PH0-

OSC_

IN (PH0)

I/O FT - EVENTOUT OSC_IN

- 6 6D6D76D113 G1

PH1-

OSC_

OUT

(PH1)

I/O FT - EVENTOUT OSC_OUT

4 7 7 D5 D6 7 E1 14 H2 NRST I/O RST - - -

DS11453 Rev 3 61/208

STM32L431xx Pinouts and pin description

--- -D58E315H1 PC0 I/OFT_fa-

LPTIM1_IN1, I2C3_SCL,

LPUART1_RX,

LPTIM2_IN1,

EVENTOUT

ADC1_IN1

--- -E89E216J2 PC1 I/OFT_fa-

LPTIM1_OUT,

I2C3_SDA,

LPUART1_TX,

EVENTOUT

ADC1_IN2

--- -E710F217J3 PC2 I/OFT_a- LPTIM1_IN2,

SPI2_MISO, EVENTOUT ADC1_IN3

- - - E6 E6 11 G1 18 K2 PC3 I/O FT_a -

LPTIM1_ETR,

SPI2_MOSI, SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

ADC1_IN4

- - - - - - - 19 J1 VSSA S - - - -

- - - - - - - 20 K1 VREF- S - - - -

-88E7F812F1 - - VSSA/

VREF- S-- - -

- - - - - - - 21 L1 VREF+ S - - - VREFBUF_

OUT

--- - - - -22M1 VDDA S - - - -

599F7G813H1 - - VDDA/

VREF+ S-- - -

- 1010F6 F714G2 23 L2 PA0 I/O FT_a -

TIM2_CH1,

USART2_CTS,

COMP1_OUT,

SAI1_EXTCLK,

TIM2_ETR, EVENTOUT

OPAMP1_

VINP,

COMP1_INM,

ADC1_IN5,

RTC_TAMP2,

WKUP1

6--- --- - - PA0/

CK_IN I/O FT_a -

TIM2_CH1,

USART2_CTS,

COMP1_OUT,

SAI1_EXTCLK,

TIM2_ETR, EVENTOUT

OPAMP1_

VINP,

COMP1_INM,

ADC1_IN5,

RTC_TAMP2,

WKUP1,

CK_IN

71111G7G715H224 M2 PA1 I/O FT_a -

TIM2_CH2, I2C1_SMBA,

SPI1_SCK,

USART2_RTS_DE,

TIM15_CH1N,

EVENTOUT

OPAMP1_

VINM,

COMP1_INP,

ADC1_IN6

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

Pinouts and pin description STM32L431xx

62/208 DS11453 Rev 3

81212E5F616F3 25 K3 PA2 I/O FT_a -

TIM2_CH3, USART2_TX,

LPUART1_TX,

QUADSPI_BK1_NCS,

COMP2_OUT,

TIM15_CH1, EVENTOUT

COMP2_INM,

ADC1_IN7,

WKUP4,

LSCO

91313E4G617G326 L3 PA3 I/O TT_a -

TIM2_CH4, USART2_RX,

LPUART1_RX,

QUADSPI_CLK,

SAI1_MCLK_A,

TIM15_CH2, EVENTOUT

OPAMP1_

VOUT,

COMP2_INP,

ADC1_IN8

--- -H818C227E3 VSS S - - - -

--- -H719D228H3 VDD S - - - -

10 14 14 G6 E5 20 H3 29 M3 PA4 I/O TT_a -

SPI1_NSS, SPI3_NSS,

USART2_CK,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

COMP1_INM,

COMP2_INM,

ADC1_IN9,

DAC1_OUT1

11 15 15 F5 F5 21 F4 30 K4 PA5 I/O TT_a -

TIM2_CH1, TIM2_ETR,

SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

COMP1_INM,

COMP2_INM,

ADC1_IN10,

DAC1_OUT2

12 16 16 F4 G5 22 G4 31 L4 PA6 I/O FT_a -

TIM1_BKIN, SPI1_MISO,

COMP1_OUT,

USART3_CTS,

LPUART1_CTS,

QUADSPI_BK1_IO3,

TIM1_BKIN_COMP2,

TIM16_CH1, EVENTOUT

ADC1_IN11

13 17 17 F3 H6 23 H4 32 M4 PA7 I/O FT_fa -

TIM1_CH1N, I2C3_SCL,

SPI1_MOSI,

QUADSPI_BK1_IO2,

COMP2_OUT,

EVENTOUT

ADC1_IN12

--- -D424H533K5 PC4 I/OFT_a- USART3_TX,

EVENTOUT

COMP1_INM,

ADC1_IN13

--- -E425H634L5 PC5 I/OFT_a- USART3_RX,

EVENTOUT

COMP1_INP,

ADC1_IN14,

WKUP5

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

DS11453 Rev 3 63/208

STM32L431xx Pinouts and pin description

14 18 18 G5 F4 26 F5 35 M5 PB0 I/O FT_a -

TIM1_CH2N, SPI1_NSS,

USART3_CK,

QUADSPI_BK1_IO1,

COMP1_OUT,

SAI1_EXTCLK,

EVENTOUT

ADC1_IN15

15 19 19 G4 H5 27 G5 36 M6 PB1 I/O FT_a -

TIM1_CH3N,

USART3_RTS_DE,

LPUART1_RTS_DE,

QUADSPI_BK1_IO0,

LPTIM2_IN1,

EVENTOUT

COMP1_INM,

ADC1_IN16

- 2020G3G428G6 37 L6 PB2 I/O FT_a - RTC_OUT, LPTIM1_OUT,

I2C3_SMBA, EVENTOUT COMP1_INP

--- - - - -38M7 PE7 I/O FT -

TIM1_ETR, SAI1_SD_B,

EVENTOUT -

--- - - - -39L7 PE8 I/O FT -

TIM1_CH1N,

SAI1_SCK_B,

EVENTOUT

--- - - - -40M8 PE9 I/O FT -

TIM1_CH1, SAI1_FS_B,

EVENTOUT -

--- - - - -41L8 PE10 I/O FT -

TIM1_CH2N,

TSC_G5_IO1,

QUADSPI_CLK,

SAI1_MCLK_B,

EVENTOUT

--- - - - -42M9 PE11 I/O FT -

TIM1_CH2,

TSC_G5_IO2,

QUADSPI_BK1_NCS,

EVENTOUT

--- - - - -43L9 PE12 I/O FT -

TIM1_CH3N, SPI1_NSS,

TSC_G5_IO3,

QUADSPI_BK1_IO0,

EVENTOUT

--- - - - -44M10 PE13 I/O FT -

TIM1_CH3, SPI1_SCK,

TSC_G5_IO4,

QUADSPI_BK1_IO1,

EVENTOUT

--- - - - -45M11 PE14 I/O FT -

TIM1_CH4, TIM1_BKIN2,

TIM1_BKIN2_COMP2,

SPI1_MISO,

QUADSPI_BK1_IO2,

EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

Pinouts and pin description STM32L431xx

64/208 DS11453 Rev 3

--- - - - -46M12 PE15 I/O FT -

TIM1_BKIN,

TIM1_BKIN_COMP1,

SPI1_MOSI,

QUADSPI_BK1_IO3,

EVENTOUT

- 21 21 E3 H4 29 G7 47 L10 PB10 I/O FT_f -

TIM2_CH3, I2C2_SCL,

SPI2_SCK, USART3_TX,

LPUART1_RX,

TSC_SYNC,

QUADSPI_CLK,

COMP1_OUT,

SAI1_SCK_A,

EVENTOUT

-2222F2H330H748L11 PB11 I/O FT_f -

TIM2_CH4, I2C2_SDA,

USART3_RX,

LPUART1_TX,

QUADSPI_BK1_NCS,

COMP2_OUT,

EVENTOUT

16 23 23 G2 H2 31 D6 49 F12 VSS S - - - -

17 24 24 G1 H1 32 E6 50 G12 VDD S - - - -

- 25 25 F1 G3 33 H8 51 L12 PB12 I/O FT -

TIM1_BKIN,

TIM1_BKIN_COMP2,

I2C2_SMBA, SPI2_NSS,

USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1,

SWPMI1_IO,

SAI1_FS_A,

TIM15_BKIN,

EVENTOUT

- 26 26 E2 G2 34 G8 52 K12 PB13 I/O FT_f -

TIM1_CH1N, I2C2_SCL,

SPI2_SCK,

USART3_CTS,

LPUART1_CTS,

TSC_G1_IO2,

SWPMI1_TX,

SAI1_SCK_A,

TIM15_CH1N,

EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

DS11453 Rev 3 65/208

STM32L431xx Pinouts and pin description

- 27 27 E1 G1 35 F8 53 K11 PB14 I/O FT_f -

TIM1_CH2N, I2C2_SDA,

SPI2_MISO,

USART3_RTS_DE,

TSC_G1_IO3,

SWPMI1_RX,

SAI1_MCLK_A,

TIM15_CH1, EVENTOUT

- 28 28 D3 F2 36 F7 54 K10 PB15 I/O FT -

RTC_REFIN,

TIM1_CH3N,

SPI2_MOSI,

TSC_G1_IO4,

SWPMI1_SUSPEND,

SAI1_SD_A,

TIM15_CH2, EVENTOUT

--- - - - -55K9 PD8 I/O FT - USART3_TX,

EVENTOUT -

--- - - - -56K8 PD9 I/O FT - USART3_RX,

EVENTOUT -

--- - - - -57J12 PD10 I/O FT -

USART3_CK,

TSC_G6_IO1,

EVENTOUT

--- - - - -58J11 PD11 I/O FT -

USART3_CTS,

TSC_G6_IO2,

LPTIM2_ETR,

EVENTOUT

--- - - - -59J10 PD12 I/O FT -

USART3_RTS_DE,

TSC_G6_IO3,

LPTIM2_IN1,

EVENTOUT

- - - - - - - 60 H12 PD13 I/O FT -

TSC_G6_IO4,

LPTIM2_OUT,

EVENTOUT

- - - - - - - 61 H11 PD14 I/O FT - EVENTOUT -

- - - - - - - 62 H10 PD15 I/O FT - EVENTOUT -

--- -F137F663E12 PC6 I/O FT -

TSC_G4_IO1,

SDMMC1_D6,

EVENTOUT

--- -E138E764E11 PC7 I/O FT -

TSC_G4_IO2,

SDMMC1_D7,

EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

Pinouts and pin description STM32L431xx

66/208 DS11453 Rev 3

--- -F339E865E10 PC8 I/O FT -

TSC_G4_IO3,

SDMMC1_D0,

EVENTOUT

--- -E240D866D12 PC9 I/O FT -

TSC_G4_IO4,

SDMMC1_D1,

EVENTOUT

18 29 29 D1 E3 41 D7 67 D11 PA8 I/O FT -

MCO, TIM1_CH1,

USART1_CK,

SWPMI1_IO,

SAI1_SCK_A,

LPTIM2_OUT,

EVENTOUT

19 30 30 D2 D1 42 C7 68 D10 PA9 I/O FT_f -

TIM1_CH2, I2C1_SCL,

USART1_TX,

SAI1_FS_A,

TIM15_BKIN,

EVENTOUT

20 31 31 C2 D2 43 C6 69 C12 PA10 I/O FT_f -

TIM1_CH3, I2C1_SDA,

USART1_RX,

SAI1_SD_A, EVENTOUT

21 32 32 C1 D3 44 C8 70 B12 PA11 I/O FT -

TIM1_CH4, TIM1_BKIN2,

SPI1_MISO,

COMP1_OUT,

USART1_CTS,

CAN1_RX,

TIM1_BKIN2_COMP1,

EVENTOUT

22 33 33 C3 C1 45 B8 71 A12 PA12 I/O FT -

TIM1_ETR, SPI1_MOSI,

USART1_RTS_DE,

CAN1_TX, EVENTOUT

23 34 34 B2 C2 46 A8 72 A11

PA13

(JTMS-

SWDIO)

I/O FT (3)

JTMS-SWDIO, IR_OUT,

SWPMI1_TX,

SAI1_SD_B, EVENTOUT

- 35 35 B1 B1 47 D5 - - VSS S - - - -

-3636A1A148E573C11 VDD S - - - -

--- - - - -74F11 VSS S - - - -

--- - - - -75G11 VDD S - - - -

24 37 37 A2 B2 49 A7 76 A10

PA14

(JTCK-

SWCLK)

I/O FT (3)

JTCK-SWCLK,

LPTIM1_OUT,

I2C1_SMBA,

SWPMI1_RX,

SAI1_FS_B, EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

DS11453 Rev 3 67/208

STM32L431xx Pinouts and pin description

25 38 38 B3 A2 50 A6 77 A9 PA15

(JTDI) I/O FT (3)

JTDI, TIM2_CH1,

TIM2_ETR, USART2_RX,

SPI1_NSS, SPI3_NSS,

USART3_RTS_DE,

TSC_G3_IO1,

SWPMI1_SUSPEND,

EVENTOUT

--- -C351B778B11 PC10 I/O FT -

SPI3_SCK, USART3_TX,

TSC_G3_IO2,

SDMMC1_D2,

EVENTOUT

--- -B352B679C10 PC11 I/O FT -

SPI3_MISO,

USART3_RX,

TSC_G3_IO3,

SDMMC1_D3,

EVENTOUT

- - - - A3 53 C5 80 B10 PC12 I/O FT -

SPI3_MOSI,

USART3_CK,

TSC_G3_IO4,

SDMMC1_CK,

EVENTOUT

--- - - - -81C9 PD0 I/O FT - SPI2_NSS, CAN1_RX,

EVENTOUT -

--- - - - -82B9 PD1 I/O FT - SPI2_SCK, CAN1_TX,

EVENTOUT -

--- -A454B583C8 PD2 I/O FT -

USART3_RTS_DE,

TSC_SYNC,

SDMMC1_CMD,

EVENTOUT

--- - - - -84B8 PD3 I/O FT -

SPI2_MISO,

USART2_CTS,

QUADSPI_BK2_NCS,

EVENTOUT

--- - - - -85B7 PD4 I/O FT -

SPI2_MOSI,

USART2_RTS_DE,

QUADSPI_BK2_IO0,

EVENTOUT

--- - - - -86A6 PD5 I/O FT -

USART2_TX,

QUADSPI_BK2_IO1,

EVENTOUT

--- - - - -87B6 PD6 I/O FT -

USART2_RX,

QUADSPI_BK2_IO2,

SAI1_SD_A, EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

Pinouts and pin description STM32L431xx

68/208 DS11453 Rev 3

--- - - - -88A5 PD7 I/O FT -

USART2_CK,

QUADSPI_BK2_IO3,

EVENTOUT

26 39 39 A3 A5 55 A5 89 A8

PB3

(JTDO-

TRACE

SWO)

I/O FT_a (3)

JTDO-TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

SAI1_SCK_B,

EVENTOUT

COMP2_INM

27 40 40 A4 B4 56 A4 90 A7 PB4

(NJTRST) I/O FT_fa (3)

NJTRST, I2C3_SDA,

SPI1_MISO, SPI3_MISO,

USART1_CTS,

TSC_G2_IO1,

SAI1_MCLK_B,

EVENTOUT

COMP2_INP

28 41 41 B4 C4 57 C4 91 C5 PB5 I/O FT -

LPTIM1_IN1,

I2C1_SMBA,

SPI1_MOSI, SPI3_MOSI,

USART1_CK,

TSC_G2_IO2,

COMP2_OUT,

SAI1_SD_B,

TIM16_BKIN,

EVENTOUT

29 42 42 C4 B5 58 D3 92 B5 PB6 I/O FT_fa -

LPTIM1_ETR, I2C1_SCL,

USART1_TX,

TSC_G2_IO3,

SAI1_FS_B,

TIM16_CH1N,

EVENTOUT

COMP2_INP

30 43 43 D4 A6 59 C3 93 B4 PB7 I/O FT_fa -

LPTIM1_IN2, I2C1_SDA,

USART1_RX,

TSC_G2_IO4,

EVENTOUT

COMP2_INM,

PVD_IN

31 44 44 A5 C5 60 B4 94 A4 PH3/

BOOT0 I/O FT - EVENTOUT BOOT0

- 45 45 B5 C6 61 B3 95 A3 PB8 I/O FT_f -

I2C1_SCL, CAN1_RX,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1, EVENTOUT

- 46 46 C5 B6 62 A3 96 B3 PB9 I/O FT_f -

IR_OUT, I2C1_SDA,

SPI2_NSS, CAN1_TX,

SDMMC1_D5,

SAI1_FS_A, EVENTOUT

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

DS11453 Rev 3 69/208

STM32L431xx Pinouts and pin description

- - - - - - - 97 C3 PE0 I/O FT - TIM16_CH1, EVENTOUT -

- - - - - - - 98 A2 PE1 I/O FT - EVENTOUT -

32 47 47 A6 A7 63 D4 99 D3 VSS S - - - -

1 48 48 A7 A8 64 E4 100 C4 VDD S - - - -

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of

the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup

domain and RTC register descriptions in the RM0394 reference manual.

3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4

pins and the internal pull-down on PA14 pin are activated.

Table 15. STM32L431xx pin definitions (continued)

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

Notes

Pin functions

UFQFPN32

LQFP48

UFQFPN48

WLCSP49

WLCSP64

LQFP64

UFBGA64

LQFP100

UFBGA100

Alternate functions Additional

functions

Pinouts and pin description STM32L431xx

70/208 DS11453 Rev 3

Table 16. Alternate function AF0 to AF7(1)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2/

LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3

USART1/

USART2/

USART3

Port A

PA0-TIM2_CH1-----USART2_CTS

PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - USART2_RTS_

PA2-TIM2_CH3-----USART2_TX

PA3-TIM2_CH4-----USART2_RX

PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK

PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - -

PA6 - TIM1_BKIN - - - SPI1_MISO COMP1_OUT USART3_CTS

PA7 - TIM1_CH1N - - I2C3_SCL SPI1_MOSI - -

PA8MCOTIM1_CH1-----USART1_CK

PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX

PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX

PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS

PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_

PA13JTMS-SWDIOIR_OUT------

PA14 JTCK-SWCLK LPTIM1_OUT - - I2C1_SMBA - - -

PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_

STM32L431xx Pinouts and pin description

DS11453 Rev 3 71/208

Port B

PB0 - TIM1_CH2N - - - SPI1_NSS - USART3_CK

PB1-TIM1_CH3N-----

USART3_RTS_

PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - - -

PB3 JTDO-

TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_

PB4 NJTRST - - - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS

Port B

PB5 - LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK

PB6 - LPTIM1_ETR - - I2C1_SCL - - USART1_TX

PB7 - LPTIM1_IN2 - - I2C1_SDA - - USART1_RX

PB8----I2C1_SCL---

PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - -

PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX

PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX

PB12 - TIM1_BKIN - TIM1_BKIN_

COMP2 I2C2_SMBA SPI2_NSS - USART3_CK

PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS

PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO - USART3_RTS_

PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - -

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2/

LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3

USART1/

USART2/

USART3

Pinouts and pin description STM32L431xx

72/208 DS11453 Rev 3

Port C

PC0 - LPTIM1_IN1 - - I2C3_SCL - - -

PC1 - LPTIM1_OUT - - I2C3_SDA - - -

PC2 - LPTIM1_IN2 - - - SPI2_MISO - -

PC3 - LPTIM1_ETR - - - SPI2_MOSI - -

PC4-------USART3_TX

PC5-------USART3_RX

PC6--------

PC7--------

PC8--------

PC9--------

PC10------SPI3_SCKUSART3_TX

Port C

PC11------SPI3_MISOUSART3_RX

PC12------SPI3_MOSIUSART3_CK

PC13--------

PC14--------

PC15--------

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2/

LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3

USART1/

USART2/

USART3

STM32L431xx Pinouts and pin description

DS11453 Rev 3 73/208

Port D

PD0 - - - - - SPI2_NSS - -

PD1 - - - - - SPI2_SCK - -

PD2-------

USART3_RTS_

PD3 - - - - - SPI2_MISO - USART2_CTS

PD4 - - - - - SPI2_MOSI - USART2_RTS_

PD5-------USART2_TX

PD6-------USART2_RX

PD7-------USART2_CK

PD8-------USART3_TX

PD9-------USART3_RX

PD10-------USART3_CK

PD11-------USART3_CTS

PD12-------

USART3_RTS_

PD13--------

PD14--------

PD15--------

Port EPE0--------

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2/

LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3

USART1/

USART2/

USART3

Pinouts and pin description STM32L431xx

74/208 DS11453 Rev 3

Port E

PE1--------

PE2TRACECK-------

PE3TRACED0-------

PE4TRACED1-------

PE5TRACED2-------

PE6TRACED3-------

PE7-TIM1_ETR------

PE8-TIM1_CH1N------

PE9-TIM1_CH1------

PE10-TIM1_CH2N------

PE11-TIM1_CH2------

PE12 - TIM1_CH3N - - - SPI1_NSS - -

PE13 - TIM1_CH3 - - - SPI1_SCK - -

PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_

COMP2 - SPI1_MISO - -

PE15 - TIM1_BKIN - TIM1_BKIN_

COMP1 - SPI1_MOSI - -

Port H

PH0--------

PH1--------

PH3--------

1. Please refer to Table 17 for AF8 to AF15.

Table 16. Alternate function AF0 to AF7(1) (continued)

Port

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SYS_AF TIM1/TIM2/

LPTIM1 TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3

USART1/

USART2/

USART3

STM32L431xx Pinouts and pin description

DS11453 Rev 3 75/208

Table 17. Alternate function AF8 to AF15(1)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

LPUART1 CAN1/TSC QUADSPI

SDMMC1/

COMP1/

COMP2/

SWPMI1

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Port A

PA0 - - - - COMP1_OUT SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1 - - - - - TIM15_CH1N EVENTOUT

PA2 LPUART1_TX - QUADSPI_

BK1_NCS COMP2_OUT - TIM15_CH1 EVENTOUT

PA3 LPUART1_RX - QUADSPI_CLK - SAI1_MCLK_A TIM15_CH2 EVENTOUT

PA4-----SAI1_FS_BLPTIM2_OUTEVENTOUT

PA5------LPTIM2_ETREVENTOUT

PA6 LPUART1_CTS - QUADSPI_

BK1_IO3

TIM1_BKIN_

COMP2 - TIM16_CH1 EVENTOUT

PA7 - - QUADSPI_

BK1_IO2 COMP2_OUT - - EVENTOUT

PA8 - - - SWPMI1_IO SAI1_SCK_A LPTIM2_OUT EVENTOUT

PA9 - - - - SAI1_FS_A TIM15_BKIN EVENTOUT

PA10 - - - SAI1_SD_A - EVENTOUT

PA11 - CAN1_RX - TIM1_BKIN2_

COMP1 - - EVENTOUT

PA12 - CAN1_TX - - - - EVENTOUT

PA13 - - - SWPMI1_TX SAI1_SD_B - EVENTOUT

PA14 - - - - SWPMI1_RX SAI1_FS_B - EVENTOUT

PA15 - TSC_G3_IO1 - SWPMI1_

SUSPEND - - EVENTOUT

Pinouts and pin description STM32L431xx

76/208 DS11453 Rev 3

Port B

PB0 - - QUADSPI_

BK1_IO1 COMP1_OUT SAI1_EXTCLK - EVENTOUT

PB1 LPUART1_RTS

_DE -QUADSPI_

BK1_IO0 - - LPTIM2_IN1 EVENTOUT

PB2 - - - - - - EVENTOUT

PB3 - - - - SAI1_SCK_B - EVENTOUT

PB4 - TSC_G2_IO1 - - SAI1_MCLK_B - EVENTOUT

PB5 - TSC_G2_IO2 - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT

PB6 - TSC_G2_IO3 - - - SAI1_FS_B TIM16_CH1N EVENTOUT

PB7 - TSC_G2_IO4 - - - - EVENTOUT

PB8 - CAN1_RX - SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT

PB9 - CAN1_TX - SDMMC1_D5 SAI1_FS_A - EVENTOUT

PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK COMP1_OUT SAI1_SCK_A - EVENTOUT

PB11 LPUART1_TX - QUADSPI_

BK1_NCS COMP2_OUT - - EVENTOUT

PB12 LPUART1_RTS

_DE TSC_G1_IO1 - SWPMI1_IO SAI1_FS_A TIM15_BKIN EVENTOUT

PB13 LPUART1_CTS TSC_G1_IO2 - SWPMI1_TX SAI1_SCK_A TIM15_CH1N EVENTOUT

PB14 - TSC_G1_IO3 - SWPMI1_RX SAI1_MCLK_A TIM15_CH1 EVENTOUT

PB15 - TSC_G1_IO4 - SWPMI1_

SUSPEND SAI1_SD_A TIM15_CH2 EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

LPUART1 CAN1/TSC QUADSPI

SDMMC1/

COMP1/

COMP2/

SWPMI1

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

STM32L431xx Pinouts and pin description

DS11453 Rev 3 77/208

Port C

PC0 LPUART1_RX - - - - LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - - - - - EVENTOUT

PC2 - - - - - - EVENTOUT

Port C

PC3 - - - - SAI1_SD_A LPTIM2_ETR EVENTOUT

PC4 - - - - - - EVENTOUT

PC5 - - - - - - EVENTOUT

PC6 - TSC_G4_IO1 - SDMMC1_D6 - - EVENTOUT

PC7 - TSC_G4_IO2 - SDMMC1_D7 - - EVENTOUT

PC8 - TSC_G4_IO3 - SDMMC1_D0 - - EVENTOUT

PC9 - TSC_G4_IO4 SDMMC1_D1 - - EVENTOUT

PC10 - TSC_G3_IO2 - SDMMC1_D2 - - EVENTOUT

PC11 - TSC_G3_IO3 - SDMMC1_D3 - - EVENTOUT

PC12 - TSC_G3_IO4 - SDMMC1_CK - - EVENTOUT

PC13------ -EVENTOUT

PC14------ -EVENTOUT

PC15------ -EVENTOUT

Port D

PD0 - CAN1_RX - - - - - EVENTOUT

PD1 - CAN1_TX - - - - - EVENTOUT

PD2 - TSC_SYNC - SDMMC1_

CMD - - EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

LPUART1 CAN1/TSC QUADSPI

SDMMC1/

COMP1/

COMP2/

SWPMI1

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Pinouts and pin description STM32L431xx

78/208 DS11453 Rev 3

Port D

PD3 - - QUADSPI_BK2

_NCS - - - - EVENTOUT

PD4 - - QUADSPI_BK2

_IO0 - - - - EVENTOUT

PD5 - - QUADSPI_BK2

_IO1 - - - - EVENTOUT

PD6 - - QUADSPI_BK2

_IO2 - - SAI1_SD_A - EVENTOUT

PD7 - - QUADSPI_BK2

_IO3 - - - - EVENTOUT

PD8 - - - - - - EVENTOUT

PD9 - - - - - - EVENTOUT

PD10 - TSC_G6_IO1 - - - - EVENTOUT

PD11 - TSC_G6_IO2 - - - LPTIM2_ETR EVENTOUT

PD12 - TSC_G6_IO3 - - - LPTIM2_IN1 EVENTOUT

PD13 - TSC_G6_IO4 - - - LPTIM2_OUT EVENTOUT

PD14 - - - - - - EVENTOUT

PD15 - - - - - - EVENTOUT

Port E

PE0 - - - - - TIM16_CH1 EVENTOUT

PE1 - - - - - - EVENTOUT

PE2 - TSC_G7_IO1 - - SAI1_MCLK_A - EVENTOUT

PE3 - TSC_G7_IO2 - - SAI1_SD_B - EVENTOUT

PE4 - TSC_G7_IO3 - - - SAI1_FS_A - EVENTOUT

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

LPUART1 CAN1/TSC QUADSPI

SDMMC1/

COMP1/

COMP2/

SWPMI1

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

STM32L431xx Pinouts and pin description

DS11453 Rev 3 79/208

Port E

PE5 - TSC_G7_IO4 - - - SAI1_SCK_A - EVENTOUT

PE6-----SAI1_SD_A-EVENTOUT

PE7-----SAI1_SD_B-EVENTOUT

PE8-----SAI1_SCK_B-EVENTOUT

PE9-----SAI1_FS_B-EVENTOUT

PE10 - TSC_G5_IO1 QUADSPI_CLK - - SAI1_MCLK_B - EVENTOUT

PE11 - TSC_G5_IO2 QUADSPI_BK1

_NCS - - - - EVENTOUT

PE12 - TSC_G5_IO3 QUADSPI_BK1

_IO0 - - - - EVENTOUT

PE13 - TSC_G5_IO4 QUADSPI_BK1

_IO1 - - - - EVENTOUT

PE14 - - QUADSPI_BK1

_IO2 - - - - EVENTOUT

PE15 - - QUADSPI_BK1

_IO3 - - - - EVENTOUT

Port H

PH0------ -EVENTOUT

PH1------ -EVENTOUT

PH3------ -EVENTOUT

1. Please refer to Table 16 for AF0 to AF7.

Table 17. Alternate function AF8 to AF15(1) (continued)

Port

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

LPUART1 CAN1/TSC QUADSPI

SDMMC1/

COMP1/

COMP2/

SWPMI1

SAI1 TIM2/TIM15/

TIM16/LPTIM2 EVENTOUT

Memory mapping STM32L431xx

80/208 DS11453 Rev 3

5 Memory mapping

Figure 15. STM32L431xx memory map

MSv36892V2

0xFFFF FFFF

0xE000 0000

0xC000 0000

0xA000 1000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

Cortex™-M4

with FPU

Internal

Peripherals

SRAM1

CODE

OTP area

System memory

Flash memory

Flash, system memory

or SRAM, depending on

BOOT configuration

AHB2

AHB1

APB2

APB1

0x5006 0C00

0x4800 0000

0x4002 4400

0x4002 0000

0x4001 5800

0x4001 0000

0x4000 9800

0x4000 0000

0x1FFF FFFF

0x1FFF 0000

0x0804 0000

0x0800 0000

0x0004 0000

0x0000 0000

Reserved

0x1000 4000

0x1000 0000

SRAM2

QUADSPI

registers

Options Bytes

0x1FFF 7000

0x1FFF 7400

0x1FFF 7800

0x1FFF 7810

Reserved

QUADSPI registers

0xBFFF FFFF

0xA000 1400

0xA000 1000

Reserved

0x5FFF FFFF

0x9000 0000

QUADSPI Flash

bank

SRAM2

0x2000 C000

0xA000 0000

DS11453 Rev 3 81/208

STM32L431xx Memory mapping

Table 18. STM32L431xx memory map and peripheral register boundary addresses(1)

Bus Boundary address Size(bytes) Peripheral

AHB2

0x5006 0800 - 0x5006 0BFF 1 KB RNG

0x5004 0400 - 0x5006 07FF 158 KB Reserved

0x5004 0000 - 0x5004 03FF 1 KB ADC

0x5000 0000 - 0x5003 FFFF 16 KB Reserved

0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved

0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH

0x4800 1400 - 0x4800 1BFF 2 KB Reserved

0x4800 1000 - 0x4800 13FF 1 KB GPIOE

0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD

0x4800 0800 - 0x4800 0BFF 1 KB GPIOC

0x4800 0400 - 0x4800 07FF 1 KB GPIOB

0x4800 0000 - 0x4800 03FF 1 KB GPIOA

-0x4002 4400 - 0x47FF FFFF ~127 MB Reserved

AHB1

0x4002 4000 - 0x4002 43FF 1 KB TSC

0x4002 3400 - 0x4002 3FFF 1 KB Reserved

0x4002 3000 - 0x4002 33FF 1 KB CRC

0x4002 2400 - 0x4002 2FFF 3 KB Reserved

0x4002 2000 - 0x4002 23FF 1 KB FLASH registers

0x4002 1400 - 0x4002 1FFF 3 KB Reserved

0x4002 1000 - 0x4002 13FF 1 KB RCC

0x4002 0800 - 0x4002 0FFF 2 KB Reserved

0x4002 0400 - 0x4002 07FF 1 KB DMA2

0x4002 0000 - 0x4002 03FF 1 KB DMA1

APB2

0x4001 5800 - 0x4001 FFFF 42 KB Reserved

0x4001 5400 - 0x4000 57FF 1 KB SAI1

0x4001 4800 - 0x4000 53FF 3 KB Reserved

0x4001 4400 - 0x4001 47FF 1 KB TIM16

0x4001 4000 - 0x4001 43FF 1 KB TIM15

0x4001 3C00 - 0x4001 3FFF 1 KB Reserved

0x4001 3800 - 0x4001 3BFF 1 KB USART1

0x4001 3400 - 0x4001 37FF 1 KB Reserved

Memory mapping STM32L431xx

82/208 DS11453 Rev 3

APB2

0x4001 3000 - 0x4001 33FF 1 KB SPI1

0x4001 2C00 - 0x4001 2FFF 1 KB TIM1

0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1

0x4001 2000 - 0x4001 27FF 2 KB Reserved

0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL

0x4001 0800- 0x4001 1BFF 5 KB Reserved

0x4001 0400 - 0x4001 07FF 1 KB EXTI

0x4001 0200 - 0x4001 03FF

1 KB

COMP

0x4001 0030 - 0x4001 01FF VREFBUF

0x4001 0000 - 0x4001 002F SYSCFG

APB1

0x4000 9800 - 0x4000 FFFF 26 KB Reserved

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2

0x4000 8C00 - 0x4000 93FF 2 KB Reserved

0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1

0x4000 8400 - 0x4000 87FF 1 KB Reserved

0x4000 8000 - 0x4000 83FF 1 KB LPUART1

0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1

0x4000 7800 - 0x4000 7BFF 1 KB OPAMP

0x4000 7400 - 0x4000 77FF 1 KB DAC1

0x4000 7000 - 0x4000 73FF 1 KB PWR

0x4000 6800 - 0x4000 6FFF 2 KB Reserved

0x4000 6400 - 0x4000 67FF 1 KB CAN1

0x4000 6000 - 0x4000 63FF 1 KB CRS

0x4000 5C00- 0x4000 5FFF 1 KB I2C3

0x4000 5800 - 0x4000 5BFF 1 KB I2C2

0x4000 5400 - 0x4000 57FF 1 KB I2C1

0x4000 4C00 - 0x4000 53FF 2 KB Reserved

0x4000 4800 - 0x4000 4BFF 1 KB USART3

0x4000 4400 - 0x4000 47FF 1 KB USART2

0x4000 4000 - 0x4000 43FF 1 KB Reserved

0x4000 3C00 - 0x4000 3FFF 1 KB SPI3

0x4000 3800 - 0x4000 3BFF 1 KB SPI2

0x4000 3400 - 0x4000 37FF 1 KB Reserved

0x4000 3000 - 0x4000 33FF 1 KB IWDG

Table 18. STM32L431xx memory map and peripheral register boundary addresses(1)

(continued)

Bus Boundary address Size(bytes) Peripheral

DS11453 Rev 3 83/208

STM32L431xx Memory mapping

APB1

0x4000 2C00 - 0x4000 2FFF 1 KB WWDG

0x4000 2800 - 0x4000 2BFF 1 KB RTC

0x4000 1800 - 0x4000 27FF 4 KB Reserved

0x4000 1400 - 0x4000 17FF 1 KB TIM7

0x4000 1000 - 0x4000 13FF 1 KB TIM6

0x4000 0400- 0x4000 0FFF 3 KB Reserved

0x4000 0000 - 0x4000 03FF 1 KB TIM2

1. The gray color is used for reserved boundary addresses.

Table 18. STM32L431xx memory map and peripheral register boundary addresses(1)

(continued)

Bus Boundary address Size(bytes) Peripheral

Figure 16. Pin loading conditions 5L Figure 17. Pin input voltage

Electrical characteristics STM32L431xx

84/208 DS11453 Rev 3

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They

are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ±2).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 16.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 17.

Figure 16. Pin loading conditions Figure 17. Pin input voltage

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

DS11453 Rev 3 85/208

STM32L431xx Electrical characteristics

176

6.1.6 Power supply scheme

Figure 18. Power supply scheme

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic

capacitors as shown above. These capacitors must be placed as close as possible to, or

below, the appropriate pins on the underside of the PCB to ensure the good functionality of

the device.

MSv41628V1

VDD

Level shifter

logic

Kernel logic

(CPU, Digital

& Memories)

Backup circuitry

(LSE, RTC,

Backup registers)

OUT

Regulator

GPIOs

1.55 – 3.6 V

n x 100 nF

+1 x 4.7 μF

n x VSS

n x VDD

VBAT

VCORE

Power switch

VDDIO1

ADCs/

DACs/

OPAMPs/

COMPs/

VREFBUF

VREF+

VREF-

VDDA

10 nF

+1 μF

VDDA

VSSA

VREF

100 nF +1 μF

Electrical characteristics STM32L431xx

86/208 DS11453 Rev 3

6.1.7 Current consumption measurement

Figure 19. Current consumption measurement scheme

The IDD_ALL parameters given in Table 26 to Table 38 represent the total MCU consumption

including the current supplying VDD, VDDA and VBAT.

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,

Table 20: Current characteristics and Table 21: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability. Device mission profile (application conditions)

is compliant with JEDEC JESD47 qualification standard, extended mission profiles are

available on demand.

MSv41629V1

VBAT

VDD

VDDA

IDD

IDDA

IDD_VBAT

Table 19. Voltage characteristics(1)

Symbol Ratings Min Max Unit

VDDX - VSS

External main supply voltage (including

VDD, VDDA, VBAT)-0.3 4.0 V

VIN(2)

Input voltage on FT_xxx pins VSS-0.3 min (VDD, VDDA) + 4.0(3)(4)

VInput voltage on TT_xx pins VSS-0.3 4.0

Input voltage on any other pins VSS-0.3 4.0

|VDDx|Variations between different VDDX power

pins of the same domain -50mV

|VSSx-VSS|Variations between all the different ground

pins(5) -50mV

1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in

the permitted range.

2. VIN maximum must always be respected. Refer to Table 20: Current characteristics for the maximum allowed injected

current values.

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the inte<