MAX96705 Datasheet by Analog Devices Inc./Maxim Integrated

MAX96705 16-Bit GMSL Serializer with High-Immunity]
General Description
The MAX96705 is a compact serializer with features
especially suited for automotive camera applications. It is
function and pin compatible with the MAX9271. In high-
bandwidth mode, the parallel-clock maximum is 116MHz
for 12-bit linear or combined HDR data types.
The embedded control channel operates at 9.6kbps to
1Mbps in UART, I2C, and mixed UART/I2C modes, allow-
ing programming of serializer, deserializer, and camera
registers independent of video timing.
For driving longer cables, the IC has programmable
pre/deemphasis. Programmable spread spectrum is
available on the serial output. The serial output meets
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V, and the I/O supply range is
1.7V to 3.6V.
The MAX96705 is available in a 32-pin (5mm x 5mm)
TQFN package with 0.5mm lead pitch, and operates over
the -40°C to +115°C temperature range.
Applications
●Automotive Camera Applications
Benefits and Features
●Ideal for Safety Camera Applications
• Works with Low-Cost 50Ω Coax (100Ω STP) Cables
• Error Detection of Video/Control Data
• High-Immunity Mode for Robust Control-Channel
EMC Tolerance
• Retransmission of Control Data Upon Error
Detection
• Best-in-Class Supply Current: 93mA (max)
• Pre/Deemphasis Allows 15m Cable at Full Speed
• 32-Pin (5mm x 5mm) TQFN Package with 0.5mm
Lead Pitch
●High-Speed Data Serialization for Megapixel
Cameras
• Up to 1.74Gbps Serial-Bit Rate
• 12.5MHz to 87MHz x 14 Bit + H/V Data
• 36.66MHz to 116MHz x 12-Bit + H/V Data
(through Internal Encoding)
●Multiple Modes for System Flexibility
• 9.6kbps to 1Mbps Control Channel in UART, I2C
(with Clock Stretch), or UART-to-I2C Modes
• Crosspoint Switch Accepts Any Input Bitmap
• Modes for Encoded VSYNC and HSYNC
●Reduces EMI and Shielding Requirements
• Programmable Output Spread Spectrum
• Tracks Spread Spectrum Applied at the Parallel
Input
• 1.7V to 3.6V I/O Supply
●Peripheral Features for Camera Power-Up and
Verification
• Built-In PRBS Generator for BER Testing
• Dedicated GPO for Camera Frame-Sync Trigger
and Other Uses
• Remote/Local Wake-Up from Sleep Mode
●Meets AEC-Q100 Automotive Specification
• -40°C to +115°C Operating Temperature
• ±8kV Contact and ±15kV Air IEC 61000-4-2 and
ISO 10605 ESD Protection
Ordering Information appears at end of data sheet.
19-8434; Rev 1; 2/17
CAM MAX96705 MAX96706
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Simplified Block Diagram
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
EVALUATION KIT AVAILABLE
General Description ............................................................................ 1
Applications .................................................................................. 1
Benefits and Features .......................................................................... 1
Simplified Block Diagram........................................................................ 1
Absolute Maximum Ratings ...................................................................... 6
Package Information ........................................................................... 6
32-Pin TQFN-EP.............................................................................6
DC Electrical Characteristics ..................................................................... 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Operating Characteristics ................................................................ 13
Pin Configuration ............................................................................. 15
Pin Description ............................................................................... 15
Functional Block Diagram ...................................................................... 18
Detailed Description........................................................................... 23
Serial Link Signaling and Data Format ...........................................................23
Operating Modes .........................................................................23
Video/Configuration Link ...................................................................23
Single/Double Mode.......................................................................24
HS/VS Encoding .........................................................................24
Error Detection...........................................................................24
Bus Widths ..............................................................................24
Control Channel and Register Programming ......................................................28
Forward Control Channel...................................................................28
Reverse Control Channel...................................................................28
UART Interface ..........................................................................28
I2C Interface.............................................................................28
Remote-End Operation ....................................................................28
Clock-Stretch Timing ......................................................................28
Packet-Based I2C...........................................................................28
Packet Protocol Summary ..................................................................29
Control-Channel Error Detection and Packet Retransmission ......................................29
GPO/GPI Control ...........................................................................29
Spread Spectrum ...........................................................................29
Cable Type Configuration .....................................................................29
Crossbar Switch ............................................................................29
Video Timing Generator ......................................................................29
Shutdown/Sleep Modes ......................................................................31
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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TABLE OF CONTENTS
Configuration Link ........................................................................31
Serialization Disable ......................................................................31
Sleep Mode .............................................................................31
Power-Down Mode........................................................................32
Link Startup Procedure .......................................................................32
Register Map ................................................................................ 33
GMSL Register Map .........................................................................33
Applications Information........................................................................ 69
Parallel Interface ............................................................................69
Bus Data Width ..........................................................................69
Bus Data Rates ..........................................................................69
Crossbar-Switch Programming ..............................................................70
Recommended Crossbar-Switch Program Procedure ............................................70
Timing-Generator Programming ................................................................73
Double-Mode Alignment ......................................................................73
External High/Low Signal ..................................................................73
Align from HS or DE ......................................................................73
Control-Channel Interfaces....................................................................73
I2C ....................................................................................73
I2C Bit Rate .............................................................................73
Software Programming of Device Addresses ...................................................74
I2C Address Translation....................................................................74
Configuration Blocking.....................................................................74
Cascaded/Parallel Devices .................................................................74
UART ..................................................................................74
Base Mode ..............................................................................74
UART Timing ............................................................................74
UART-to-I2C Conversion ...................................................................76
UART Bypass Mode ......................................................................77
Device Address ..........................................................................77
Spread Spectrum ...........................................................................77
Manual Programming of the Spread-Spectrum Divider ..............................................77
Equation: ...............................................................................77
Board Layout ...............................................................................78
Power-Supply Circuits and Bypassing.........................................................78
High-Frequency Signals....................................................................78
ESD Protection .............................................................................78
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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TABLE OF CONTENTS (CONTINUED)
Compatibility with Other GMSL Devices .........................................................79
Device Configuration and Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Internal Input Pulldowns....................................................................79
Three-Level Configuration Inputs ............................................................79
I2C/UART Pullup Resistors .................................................................80
AC-Coupling Capacitors ...................................................................80
Cables and Connectors ....................................................................80
PRBS.....................................................................................80
GPI/GPO ..................................................................................80
Fast Detection of Loss-of-Lock ..............................................................81
Providing a Frame Sync (Camera Applications) .................................................81
Entering/Exiting Sleep Mode ..................................................................81
Typical Application Circuits ..................................................................... 82
Ordering Information .......................................................................... 82
Revision History .............................................................................. 83
Figure 1. Serial-Output Parameters............................................................... 18
Figure 2. Output Waveforms at OUT+, OUT-........................................................ 19
Figure 3. Single-Ended Output Template .......................................................... 19
Figure 4. Worst-Case Pattern Input ............................................................... 19
Figure 5. Parallel Clock Input Requirements ........................................................ 19
Figure 6. I2C Timing Parameters ................................................................. 20
Figure 7. Differential Output Template ............................................................. 20
Figure 8. Input Setup and Hold Times ............................................................. 21
Figure 9. GPI-to-GPO Delay .................................................................... 21
Figure 10. Serializer Delay...................................................................... 22
Figure 11. Link Startup Time .................................................................... 22
Figure 12. Power-Up Delay ..................................................................... 23
Figure 13. 24-Bit Mode Serial-Data Format......................................................... 25
Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format ........................................... 26
Figure 15. 32-Bit Mode Serial-Data Format......................................................... 27
Figure 16. Coax Connection .................................................................... 29
Figure 17. Crossbar Switch Dataflow .............................................................. 30
Figure 18. Sync-Signal Format For Video-Timing Generation .......................................... 30
Figure 19. State Diagram ....................................................................... 31
Figure 20. Crossbar-Switch Default Mapping ....................................................... 72
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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LIST OF FIGURES
TABLE OF CONTENTS (CONTINUED)
Figure 21. GMSL-UART Data Format for Base Mode ................................................. 75
Figure 22. GMSL-UART Protocol for Base Mode .................................................... 75
Figure 23. SYNC Byte (0x79).................................................................... 75
Figure 24. ACK Byte (0xC3)..................................................................... 75
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)........ 76
Figure 26. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) ........ 76
Figure 27. Human Body Model ESD Test Circuit ..................................................... 78
Figure 28. IEC 61000-4-2 Contact Discharge ESD Test Circuit ......................................... 78
Figure 29. ISO 10605 Contact Discharge ESD Test Circuit ............................................ 78
Table 1. Reverse Control-Channel Modes.......................................................... 28
Table 2. Link-Startup Procedure ................................................................. 31
Table 3. Input Data-Width Selection .............................................................. 68
Table 4. Data-Rate Selection.................................................................... 68
Table 5. Crossbar Output to Serial Link Map (D23:0) ................................................. 69
Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets) ............................... 70
Table 7. Legend .............................................................................. 71
Table 8. Timing-Generator Parameter Restrictions ................................................... 72
Table 9. Output Spread ........................................................................ 76
Table 10. Spread Limitations .................................................................... 76
Table 11. Modulation Coefficients and Maximum SDIV Settings ........................................ 77
Table 12. Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 13. Three-Level Configuration Input Map ..................................................... 79
Table 14. Suggested Connectors and Cables for GMSL............................................... 79
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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LIST OF TABLES
LIST OF FIGURES (CONTINUED)
AVDD to EP* ........................................................-0.5V to +1.9V
DVDD to EP* ........................................................-0.5V to +1.9V
IOVDD to EP* ....................................................... -0.5V to +3.9V
OUT+, OUT- to EP* .............................................. -0.5V to +1.9V
All Other Pins to EP* ............................-0.5V to (IOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation, TA = +70°C
TQFN (derate 34.5 mW/°C above +70°C) .............2758.6mW
Operating Temperature Range .......................... -40°C to +115°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -40°C to +150°C
Soldering Temperature (reflow) ....................................... +260°C
*EP connected to IC ground.
32-Pin TQFN-EP
Package Code T3255+8
Outline Number 21-0140
Land Pattern Number 90-0013
Single-Layer Board:
Junction-to-Ambient Thermal Resistance (θJA) 47
Junction-to-Case Thermal Resistance (θJC) 1.7
Four-Layer Board:
Junction-to-Ambient Thermal Resistance (θJA) 29
Junction-to-Case Thermal Resistance (θJC) 1.7
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP connected to PCB
ground, typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (LCCEN, DIN_, PCLKIN, HS, VS, DE, BWS, DBL, HIM, MS, HVEN, PWDNB)
High-Level Input Voltage VIH
0.65 x
VIOVDD
V
Low-Level Input Voltage VIL
0.35 x
VIOVDD
V
Input Current IIN VIN = 0 to VIOVDD -20 +20 μA
THREE-LEVEL INPUTS (CONF0, CONF1)
High-Level Input Voltage VIH
0.7 x
VIOVDD
V
Low-Level Input Voltage VIL
0.3 x
VIOVDD
V
Mid-Level Input Current IINM
Open or connected to a driver with output
in high impedance (Note 2) -10 +10 μA
Input Current IIN High or low, PWDNB high or low -220 +220 µA
SINGLE-ENDED OUTPUT (GPO)
High-Level Output
Voltage VOH IOH = -2mA VIOVDD
- 0.2 V
Low-Level Output
Voltage VOL IOL = 2mA 0.2 V
Output Short-Circuit Current IOS
VO = 0V, VIOVDD = 3.0V to 3.6V -16 -35 -64 mA
VO = 0V, VIOVDD = 1.7V to 1.9V -3 -12 -21
UART/I2C and GENERAL-PURPOSE I/Os (RX/SDA, TX/SCL, GPIO_) with OPEN-DRAIN OUTPUTS
High-Level Input Voltage VIH
0.7 x
VIOVDD
V
Low-Level Input Voltage VIL
0.3 x
VIOVDD
V
Input Current IIN
VIN = 0 to VIOVDD (Note 3),
RX/SDA, TX/SCL -110 +5 µA
VIN = 0 to VIOVDD (Note 3), GPIO_ -80 +5
Low-Level Open-Drain
Output Voltage VOL
IOL = 3mA, VIOVDD = 1.7V to 1.9V 0.4 V
IOL = 3mA, VIOVDD = 3.0V to 3.6V 0.3
Input Capacitance CIN Each pin (Note 4) 10 pF
DC Electrical Characteristics
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP connected to PCB
ground, typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFFERENTIAL OUTPUTS (OUT+, OUT-)
Differential Output Voltage VOD
Preemphasis off, high drive (Figure 1) 300 400 500
mV3.3dB preemphasis, high drive (Figure 2) 350 610
3.3dB deemphasis, high drive (Figure 2) 240 425
Change in VOD Between
Complementary Output
States
ΔVOD 25 mV
Output Offset Voltage
(VOUT+ + VOUT-)/2 = VOS
VOS Preemphasis off 1.1 1.4 1.56 V
Change in VOS Between
Complementary Output
States
ΔVOS 25 mV
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -60 mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential
Output Short-Circuit Current IOSD VOD = 0V 25 mA
Output-Termination
Resistance (Internal) ROFrom OUT+ or OUT- to AVDD 45 54 63 Ω
REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)
High-Switching Threshold VCHR
Legacy 27 mV
High immunity 40
Low-Switching Threshold VCLR
Legacy -27 mV
High immunity -40
SINGLE-ENDED SERIAL OUTPUTS (OUT+ or OUT-)
Single-Ended Output
Voltage VO
Preemphasis off, high drive (Figure 3) 375 500 625
mV3.3dB preemphasis, high drive (Figure 2) 435 765
3.3dB deemphasis, high drive (Figure 2) 300 535
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -69 mA
VOUT+ or VOUT- = 1.9V 32
Output-Termination
Resistance (Internal) ROFrom OUT+ or OUT- to AVDD 45 54 63 Ω
DC Electrical Characteristics (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP Connected to PCB
ground, typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Current, Worst-Case
Pattern (Figure 4)IWCS
fPCLKIN = 116MHz, HIBW = 0, BWS = 0,
default register values, AVDD + DVDD
(1.9V)
64 90
mA
fPCLKIN = 116MHz, HIBW = 0, BWS = 0,
default register values, IOVDD (3.6V) 1.8 2.7
fPCLKIN = 116MHz, HIBW = 0, BWS =
0, default register values, IOVDD (1.9V)
(Note 4)
0.45 0.69
fPCLKIN = 116MHz, HIBW = 1, BWS = 0,
default register values, AVDD + DVDD
(1.9V)
62 83
fPCLKIN = 116MHz, HIBW = 1, BWS = 0,
default register values, IOVDD (3.6V) 1.8 2.7
fPCLKIN = 116MHz, HIBW = 1, BWS =
0, default register values, IOVDD (1.9V)
(Note 4)
0.45 0.69
fPCLKIN = 87MHz, BWS = 1,
default register values, AVDD + DVDD
(1.9V)
61 85
fPCLKIN = 87MHz, BWS = 1, default
register values, IOVDD (3.6V) 1.4 2.0
fPCLKIN = 87MHz, BWS = 1, default
register values, IOVDD (1.9V) (Note 4) 0.37 0.61
Sleep-Mode Supply Current ICCS Wake-up receiver enabled 40 100 µA
Power-Down Supply Current ICCZ PWDNB = low 15 70 µA
ESD PROTECTION
OUT+, OUT- (Note 5) VESD
Human Body Model, RD = 1.5kΩ,
CS = 100pF ±8
kV
IEC 61000-4-2, RD = 330Ω, CS = 150pF,
Contact Discharge ±8
IEC 61000-4-2, RD = 330Ω, CS = 150pF,
Air Discharge ±15
ISO 10605, RD = 2kΩ, CS = 330pF,
Contact Discharge ±8
ISO 10605, RD = 2kΩ, CS = 330pF,
Air Discharge ±15
All Other Pins (Note 6) VESD
Human Body Model, RD = 1.5kΩ,
CS = 100pF ±4 kV
DC Electrical Characteristics (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP connected to PCB
ground, typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PARALLEL CLOCK INPUT (PCLKIN)
Clock Frequency fPCLKIN
BWS = 0, HIBW = 0, single input 16.66 58
MHz
BWS = 0, HIBW = 1, single input 36.66 58
BWS = 1, single input 12.5 43.5
BWS = 0, HIBW = 0, double input 33.32 116
BWS = 0, HIBW = 1, double input 73.33 116
BWS = 1, double input 25 87
Clock Duty Cycle DC tHIGH/tT or tLOW/tT (Note 4, Figure 5) 35 50 65 %
Clock Transition Time tR, tF(Note 4, Figure 5) 4 ns
Clock Jitter tJ
1.74Gbps bit rate, 300kHz sinusoidal jitter
(Note 4) 800 ps
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
Output Rise Time tR30% to 70%, CL = 10pF to 100pF, 1kΩ
pullup to IOVDD 20 150 ns
Output Fall Time tF70% to 30%, CL = 10pF to 100pF, 1kΩ
pullup to IOVDD 20 150 ns
I2C TIMING (Figure 6)
SCL Clock Frequency fSCL
Low fSCL range: (I2CMSTBT = 010,
I2CSLVSH = 10) 9.6 100
kHz
Mid fSCL range: (I2CMSTBT 101,
I2CSLVSH = 01) > 100 400
High fSCL range: (I2CMSTBT = 111,
I2CSLVSH = 00) > 400 1000
START Condition Hold Time tHD:STA
fSCL range, low 4
µsfSCL range, mid 0.6
fSCL range, high 0.26
Low Period of SCL Clock tLOW
fSCL range, low 4.7
µsfSCL range, mid 1.3
fSCL range, high 0.5
High Period of SCL Clock tHIGH
fSCL range, low 4
µsfSCL range, mid 0.6
fSCL range, high 0.26
Repeated START Condition
Setup Time tSU:STA
fSCL range, low 4.7
µsfSCL range, mid 0.6
fSCL range, high 0.26
AC Electrical Characteristics
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP connected to PCB
ground, typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Hold Time tHD:DAT
fSCL range, low 0
nsfSCL range, mid 0
fSCL range, high 0
Data Setup Time tSU:DAT
fSCL range, low 250
nsfSCL range, mid 100
fSCL range, high 50
Setup Time for STOP
Condition tSU:STO
fSCL range, low 4
µsfSCL range, mid 0.6
fSCL range, high 0.26
Bus-Free Time tBUF
fSCL range, low 4.7
µsfSCL range, mid 1.3
fSCL range, high 0.5
Data Valid Time tVD:DAT
fSCL range, low 3.45
µsfSCL range, mid 0.9
fSCL range, high 0.45
Data Valid-Acknowledge
Time tVD:ACK
fSCL range, low 3.45
µsfSCL range, mid 0.9
fSCL range, high 0.45
Pulse Width of Spikes
Suppressed tSP
fSCL range, low 50
nsfSCL range, mid 50
fSCL range, high 50
Capacitive Load of Each
Bus Line CBNote 4 100 pF
SWITCHING CHARACTERISTICS (Note 4)
Differential/Single-Ended
Output Rise/Fall Time tR, tF
20% to 80%, VOD, 400mV differential RL
= 100Ω, 500mV single-ended RL = 50Ω,
serial bit rate = 1.74Gbps
250 ps
Total Serial-Output Jitter
(Differential Output) tTSOJ1
1.74Gbps PRBS, measured at VOD = 0V
differential, preemphasis disabled (Figure 7)0.25 UI
Deterministic Serial-Output
Jitter (Differential Output) tDSOJ2
1.74Gbps PRBS, measured at VOD = 0V
differential, preemphasis disabled (Figure 7)0.15 UI
Total Serial-Output Jitter
(Single-Ended Output) tTSOJ1
1.74Gbps PRBS, measured at VO/2,
preemphasis disabled (Figure 3)0.25 UI
Deterministic Serial-Output
Jitter (Single-Ended Output) tDSOJ2
1.74Gbps PRBS, measured at VO/2,
preemphasis disabled (Figure 3)0.15 UI
Parallel Data-Input Setup
Time tSET (Figure 8) 2 ns
AC Electrical Characteristics (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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Note 1: Limits are 100% production tested at TA = +115°C. Limits over the operating temperature range are guaranteed by design
and characterization, unless otherwise noted.
Note 2: To provide a mid-level voltage, leave the input open; or, if driven, put the driver in high-impedance state. High-impedance
leakage current must be less than ±10μA.
Note 3: IIN min is due to voltage drop across the internal pullup resistor.
Note 4: Not production tested. Guaranteed by design.
Note 5: Specified pin to ground.
Note 6: Specified pin to all supply/ground.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = 0; bit time = 1/(40 x fPCLKIN) for BWS = 1.
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +115°C, EP connected to PCB
ground, typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Parallel Data Input Hold
Time tHOLD (Figure 8) (Note 4) 1 ns
GPI-to-GPO Delay tGPIO Deserializer GPI to serializer GPO (Figure 9) 350 µs
Serializer Delay tSD
Spread spectrum enabled (Figure 10)
(Notes 4, 7) 2065
Bits
Spread spectrum disabled (Figure 10)
(Notes 4, 7) 1095
Link Start Time tLOCK (Figure 11) 2 ms
Power-Up Time tPU (Figure 12) 7 ms
AC Electrical Characteristics (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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12
SUPPLY CURRENY vs SUPPLY CHRRENT vs. um DB
(VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.)
40
45
50
55
60
65
70
75
15 35 55 75 95 115
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 0, HIBW = 1) toc02
PRBS ON,
COAX
MODE,
SS OFF
PE OFF
PE = 0xB to 0xF
PE = 0x1 to 0x4
DBL = 1
DBL = 0
40
45
50
55
60
65
70
75
15 35 55 75 95 115
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 0, HIBW = 0) toc01
PRBS ON,
COAX
MODE,
SS OFF
PE OFF
PE = 0xB to 0xF
PE = 0x1 to 0x4
DBL = 1
DBL = 0
40
45
50
55
60
65
70
10 30 50 70 90
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 1, HIBW = 0) toc03
PRBS ON,
COAX
MODE,
SS OFF
PE OFF
PE = 0xB to 0xF
PE = 0x1 to 0x4
DBL = 1
DBL = 0
40
45
50
55
60
65
15 35 55 75 95 115
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 0, HIBW = 0) toc04
PRBS ON,
COAX
MODE,
PE OFF
ALL SPREAD VALUES
DBL = 1
DBL = 0
40
45
50
55
60
65
15 35 55 75 95 115
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 0, HIBW = 1) toc05
PRBS ON,
COAX
MODE,
PE OFF
ALL SPREAD VALUES
DBL = 1
DBL = 0
40
45
50
55
60
65
10 30 50 70 90
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY
(BWS = 1, HIBW = 0) toc06
PRBS ON,
COAX
MODE,
PE OFF
ALL SPREAD
VALUES
DBL = 1
DBL = 0
Typical Operating Characteristics
Maxim Integrated
│
13
www.maximintegrated.com
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
amPuI POWER SPECYRUM vs. ouIPur POWER sPEchuM vs. SUFFLYCURRENTIIMI MAXIMUM PIXEL CLOCK rREquEch vs. MAXIMUM PIXEL cLocK FREQUENCY vs. SERIAL LINK SWITCHING PATIERN SERIAL LINK swncIIIIIG FAnERN erII Ame FREEMPHASIS wmI 3.345 FREEMPHASIS (1.55m. Inm srr CAELE) (1.55hps,10m coAx CABLE)
(VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.)
-80
-70
-60
-50
-40
-30
-20
-10
0
10
18.5 19.0 19.5 20.0 20.5 21.0 21.5
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM vs.
PCLK FREQUENCY
(VARIOUS SPREAD) toc07
fPCLKIN = 20MHz
4% SPREAD
2% SPREAD
1% SPREAD 0.5% SPREAD
NO SPREAD
-80
-70
-60
-50
-40
-30
-20
-10
0
10
47 48 49 50 51 52 53
SUPPLY CURRENT (mA)
PIXEL CLOCK FREQUENCY (MHz)
OUTPUT POWER SPECTRUM vs.
PCLK FREQUENCY
(VARIOUS SPREAD) toc08
fPCLKIN = 50MHz
4% SPREAD
2% SPREAD
1% SPREAD 0.5% SPREAD
NO SPREAD
0
10
20
30
40
50
60
70
0 5 10 15 20 25
PIXEL CLOCK FREQUENCY (MHz)
STP CABLE LENGTH (m)
MAXIMUM PIXEL CLOCK FREQUENCY vs.
STP CABLE LENGTH
(BER < 10-10)toc09
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
AEQ
NO EQ
4.3dB EQ
9.7dB EQ
NO PE, DBL = 0
0
10
20
30
40
50
60
70
010 20 30 40
PIXEL CLOCK FREQUENCY (MHz)
COAX CABLE LENGTH (m)
MAXIMUM PIXEL CLOCK FREQUENCY vs.
COAX CABLE LENGTH (BER < 10-10)
toc10
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
AEQ
NO EQ
4.3dB EQ
NO PE, DBL = 0
100mV/div
toc11
200ps/div
SERIAL LINK SWITCHING PATTERN
WITH 4.4dB PREEMPHASIS
(1.5Gbps, 10m STP CABLE)
50mV/div
toc12
200ps/div
SERIAL LINK SWITCHING PATTERN
WITH 3.3dB PREEMPHASIS
(1.5Gbps, 20m COAX CABLE)
Typical Operating Characteristics (continued)
Maxim Integrated
│
14
www.maximintegrated.com
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
PIN NAME FUNCTION REF SUPPLY TYPE
POWER
5, 22 AVDD
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1μF, and
0.001μF capacitors as close as possible to the device with the
smaller value capacitor closest to AVDD.
Power
12 IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass
IOVDD to EP with 0.1μF and 0.001μF capacitors as close as
possible to the device with the smaller value capacitor closest to
IOVDD.
Power
29 DVDD
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1μF, and
0.001μF capacitors as close as possible to the device with the
smaller value capacitor closest to DVDD.
Power
EP —
Exposed Pad. EP is internally connected to device ground. Must
connect EP to the PCB ground plane through a via array for proper
thermal and electrical performance.
Power
Pin Configuration
Pin Description
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
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PIN NAME FUNCTION REF SUPPLY TYPE
HIGH-SPEED DIGITAL
Single Function
1 DIN6 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
2 DIN7 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
3 DIN8 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
4 DIN9 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
25 PCLKIN Parallel Clock Input with Internal Pulldown to EP. Latches parallel
data inputs and provides the PLL reference clock. IOVDD Digital
26 DIN0 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
27 DIN1 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
28 DIN2 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
30 DIN3 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
31 DIN4 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
32 DIN5 Parallel Data Input. Internal pulldown to EP. IOVDD Digital
Multifunction
6 DIN10/GPIO2
Parallel Data Input/GPIO. Defaults to parallel data input on power-
up. Parallel data input has internal pulldown to EP. GPIO2 has an
open-drain input/output with internal 60kΩ pullup to IOVDD.
IOVDD Digital
7 DIN11/GPIO3
Parallel Data Input/GPIO. Defaults to parallel data input on power-
up. Parallel data input has internal pulldown to EP. GPIO3 has an
open-drain input/output with internal 60kΩ pullup to IOVDD.
IOVDD Digital
8 DIN12/GPIO4
Parallel Data Input/GPIO. Defaults to parallel data input on power-
up. Parallel data input has internal pulldown to EP. GPIO4 has an
open-drain input/output with internal 60kΩ pullup to IOVDD.
IOVDD Digital
9DIN13/
GPIO5/DE
Parallel Data Input/GPIO/Data Enable with Internal Pulldown to EP.
Defaults to parallel data input on power-up. GPIO5 has an open-
drain input/output with internal 60kΩ pullup to IOVDD. Data enable
input in high-bandwidth mode.
IOVDD Digital
10 DIN14/HS
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP.
Defaults to parallel data input on power-up. Defaults to horizontal-
sync input when HS/VS encoding is enabled, or when in high-
bandwidth mode.
IOVDD Digital
11 DIN15/VS
Parallel Data Input/Vertical Sync with Internal Pulldown to EP.
Defaults to parallel data input on power-up. Defaults to vertical-
sync input when HS/VS encoding is enabled, or when in high-
bandwidth mode.
IOVDD Digital
Multifunction Configuration (from LCCEN)
14 GPIO1/BWS
GPIO1/Bus-Width Select Input. Function is determined by the state
of LCCEN. GPIO1 (LCCEN = high): Open-drain, general-purpose
input/output with internal 60kΩ pullup to IOVDD. BWS (LCCEN =
low): Input with internal pulldown to EP. Set BWS = low for 22-bit
input latch. Set BWS = high for 30-bit input latch.
IOVDD Digital
Pin Description (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
16
PIN NAME FUNCTION REF SUPPLY TYPE
15 MS/HVEN
Mode-Select/HS and VS Encoding Enable Input with Internal
Pulldown to EP. Function is determined by the state of LCCEN.
MS (LCCEN high): Set MS low to select base mode. Set MS high
to select bypass mode. HVEN: (LCCEN low): Set HVEN = high to
enable HS/VS encoding. Set HVEN = low to disable HS/VS
encoding.
IOVDD Digital
17 LCCEN
Local Control-Channel Enable input with internal Pulldown to EP.
LCCEN = high enables the control-channel interface pins. LCCEN
= low disables the control-channel interface pins and selects an
alternate function on the indicated pins.
IOVDD Digital
24 TX/SCL/DBL
Transmit/Serial Clock/Double Mode. Function is determined by the
state of LCCEN. TX/SCL (LCCEN = high): Input/output with internal
30kΩ pullup to IOVDD. In UART mode, TX/SCL is the Tx output of
the serializer's UART. In I2C mode, TX/SCL is the SCL input/output
of the serializer's I2C master/slave. TX/SCL has an open-drain
driver and requires a pullup resistor. DBL (LCCEN = low): Input with
internal pulldown to EP. Set DBL = high to use double-input mode.
Set DBL = low to use single-input mode.
IOVDD Digital
Configuration and Interface
13 GPO/HIM
General-Purpose Output/High-Immunity Mode Input with internal
Pulldown to EP. HIM is latched at power-up or when resuming from
power-down mode (PWDNB = low), and switches to GPO output
automatically after power-up. Connect HIM to IOVDD with a 30kΩ
resistor to set high, or leave open to set low. HIGHIMM can be
programmed to a different value after power-up. HIGHIMM in the
deserializer must be set to the same value. GPO output follows the
state of the GPI (or INT) input on the GMSL deserializer. GPO is
low upon power-up or when PWDNB is low.
IOVDD Digital
16 PWDNB
Active-Low, Power-Down Input with Internal Pulldown to EP.
To reduce power consumption, set PWDNB low to enter power-
down mode.
IOVDD Digital
18 CONF0
Configuration 0. Three-level configuration input (Table 13). CONF0
pin value is latched at power-up, or when resuming from power-
down mode.
IOVDD 3-Level
19 CONF1
Configuration 1. Three-level configuration input (Table 13). CONF1
pin value is latched at power up or when resuming from power-
down mode.
IOVDD 3-Level
20 OUT- Inverting Coax/Twisted-Pair Serial Output. Digital
21 OUT+ Noninverting Coax/Twisted-Pair Serial Output Digital
23 RX/SDA
Receive/Serial Data. Input/output with internal 30kΩ pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the serializer's
UART. In I2C mode, RX/SDA is the SDA input/output of the
serializer's I2C master/slave. RX/SDA has an open-drain driver and
requires a pullup resistor.
IOVDD Digital
Pin Description (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
17
REVERSE CONTROL TX SJ so mm) ‘
Figure 1. Serial-Output Parameters
Functional Block Diagram
OUT-
VOD
VOS
GND
RL/2
RL/2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
VOS(-) VOS(+)
((OUT+) + (OUT-))/2
VOS(-)
VOD(-)
VOD(-)
VOD = 0V
DVOS = |VOS(+) - VOS(-)|
DVOD = |VOD(+) - VOD(-)|
VOD(+)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
18
Figure 2. Output Waveforms at OUT+, OUT-
Figure 3. Single-Ended Output Template
Figure 4. Worst-Case Pattern Input
Figure 5. Parallel Clock Input Requirements
OUT+
OUT-
VOS VOD(P) VOD(D)
SERIAL-BIT
TIME
OUT+
OR
OUT-
VO/2 VO/2
VOVO
PCLKIN
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
DIN_
VIL MAX
tHIGH
tLOW
tT
tR
tF
VIH MIN
PCLKIN
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
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g3 l 1301‘}
Figure 6. I2C Timing Parameters
Figure 7. Differential Output Template
PROTOCOL
SCL
SDA
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
tSU;STA
VIOVDD x 0.7
VIOVDD x 0.7
VIOVDD x 0.3
VIOVDD x 0.3
tLOW tHIGH
tBUF
tHD;STA
tr
tSP
tf
tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO
1/fSCL
800mVP-P
tTSOJ1
2
tTSOJ1
2
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
20
3‘7 4.; 97 4.;
Figure 8. Input Setup and Hold Times
Figure 9. GPI-to-GPO Delay
VIH MIN
VIH MIN
VIH MIN
VIL MAX VIL MAX
VIL MAX
PCLKIN
DIN_
tHOLD
tSET
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
tGPIO tGPIO
VOH_MIN
VOL_MAX
VIH_MIN
VIL_MAX
DESERIALIZER
GPI
SERIALIZER
GPO
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
21
KS
Figure 10. Serializer Delay
Figure 11. Link Startup Time
tSD FIRST BIT LAST BIT
N
N+3
EXPANDED TIME SCALE
N+4
NN+1 N+2
N-1
DIN_
PCLKIN
OUT+/-
SERIAL LINK INACTIVE SERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
ENABLED
tLOCK
500Fs
PCLKIN
REVERSE CONTROL CHANNEL
AVAILABLE
PWDNB MUST BE HIGH
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
22
Detailed Description
The MAX96705 is a compact device with features
especially suited for automotive camera applications. The
device operates at a variety of input widths and word
rates up to a total serial-data rate up to 1.74Gbps. High-
bandwidth mode offers a 116MHz parallel clock rate with
12 bits of video data and 2 bits of sync (HS/VS) data. An
embedded 9.6kbps to 1Mbps control channel programs
the serializer, deserializer, and any attached UART or I2C
peripherals.
To promote safety applications, the device features
CRC protection of video and control data. In addition,
control-channel retransmission and high-immunity modes
reduce the effects of bit errors corrupting communica-
tion. Preemphasis and a PRBS tester allow for in-system
evaluation and optimization of the link quality.
This MAX96705 operates over the -40°C to +115°C
automotive temperature range.
Serial Link Signaling and Data Format
The serializer scrambles the input parallel data and
combines this with the forward control data. The data is
then encoded for transmission and output as a single-
serialized bitstream at several times the input word rate
(depending on bus width). The deserializer receives the
serial data and recovers the clock signal. The data is then
deserialized, decoded, and descrambled into parallel out-
put data and forward control data.
Operating Modes
The GMSL devices are configurable to operate in many
modes depending on the application. These modes allow
for a more efficient use of serial bandwidth. Most of these
settings are set during system design, and are configured
using the external configuration pins or through register
bits.
Video/Configuration Link
In normal operation, the serializer runs in video link mode
(serializer SEREN = 1) with video data and control data
sent across the serial link. Set SEREN = 0 in the serializer
to turn off serialization. The serializer powers up in video
link mode and requires a valid PCLK for operation.
A configuration link is available to set up the serializer,
deserializer, and peripherals when PCLK is not available.
Set SEREN = 0 and CLINK = 1 in the serializer to enable
the configuration link (SEREN = 1 forces the serializer into
video link mode). Once PCLK has been established, turn
on the video link (SEREN = 1).
By default, video link mode requires a valid PCLK for
operation. Set AUTO_CLINK bit = 1 and SEREN = 1 in the
serializer to have the device automatically switch between
the video link and configuration link whenever PCLK is
not present.
Figure 12. Power-Up Delay
PWDNB
POWERED DOWN
VIH1
tPU
REVERSE CONTROL CHANNEL DISABLED
500µs
PCLKIN
POWERED UP,
SERIAL LINK INACTIVE POWERED UP, SERIAL LINK ACTIVE
REVERSE CONTROL
CHANNEL ENABLED
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23
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Single/Double Mode
Single-/double-mode operation configures the available
1.74Gbps bandwidth into a variety of widths and word
rates. Single-mode operation is compatible with all GMSL
devices and serializers, yielding one parallel word for
each serial word. Double mode serializes two half-width
parallel words for each serial word, resulting in a 2x
increase in the parallel word rate range (compared to
single mode). Set DBL = 0 for single-mode operation and
DBL = 1 for double-mode operation.
HS/VS Encoding
By default, GMSL assigns a video bit slot to HSYNC,
VSYNC, and DE (if used). With HS/VS encoding, the
device instead encodes special packets to sync signals to
free up additional video bit slots. HS/VS encoding is on by
default when the device is in high-bandwidth mode (HIBW
= 1). DE is encoded only when HIBW = 1 and DE_EN =
1. Set HVEN = 1 to turn on HS/VS encoding when HIBW
= 0 (DE, if enabled, uses up a video bit). HS/VS encoding
requires that HSYNC, VSYNC, and DE (if used) remain
high during the active video and low during the blanking
period. Use HS/VS inversion when using reverse-polarity
sync signals.
Error Detection
The serial link's 8b/10b encoding/decoding and 1-bit
parity detect bit errors that occur on the serial link. An
optional 6-bit CRC check is available at the expense of 6
video bits (when HIBW = 0). To activate 6-bit CRC mode,
set PXL_CRC = 1 in the remote-side device first, then in
the local-side device. When using 6-bit CRC mode, the
available internal bus width is reduced by 6 bits in single-
input mode (DBL = 0) and 3 bits in double-input mode
(DBL = 1). Note that the input bus width may already have
been reduced due to pin availability of the serializer or
deserializer; thus, the reduction of bandwidth from CRC
may not be visible (see Table 3).
An additional 32-bit video line CRC is available by
setting LINE_CRC_EN = 1. When enabled, the serializer
calculates the 32-bit CRC of the video line and sends this
information during the blanking period. The deserializer
compares the received CRC with the video line data. The
deserializer's LINE_CRC_ERR bit latches when a CRC
error is detected. LINE_CRC_ERR clears when read.
Bus Widths
The serial link has multiple bus-width settings that
determine the parallel bus width and the resulting parallel
word rate. The serial link operates to a maximum serial
bit rate of 1.74Gbps. The BWS bit determines if each
serial packet is 30 or 40 bits long, which translates to a
maximum serial packet rate (and resulting maximum
parallel word rate) of 58MHz or 43.5MHz when BWS = 0
or 1 respectively. Encoding translates the 24, 27, or 32
parallel bits into 30- or 40-bit serial packets. One bit is
used for parity, while a second is reserved for the control
channel. An additional 6 bits are used during optional
6-bit CRC. In addition, double mode splits the remaining
word size in half, if used. The remaining bits can be used
for video bits (minus any sync bits if H/V encoding is not
used)
The following modes list the internal bus widths. The
number of available input and output pins may limit the
actual bus width available.
●24-Bit Mode (Figure 13)
When BWS = 0 and HIBW = 0, the 30-bit serial packet
corresponds with three 8b/10b symbols representing 24
bits (24-bit mode). After the parity and control channel,
this leaves 16/22 bits of video data if CRC is/or is not used
(single mode), or 8/11 bits of video data if CRC is/or is not
used (double mode).
●27-Bit High-Bandwidth Mode (Figure 14)
When BWS = 0 and HIBW = 1 (high-bandwidth mode),
the 30-bit serial packet represents three 9b/10b symbols
representing 27 bits. After the parity and control channel,
this leaves 19/25 bits of video data if CRC is/or is not used
(single mode), or 9/12 bits of video data if CRC is/or is not
used (double mode).
●32-Bit Mode (Figure 15)
When BWS = 1, the 40-bit serial packet corresponds with
four 8b/10b symbols representing 32 bits (32-bit mode).
After parity and control channel, this leaves 24/30 bits of
video data if CRC is/or is not used (single mode), or 12/15
bits of video data if CRC is/or is not used (double mode).
www.maximintegrated.com Maxim Integrated
│
24
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
/\, A, mg: H ‘5 VIDEO ND PXLVCRE um qu \
Figure 13. 24-Bit Mode Serial-Data Format
24-BIT
MODE
PACKET PARITY-
CHECK BIT
FCC PCBD0 D1 D21D20
D19D18D17
SERIAL
DATA
NO PXL_CRC
RX/
SDA
TX/
SCL
UART/I
2
C
FORWARD
CONTROL-CHANNEL
BIT
D0 D1 D21 D0 D1 D15 D21
D20D19D18D17
2 BITS
16 VIDEO
BITS
D16D15
22 BITS
22 VIDEO
BITS
D16
6
PXL_CRC
BITS
PXL_CRC ON
PXL_CRC
DBL = 0
D0 D1 D21
22 VIDEO
BITS*
DBL = 1
D0 D1 D10
D11 D12 D21
11 x 2
VIDEO
BITS*
D0 D1 D15
16 VIDEO
BITS*
D0 D1 D7
D8 D9 D15
8 x 2
VIDEO
BITS*
DBL = 0 DBL = 1
NO PXL_CRC, DBL = 0
58MHz (max) NO PXL_CRC, DBL = 1
116MHz (max)
PXL_CRC ON, DBL = 0
58MHz (max) PXL_CRC ON, DBL = 1
116MHz (max)
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
25
ND mp7s um um , w VIDEO /¥ aws‘ . A ‘ ‘ , ‘ ‘ AC
Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
www.maximintegrated.com Maxim Integrated
│
26
NO PXLVCRE H DEO A 2mm)
Figure 15. 32-Bit Mode Serial-Data Format
32-BIT
MODE
PACKET
PARITY-
CHECK BIT
FCC PCB
D0 D1 D24D23 D29D28D27
SERIAL
DATA
NO PXL_CRC
RX/
SDA
TX/
SCL
UART/I
2
C
FORWARD
CONTROL-CHANNEL
BIT
D0 D2 D29 D0 D2 D23 D29D28D27D26D25
2 BITS
24 VIDEO
BITS
D26D25
30 BITS
30 VIDEO
BITS
D24
6
PXL_CRC
BITS
PXL_CRC ON
PXL_CRC
D0 D1 D29
30 VIDEO
BITS*
D0 D1 D14
D15 D16 D29
15 x 2
VIDEO
BITS*
D0 D1 D23
24 VIDEO
BITS*
D0 D1 D11
D12 D13 D23
12 x 2
VIDEO
BITS*
DBL = 0 DBL = 1
DBL = 0 DBL = 1
NO PXL_CRC, DBL = 0
43.5MHz (max) NO PXL_CRC, DBL = 1
87MHz (max)
PXL_CRC ON, DBL = 0
43.5MHz (max) PXL_CRC ON, DBL = 1
87MHz (max)
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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X = Don’t care.
Control Channel and Register Programming
The control channel sends information across the serial
link for control of the serializer, deserializer, and any
attached peripherals. The control channel is multiplexed
onto the serial link and is available with or without the
video channel.
Forward Control Channel
Control data sent from the serializer to the deserializer is
sent on the forward control channel. The data is encoded
as one of the serial bits in the forward high-speed link. After
deserialization, the forward control-channel data is extract-
ed from the serial link. The forward control-channel band-
width exceeds the maximum external control data rate, and
all data sent on the forward control channel appears on
the remote side after transmission delay of a few bit times.
Reverse Control Channel
Control data sent from the deserializer to the serial-
izer is sent on the reverse control channel. The data is
encoded as a series of 1μs pulses, with a maximum raw
data rate of 1Mbps. High-immunity mode is available to
increase the robustness of the reverse control channel
at a reduced raw bit rate of 500kbps. In Table 1, setting
the REV_FAST bit = 1 increases this rate back to 1Mbps.
In I2C mode, when the input data rate (after encoding)
exceeds the reverse data rate, the input clock is held
through clock stretching to slow the external clock to
match the internal bit rate.
UART Interface
The UART interface, compatible with all GMSL devices,
sends commands from device to device through several
UART packets. Two modes are available: base mode
and bypass mode. Base mode is used to communicate
with the serializer, deserializer, and to I2C peripherals
using UART-to-I2C translation. Bypass mode allows for
full-duplex UART communication to peripherals using any
UART protocol.
I2C Interface
The serial link connects the serializer and deserializer I2C
interfaces together through the control channel. When
an I2C master sends a command to one side of the link
(local side) the control channel forwards this information
to and from the other side of the link (remote side), allow-
ing a single microcontroller to configure the serializer,
deserializer, and peripherals. The microcontroller can be
located on the serializer side (display applications) and
the deserializer side (camera applications). Dual micro-
controller operations are supported as long as a software-
arbitration method is used. The serial link assumes that
only one microcontroller is talking at any given time.
Remote-End Operation
When an I2C master initiates communication on the local
slave device (the serializer/deserializer directly connected
to the master), the remote-side device acts as a master
device that sends data forwarded from the local-side
device, and forwards any data received from peripher-
als attached to the remote-side device. This remote-
side master device operates according to the timing
settings in the I2C master setting register. Set the master
settings to match the timing settings used by the
external microcontroller.
Clock-Stretch Timing
The I2C interface uses clock stretching to allow time for
data to be forwarded across the serial link. The master
microcontroller, along with any attached peripherals, must
accept clock stretching of the GMSL devices.
Packet-Based I2C
A packet-based control channel is available for enhanced
error handling of the control channel. This control-
channel method handles simultaneous GPI/GPO and
I2C transmission, along with error detection and retrans-
mission.
HIM PIN SETTING REVFAST BIT REVERSE CONTROL-CHANNEL
MODE
MAXIMUM UART/I2C BIT
RATE (kBPS)
Low X
Legacy reverse control-channel
mode (compatible with all GMSL
devices)
1000
High
0 High-immunity mode 500
1
Fast high-immunity mode
(requires HIBW = 0, serial-data
rate > 1.25Gbps)
1000
Table 1. Reverse Control-Channel Modes
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Packet Protocol Summary
The packet-based control channel uses a synchronous,
symbol-based system to send data across the control
channel. Data to be sent across the control channel is
split into symbols and stored in a transmit queue and then
sent across the link. If both GPI and I2C data needs to be
sent (e.g., when GPI transitions during an I2C transmis-
sion), the symbols from both commands are combined
in the queue. If the transmit queue is empty, idle pack-
ets are sent across the link to maintain control-channel
lock. Received I2C packets are output as determined by
the microcontroller SCL rate (local device) or the pro-
grammed master bit rate (remote device). The device
holds SCL low (clock stretch) until data has been received
from the remote-side device.
Control-Channel Error Detection and Packet
Retransmission
When the packet-based control channel is used, all pack-
ets are checked for errors through CRC. Using 1, 5, or 8
bits, CRC detects 1, 3, or 4 random bit errors in a packet.
The transmitter retransmits packets whenever an error is
detected. The transmitter sets a flag if a number of retries
exceed 8. The receiver filters out packets with errors.
GPO/GPI Control
GPO on the serializer follows GPI transitions on the dese-
rializer. This GPO/GPI function can be used to transmit
signals such as a frame sync in a surround-view cam-
era system (see the Providing a Frame Sync (Camera
Applications) section). Optionally, GPO can be set directly
by register bits.
Spread Spectrum
The serializer contains a programmable spread-spectrum
output to lower emission levels by spreading the clock-
frequency peaks across a frequency spectrum. In addition,
the serializer and deserializer can track a spread input
clock, eliminating the need for multiple spread clocks.
Cable Type Configuration
The driver output is programmable for two kinds of
cable,100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75Ω cables). In coax
mode, connect OUT+ to IN+ of the deserializer. Leave
the unused IN_ pin unconnected, or connect it to ground
through 50Ω, and a capacitor for increased power-supply
rejection. Connect OUT- to VDD through a 50Ω resistor
(Figure 16).
Crossbar Switch
The crossbar switch routes data between the parallel input/
output and the SerDes. The anything-to-anything rout-
ing assures the mapping between the video source and
destination. For each crossbar output (XBO_) an input
multiplexer selects from the available crossbar inputs
(XBI_) using the CROSSBAR_ register bits (Figure 17).
Multiple crossbar outputs can use the same crossbar input.
By default, the sync signals share the same inputs as the
MSBs of the video data.
Video Timing Generator
The serializer includes a programmable video timing
generator to generate/retime the input sync signals. The
timing generator can be used to modify a camera's input
timing, filter out glitches in the sync signals, or to reduce
the number of required input sync signals. Each sync
signal can be individually retimed or left unmodified.
Several registers determine the length of the timing
parameters (in PCLK cycles) shown in Figure 18. Timing
parameters include high/low period length, line count, and
delay from the input VS signal.
The timing generator uses three different trigger modes,
tracking, single trigger, and autorun. Tracking mode looks
at the input VSYNC and locks once it receives three
consecutive identical VSYNC signals. The tracker then
continues to output the same identical signal, erasing any
glitches that may appear on VSYNC. The tracker attempts
to relock to a new signal if three consecutive input wave-
forms do not match the locked signal. Single trigger gen-
erates one generated frame for each input VSYNC edge.
Autorun generates a new frame at the rate determined
by the VSYNC high/low period. If a new VSYNC signal
appears before a frame is complete in either single trig-
ger or autorun modes, a new frame immediately starts,
cutting the previous frame short.
Figure 16. Coax Connection
OUT+
OUT-
IN+
OPTIONAL COMPONENTS
FOR INCREASED
POWER-SUPPLY REJECTION
IN-
AVDD
50Ω
GMSL
DESERIALIZER
GMSL
SERIALIZER
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
xsm xsw xauu xam xauz xaua xam xaus xawzs xawzs xam xawzs xawzg xam xaou no BO m x3029 019 XBOHS HS xsuvs vs xaus xaus xawan xam xawan xam xam XBH xam xau >5 >5
Figure 18. Sync-Signal Format For Video-Timing Generation
Figure 17. Crossbar Switch Dataflow
DE OUT
DE_H DE_CNT (PULSE COUNT)
DE_L
HS OUT
HS_H HS_CNT (PULSE COUNT)
HS_L
VS_H
VS_OUT
VS_IN
VS_DLY
HS_DLY
DE_DLY
VS_L
LOW INPUT
XBI0
:
DIN14/HS
DIN15/VS
DIN9
DIN13
DIN12
DIN11
DIN10
DIN0
DIN1 XBI1
XBI9
XBI10
XBI11
XBI12
XBI13
XBI14
XBI15
XBI16
:
DIN14/HS
DIN9
DIN13
DIN12
DIN11
DIN10
DIN0
DIN1 XBI17
XBI25
XBI26
XBI27
XBI28
XBI29
XBI30
HIGH INPUT
(DBL = 1 only)
:
:
XBI0
XBI1
XB30
XB31
::
CROSSBAR_
5
FORCE_MUX_
01
0
INVERT_MUX_
01
XBO_
34 SWITCHES
XBO0
XBO1
D0
D1
: :
XBO29
XBO30
D29
D30
XBOHS HS
XBOVS VS
XBODE DE
DATA
SYNC
PCLK
DIN15/VS XBI15
HS/DE* HS/DE HS/DE
HI_LO*
*REGISTER SETTINGS DECIDE IF HS, DE, OR HI_LO DETERMINES THE HIGH/LOW INPUT TIMING.
DIN14/HS XBI30 XBI14
XBI15
XBI30 XBI14
DIN13 XBI29 XBI13
DIN1 XBI17 XBI1
DIN0 XBI16 XBI0
XBI29 XBI13
XBI17 XBI1
XBI16 XBI0
......
:
:
XBI31 XBI31
DIN15/VS XBI31
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Shutdown/Sleep Modes
Several sleep and shutdown modes are available when
full operation is not needed.
Configuration Link
When the high-speed video link is not needed, or unavail-
able, a configuration link can be used in its place. In
configuration link mode, the parallel digital input/output is
disabled, the LOCK pin remains low, and the serial link
internally generates its own clock to allow full operation of
the control channel (UART/I2C and GPIO).
Serialization Disable
When the serial link is not needed, such as when down-
stream devices are powered off, the user can disable
serialization. In this mode, all forward communication is
shut down. The user can reenable serialization either
locally, or through the reverse channel.
Sleep Mode
To reduce power consumption further, the devices can
be put into sleep mode. In this mode, all registers keep
their programmed values, and all functions in the device
are powered down except for the wake-up detectors on
the local control interface, and the serial link. Any activity
seen by the wake-up detectors temporarily turns on the
control-channel interface. During this time, a microcon-
troller can command the device to exit sleep mode. See
the Shutdown/Sleep Modes section.
Figure 19. State Diagram
ALL STATES
POWER
DOWN
OR
POWER OFF
POWER ON
IDLE
CONFIG
LINK
STARTED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
VIDEO
LINK
LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
PWDNB = LOW OR
POWER OFF
CLINKEN = 1
CLINKEN = 0
OR SEREN = 1
CLINKEN = 0
OR SEREN = 1
PWDNB = HIGH,
POWER ON
CONFIG LINK
LOCKED
CONFIG LINK
UNLOCKED
VIDEO LINK
UNLOCKED
VIDEO LINK
LOCKED PRBSEN = 1
PRBSEN = 0
SEREN = 0 OR
NO PCLKIN
SEREN = 0 OR
NO PCLKIN
SEREN = 1,
PCLKIN RUNNING
WAKEUPSLEEP
SLEEP = 1
FOR > 8ms
LINK WAKEUP SIGNAL
SLEEP = 1 SLEEP = 0,
SEREN = 1
SLEEP = 0,
SEREN = 0
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Power-Down Mode
The lowest power consumption mode is power-down
mode. In this mode, all functions are powered down, and
all register values are lost.
Link Startup Procedure
NO. μCSERIALIZER DESERIALIZER
—μC Connected to Deserializer Set Configuration Inputs Set Configuration Inputs
1 Powers up (wait tPU).
Powers up and loads default
settings. Establishes video link
when valid PCLK is available.
Powers up and loads default
settings. Locks to video link
signal if available.
1a If no PCLK, programs CLINKEN, SEREN, and/or
AUTOCLINK bits. Wait 5ms after each command. Establishes configuration link. Locks to configuration link if
available.
1b
If not locked, sets any additional configuration bits
that are mismatched between the serializer and
deserializer (e.g., BWS, CX/TP). Wait 5ms for lock
after each command.
Configuration changed.
Reestablishes configuration/video
link if needed.
Configuration changed. Locks
to configuration/video link.
2Sets register 0x07 configuration bits in the serializer
(DBL, BWS, HIBW, PXL_CRC, etc.). Wait 2ms.
Configuration changed.
Reestablishes configuration/video
link if needed.
Loss-of-lock may occur.
3
Sets register 0x07 configuration bits in the deserial-
izer (DBL, BWS, HIBW, PXL_CRC, etc.). Wait 5ms for
lock to reestablish.
—Configuration changed. Locks
to configuration/video link.
4Writes rest of serializer/deserializer configuration bits. Configuration changed. Configuration changed.
5Writes camera/peripheral configuration bits. Forwards commands from μC to
serializer.
Forwards commands to
camera/peripherals.
5a If in configuration link, when PCLK is available, set
SEREN = 1. Wait 5ms for lock. Enables video link. Locks to video link.
Table 2. Link-Startup Procedure
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Register Map
OFFSET NAME MSB LSB
0x00 seraddr SERADDR[6:0] CFG-
BLOCK
0x01 desaddr DESADDR[6:0] RSVD
0x02 ss SS[2:0] RSVD PRNG[1:0] SRNG[1:0]
0x03 sdiv AUTOFM[1:0] SDIV[5:0]
0x04 main_control SEREN CLINKEN PRBSEN SLEEP INTTYPE[1:0] REVCCEN FWDCCEN
0x05 prbs_len I2C-
METHOD RSVD PRBS_LEN[1:0] RSVD RSVD RSVD RSVD
0x06 cmllvl_preemp CMLLVL[3:0] PREEMP[3:0]
0x07 config DBL HIBW BWS ES RSVD HVEN RSVD PXL_CRC
0x08 rsvd_8 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
0x09 i2c_source A I2C_SRC_A[6:0] RSVD
0x0A i2c_dest A I2C_DST_A[6:0] RSVD
0x0B i2c_source B I2C_SRC_B[6:0] RSVD
0x0C i2c_dest B I2C_DST_B[6:0] RSVD
0x0D i2c_config I2C_LOC_
ACK I2C_SLV_SH[1:0] I2C_MST_BT[2:0] I2C_SLV_TO[1:0]
0x0E gpio_en RSVD RSVD GPIO_
EN_5
GPIO_
EN_4
GPIO_
EN_3
GPIO_
EN_2
GPIO_
EN_1 RSVD
0x0F gpio_out EN_SET_
GPO RSVD GPIO_
OUT_5
GPIO_
OUT_4
GPIO_
OUT_3
GPIO_
OUT_2
GPIO_
OUT_1 SET_GPO
0x10 gpio_in RSVD RSVD GPIO_
IN_5
GPIO_
IN_4
GPIO_
IN_3
GPIO_
IN_2
GPIO_
IN_1 GPO_L
0x11 errg ERRG_RATE[1:0] ERRG_TYPE[1:0] ERRG_CNT[1:0] ERRG_
PER ERRG_EN
0x12 rsvd_12 RSVD RSVD RSVD RSVD[4:0]
0x13 pd SOFT_PD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
0x14 pktcc_lock RSVD[1:0] RSVD RSVD RSVD RSVD CC_
WBLOCK
REM_
CCLOCK
0x15 input_status CX_TP RSVD LCCEN RSVD RSVD RSVD OUT-
PUTEN PCLKDET
0x16 max_rt_err RSVD MAX_RT_
ERR RSVD[5:0]
0x17 rsvd_17 RSVD[7:0]
0x18 crc 0 CRC_VALUE_0[7:0]
0x19 crc 1 CRC_VALUE_1[7:0]
0x1A crc 2 CRC_VALUE_2[7:0]
0x1B crc 3 CRC_VALUE_3[7:0]
0x1C cc_crc_errcnt CC_CRC_ERRCNT[7:0]
0x1D rsvd_1d RSVD[7:0]
GMSL Register Map
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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OFFSET NAME MSB LSB
0x1E id[7:0] ID[7:0]
0x1F revision RSVD RSVD RSVD HDCPCAP REVISION[3:0]
0x20 crossbar 0 RSVD FORCE_
MUX_0
INVERT_
MUX_0 CROSSBAR_0[4:0]
0x21 crossbar 1 RSVD FORCE_
MUX_1
INVERT_
MUX_1 CROSSBAR_1[4:0]
0x22 crossbar 2 RSVD FORCE_
MUX_2
INVERT_
MUX_2 CROSSBAR_2[4:0]
0x23 crossbar 3 RSVD FORCE_
MUX_3
INVERT_
MUX_3 CROSSBAR_3[4:0]
0x24 crossbar 4 RSVD FORCE_
MUX_4
INVERT_
MUX_4 CROSSBAR_4[4:0]
0x25 crossbar 5 RSVD FORCE_
MUX_5
INVERT_
MUX_5 CROSSBAR_5[4:0]
0x26 crossbar 6 RSVD FORCE_
MUX_6
INVERT_
MUX_6 CROSSBAR_6[4:0]
0x27 crossbar 7 RSVD FORCE_
MUX_7
INVERT_
MUX_7 CROSSBAR_7[4:0]
0x28 crossbar 8 RSVD FORCE_
MUX_8
INVERT_
MUX_8 CROSSBAR_8[4:0]
0x29 crossbar 9 RSVD FORCE_
MUX_9
INVERT_
MUX_9 CROSSBAR_9[4:0]
0x2A crossbar 10 RSVD FORCE_
MUX_10
INVERT_
MUX_10 CROSSBAR_10[4:0]
0x2B crossbar 11 RSVD FORCE_
MUX_11
INVERT_
MUX_11 CROSSBAR_11[4:0]
0x2C crossbar 12 RSVD FORCE_
MUX_12
INVERT_
MUX_12 CROSSBAR_12[4:0]
0x2D crossbar 13 RSVD FORCE_
MUX_13
INVERT_
MUX_13 CROSSBAR_13[4:0]
0x2E crossbar 14 RSVD FORCE_
MUX_14
INVERT_
MUX_14 CROSSBAR_14[4:0]
0x2F crossbar 15 RSVD FORCE_
MUX_15
INVERT_
MUX_15 CROSSBAR_15[4:0]
0x30 crossbar 16 RSVD FORCE_
MUX_16
INVERT_
MUX_16 CROSSBAR_16[4:0]
0x31 crossbar 17 RSVD FORCE_
MUX_17
INVERT_
MUX_17 CROSSBAR_17[4:0]
0x32 crossbar 18 RSVD FORCE_
MUX_18
INVERT_
MUX_18 CROSSBAR_18[4:0]
0x33 crossbar 19 RSVD FORCE_
MUX_19
INVERT_
MUX_19 CROSSBAR_19[4:0]
0x34 crossbar 20 RSVD FORCE_
MUX_20
INVERT_
MUX_20 CROSSBAR_20[4:0]
GMSL Register Map (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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OFFSET NAME MSB LSB
0x35 crossbar 21 RSVD FORCE_
MUX_21
INVERT_
MUX_21 CROSSBAR_21[4:0]
0x36 crossbar 22 RSVD FORCE_
MUX_22
INVERT_
MUX_22 CROSSBAR_22[4:0]
0x37 crossbar 23 RSVD FORCE_
MUX_23
INVERT_
MUX_23 CROSSBAR_23[4:0]
0x38 crossbar 24 RSVD FORCE_
MUX_24
INVERT_
MUX_24 CROSSBAR_24[4:0]
0x39 crossbar 25 RSVD FORCE_
MUX_25
INVERT_
MUX_25 CROSSBAR_25[4:0]
0x3A crossbar 26 RSVD FORCE_
MUX_26
INVERT_
MUX_26 CROSSBAR_26[4:0]
0x3B crossbar 27 RSVD FORCE_
MUX_27
INVERT_
MUX_27 CROSSBAR_27[4:0]
0x3C crossbar 28 RSVD FORCE_
MUX_28
INVERT_
MUX_28 CROSSBAR_28[4:0]
0x3D crossbar 29 RSVD FORCE_
MUX_29
INVERT_
MUX_29 CROSSBAR_29[4:0]
0x3E crossbar 30 RSVD FORCE_
MUX_30
INVERT_
MUX_30 CROSSBAR_30[4:0]
0x3F crossbar_hs RSVD FORCE_
MUX_HS
INVERT_
MUX_HS CROSSBARHS[4:0]
0x40 crossbar_vs RSVD FORCE_
MUX_VS
INVERT_
MUX_VS CROSSBARVS[4:0]
0x41 crossbar_de RSVD FORCE_
MUX_DE
INVERT_
MUX_DE CROSSBARDE[4:0]
0x42 link_config LINE_CRC_LOC[1:0] LINE_
CRC_EN
MAX_
RT_EN RSVD
GPI_
COMP_
EN
GPI_RT_
EN GPO_EN
0x43 sync_gen_config RSVD RSVD GEN_VS GEN_HS GEN_DE VS_
TRIG VTG_MODE[1:0]
0x44 vs_dly 2 VS_DLY[7:0]
0x45 vs_dly 1 VS_DLY[7:0]
0x46 vs_dly 0 VS_DLY[7:0]
0x47 vs_h 2 VS_H[7:0]
0x48 vs_h 1 VS_H[7:0]
0x49 vs_h 0 VS_H[7:0]
0x4A vs_l 2 VS_L[7:0]
0x4B vs_l 1 VS_L[7:0]
0x4C vs_l 0 VS_L[7:0]
0x4D cxtp HIGHIMM CXTP RSVD RSVD VSYNC_
INV
HSYNC_
INV DE_INV RSVD
0x4E hs_dly 2 HS_DLY[7:0]
GMSL Register Map (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
35
OFFSET NAME MSB LSB
0x4F hs_dly 1 HS_DLY[7:0]
0x50 hs_dly 0 HS_DLY[7:0]
0x51 rsvd51 RSVD[7:0]
0x52 rsvd52 RSVD[7:0]
0x53 rsvd53 RSVD[7:0]
0x54 hs_h 1 HS_H[7:0]
0x55 hs_h 0 HS_H[7:0]
0x56 hs_l 1 HS_L[7:0]
0x57 hs_l 0 HS_L[7:0]
0x58 hs_cnt 1 HS_CNT[7:0]
0x59 hs_cnt 0 HS_CNT[7:0]
0x5A de_dly 2 DE_DLY[7:0]
0x5B de_dly 1 DE_DLY[7:0]
0x5C de_dly 0 DE_DLY[7:0]
0x5D rsvd5D RSVD[7:0]
0x5E rsvd5E RSVD[7:0]
0x5F rsvd5F RSVD[7:0]
0x60 de_h 1 DE_H[7:0]
0x61 de_h 0 DE_H[7:0]
0x62 de_l 1 DE_L[7:0]
0x63 de_l 0 DE_L[7:0]
0x64 de_cnt 1 DE_CNT_1[7:0]
0x65 de_cnt 0 DE_CNT_0[7:0]
0x66 prbs_type RSVD[1:0] PRBS_
TYPE
REV_
FAST DE_EN DIS_
RWAKE RSVD CXSEL
0x67 dbl_align_to RSVD[1:0] AUTO_
CLINK RSVD RSVD DBL_ALIGN_TO[2:0]
0x68 cc_crc_length RSVD RSVD[2:0] RSVD[1:0] CC_CRC_
LENGTH[1:0]
0x69 hi_lo RSVD EN_HI_
LO
INVERT_
HI_LO CROSSBAR_HI_LO[4:0]
0x96 rsvd_96 RSVD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
0x97 rsvd_97 RSVD RSVD RSVD RSVD RSVD RSVD[2:0]
0x98 rsvd_98 RSVD[1:0] RSVD[2:0] RSVD[2:0]
0x99 rsvd_99 RSVD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
0x9A pktcc_en RSVD[1:0] RSVD[1:0] PKTCC_
EN RSVD[1:0] RSVD
GMSL Register Map (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
36
seraddr (0x00)
BIT 76543210
Field SERADDR[6:0] CFGBLOCK
Reset 1000000 0b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
SERADDR 7:1 Serializer Address: Serializer device address
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
CFG-
BLOCK 0
Configuration Block: Set to 1 to make all
registers read-only. Set PWDNB low, or a power-on
reset to clear this bit.
0: Make all registers read/write
1: Make all registers read-only
desaddr (0x01)
BIT 76543210
Field DESADDR[6:0] RSVD
Reset 1001000b 0b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
DESADDR 7:1 Deserializer Address: Deserializer device address
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
RSVD 0 Reserved: Do not change from default value 0: Reserved
OFFSET NAME MSB LSB
0xC8 rsvd_c8 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
0xC9 rsvd_c9 RSVD[7:0]
0xFC rsvd_fc RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
0xFD rsvd_fd RSVD[7:0]
0xFE rsvd_fe RSVD[3:0] RSVD[3:0]
0xFF rsvd_ff RSVD RSVD RSVD RSVD RSVD[3:0]
GMSL Register Map (continued)
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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37
ss (0x02)
BIT 76543210
Field SS[2:0] RSVD PRNG[1:0] SRNG[1:0]
Reset 000b 1b 11b 11b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
SS 7:5 Spread Spectrum: Spread-spectrum setting
000: Spread is off
001: 0.5% Spread setting
010: 1.5% Spread setting
011: 2% Spread setting
100: Spread is off
101: 1% Spread setting
110: 3% Spread setting
111: 4% Spread setting
RSVD 4 Reserved: Do not change from default value 1: Reserved
PRNG 3:2 Pixel Clock Range: Pixel clock-range selection
Stated ranges depend on DBL = setting
00: Select 12.5MHz to 25MHz (DBL = 0) or 25MHz
to 50MHz (DBL = 1) pixel clock range
01: Select 25MHz to 58MHz (DBL = 0) or 50MHz to
116MHz (DBL = 1) pixel clock range
10: Automatically detect pixel clock range
11: Automatically detect pixel clock range.
SRNG 1:0 Serial-Data Rate Range
00: 0.5Gbps to 1Gbps serial-data range
01: 1Gbps to 1.74Gbps serial-data range
10: Automatically detect serial-data range
11: Automatically detect serial-data range
sdiv (0x03)
BIT 76543210
Field AUTOFM[1:0] SDIV[5:0]
Reset 00b 000000b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
AUTOFM 7:6 Automatic Frequency Modulation: Modulation-
rate calibration interval
00: Calibration occurs once
01: Calibration occurs every 2ms
10: Calibration occurs every 16ms
11: Calibration occurs every 256ms
SDIV 5:0
Sawtooth Divider: Sawtooth divider value
0x00 sets the sawtooth divider to autocalibrate
mode
000000: Sawtooth divider automatically calibrates
the divider value
000001: Sawtooth divider set to 1
111111: Sawtooth divider set to 63
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
38
main_control (0x04)
BIT 76543210
Field SEREN CLINKEN PRBSEN SLEEP INTTYPE[1:0] REVCCEN FWDCCEN
Reset 1b 0b 0b 0b 01b 1b 1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
SEREN 7 Serialization Enable: Requires a valid PCLK for
serialization
0: Disable serialization
1: Enable serialization
CLINKEN 6
Configuration Link Enable: Configuration link
enabled only when the video link is not enabled
(SEREN = 1)
0: Disable configuration link
1: Enable configuration link
PRBSEN 5 PRBS Test Enable: See the PRBS test section for
more details
0: Disable PRBS test
1: Enable PRBS test
SLEEP 4
Sleep Mode Enable: Activates sleep mode
(see the Shutdown/Sleep Modes section for more
information)
0: Disable sleep mode
1: Enable sleep mode
INTTYPE 3:2
UART/I2C Interface Type: Local control-channel
interface when in UART/UART or UART/I2C mode
(I2CSEL = 0)
00: Device performs UART-to-I2C conversion when
functioning as the remote device
01: Device outputs UART packets when functioning
as the remote device
10: Tx/Rx input/outputs disabled when functioning
as the remote device
11: Tx/Rx input/outputs disabled when functioning
as the remote device
REVCCEN 1
Reverse Control-Channel Enable: Enable
reverse control-channel receiver (data from
deserializer)
0: Disable reverse control-channel receiver
1: Enable reverse control-channel receiver
FWDCCEN 0
Forward Control-Channel Enable: Enable
forward control channel receiver
(data to deserializer)
0: Disable forward control channel transmitter
1: Enable forward control channel transmitter
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
39
prbs_len (0x05)
BIT 76543210
Field I2C-
METHOD RSVD PRBS_LEN[1:0] RSVD RSVD RSVD RSVD
Reset 0b 0b 00b 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
I2CMETHOD 7
UART-to-I2C Method: When set, skip the sending
of the register address when converting UART to
I2C (I2CSEL = 0).
0: Do not skip the sending of the register address
1: Skip the sending of the register address
RSVD 6 Reserved: Do not change from default value. 0: Reserved
PRBS_LEN 5:4 PRBS Length: PRBS test pattern length
00: Continuous bit pattern (infinite length)
01: 9.8Mbit length
10: 167.1Mbit length
11: 1341.5Mbit length
RSVD 3 Reserved: Do not change from default value 0: Reserved
RSVD 2 Reserved: Do not change from default value. 0: Reserved
RSVD 1 Reserved: Do not change from default value. 0: Reserved
RSVD 0 Reserved: Do not change from default value. 0: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
40
cmllvl_preemp (0x06)
BIT 76543210
Field CMLLVL[3:0] PREEMP[3:0]
Reset 10X0b 0000b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
CMLLVL 7:4
CML Level: Output CML signal level = (register
value) x 50mV
Default level depends on cable type (CXTP)
0000: Do not use
0001: Do not use
0010: 100mV output
0011: 150mV output
0100: 200mV output
0101: 250mV output
0110: 300mV output
0111: 350mV output
1000: 400mV output (STP default)
1001: 450mV output
1010: 500mV output (coax default)
1011: Do not use
1100: Do not use
1101: Do not use
111X: Do not use
PREEMP 3:0 Preemphasis Level: Preemphasis setting
Negative preemphasis levels denote deemphasis
0000: Preemphasis off
0001: 1.2dB deemphasis
0010: 2.5dB deemphasis
0011: 4.1dB deemphasis
0100: 6.0dB deemphasis
0101: Do not use
011X: Do not use
1000: 1.1dB preemphasis
1001: 2.2dB preemphasis
1010: 3.3dB preemphasis
1011: 4.4dB preemphasis
1100: 6.0dB preemphasis
1101: 8.0dB preemphasis
1110: 10.5dB preemphasis
1111: 14.0dB preemphasis
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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41
config (0x07)
BIT 76543210
Field DBL HIBW BWS ES RSVD HVEN RSVD PXL_CRC
Reset 0b 0b Xb Xb 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
DBL 7
Double-Input Mode Enable: Set high to enable
double-input mode. Default setting is determined
by LCCEN and TX/SCL/DBL pin setting at
power-up.
0: Single-input mode
1: Double-input mode
HIBW 6 High-Bandwidth Mode Enable: High-bandwidth
mode select (effective only when BWS = 0)
0: Use 24-bit mode when BWS = 0
1: Use high-bandwidth mode when BWS = 0
BWS 5 Bus-Width Select: Default value is determined by
LCCEN and GPIO1/BWS pin setting at power-up.
0: 24-bit and high-bandwidth mode
1: 32-bit mode
ES 4 Edge Select: Default value is determined by
CONF[1:0] pins at power-up
0: Parallel data clocked in on rising edge
1: Parallel data clocked in on falling edge
RSVD 3 Reserved: Do not change from default value. 0: Reserved
HVEN 2
HSYNC/VSYNC Encoding Enable: Default value
is determined by LCCEN and MS/HVEN pin setting
at powerup
0: Disable HS/VS encoding
1: Enable HS/VS encoding
RSVD 1 Reserved: Do not change from default value. 0: Reserved
PXL_CRC 0 Pixel CRC Type: pixel error-detection type
Effective only when HIBW = 0
0: Serial data uses 1-bit parity
1: Serial data uses 6-bit CRC
rsvd_8 (0x08)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reset 0b 0b 0b 0b 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value. 0: Reserved
RSVD 6 Reserved: Do not change from default value. 0: Reserved
RSVD 5 Reserved: Do not change from default value. 0: Reserved
RSVD 4 Reserved: Do not change from default value. 0: Reserved
RSVD 3 Reserved: Do not change from default value. 0: Reserved
RSVD 2 Reserved: Do not change from default value. 0: Reserved
RSVD 1 Reserved: Do not change from default value. 0: Reserved
RSVD 0 Reserved: Do not change from default value. 0: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
42
i2c_source (0x09, 0x0B)
BIT 76543210
Field I2C_SRC[6:0] RSVD
Reset 0000000b 0b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
I2C_SRC 7:1 I2C Source: I2C address translator source
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
RSVD 0 Reserved: Do not change from default value. 0: Reserved
i2c_dest (0x0A, 0x0C)
BIT 76543210
Field I2C_DST[6:0] RSVD
Reset 0000000b 0b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
I2C_DST 7:1 I2C Destination: I2C address translator destination
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
RSVD 0 Reserved: Do not change from default value. 0: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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43
i2c_config (0x0D)
BIT 76543210
Field I2C_LOC_
ACK I2C_SLV_SH[1:0] I2C_MST_BT[2:0] I2C_SLV_TO[1:0]
Reset 1b 01b 101b 10b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
I2C_LOC_
ACK 7
I2C Local Acknowledge: I2C-to-I2C slave
generates local acknowledge when forward
channel is not available
0: Do not send local autoacknowledge when
control channel is absent
1: Send local autoacknowledge when control
channel is absent
I2C_SLV_
SH 6:5 I2C Slave Setup/Hold Time: I2C-to-I2C slave
setup and hold-time setting (setup, hold) (typ)
00: (352ns, 117ns) setup/hold time
01: (469ns, 234ns) setup/hold time
10: (938ns, 352ns) setup/hold time
11: (1406ns, 469ns) setup/hold time
I2C_MST_
BT 4:2 I2C Master Bit Rate: I2C-to-I2C master bit-rate
setting (min, typ, max)
000: (6.61, 8.47, 9.92) kbps
001: (22.1, 28.3, 33.2) kbps
010: (66.1, 84.7, 99.2) kbps
011: (82, 105, 123) kbps
100: (136, 173, 203) kbps
101: (265, 339, 397) kbps
110: (417, 533, 625) kbps
111: (654, 837, 980) kbps
I2C_SLV_
TO 1:0 I2C Slave Timeout: I2C-to-I2C slave remote-side
timeout setting (typ).
00: 64μs slave timeout
01: 256μs slave timeout
10: 1024μs slave timeout
11: Slave timeout disabled
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
44
gpio_en (0x0E)
BIT 76543210
Field RSVD RSVD GPIO_EN_5 GPIO_EN_4 GPIO_EN_3 GPIO_EN_2 GPIO_EN_1 RSVD
Reset 0b 0b 0b 0b 0b 0b 1b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value. 0: Reserved
RSVD 6 Reserved: Do not change from default value. 0: Reserved
GPIO_EN_5 5 GPIO Enable: Disabled by default 0: Pin functions as a parallel input
1: Pin functions as a GPIO
GPIO_EN_4 4 GPIO Enable: Disabled by default. 0: Pin functions as a parallel input
1: Pin functions as a GPIO
GPIO_EN_3 3 GPIO Enable: Disabled by default. 0: Pin functions as a parallel input
1: Pin functions as a GPIO
GPIO_EN_2 2 GPIO Enable: Disabled by default 0: Pin functions as a parallel input
1: Pin functions as a GPIO
GPIO_EN_1 1 GPIO Enable: Disabled by default 0: Pin functions as parallel input
1: Pin functions as GPIO
RSVD 0 Reserved: Do not change from default value 0: Reserved
gpio_out (0x0F)
BIT 76543210
Field EN_SET_
GPO RSVD GPIO_
OUT_5
GPIO_
OUT_4
GPIO_
OUT_3
GPIO_
OUT_2
GPIO_
OUT_1 SET_GPO
Reset 0b 0b 1b 1b 1b 1b 1b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
EN_SET_GPO 7 Enable Set GPO: Set to 1 to enable setting of GPO
from SET_GPO
0: Disable setting of GPO through SET_GPO
1: Enable setting of GPO through SET_GPO
RSVD 6 Reserved: Do not change from default value 0: Reserved
GPIO_OUT_5 5 GPIO Output Level: Pull down GPIO when 0 0: Set GPIO output level low
1: Set GPIO output level high
GPIO_OUT_4 4 GPIO Output Level: Pull down GPIO when 0 0: Set GPIO output level lo
1: Set GPIO output level high
GPIO_OUT_3 3 GPIO Output Level: Pull down GPIO when 0 0: Set GPIO output leve
1: Set GPIO output level high
GPIO_OUT_2 2 GPIO Output Level: Pull down GPIO when 0 0: Set GPIO output level low
1: Set GPIO output level high
GPIO_OUT_1 1 GPIO Output Level: Pull down GPIO when 0 0: Set GPIO output level low
1: Set GPIO output level high
SET_GPO 0 Set GPO Level: Set GPO output high or low (when
EN_SET_GPO = 1)
0: Set GPO output low
1: Set GPO output high
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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45
gpio_in (0x10)
BIT 76543210
Field RSVD RSVD GPIO_IN_5 GPIO_IN_4 GPIO_IN_3 GPIO_IN_2 GPIO_IN_1 GPO_L
Reset 0b 0b Xb Xb Xb Xb Xb Xb
Access Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved 0: Reserved
RSVD 6 Reserved 0: Reserved
GPIO_IN_5 5 GPIO Input Level: Input pin level of GPIO 0: GPIO input is low
1: GPIO input is high
GPIO_IN_4 4 GPIO Input Level: Input pin level of GPIO 0: GPIO input is low
1: GPIO input is high
GPIO_IN_3 3 GPIO Input Level: Input pin level of GPIO 0: GPIO input is low
1: GPIO input is high
GPIO_IN_2 2 GPIO Input Level: Input pin level of GPIO 0: GPIO input is low
1: GPIO input is high
GPIO_IN_1 1 GPIO Input Level: Input pin level of GPIO 0: GPIO input is low
1: GPIO input is high
GPO_L 0 GPO Output Level 0: GPO output level is low
1: GPO output level is high
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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46
errg (0x11)
BIT 76543210
Field ERRG_RATE[1:0] ERRG_TYPE[1:0] ERRG_CNT[1:0] ERRG_PER ERRG_EN
Reset 0b 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
ERRG_RATE 7:6 Error-Generation Rate: Error-generation rate, on
average
00: Generate errors every 2560 bits
01: Generate errors every 40,960 bits
10: Generate errors every 655,360 bits
11: Generate errors every 10,485,760 bits
ERRG_TYPE 5:4 Error-Generation Type: Type of generated errors
00: Single-bit errors
01: 2 8b/10b symbols
10: 3 8b/10b symbols
11: 4 8b/10b symbols
ERRG_CNT 3:2 Error-Generation Count: Number of generated
errors
00: Generate errors continuously
01: Generate16 errors
10: Generate 128 errors
11: Generate 1024 errors
ERRG_PER 1 Periodic Error Generation Enable
0: Generator creates errors randomly (based on
error rate)
1: Generator creates errors periodically (based
on error rate)
ERRG_EN 0 Error Generator Enable 0: Disable error generator
1: Enable error generator
rsvd_12 (0x12)
BIT 76543210
Field RSVD RSVD RSVD RSVD[4:0]
Reset 0b 1b 0b 00000b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 1: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4:0 Reserved: Do not change from default value 00000: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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47
pd (0x13)
BIT 76543210
Field SOFT_PD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
Reset 0b 0b 0b 0b 0b 0b 10b
Access Type Write 1 to
Set, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
SOFT_PD 7 Soft Power Down: Set this bit to 1 to reset the
device; this bit is cleared after the device resets
0: Normal operation
1: Reset the device (bit clears itself)
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3 Reserved: Do not change from default value 0: Reserved
RSVD 2 Reserved: Do not change from default value 0: Reserved
RSVD 1:0 Reserved: Do not change from default value 10: Reserved
pktcc_lock (0x14)
BIT 76543210
Field RSVD[1:0] RSVD RSVD RSVD RSVD CC_
WBLOCK
REM_
CCLOCK
Reset XXb Xb Xb Xb Xb Xb Xb
Access Type Read Only Read Only Read Only Read Clears
All Read Only Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:6 Reserved XX: Reserved
RSVD 5 Reserved X: Reserved
RSVD 4 Reserved X: Reserved
RSVD 3 Reserved X: Reserved
RSVD 2 Reserved X: Reserved
CC_
WBLOCK 1Control-Channel Word Boundary Locked 0: Control-channel word boundary is not locked
1: Control-channel word boundary is locked
REM_
CCLOCK 0Remote-Side Control Channel Locked 0: Remote side control channel is not locked
1: Remote side control channel is locked
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
48
input_status (0x15)
BIT 76543210
Field CX_TP RSVD LCCEN RSVD RSVD RSVD OUTPUTEN PCLKDET
Reset Xb Xb Xb 0b 0b 0b Xb Xb
Access Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
CX_TP 7 Coax/Twisted Pair level: CX_TP pin level 0: CX/TP input is low
1: CX/TP input is high
RSVD 6 Reserved X: Reserved
LCCEN 5 Detected LCCEN pin level 0: Pin is input low
1: Pin is input high
RSVD 4 Reserved 0: Reserved
RSVD 3 Reserved 0: Reserved
RSVD 2 Reserved 0: Reserved
OUT-
PUTEN 1Output Enabled 0: Output disabled
1: Output enabled
PCLKDET 0 PCLK Detected: Valid PCLK detected 0: No valid PCLK detected
1: Valid PCLK detected
max_rt_err (0x16)
BIT 76543210
Field RSVD MAX_RT_
ERR RSVD[5:0]
Reset 0b Xb XXXXXXb
Access Type Read Only Read Clears
All Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved 0: Reserved
MAX_RT_ERR 6
Maximum Retransmission Error: maximum
retransmission error bit
Goes high if packet control channel hits maximum
retransmission limit (8 retries). Cleared when read.
0: Device has not reached maximum retransmis-
sion limit.
1: Device has reached maximum retransmission
limit.
RSVD 5:0 Reserved XXXXXX: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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49
rsvd_17 (0x17)
BIT 76543210
Field RSVD[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:0 Reserved XXXXXXXX: Reserved
crc (0x18 to 0x1B)
BIT 76543210
Field CRC_VALUE[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
CRC_VALUE 7:0
CRC Value: CRC output for latest line
CRC_VALUE_3 to CRC_VALUE_0 represents
CRC[31:0]
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
cc_crc_errcnt (0x1C)
BIT 76543210
Field CC_CRC_ERRCNT[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
CC_CRC_
ERRCNT 7:0 Control-Channel CRC Error Count: Packet-
based control-channel CRC error counter
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
rsvd_1d (0x1D)
BIT 76543210
Field RSVD[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:0 Reserved XXXXXXXX: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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50
id (0x1E)
BIT 76543210
Field ID[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
ID 7:0 Device ID: 8-bit value depends on the GMSL
device attached 01000001 Device is a MAX96705
revision (0x1F)
BIT 76543210
Field RSVD RSVD RSVD HDCPCAP REVISION[3:0]
Reset 0b 0b 0b Xb XXXXb
Access Type Read Only Read Only Read Only Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved 0: Reserved
RSVD 6 Reserved 0: Reserved
RSVD 5 Reserved 0: Reserved
HDCPCAP 4 HDCP Capability: 1 = HDCP capable 0: Device does not have HDCP
1: Device is HDCP capable
REVISION 3:0 Device Revision
0000: Value is 0
0001: Value is 1
1111: Value is 15
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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│
51
crossbar (0x20 to 0x3E)
BIT 76543210
Field RSVD FORCE_
MUX
INVERT_
MUX CROSSBAR[4:0]
Reset 0b 0b 0b XXXXXb
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
FORCE_
MUX 6Force Mux Output 0: Input mapped to mux output
1: Force mux output low
INVERT_
MUX 5Invert Mux Output 0: Do not invert mux output
1: Invert mux output
CROSS-
BAR 4:0
Crossbar Setting
Select 1 of 32 input signals. Default values connect
Mux N with input N for flow-through routing (i.e.,
DIN_ mapped to DOUT_).
00000: Mux outputs data from input 0
00001: Mux outputs data from input 1
11111: Mux outputs data from input 31
crossbar_hs (0x3F)
BIT 76543210
Field RSVD FORCE_
MUX_HS
INVERT_
MUX_HS CROSSBARHS[4:0]
Reset 0b 0b 0b 01110b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
FORCE_
MUX_HS 6Force Mux Output 0: Input mapped to mux output
1: Force mux output low
INVERT_
MUX_HS 5Invert Mux Output 0: Do not invert mux output
1: Invert mux output
CROSS-
BARHS 4:0
Crossbar Setting HS: Select 1 of 16 input pins
for HS. Default values connect HS with the
corresponding named input pin.
00000: Mux sync signal from DIN0
00001: Mux sync signal from DIN1
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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52
crossbar (0x40)
BIT 76543210
Field RSVD FORCE_
MUX_VS
INVERT_
MUX_VS CROSSBARVS[4:0]
Reset 0b 0b 0b 01111b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
FORCE_
MUX_VS 6Force Mux Output 0: Input mapped to mux output
1: Force mux output low
INVERT_
MUX_VS 5Invert Mux Output 0: Do not invert mux output
1: Invert mux output
CROSS-
BARVS 4:0
Crossbar Setting VS: Select 1 of 16 input pins for
VS. Default values connect VS with the correspond-
ing named input pin.
00000: Mux sync signal from DIN0
00001: Mux sync signal from DIN1
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
crossbar_de (0x41)
BIT 76543210
Field RSVD FORCE_
MUX_DE
INVERT_
MUX_DE CROSSBARDE[4:0]
Reset 0b 0b 0b 01101b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
FORCE_
MUX_DE 6Force Mux Output 0: Input mapped to mux output.
1: Force mux output low.
INVERT_
MUX_DE 5Invert Mux Output 0: Do not invert mux output.
1: Invert mux output.
CROSS-
BARDE 4:0 Crossbar Setting DE: Select 1 of 16 input pins for
DE. Default values connect DE with DIN13.
00000: Mux sync signal from DIN0
00001: Mux sync signal from DIN1
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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│
53
link_config (0x42)
BIT 76543210
Field LINE_CRC_LOC[1:0] LINE_CRC_
EN
MAX_RT_
EN RSVD GPI_
COMP_EN GPI_RT_EN GPO_EN
Reset 01b 0b 1b 1b 0b 1b 1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
LINE_CRC_
LOC 7:6 Line CRC Location: Video line CRC insertion
location
00: CRC insertion at [1...4]
01: CRC insertion at [5...8]
10: CRC insertion at [9...12]
11: CRC insertion at [13...16]
LINE_CRC_
EN 5Line CRC Enable: Video line CRC enable 0: Disable CRC
1: Enable CRC
MAX_RT_EN 4 Maximum Retransmission Limit Enable 0: Disable maximum retransmission limit
1: Enable maximum retransmission limit
RSVD 3 Reserved: Do not change from default value 1: Reserved
GPI_COMP_
EN 2GPI Compensation Enable 0: Disable GPI compensation
1: Enable GPI compensation
GPI_RT_EN 1 GPI Retransmission Enable 0: Disable GPI retransmission
1: Enable GPI retransmission
GPO_EN 0 GPO Enable: Enable GPO pin 0: Disable GPO pin
1: Enable GPO pin
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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sync_gen_config (0x43)
BIT 76543210
Field RSVD RSVD GEN_VS GEN_HS GEN_DE VS_TRIG VTG_MODE[1:0]
Reset 0b 0b 0b 0b 0b 1b 01b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
GEN_VS 5 VSYNC Generation: Enable to generate VS output
according to the timing definition
0: Disable VS output generation (VS used from
input)
1: Enable VS output generation (VS internally
generated)
GEN_HS 4 HSYNC Generation: Enable to generate HS
utput according to the timing definition
0: Disable HS output generation (HS used from
input)
1: Enable HS output generation (HS internally
generated)
GEN_DE 3 DE Generation: Enable to generate DE output
according to the timing definition
0: Disable DE output generation (DE used from
input)
1: Enable DE output generation (DE internally
generated)
VS_TRIG 2 VSYNC Trigger Edge Select 0: VS trigger uses falling edge
1: VS trigger uses rising edge
VTG_
MODE 1:0 Video Timing Generator Mode
00: VS input is tracked and then locked after three
consecutive matches (three consecutive mismatch-
es unlock tracking)
01: VS edge triggers one VS frame (current frame
is extended/cut short to adjust timing to next
trigger)
10: VS edge triggers VS generation (current frame
is extended/cut short to adjust timing to next
trigger)
11: Same as above
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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55
vs_dly (0x44 to 0x46)
BIT 76543210
Field VS_DLY[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
VS_DLY 7:0
VSYNC Delay: VS delay in terms of PCLK cycles;
the output VS delay by VS_DELAY cycles from the
input VS.
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
vs_h (0x47 to 0x49)
BIT 76543210
Field VS_H[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
VS_H 7:0 VSYNC High: VS high period in terms of PCLK
cycles.
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
vs_l (0x4A to 0x4C)
BIT 76543210
Field VS_L[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
VS_L 7:0 VSYNC Low: VS low period in terms of PCLK
cycles
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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56
cxtp (0x4D)
BIT 76543210
Field HIGHIMM CXTP RSVD RSVD VSYNC_
INV
HSYNC_
INV DE_INV RSVD
Reset Xb 0b 0b 0b 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
HIGHIMM 7 High-Immunity Mode: Default value depends on
the state of the HIM input
0: Use legacy reverse-channel mode
1: Use high-immunity mode
CXTP 6
Coax/Twisted Pair Select
Default value depends on the state of the CONF0,
CONF1 inputs
0: Use differential output (STP mode)
1: Use dual single ended outputs (coax)
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
VSYNC_
INV 3VSYNC Inversion: Invert output VSYNC in
TIMING GEN
0: Do not invert VS in timing generator
1: Invert VS in timing generator
HSYNC_
INV 2HSYNC Inversion: Invert output HSYNC in
TIMING GEN
0: Do not invert HS in timing generator
1: Invert HS in timing generator
DE_INV 1 DE Inversion: Invert output DE in TIMING GEN 0: Do not invert DE in timing generator
1: Invert DE in timing generator
RSVD 0 Reserved: Do not change from default value 0: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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hs_dly (0x4E to 0x50)
BIT 76543210
Field HS_DLY[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
HS_DLY 7:0
VSYNC to HSYNC Delay: VS edge to the rising
edge of the first HS in terms of PCLK cycles
(bits [15:8])
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
rsvd (0x51 to 0x53, 0x5D to 0x5F)
BIT 76543210
Field RSVD[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD [7:0] Reserved: Do not change from default value 00000000: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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58
hs_h (0x54, 0x55)
BIT 76543210
Field HS_H[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
HS_H 7:0 HSYNC High Period: HS high period in terms of
PCLK cycles
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
hs_l (0x56, 0x57)
BIT 76543210
Field HS_L[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
HS_L 7:0 HSYNC Low Period: HS low period in terms of
PCLK cycles.
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
hs_cnt (0x58, 0x59)
BIT 76543210
Field HS_CNT[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
HS_CNT 7:0 HSYNC Count: Lines per panel (bits [7:0]). 00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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59
de_dly (0x5A to 0x5C)
BIT 76543210
Field DE_DLY[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
DE_DLY 7:0
VSYNC to DE
VS falling edge to the rising edge of the first DE in
terms of PCLK cycles.
00000000: Value is 0.
00000001: Value is 1.
11111111: Value is 255.
de_h (0x60, 0x61)
BIT 76543210
Field DE_H[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
DE_H 7:0 DE High Period: DE high period in terms of PCLK
cycles.
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
de_l (0x62, 0x63)
BIT 76543210
Field DE_L[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
DE_L 7:0 DE Low Period: DE low period in terms of PCLK
cycles
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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de_cnt (0x64, 0x65)
BIT 76543210
Field DE_CNT[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
DE_CNT 7:0 DE Count: Active lines per panel
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
prbs_type (0x66)
BIT 76543210
Field RSVD[1:0] PRBS_
TYPE REV_FAST DE_EN DIS_
RWAKE RSVD CXSEL
Reset 01b 1b 0b 0b 0b 0b 1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:6 Reserved: Do not change from default value 01: Reserved
PRBS_
TYPE 5PRBS Type: PRBS type select 0: Select legacy PRBS mode
1: Select MAX9271–MAX9273 PRBS mode
REV_
FAST 4Reverse Channel Fast-Mode Enable 0: Disable reverse channel fast mode
1: Enable reverse channel fast mode
DE_EN 3 DE Enable: Enable processing separate HS and
DE signals
0: Disable separate processing of HS and DE
signals
1: Enable separate processing of HS and DE
signals
DIS_
RWAKE 2Disable Remote Wake-Up: Disable wake-up
receiver
0: Do not disable remote wake-up receiver
1: Disable remote wake-up receiver
RSVD 1 Reserved: Do not change from default value 0: Reserved
CXSEL 0 Coax Select 0: Coax cable connected to inverting output
1: Coax cable connected to noninverting output
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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dbl_align_to (0x67)
BIT 76543210
Field RSVD[1:0] AUTO_
CLINK RSVD RSVD DBL_ALIGN_TO[2:0]
Reset 11b 0b 0b 0b 111b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:6 Reserved: Do not change from default value 11: Reserved
AUTO_
CLINK 5Auto Configuration Link: Automatic control of
configuration link
0: Enable configuration link only when
CLINKEN = 1 and SEREN = 0
1: Automatically enable configuration link when
SEREN = 1 and PCLKDET = 0
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3 Reserved: Do not change from default value 0: Reserved
DBL_
ALIGN_TO 2:0
Double Alignment Mode: Sets the alignment
mode when DBL = 1 in the serializer and DBL =
0 in the deserializer. Set DBL_ALIGN_TO = 000
when an external high-low signal is used
(EN_HI_LO =1).
000: Align at each rising edge of HS. Turn off
alignment after HS is low (MAX9286). Use this
setting when an external high/low signal is used.
001: Do not use
010: Force align
011: Do not use
100: Align at each rising edge of HS
101: Align at each rising edge of DE
110: Force align
111: No alignment done while in DBL mode
cc_crc_length (0x68)
BIT 76543210
Field RSVD RSVD[2:0] RSVD[1:0] CC_CRC_LENGTH[1:0]
Reset 0b 001b 10b 01b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6:4 Reserved: Do not change from default value 001: Reserved
RSVD 3:2 Reserved: Do not change from default value 10: Reserved
CC_CRC_
LENGTH 1:0 Control-Channel CRC Length
00: 1-bit CC CRC length
01: 5-bit CC CRC length
10: 8-bit CC CRC length
11: Do not use
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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hi_lo (0x69)
BIT 76543210
Field RSVD EN_HI_LO INVERT_
HI_LO CROSSBAR_HI_LO[4:0]
Reset 0b 0b 0b 01111b
Access Type Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
EN_HI_LO 6 Enable High/Low Signal Alignment 0: Do not align using a Hi-Lo signal
1: Use a Hi-Lo signal to align input data
INVERT_
HI_LO 5Invert High/Low Signal Alignment 0: Do not invert Hi-Lo signal
1: Invert Hi-Lo signal
CROSS-
BAR_HI_
LO
4:0
Crossbar High Low: Select 1 of 16 input pins for
the Hi-Lo signal. Default values connect the Hi-Lo
signal to the VS input pin (effective when
DBL_ALIGN_TO = 000).
00000: Mux Hi-Lo signal from DIN0
00001: Mux Hi-Lo signal from DIN1
01111: Mux Hi-Lo signal from DIN15
1XXXX: Do Not Use
rsvd_96 (0x96)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
Reset 0b 0b 0b 0b 0b Xb 10b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3 Reserved: Do not change from default value 0: Reserved
RSVD 2 Reserved: Do not change from default value X: Reserved
RSVD 1:0 Reserved: Do not change from default value 10: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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rsvd_97 (0x97)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD[2:0]
Reset 0b 0b 0b 1b 1b 111b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 1: Reserved
RSVD 3 Reserved: Do not change from default value 1: Reserved
RSVD 2:0 Reserved: Do not change from default value 111: Reserved
rsvd_98 (0x98)
BIT 76543210
Field RSVD[1:0] RSVD[2:0] RSVD[2:0]
Reset 01b 001b 010b
Access Type Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:6 Reserved: Do not change from default value 01: Reserved
RSVD 5:3 Reserved: Do not change from default value 001: Reserved
RSVD 2:0 Reserved: Do not change from default value 010: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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rsvd_99 (0x99)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD[1:0]
Reset 0b 0b 0b 0b 1b 1b 01b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3 Reserved: Do not change from default value 1: Reserved
RSVD 2 Reserved: Do not change from default value 1: Reserved
RSVD 1:0 Reserved: Do not change from default value 01: Reserved
pktcc_en (0x9A)
BIT 76543210
Field RSVD[1:0] RSVD[1:0] PKTCC_EN RSVD[1:0] RSVD
Reset 00b 01b 0b 00b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:6 Reserved: Do not change from default value 00: Reserved
RSVD 5:4 Reserved: Do not change from default value 01: Reserved
PKTCC_
EN 3Packet-Based Control-Channel-Mode Enable 0: Disable packet-based control-channel mode
1: Enable packet-based control-channel mode
RSVD 2:1 Reserved: Do not change from default value 00: Reserved
RSVD 0 Reserved: Do not change from default value 0: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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rsvd_C8 (0xC8)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reset 0b Xb Xb Xb 0b 0b 0b 0b
Access Type Write, Read Read Only Read Only Read Only Read Only Read Only Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved X: Reserved
RSVD 5 Reserved X: Reserved
RSVD 4 Reserved X: Reserved
RSVD 3 Reserved 0: Reserved
RSVD 2 Reserved 0: Reserved
RSVD 1 Reserved 0: Reserved
RSVD 0 Reserved 0: Reserved
rsvd_c9 (0xC9)
BIT 76543210
Field RSVD[7:0]
Reset XXXXXXXXb
Access Type Read Only
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:0 Reserved XXXXXXXX: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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rsvd_fc (0xFC)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reset 0b 0b 0b 0b 0b 0b 0b 0b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3 Reserved: Do not change from default value 0: Reserved
RSVD 2 Reserved: Do not change from default value 0: Reserved
RSVD 1 Reserved: Do not change from default value 0: Reserved
RSVD 0 Reserved: Do not change from default value 0: Reserved
rsvd_fd (0xFD)
BIT 76543210
Field RSVD[7:0]
Reset 00000000b
Access Type Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:0 Reserved: Do not change from default value 00000000: Reserved
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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BITFIELD BITS DESCRIPTION DECODE
RSVD 7 Reserved: Do not change from default value 0: Reserved
RSVD 6 Reserved: Do not change from default value 0: Reserved
RSVD 5 Reserved: Do not change from default value 0: Reserved
RSVD 4 Reserved: Do not change from default value 0: Reserved
RSVD 3:0 Reserved XXXX: Reserved
rsvd_fe (0xFE)
BIT 76543210
Field RSVD[3:0] RSVD[3:0]
Reset 0000b 0000b
Access Type Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
RSVD 7:4 Reserved: Do not change from default value 0000: Reserved
RSVD 3:0 Reserved: Do not change from default value 0000: Reserved
rsvd_ff (0xFF)
BIT 76543210
Field RSVD RSVD RSVD RSVD RSVD[3:0]
Reset 0b 0b 0b 0b XXXXb
Access Type Write, Read Write, Read Write, Read Write, Read Read Only
MAX96705 16-Bit GMSL Serializer with High-Immunity/
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* The input bit width is limited by the number of available inputs.
** The input bit width is limited by the number of available outputs on the deserializer.
Table 2 lists the startup procedure for image-sensing
applications. The control channel is available after the
video link or the configuration link is established. If the
deserializer powers up after the serializer, the control
channel becomes unavailable until 2ms after power-up.
Applications Information
Parallel Interface
The CMOS parallel interface-data width is programmable
and depends on the application. Using a larger width
(BWS = 1) results in a lower-pixel clock rate, while a
smaller width (BWS = 0) allows a higher-pixel clock rate.
Bus Data Width
The bus data width depends on the selected modes. The
available bus width is less when using error detection or
when in double mode (DBL = 1). Table 3 shows the avail-
able bit widths and default mapping for various modes.
REGISTER BIT SETTINGS INPUT MAPPING
(WITH 96706)
INPUT MAPPING
(WITH OTHER)
DBL BWS HIBW PXL_CRC HVEN
1 1 — 1 1 DIN11:0, HS, VS DIN11:0, HS, VS
1 1 — 1 0 DIN11:0 DIN11:0
1 1 — 0 1 DIN11:0**, HS, VS DIN13:0*, HS, VS
1 1 — 0 0 DIN13:0** DIN14:0
1 0 1 1 — DIN8:0, HS, VS DIN8:0, HS, VS
1 0 1 0 — DIN11:0, HS, VS DIN11:0, HS, VS
1 0 0 1 1 DIN7:0, HS, VS DIN7:0, HS, VS
1 0 0 1 0 DIN7:0 DIN7:0
1 0 0 0 1 DIN10:0, HS, VS DIN10:0, HS, VS
1 0 0 0 0 DIN10:0 DIN10:0
0 1 — 1 1 DIN11:0**, HS, VS DIN13:0*, HS, VS
0 1 — 1 0 DIN13:0** DIN15:0*
0 1 — 0 1 DIN11:0**, HS, VS DIN13:0*, HS, VS
0 1 — 0 0 DIN13:0* DIN15:0*
0 0 1 - — DIN11:0**, HS, VS DIN13:0*, HS, VS
0 0 0 1 1 DIN11:0**, HS, VS DIN13:0*, HS, VS
0 0 0 1 0 DIN13:0** DIN15:0*
0 0 0 0 1 DIN11:0**, HS, VS DIN13:0*, HS, VS
0 0 0 0 0 DIN13:0** DIN15:0*
DBL BWS HIBW PCLK RANGE (MHz)
1 1 0 25 to 87
1 0 0 33.3 to 116
1 0 1 73.3 to 116
0 1 0 12.5 to 43.5
0 0 0 16.7 to 58
0 0 1 36.6 to 58
Table 3. Input Data-Width Selection
Table 4. Data-Rate Selection
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Bus Data Rates
The bus data rate depends on the settings for BWS and
DBL. Table 4 lists the available PCLK rates available for
different bus-width settings. For lower PCLK rates, set
DBL = 0 (if DBL = 1 in both the serializer and deserializer).
Crossbar Switch
By default, the crossbar switch connects the serializer
input pins DIN_ and HS/VS (when HV encoding is used)
to the corresponding deserializer output pins DOUT_ and
HS/VS. Reprogram the crossbar switch when changing
the input or output pin assignments, or when connecting
to devices that do not have a DBL = 1 mode.
Crossbar-Switch Programming
Each crossbar-switch output can select any of the 16
DIN_ inputs for either high or low words (when DBL =
1) for a total of 32 possible inputs. Multiple outputs can
share the same input. HS, VS, and DE remain the same
for both word halves, and should be programmed to use
the low-word input of the corresponding pin. To invert
an input data bit, set the respective INVERT_MUX_ =
1. To force an output low, (and ignore the input) set the
FORCE_MUX_ bit = 1. To force an output high set both
INVERT_MUX_ and FORCE_MUX_ = 1.
Recommended Crossbar-Switch Program Procedure
The procedure to program the crossbar switch depends on
the DBL settings on the serializer and deserializer. Devices
without double mode can be assumed to have DBL = 0.
●Both Devices' DBL Set to the Same Value
1. For the crossbar-output equivalent of DIN0 (XBO0,
XBO16) select which pin to map (e.g., DIN4 ➔ XBI4,
XBI20).
2. Set the low- and high-input crossbar bits (CROSSBAR0,
CROSSBAR 16) to the desired selected mapped input
(e.g., CROSSBAR0 = 00100, CROSSBAR16 = 10100).
3. Repeat for the other crossbar outputs, making sure
the set of high and low crossbar outputs are assigned
to the same crossbar input set. In general, XBO[i] and
XBO[i+16] should be assigned to XBI[j] and XBI[j+16].
4. For XBOHS, XBOVS, and XBODE, set crossbar to use
the low-input pins (CROSSBAR_ = 00000 to 01111). Note
that HS, VS, and DE use both the low and high input.
●Both Devices' DBL Do Not Match
1. Table 5, Table 6, and Table 7 list which crossbar output
(XBO_) maps to each serial bit.
2. For each crossbar output, select which pin and high/
low clock cycle (if needed) to map (e.g., DIN4 low input).
3. Set the crossbar bits (CROSSBAR_) to select the
desired selected mapped input (e.g., CROSSBAR0 =
00100 maps DIN4 low input to XBO0).
4. Repeat for the other crossbar outputs; any unused
serial bits should have a force low mapped to the
respective crossbar output.
BIT SETTING SERIAL BITS
DB HV BW HB CR DE 012345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
00000X01234567891011 12 13 14 15 Z Z Z Z Z Z F P
00001X01234567891011 12 13 14 15 F E E E E E E P
00010X01234567891011 12 13 14 15 Z Z Z Z Z Z F P
00011X01234567891011 12 13 14 15 Z Z Z F E E E P
00100X01234567891011 12 13 14 15 Z Z Z Z Z Z Z Z
00101X01234567891011 12 13 14 15 Z Z Z Z Z Z Z Z
01000X01234567891011 12 13 14 15 Z Z Z Z Z Z F P
01001X01234567891011 12 13 14 15 F E E E E E E P
01100X01234567891011 12 13 14 15 Z Z Z Z Z Z Z Z
01101X01234567891011 12 13 14 15 Z Z Z Z Z Z Z Z
1 0 0 0 0 X 16 17 18 19 20 21 22 23 24 25 26 0 1 2 3 4 5 6 7 8 9 10 F P
1 0 0 0 1 X 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 F E E E E E E P
1 0 0 1 0 X 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 Z F P
Table 5. Crossbar Output to Serial Link Map (D23:0)
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Table 5. Crossbar Output to Serial Link Map (D23:0) (continued)
BIT SETTING SERIAL BITS
DB HV BW HB CR DE 012345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 0 0 1 1 X 16 17 18 19 20 21 22 23 24 0 1 2 3 4 5 6 7 8 Z F E E E P
1 0 1 0 0 X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0 1 2 3 4 5 6 7 8
1 0 1 0 1 1 16 17 18 19 20 21 22 23 24 25 26 DH 0 1 2 3 4 5 6 7 8 9 10 DL
1 0 1 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 9 10 11
1 1 0 0 0 1 16 17 18 19 20 21 22 23 24 25 DH 0 1 2 3 4 5 6 7 8 9 DL F P
1 1 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 0 1 2 3 4 5 6 7 8 9 10 F P
1 1 0 0 1 1 16 17 18 19 20 21 22 DH 0 1 2 3 4 5 6 DL F E E E E E E P
1 1 0 0 1 0 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 F E E E E E E P
1 1 1 0 0 X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0 1 2 3 4 5 6 7 8
1 1 1 0 1 1 16 17 18 19 20 21 22 23 24 25 26 DH 0 1 2 3 4 5 6 7 8 9 10 DL
1 1 1 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 9 10 11
Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets)
BIT SETTING SPECIAL PACKETS
DB HV BW HB CR DE 24 25 26 27 28 29 30 31 C0 C1 C2 C3 HS VS DE
0 0 0 0 0 X — — — — — — — — — — — — — — —
0 0 0 0 1 X — — — — — — — — — — — — — — —
0 0 0 1 0 X Z Z Z — — — — — Z Z Z Z H V D
0 0 0 1 1 X E E E — — — — — Z Z Z Z H V D
0 0 1 0 0 X Z Z Z Z Z Z F P — — — — — — —
0 0 1 0 1 X F E E E E E E P — — — — — — —
0 1 0 0 0 X — — — — — — — — — — — — H V —
0 1 0 0 1 X — — — — — — — — — — — — H V —
0 1 1 0 0 X Z Z Z Z Z Z F P — — — — H V —
0 1 1 0 1 X F E E E E E E P — — — — H V —
1 0 0 0 0 X — — — — — — — — — — — — — — —
1 0 0 0 1 X — — — — — — — — — — — — — — —
1 0 0 1 0 X 9 10 11 — — — — — A Z A A H V D
1 0 0 1 1 X E E E — — — — — A Z A A H V D
1 0 1 0 0 X 9 10 11 12 13 14 F P — — — — — — —
1 0 1 0 1 1 F E E E E E E P — — — — — — —
1 0 1 0 1 0 F E E E E E E P — — — — — — —
1 1 0 0 0 1 — — — — — — — — — — — — HH/L VH/L —
1 1 0 0 0 0 — — — — — — — — — — — — HH/L VH/L —
1 1 0 0 1 1 — — — — — — — — — — — — HH/L VH/L —
1 1 0 0 1 0 — — — — — — — — — — — — HH/L VH/L —
1 1 1 0 0 X 9 10 11 12 13 14 F P — — — — HH/L VH/L —
1 1 1 0 1 1 F E E E E E E P — — — — HH/L VH/L —
1 1 1 0 1 0 F E E E E E E P - - - - HH/L VH/L -
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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xaus xmao xam xmze xaus xmza xauz xam xam xmze xauu xmzs xawe xaw xawa xmzs xaw xmzz xawe xam xaws xmzo XBM xaue xaws xaua xawz xaw xau HS
Table 7. Legend
BIT SETTINGS MAP INPUTS
DB Double-mode bit DBL H HSYNC ( when DBL = 0 or HIBW = 1)
HV H/V Encoding bit HVEN V VSYNC ( when DBL = 0 or HIBW = 1)
BW BWS bit D DE ( when DBL = 0 or HIBW = 1)
HB HIBW bit HH HSYNC (high word, DBL = 1)
CR PXL_CRC bit VH VSYNC (high word, DBL = 1)
DE DE = 1 when DEEN = 1 and not processed in RGB888 mode DH DE (high word, DBL = 1)
X 1 or 0 HL HSYNC (low word, DBL = 1)
SPECIAL PACKETS VL VSYNC (low word, DBL = 1)
C0 CNT_0 DL DE (low word, DBL = 1)
C1 CNT_1 # XBO output from crossbar switch
C2 CNT_2 F Internal forward control-channel bit
C3 CNT_3 E Internal pixel CRC bit
BIT COLOR P Internal pixel parity bit
Output bits from crossbar — Serial bit not sent
Internal bits Z Zero
Other output bits A Internal alignment bit (used when HIBW=1)
Output bits from sync
Figure 20. Crossbar-Switch Default Mapping
XBI15
XBI30 XBI14
XBI29 XBI13
XBI28 XBI12
XBI27 XBI11
XBI26 XBI10
XBI25 XBI9
XBI24 XBI8
XBI23 XBI7
XBI22 XBI6
XBI21 XBI5
XBI20 XBI4
XBI19 XBI3
XBI18 XBI2
XBI17 XBI1
XBI16 XBI0
DIN15/VS
INPUT PIN
DIN14/HS
DIN13
DIN12
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
ALIGNMENT
HS* HS HS
HI_LO*
PCLK
XBI15
XBI30 XBI14
XBI29 XBI13
XBI28 XBI12
XBI27 XBI11
XBI26 XBI10
XBI25 XBI9
XBI24 XBI8
XBI23 XBI7
XBI22 XBI6
XBI21 XBI5
XBI20 XBI4
XBI19 XBI3
XBI18 XBI2
XBI17 XBI1
XBI16 XBI0
PIXEL N N+1
DE* DE DE
XBI31
XBI31
*REGISTER SETTINGS
DECIDE IF HS, DE, OR HI_LO
DETERMINES THE HIGH/LOW
INPUT TIMING.
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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5. For XBOHS, XBOVS, and XBODE, set crossbar to use
the low-input pins (CROSSBAR_ = 00000 to 01111). Note
that HS, VS, and DE use both the low and high input.
Timing-Generator Programming
Timing-generator parameters are stored in the registers
as unsigned integers as PCLK periods. To prevent out-
put glitches, program all timing-generator parameters
while the device is in configuration-link mode, or when
PCLK is not applied. By default, the timing generator
is set to single trigger, and is disabled. Figure 18 show
the timing waveforms under the default conditions with
rising-edge trigger, and noninverted signals. Do not pro-
gram the HSYNC or DE signals such that the total length
exceeds the length of a VSYNC period (Table 8). All delay
parameters are positive. To implement a negative delay,
set the delay value subtracted from the VSYNC period
(e.g., a delay value of VS_HIGH + VS_LOW - N creates
a delay of -N PCLK cycles). Do not set any delay lengths
larger than the VSYNC period.
Double-Mode Alignment
When DBL = 1 in both the serializer and deserializer, GMSL
automatically keeps the pixels in order. Use double-mode
alignment when DBL = 1 in the serializer and DBL = 0
(or is not supported) in the deserializer. Two different
methods are available for double-mode alignment.
External High/Low Signal
To use an external alignment signal, set EN_HI_LO =
1, DBL_ALIGN_TO = 000, and select which input DIN_
pin to use by setting the CROSSBAR_HI_LO bits. The
external signal designates whether the clocked word is
the high or low word (e.g., for pixels [1H, 1L, 2H, 2L...] the
high/low signal would be [1, 0, 1, 0...]).
Align from HS or DE
To align from a sync signal, set the DBL_ALIGN_TO to
select the input signal. When using this mode, ensure
that the signal used for alignment uses the same value
for both the high and low word (e.g., for pixels [1H, 1L,
2H, 2L...], aligning on DE requires values of [DE1, DE1,
DE2, DE2...]).
Control-Channel Interfaces
I2C
Set I2CSEL = 1 to configure the control channel for I2C
to I2C. In this mode, the control channel forwards I2C
commands from the microcontroller side to the other
side of the GMSL link. The remote device acts as an I2C
master to the other peripherals connected to the remote-
side device. I2C-to-I2C mode uses clock stretching to hold
the microcontroller until the data and an acknowledge or
not acknowledge have been sent across the link.
I2C Bit Rate
The I2C interface accepts bit rates from 9.6kbps to
1Mbps. The local I2C rate is set by the microcontroller.
SIGNAL SIZE (BITS) MIN VALUE
(HEX)
MAXIMUM VALUE RESTRICTION
(HEX)
VS_HIGH 24 1 VS_HIGH + VS_LOW < 0xFFFFFF
VS_LOW 24 1 VS_HIGH + VS_LOW < 0xFFFFFF
VS_DLY 24 0 VS_DLY < VS_HIGH + VS_LOW
HS_HIGH 16 1 (HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
HS_LOW 16 1 (HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
HS_CNT 16 1 (HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
HS_DLY 24 0 HS_DLY < VS_HIGH + VS_LOW
DE_HIGH 16 1 (DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
DE_LOW 16 1 (DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
DE_CNT 16 1 (DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
DE_DLY 24 0 DE_DLY < VS_HIGH + VS_LOW
Table 8. Timing-Generator Parameter Restrictions
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
The remote I2C rate is set by the remote device. By
default, the control channel is set up for a 400kbps I2C bit
rate. Program the I2C_MSTBT and SLV_SH bits (register
0x0D) to match the desired microcontroller I2C rate.
Software Programming of Device Addresses
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
I2C peripherals, to coexist on the same control channel.
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
write to the device whose address changes (register 0x00
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then, write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
I2C Address Translation
The device supports I2C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I2C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
Configuration Blocking
The device can block changes to its registers. Set
CFGBLOCK to make all registers read-only. Once set, the
registers remain blocked until the supplies are removed or
until PWDNB is low.
Cascaded/Parallel Devices
GMSL supports both cascaded and parallel devices
connected through I2C. When cascading or using parallel
links, all I2C commands are forwarded to all links. Each
link attempts to hold the control channel until it receives
an acknowledge/not acknowledge from the remote-side
device. It is important to keep the control channel active
between links to prevent timeout. If a link is unused, keep
the control channel clear by turning on the configuration
link, disconnecting the I2C lines, or powering down the
unused device.
Dual μC Control
Most systems use a single microcontroller; however μCs
can reside on each side simultaneously and trade off
in running the control channel. Contention occurs if both
μCs attempt to use the control channel at the same time.
It is up to the user to prevent this contention by imple-
menting a higher level protocol. In addition, the control
channel does not provide arbitration between I2C masters
on both sides of the link. An acknowledge frame is not
generated when communication fails due to contention. If
communication across the serial link is not required, the
μCs can disable the forward and reverse control channel
using the FWDCCEN and REVCCEN bits (0x04, D[1:0])
in the serializer/deserializer. Communication across the
serial link is stopped and contention between μCs cannot
occur.
UART
Set I2CSEL = 0 to configure the control channel for UART
or UART-to-I2C mode. In this mode, the control channel
forwards UART commands from the microcontroller side
to the other side of the GMSL link. When INTTYPE =
00, the remote device acts as an I2C master to the other
peripherals connected to the remote-side device. UART-
to-I2C mode does not support devices that use clock
stretching.
Base Mode
In base mode, UART packets control the serializer,
deserializer, and attached peripherals.
UART Timing
In base mode, the UART idles high (through a pullup
resistor). Each GMSL UART byte consists of a START bit,
8 data bits, an even-parity bit, and a STOP bit (Figure 21).
Keep the idle time between bytes of the same UART packet
to less than 4 bit times. The GMSL-UART protocol is listed in
Figure 22. A write packet consists of a SYNC byte (Figure 23),
device address byte, starting register address byte,
number of bytes to write, and the data bytes. The slave
device responds with an ACK byte (Figure 24) if the write
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
E‘ E‘
Figure 23. SYNC Byte (0x79) Figure 24. ACK Byte (0xC3)
Figure 21. GMSL-UART Data Format for Base Mode
Figure 22. GMSL-UART Protocol for Base Mode
WRITE DATA FORMAT
SYNC REG ADDR
NUMBER OF BYTES
SYNC DEV ADDR + R/W REG ADDR
NUMBER OF BYTES
BYTE 1 BYTE N
ACK
BYTE NBYTE 1ACK
MASTER READS FROM SLAVE
READ DATA FORMAT
MASTER WRITES TO SLAVE
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
DEV ADDR + R/W
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY* STOP
1 UART FRAME
FRAME 1 FRAME 2 FRAME 3
*BASE MODE USES EVEN PARITY
START STOP STARTSTOP
START
D0
10011110
D1 D2 D3 D4 D5 D6 D7
PARITY STOP START
D0
11000011
D1 D2 D3 D4 D5 D6 D7
PARITY STOP
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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was successful. A read packet consists of a SYNC byte,
device address byte, starting register address byte, and
number of bytes to read. The slave device responds with
an ACK byte, and the read data bytes.
UART-to-I2C Conversion
When using the UART control channel, the remote-side
device can communicate to I2C peripherals through
UART-to-I2C conversion. Set the INTTYPE bits in
the remote-side device to 00 to activate UART-to-I2C
conversion. The converted I2C bit rate is the same as
the incoming UART bit rate. I2C peripherals must not use
clock stretching in order to be compatible with UART-to-
I2C conversion.
There are two possible methods the devices use to
convert UART to I2C. In the first method (I2CMETHOD =
0), the register address is sent with the I2C communica-
tion (Figure 25). For devices that do not use a register
address (such as the MAX7324), set I2CMETHOD = 1
Figure 25. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
Figure 26. Format Conversion Between GMSL UART and I2C without Register Address (I2CMETHOD = 1)
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + WR DATA 0
DEV ID A
11 11 11 11
DATA N
11 11
S
1 11
ACK FRAME
7
: MASTER TO SLAVE
8
SERIALIZER/DESERIALIZER PERIPHERAL
W
1
REG ADDR
8
A
1 1 8 1
11
SYNC FRAME REGISTER ADDRESS NUMBER OF BYTESDEVICE ID + RD
11 11 11 11
ACK FRAME DATA 0
11
DATA N
11
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
S: START P: STOP A: ACKNOWLEDGE
: SLAVE TO MASTER
DATA 0 ADATA N A P
DEV ID AS
1 17
W
1
DEV ID AS
1 17
R
1
DATA N P
18
A
1
DATA 0
8
A
1
REG ADDR
8
A
1
µC SERIALIZER/DESERIALIZER
µC SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER PERIPHERAL
MASTER TO SLAVE
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZERµC
SYNC FRAME
11 11 11 11 11 11 11
1111 11 11 11 11 11
DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
ACK FRAME DATA 0 DATA N
DATA NADATA 0W ADEV IDS A P
PERIPHERAL
PERIPHERAL
S
1 1 1 8
8 81111 7 1 1
8
1 1 17
DEV ID R A A A PDATA 0 DATA N
SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Table 9. Output Spread
and send a dummy byte in place of the register address
(Figure 26). In this method, the remote device omits send-
ing the register address.
UART Bypass Mode
In UART bypass mode, the control channel acts as a
full-duplex 9.6kbps to 1Mbps link that forwards UART
commands across the serial link without responding to
the packets themselves. Set MS high to enter bypass
mode (wait 1ms after setting bypass mode if the μC is
connected on the deserializer side). Bypass uses bit rates
from 9.6kbps to 1Mbps. Do not send a logic-low value
longer than 100μs when using the GPI/GPO functionality.
Device Address
The serializer/deserializer both have a 7-bit-long slave
address stored in registers 0x00 and 0x01. The bit follow-
ing a 7-bit slave address is the R/W bit, which is low for a
write command and high for a read command. The default
slave address is 0x80. After startup, a microcontroller can
reprogram the slave address as needed.
Spread Spectrum
Program the SS bits in the serializer to turn on spread
spectrum in the serializer (Table 9). If the deserializer
driven by the serializer has programmable spread
spectrum, do not enable spread for both at the same
time or their interaction cancels benefits. The deserializer
tracks the serializer’s spread and passes the spread to
the deserializer output. Some spread-spectrum ampli-
BWS = 0 MODE, PCLKIN
FREQUENCY (MHz)
BWS = 1 MODE, PCLKIN
FREQUENCY (MHz)
SERIAL LINK BIT RATE
(MBPS) AVAILABLE SPREAD RATES
< 33.3 (DBL = 0) < 25 (DBL = 0) < 1000 All rates available
< 66.6 (DBL = 1) < 50 (DBL = 1)
33.3 to 58 (DBL = 0) 25 to 43.5 (DBL = 0) ≥ 1000 1.5%, 1%, 0.5%
66.6 to 116 (DBL = 1) 50 to 87 (DBL = 1)
Table 10. Spread Limitations
Table 9. Output Spread
SS SPREAD (%)
000 POWER-UP DEFAULT (NO SPREAD SPECTRUM)
001 ±0.5% SPREAD SPECTRUM
010 ±1.5% SPREAD SPECTRUM
011 ±2% SPREAD SPECTRUM
100 NO SPREAD SPECTRUM
101 ±1% SPREAD SPECTRUM
110 ±3% SPREAD SPECTRUM
111 ±4% SPREAD SPECTRUM
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
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tudes can only be used at lower PCLKIN frequencies
(Table 10). When the spread spectrum is turned on or off,
the serial link stops for several microseconds and then
restarts in order for the deserializer to lose and relock
to the new serial-data stream. Changing the spread-
spectrum amplitude does not cause a loss of lock.
Manual Programming of the Spread-Spectrum
Divider
By default, autodetection of the PCLKIN operation range
guarantees a spread-spectrum modulation frequency
within 20kHz to 40kHz. Additionally, manual configura-
tion of the sawtooth divider (SDIV: 0x03,D[5:0]) allows
the user to set a modulation frequency (typically 20kHz)
according to the PCLKIN frequency.
Equation:
Relation of modulation rate to the PCLKIN frequency:
fM = fPCLKIN/(MOD x SDIV)
where:
fM = Modulation frequency
fPCLKIN = PCLKIN frequency
MOD = Modulation coefficient given in Table 11
SDIV = 6-bit SDIV setting, manually programmed by the μC
To program the SDIV setting, first look up the modulation
coefficient according to the desired bus-width and spread-
spectrum settings. Solve the above equation for SDIV using
the desired pixel clock and modulation frequencies. If the
calculated SDIV value is larger than the maximum allowed
SDIV value in Table 11, set SDIV to the maximum value.
Board Layout
Power-Supply Circuits and Bypassing
The serializer uses an AVDD and DVDD of 1.7V to 1.9V.
All inputs and outputs, except for the serial output, derive
power from an IOVDD of 1.7V to 3.6V that scales with
IOVDD. Proper voltage-supply bypassing is essential for
high-frequency circuit stability.
High-Frequency Signals
Table 11. Modulation Coefficients and
Maximum SDIV Settings
BWS
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(DEC)
SDIV UPPER
LIMIT (DEC)
1
1 104 40
0.5 104 63
3 152 27
1.5 152 54
4 204 15
2 204 30
0
1 80 52
0.5 80 63
3112 37
1.5 112 63
4 152 21
2 152 42
Figure 29. ISO 10605 Contact Discharge ESD Test Circuit
Figure 27. Human Body Model ESD Test Circuit
Figure 28. IEC 61000-4-2 Contact Discharge ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩ
RD
1.5kΩ
CS
100pF
CS
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
330Ω
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
RD
2kΩ
CS
330pF
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout STP-PCB traces close to
each other for a 100Ω differential characteristic imped-
ance. The trace dimensions depend on the type of trace
used (microstrip or stripline).
Note: Two 50Ω PCB traces do not have 100Ω differential
impedance when brought close together; the impedance
goes down when the traces are brought closer. Use a 50Ω
trace for the single-ended output when driving coax. Route
the PCB traces for differential CML in parallel to maintain
the differential characteristic impedance. Avoid via arrays.
Keep PCB traces that make up a differential pair equal in
length to avoid skew within the differential pair.
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kΩ (Figure 27). The IEC 61000-4-2 discharge compo-
nents are CS = 150pF and RD = 330Ω (Figure 28). The
ISO 10605 discharge components are CS = 330pF and
RD = 2kΩ (Figure 29).
Compatibility with Other GMSL Devices
The device is designed to pair with the MAX96705–
MAX96711 family of devices, but interoperates with any
GMSL device. See Table 12 for operating limitations.
Device Configuration and Component Selection
Internal Input Pulldowns
SERIALIZER FEATURE GMSL DESERIALIZER
HSYNC/VSYNC Encoding If feature not supported in the deserializer, turn off in the serializer.
I2C to I2C If feature not supported in the deserializer, use UART to I2C or UART to UART.
Packet Control Channel If feature not supported in the deserializer, use legacy control channel.
CRC Error Detection If feature not supported in the deserializer, turn off in the serializer.
Double Input If feature not supported in the deserializer, data is output as a single word at half the in-
put frequency. Use crossbar switch and double-mode alignment to correct input mapping.
Coax If feature not supported in the deserializer, connect unused serial input through 200nF
and 50Ω in series to AVDD, and set the reverse control-channel amplitude to 100mV.
I2S Encoding If supported in the deserializer, disable I2S in the deserializer.
High-Bandwidth Mode If feature not supported in the deserializer, turn off in the serializer.
High-Immunity Mode If feature not supported in the deserializer, turn off in the serializer.
Low-Speed Mode If supported in the deserializer, set DRS to 0 in the deserializer.
Table 12. Feature Compatibility
Table 13. Three-Level Configuration Input Map
CONF1 CONF0 CXTP
(OUT+/OUT- OUTPUT TYPE)
ES
(PCLKIN LATCH EDGE)
I2CSEL
(CONTROL-CHANNEL TYPE)
LOW LOW 1 (COAX) 1 (FALLING) 1 (I2C O I2C)
LOW MID 1 (COAX) 1 (FALLING) 0 (UART TO I2C/UART)
LOW HIGH 1 (COAX) 0 (RISING) 1 (I2C TO I2C)
MID LOW 1 (COAX) 0 (RISING) 0 (UART TO I2C/UART)
MID MID 0 (STP) 1 (FALLING) 1 (I2C TO I2C)
MID HIGH 0 (STP) 1 (FALLING) 0 (UART TO I2C/UART)
HIGH LOW 0 (STP) 0 (RISING) 1 (I2C TO I2C)
HIGH MID 0 (STP) 0 (RISING) 0 (UART TO I2C/UART)
HIGH HIGH DO NOT USE DO NOT USE DO NOT USE
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
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The control and configuration inputs (except three-level
inputs) include a pulldown resistor to GND; external pull-
down resistors are not needed.
Three-Level Configuration Inputs
CONF1 and CONF0 are three-level inputs that control
the serial interface configuration and power-up defaults
(Table 13). Connect CONF1 or CONF0 to IOVDD to set a
high level, to GND to set a low level, or open to set a mid
level. For digital control, use three-state logic to drive the
three-level logic inputs. CONF pin values are latched at
power-up or resuming from power-down mode.
Multifunction Inputs
The device has several inputs/outputs that serve multiple
functions. GPO/HIM functions as the GPO output, and as
a configuration pin. On power-up, or when reverting from
a power-down state, the pins act as the HIM input. After
latching the input state, the pin becomes the GPO output.
Connect a configuration input through a 30kΩ resistor to
IOVDD to set a high level. Leave the configuration input
open to set a low level.
In addition, several multifunction pins are controlled by
the LCCEN input. When LCCEN = 1, the local control
channel (RX/SDA, TX/SCL) is active, and the GPIO1/
BWS and MS/HVEN pins behave as GPIO1 and the MS
input respectively. When LCCEN = 0, the local control
channel is disabled, and these pins operate as their alter-
nate function (DBL, BWS, HVEN inputs).
I2C/UART Pullup Resistors
The I2C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compro-
mise may be required when choosing pullup resistor
values. Every device connected to the bus introduces
some capacitance even when the device is not in opera-
tion. I2C specifies 300ns rise times (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
the I2C/UART Port Timing section in the AC Electrical
Characteristics table for details). To meet the fast-mode
rise-time requirement, choose the pullup resistors so
that rise time tR = 0.85 x RPULLUP x CBUS < 300ns.
The waveforms are not recognized if the transition time
becomes too slow. GMSL supports I2C/UART rates up
to 1Mbps (UART-to-I2C mode) and 400kbps (I2C-to-I2C
mode).
AC-Coupling Capacitors
Voltage droop and the digital-sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition
time is fixed, starting the signal transition from different
voltage levels causes timing jitter. The time constant for
an AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for
an AC-coupled link consists of the CML/coax receiver
termination resistor (RTR), the CML/coax-driver termi-
nation resistor (RTD), and the series AC-coupling
capacitors (C). The RC time constant for four equal-value
series capacitors is (C x (RTD + RTR))/4. RTD and RTR
are required to match the transmission-line impedance
(usually 100Ω differential, 50Ω single-ended). This leaves
the capacitor selection to change the system time con-
stant. Use 0.22μF or larger high-frequency, surface-mount
ceramic capacitors with sufficient voltage rating to with-
stand a short to battery, to pass the lower speed reverse
control-channel signal. Use capacitors with a case size less
than 3.2mm x 1.6mm to have lower-parasitic effects to the
high-speed signal.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω; contact the factory for 75Ω operation).
Table 14 lists the suggested cables and connectors used
in the GMSL link.
PRBS
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To
run the PRBS test, set PRBSEN = 1 (0x04, D5) in the
VENDOR CONNECTOR CABLE TYPE
Rosenberger 59S2AX-400A5-Y Dacar 302 Coax
Rosenberger D4S10A-40ML5-Z Dacar 535-2 STP
Nissei GT11L-2S F-2WME AWG28 STP
JAE MX38-FF A-BW-Lxxxxx STP
Table 14. Suggested Connectors and Cables for GMSL
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
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deserializer, then in the serializer. To exit the PRBS
test, set PRBSEN = 0 (0x04, D5) in the serializer. The
deserializer automatically ends PRBS checking and sets
the PRBS_OK bit high. During PRBS mode, the forward
control channel is not available except to exit PRBS mode
if autoacknowledge is enabled in the deserializer; other-
wise, the remote control channel is not available at all.
To run the PRBS with a 3Gbps SerDes, or when HIBW = 1,
first set the PRBS_TYPE bit = 0 in the MAX967XX. Then
set PRBSEN = 1 (0x04, D5) in the serializer and then in
the deserializer. To exit the PRBS test, set PRBSEN = 0
(0x04, D5) in the deserializer, then in the serializer.
During PRBS test, ERRB function changes to reflect
PRBS errors only. ERRB goes low when any PRBS errors
occur. ERRB goes high when the PRBS error counter is
reset when PRBS_ERR is read. Normal ERRB function
resumes when exiting the PRBS test.
GPI/GPO
GPO on the serializer follows GPI transitions on the
deserializer. By default, the GPI-to-GPO delay is 0.35ms
(max). Keep the time between GPI transitions to a
minimum 0.35ms. GPI_IN the deserializer stores the GPI
input state. GPO is low after power-up. The μC can set
GPO by writing to the SET_GPO register bit. Do not send
a logic-low value on the deserializer RX/SDA input (UART
mode) longer than 100μs in either base or bypass mode
to ensure proper GPO/GPI functionality.
Fast Detection of Loss-of-Lock
A measure of link quality is the recovery time from loss-
of-synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK output
to the GPI input (when PKTCC_EN = 0). If other sources
use the GPI input, such as a touch-screen controller, the
μC can implement a routine to distinguish between inter-
rupts from loss-of-sync and normal interrupts. Reverse
control-channel communication does not require an active
forward link to operate and accurately tracks the LOCK
status of the GMSL link. LOCK asserts for video link only
and not for the configuration link.
Providing a Frame Sync (Camera Applications)
The GPI and GPO provide a simple solution for camera
applications that require a frame-sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame-sync signal to the GPI input and connect the GPO
output to the camera frame-sync input. GPI/GPO have a
typical delay of 275μs in legacy mode and 21μs in packet
mode (with 5-bit CRC). Skew between multiple GPI/
GPO channels is 115μs (max) in legacy mode and 21μs
(max) in packet mode. If a lower skew signal is required
in legacy mode, connect the camera’s frame-sync input
to one of the serializer’s GPIOs and use an I2C broad-
cast-write command to change the GPIO output state.
This has a maximum skew of 1.5μs, independent from
the used I2C bit rate. In packet-based control-channel
mode, set GPI_COMP_EN = 1 in both the serializer and
deserializer to turn on GPI/GPO compensation. This
reduces the device-to-device skew to 0.35μs.
Entering/Exiting Sleep Mode
The procedure for entering and exiting sleep mode
depends on the location of the microcontroller, and the
type of control-channel interface used. If wake up from a
remote (deserializer) side microcontroller is not needed or
desired, set the DIS_RWAKE bit = 1 to shut down remote
wake-up for further power savings.
Legacy Control Channel:
To enter sleep mode, set SLEEP = 1. The device sleeps
after 8ms. To wake up the device, send an arbitrary
control-channel command to the serializer (the serializer
does not send an acknowledge), wait for 5ms for the chip
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
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+Denotes a lead(Pb)r/ree/RoHSrcompIiam package.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
/V denotes an automotive qualified product.
*EP = Exposed pad.
PART NUMBER TEMP RANGE PIN-PACKAGE
MAX96705GTJ+ -40°C to +115°C 32 TQFN-EP*
MAX96705GTJ+T -40°C to +115°C 32 TQFN-EP*
MAX96705GTJ/V+ -40°C to +115°C 32 TQFN-EP*
MAX96705GTJ/V+T -40°C to +115°C 32 TQFN-EP*
Typical Application Circuits
Ordering Information
MAX96705 16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 12/15 Initial release —
1 2/17
Added HIM software controls, fxed typos, disclosed hidden registers, and added three
new variants in Ordering Information (MAX96705GTJ+, MAX96705GTJ+T, and
MAX96705GTJ/V+T)
6, 29, 30, 32,
33–36, 39, 45,
46, 48–50 57,
58, 63, 66, 68,
72, 76, 79, 80,
82
1.1 Corrected formatting 29, 31
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc.
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MAX96705 16-Bit GMSL Serializer with High-Immunity/
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.