SN74HC595B Datasheet by Texas Instruments

V'.‘ 3!. B X I TEXAS INSTRUMENTS
>
R
C1
1D
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>
3S
C3
3R
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
QA
QB
QH
QE
QF
QD
Q+
QG
QC
15
1
2
3
4
5
6
7
9
14
11
10
12
13
SER
SRCLK
SRCLR
RCLK
OE
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HC595B
SCLS751 –MARCH 2016
SN74HC595B 8-Bit Shift Registers With 3-State Output Registers
1
1 Features
1 8-Bit Serial-In, Parallel-Out Shift Registers
Available in Ultra Small Logic QFN package(0.5
mm max height)
Over-Voltage Tolerant on Inputs Independent of
Vcc
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up to 15
LSTTL Loads
Low Power Consumption: 80-μA (Maximum) ICC
• tpd = 13 ns (Typical)
±6-mA Output Drive at 5 V
Low Input Current: 1 μA (Maximum)
Shift Register Has Direct Clear
• -55oC to 125oC Operating Temperature
2 Applications
Network Switches
Factory Automation
Mobile Wearables
Industrial Building Automation
Power Infrastructure
LED Displays
• Servers
3 Description
The SN74HC595B devices contain an 8-bit, serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel 3-
state outputs. Separate clocks are provided for both
the shift register and storage register. The shift
register has a direct overriding clear (SRCLR) input,
serial (SER) input, and serial outputs for cascading.
When the output-enable (OE) input is high, the all
outputs are in the high-impedance state except QH'.
Table 1. Device Information
PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
SN74HC595BRWN X1QFN (16) 2.50 mm x 2.50 mm
(1) For available package, see the orderable addendum at the
end of the data sheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
2
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Pin Configuration and Functions......................... 3
5 Specifications......................................................... 4
5.1 Absolute Maximum Ratings ...................................... 4
5.2 ESD Ratings.............................................................. 4
5.3 Recommended Operating Conditions....................... 4
5.4 Thermal Information.................................................. 5
5.5 Electrical Characteristics........................................... 5
5.6 Timing Requirements................................................ 6
5.7 Switching Characteristics.......................................... 7
5.8 Operating Characteristics.......................................... 8
5.9 Typical Characteristics.............................................. 9
6 Parameter Measurement Information ................ 10
7 Detailed Description............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1 Documentation Support ........................................ 17
11.2 Community Resources.......................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
{L} TEXAS INSTRUMENTS UDDD flflflm
4
3
2
112
11
10
9
RCLK
SRCLK
SRCLR
QH[
QF
QG
QH
GND
VCC
QA
SER
OE
16 13
15 14
8
576
QB
QC
QD
QE
3
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
4 Pin Configuration and Functions
RWN Package
16-Pin XQFN
Bottom View
Table 2. Pin Functions
PIN I/O DESCRIPTION
NAME RWN
GND 8 Ground Pin
OE 13 I Output Enable; does not control QH'
QA15 O QAOutput
QB1 O QBOutput
QC2 O QCOutput
QD3 O QDOutput
QE4 O QEOutput
QF5 O QFOutput
QG6 O QGOutput
QH7 O QHOutput
QH' 9 O QH' Output
RCLK 12 I RCLK Input
SER 14 I SER Input
SRCLK 11 I SRCLK Input
SRCLR 10 I SRCLR Input
VCC 16 Power Pin
l TEXAS INSTRUMENTS
4
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VIInput voltage -0.5 7 V
IIK Input clamp current(1) VI< 0 -20 mA
IOK Output clamp current (2) VO< 0 or VO> VCC ±20 mA
IOContinuous output current VO= 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins(2) ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs,SCBA004.
(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt= 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN74HC595B UNIT
MIN NOM MAX
VCC Supply voltage 2 5 6 V
VIH High-level input voltage
VCC = 2 V 1.5
VVCC = 4.5 V 3.15
VCC = 6 V 4.2
VIL Low-level input voltage
VCC = 2 V 0.5
VVCC = 4.5 V 1.35
VCC = 6 V 1.8
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
Δt/Δv Input transition rise or fall time(2)
VCC = 2 V 1000
nsVCC = 4.5 V 500
VCC = 6 V 400
TAOperating free-air temperature –55 125 °C
l TEXAS INSTRUMENTS
5
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.4 Thermal Information
THERMAL METRIC(1)
SN74HC595B
UNITRWN (X1QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 112
°C/W
RθJCtop Junction-to-case (top) thermal resistance 47.9
RθJB Junction-to-board thermal resistance 72.4
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 72.4
RθJCbot Junction-to-case (bottom) thermal resistance 32.2
5.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC
TA= 25°C TA= -55°C to 125°C TA= -40°C to 85°C UNIT
MIN TYP MAX MIN MAX MIN MAX
VOH VI= VIH or VIL
IOH = –20 μA
2 V 1.9 1.998 1.9 1.9
V
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
QH, IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
QA– QH, IOH = –6 mA 3.98 4.3 3.7 3.84
QH, IOH =5.2 mA 6 V 5.48 5.8 5.2 5.34
QA– QH, IOH = –7.8 mA 5.48 5.8 5.2 5.34
VOL VI= VIH or VIL
IOL = 20 μA
2 V 0.002 0.1 0.1 0.1
V
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
QH, IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
QA– QH, IOL = 6 mA 0.17 0.26 0.4 0.33
QH, IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
QA– QH, IOL = 7.8 mA 0.15 0.26 0.4 0.33
IIVI= VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO= VCC or 0, QA– QH6 V ±0.01 ±0.5 ±10 ±5 µA
ICC VI= VCC or 0, IO= 0 6 V 8 160 80 µA
Ci2 V to
6 V 3 10 10 10 pF
l TEXAS INSTRUMENTS
6
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
(1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
5.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
VCC TA= 25°C TA= -55°C to 125°C TA= -40°C to 85°C UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency
2 V 6 4.2 5
MHz4.5 V 31 21 25
6 V 36 25 29
twPulse
duration
SRCLK or RCLK high or low
2 V 80 120 100
ns
4.5 V 16 24 20
6 V 14 20 17
SRCLR low
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
tsu Set-up time
SER before SRCLK
2 V 100 150 125
ns
4.5 V 20 30 25
6 V 17 25 21
SRCLKbefore RCLK(1)
2 V 75 113 94
4.5 V 15 23 19
6 V 13 19 16
SRCLR low before RCLK
2 V 50 75 65
4.5 V 10 15 13
6 V 9 13 11
SRCLR high (inactive)
before SRCLK
2 V 50 75 60
4.5 V 10 15 12
6 V 9 13 11
thHold time, SER after SRCLK
2 V 0 0 0
ns4.5 V 0 0 0
6 V 0 0 0
l TEXAS INSTRUMENTS
7
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
5.7 Switching Characteristics
Over recommended operating free-air temperature range.
PARAMETER FROM
(INPUT) TO
(OUTPUT) LOAD
CAPACITANCE VCC TA= 25°C TA= -55°C to
125°C TA= -40°C to
85°C UNIT
MIN TYP MAX MIN MAX MIN MAX
fmax 50 pF
2 V 6 26 4.2 5
MHz4.5 V 31 38 21 25
6 V 36 42 25 29
tpd
SRCLK QH50 pF
2 V 50 160 240 200
ns
4.5 V 17 32 48 40
6 V 14 27 41 34
RCLK QA– QH50 pF
2 V 50 150 225 187
4.5 V 17 30 45 37
6 V 14 26 38 32
tPHL SRCLR QH50 pF
2 V 51 175 261 219
ns4.5 V 18 35 52 44
6 V 15 30 44 37
ten OE QA– QH50 pF
2 V 40 150 255 187
ns4.5 V 15 30 45 37
6 V 13 26 38 32
tdis OE QA– QH50 pF
2 V 42 200 300 250
ns4.5 V 23 40 60 50
6 V 20 34 51 43
tt
QA– QH50 pF
2 V 28 60 90 75
ns
4.5 V 8 12 18 15
6 V 6 10 15 13
QH50 pF
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
tpd RCLK QA– QH150 pf
2 V 60 200 300 250
ns4.5 V 22 40 60 50
6 V 19 34 51 43
ten OE QA– QH150 pf
2 V 70 200 298 250
ns4.5 V 23 40 60 50
6 V 19 34 51 43
ttQA– QH150 pf
2 V 45 210 315 265
ns4.5 V 17 42 63 53
6 V 13 36 53 45
‘5‘ TEXAS INSTRUMENTS
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH’
implies that the output is in 3-State mode.NOTE:
8
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
Figure 1. Timing Diagram
5.8 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 400 pF
l TEXAS INSTRUMENTS
0 1 2 3 4 5 6
VCC(V)
ICC(nA)
0
5
10
15
20
25
30
35
40
-5
OUTPUTS = µ+,¶
OE = µ/2:¶
9
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
5.9 Typical Characteristics
Figure 2. SN74HC595B ICC vs. VCC
{L} TEXAS INSTRUMENTS W W F b m waxxw% a W L :L‘ L F 4: 1H4
10
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
6 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
11
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The SN74HC595B is part of the HC family of logic devices intended for CMOS applications. The SN74HC595B
device is an 8-bit shift register that feeds an 8-bit D-type storage register.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register is always one clock pulse ahead of the storage register. The QH'
may be used for daisy chaining the device and will not go into high impedance when OE is asserted.
iii: 2;; y
>
R
C1
1D
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>3S
C3
3R
>
3S
C3
3R
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
>
R
2R
2S
C2
QA
QB
QH
QE
QF
QD
Q+
QG
QC
15
1
2
3
4
5
6
7
9
14
11
10
12
13
SER
SRCLK
SRCLR
RCLK
OE
12
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
7.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
13
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The SN74HC595B device is an 8-bit Serial-In, Parallel-Out shift register. It has a wide operating voltage of 2 V to
6 V, and the high-current 3-state outputs can drive up to 15 LSTTL Loads. The device has a low power
consumption of 80-μA (Maximum) ICC. Additionally, this device has a low input current of 1 μA (Maximum) and a
±6-mA output drive at 5 V. The device is available currently in the smallest logic QFN package at 0.5 mm max
height with 0.4 mm pitch. The inputs are over voltage tolerant independent of Vcc.
7.4 Device Functional Modes
Table 3 lists the functional modes of the SN74HC595B devices.
Table 3. Function Table
INPUTS FUNCTION
SER SRCLK SRCLR RCLK OE
– – – H Outputs QA– QHare disabled. QH' is active .
– – – L Outputs QA– QHare enabled.
– L – – Shift register is cleared.
LH First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
HH First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
– – Shift-register data is stored in the storage register.
l TEXAS INSTRUMENTS
Controller
SRCLR
SRCLK
RCLK
5
OE
SER
QA
QB
QC
QD
QE
QF
QG
VCC 8
16
0.1 F
GND
15
1
2
3
4
5
6
7QH
10
11
12
13
14
9Q
560
560
560
560
560
560
560
560
+5V
14
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The SN74HC595B is a low-drive CMOS device that is used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. QH' pin of the first register should be connected to the serial (SER) pin of the second register for
daisy chaining.
8.2 Typical Application
Figure 5. Typical Application Schematic
8.2.1 Design Requirements
This device uses CMOS technology and has a balanced output drive. Take care to avoid bus contention because
it can drive currents in excess of the maximum limits. The high drive will also create fast edges into light loads,
so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
Recommended input conditions
Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
Inputs are over-voltage tolerant allowing them to go as high as 5.5 V at any valid VCC
l TEXAS INSTRUMENTS
0 2 468
VCC(V)
tpd(ns)
10
20
30
40
50
60
0
15
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
Typical Application (continued)
Recommended output conditions
Load currents should not exceed 35 mA per output as per the Absolute Maximum Ratings table.
Outputs should not be pulled below Ground or above VCC
8.2.3 Application Curves
Figure 6. SN75HC595B tpd vs. VCC
l TEXAS INSTRUMENTS
Vcc
Unused Input
Input
Output
Input
Unused Input Output
16
SN74HC595B
SCLS751 –MARCH 2016
www.ti.com
Product Folder Links: SN74HC595B
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. The total current through Ground or Vcc should not exceed 70 mA as
per Absolute Maximum Ratings table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input and the gate are used, or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs, unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when
asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
10.2 Layout Example
Figure 7. Layout Diagram
l TEXAS INSTRUMENTS
17
SN74HC595B
www.ti.com
SCLS751 –MARCH 2016
Product Folder Links: SN74HC595B
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs,SCBA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
I TEXAS INSTRUMENTS Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC595BRWNR ACTIVE X1QFN RWN 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 13YI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC595BRWNR X1QFN RWN 16 2000 178.0 13.5 2.8 2.8 0.75 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2016
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC595BRWNR X1QFN RWN 16 2000 189.0 185.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2016
Pack Materials-Page 2
RWN0016A g
www.ti.com
PACKAGE OUTLINE
C
16X 0.25
0.15
16X 0.45
0.35
0.5 MAX
(0.15) TYP
0.05
0.00
12X 0.4
2X
1.2
2X 1.2
1.2 0.05
A2.55
2.45 B
2.55
2.45
8X
( X 0.12)45
X1QFN - 0.5 mm max heightRWN0016A
PLASTIC QUAD FLATPACK - NO LEAD
4221911/A 05/2015
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.000
RWN0016A
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
16X (0.2)
16X (0.6)
( ) VIA0.2
12X (0.4)
(2.3)
(2.3)
(1.2)
(R )
TYP
0.05
(1.2)
X1QFN - 0.5 mm max heightRWN0016A
PLASTIC QUAD FLATPACK - NO LEAD
4221911/A 05/2015
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
RWN0016A
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.2)
12X (0.4)
(2.3)
(2.3)
( 1.13)
(R ) TYP0.05
X1QFN - 0.5 mm max heightRWN0016A
PLASTIC QUAD FLATPACK - NO LEAD
4221911/A 05/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
SYMM
1
4
58
9
12
13
16
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated