PIC24FJ1024GA610/GB610 Family Datasheet by Microchip Technology

6‘ MICRDCHIP
2015-2019 Microchip Technology Inc. DS30010074G-page 1
PIC24FJ1024GA610/GB610 FAMILY
High-Performance CPU
Modified Harvard Architecture
Largest Program Memory Available for PIC24
(1024 Kbytes) for the Most Complex Applications
32 Kbytes SRAM for All Part Variants
Up to 16 MIPS Operation @ 32 MHz
8 MHz Fast RC Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Run-time self-calibration capability for maintaining
better than ±0.20% accuracy
- Fast start-up
17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16-Bit x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
Universal Serial Bus Features
USB v2.0 On-The-Go (OTG) Compliant
Dual Role Capable – Can Act as Either Host or Peripheral
Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s)
USB Operation in Host mode
Full-Speed USB Operation in Device mode
High-Precision PLL for USB
USB Device mode Operation from FRC Oscillator –
No Crystal Oscillator Required
Supports up to 32 Endpoints (16 bidirectional):
- USB module can use any RAM location on the
device as USB endpoint buffers
On-Chip USB Transceiver with Interface for Off-Chip
USB Transceiver
Supports Control, Interrupt, Isochronous and
Bulk Transfers
On-Chip Pull-up and Pull-Down Resistors
Analog Features
10/12-Bit, up to 24-Channel Analog-to-Digital (A/D)
Converter:
- 12-bit conversion rate of 200 ksps
- Auto-scan and threshold compare features
- Conversion available during Sleep
Three Rail-to-Rail, Enhanced Analog Comparators
with Programmable Input/Output Configuration
Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 100 ps resolution
Low-Power Features
Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
Doze mode Allows CPU to Run at a Lower Clock
Speed than Peripherals
Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
Wide Range Digitally Controlled Oscillator (DCO) for
Fast Start-up and Low-Power Operation
Special Microcontroller Features
Large, Dual Partition Flash Program Array:
- Capable of holding two independent software
applications, including bootloader
- Permits simultaneous programming of one partition
while executing application code from the other
- Allows run-time switching between
Active Partitions
10,000 Erase/Write Cycle Endurance, Typical
Data Retention: 20 Years Minimum
Self-Programmable under Software Control
Supply Voltage Range of 2.0V to 3.6V
Operating Ambient Temperature from -40°C to
+85°C for Industrial and from -40°C to +125°C for
Extended Temperature Range Devices
On-Chip Voltage Regulators (1.8V) for Low-Power
Operation
Programmable Reference Clock Output
In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via Two Pins
JTAG Boundary Scan Support
Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC Oscillator
Power-on Reset (POR), Brown-out Reset (BOR),
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Programmable High/Low-Voltage Detect (HLVD)
Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation
16-Bit Microcontrollers with Large, Dual Partition
Flash Program Memory and USB On-The-Go (OTG)
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 2 2015-2019 Microchip Technology Inc.
Peripheral Features
Peripheral Pin Select (PPS) – Allows Independent
I/O Mapping of Many Peripherals
Up to Five External Interrupt Sources
Configurable Interrupt-on-Change on All I/O Pins:
- Each pin is independently configurable for rising
edge or falling edge change detection
Eight-Channel DMA Supports All Peripheral modules:
- Minimizes CPU overhead and increases data
throughput
Five 16-Bit Timers/Counters with Prescalers:
- Can be paired as 32-bit timers/counters
Six Input Capture modules, Each with a Dedicated
16-Bit Timer
Six Output Compare/PWM modules, Each with a
Dedicated 16-Bit Timer
Four Single Output CCPs (SCCPs) and Three
Multiple Output CCPs (MCCPs):
- Independent 16/32-bit time base for each module
- Internal time base and period registers
- Legacy PIC24F Capture and Compare modes
(16 and 32-bit)
- Special Variable Frequency Pulse and Brushless
DC Motor Output modes
Enhanced Parallel Master/Slave Port (EPMP/EPSP)
Hardware Real-Time Clock/Calendar (RTCC) with
Timestamping
Three 3-Wire/4-Wire SPI modules:
- Support four Frame modes
- Eight-level FIFO buffer
- Support I2S operation
•Three I
2C modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
Six UART modules:
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Auto-Baud Detect (ABD)
- Four-level deep FIFO buffer
Programmable 32-Bit Cyclic Redundancy Check
(CRC) Generator
Four Configurable Logic Cells (CLCs):
- Two inputs and one output, all mappable to
peripherals or I/O pins
- AND/OR/XOR logic and D/JK flip-flop functions
High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Configurable Open-Drain Outputs on Digital I/O Pins
5.5V Tolerant Inputs on Multiple I/O Pins
2015-2019 Microchip Technology Inc. DS30010074G-page 3
PIC24FJ1024GA610/GB610 FAMILY
PIC24FJ1024GA610/GB610 FAMILY
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1. Their pinout diagrams appear on the following
pages.
TABLE 1: PIC24FJ1024GA610/GB610 GENERAL PURPOSE FAMILIES
Device
Memory Pins Analog Digital
RTCC
USB OTG
Program
(bytes)
Data
(bytes)
Total
I/O
10/12-Bit A/D (ch)
Comparator
CTMU
16/32-Bit Timer
IC/OC/PWM
MCCP/SCCP
I2C
SPI
UART w/IrDA®
EPMP/EPSP
CLC
PIC24FJ128GA606 128K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ256GA606 256K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ512GA606 512K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ1024GA606 1024K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ128GA610 128K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ256GA610 256K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ512GA610 512K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ1024GA610 1024K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y N
PIC24FJ128GB606 128K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ256GB606 256K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ512GB606 512K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ1024GB606 1024K 32K 64 53 16 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ128GB610 128K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ256GB610 256K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ512GB610 512K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
PIC24FJ1024GB610 1024K 32K 100 85 24 3 Y 5/2 6/6 3/4 3 3 6/2 Y 4 Y Y
MCLR
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 4 2015-2019 Microchip Technology Inc.
Pin Diagrams(2)
Legend: See Table 2 for a complete description of pin functions.
Note 1: It is recommended to connect the metal pad on the bottom of the 64-pin QFN package to VSS.
2: Gray shading indicates 5.5V tolerant input pins.
64-Pin TQFP
64-Pin QFN(1)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
22
44
24
25
26
27
28
29
30
31
32
1
46
45
23
43
42
41
40
39
63
62
61
59
60
58
57
56
54
55
53
52
51
49
50
38
37
34
36
35
33
17
19
20
21
18
64
VDD
VSS
RG9
MCLR
RG8
RG7
RG6
RE7
RE6
RE5
RB5
RB4
RB3
RB2
RB1
RB0
OSCI/RC12
OSCO/RC15
VSS
RD8
RD9
RD10
RD11
RD0
RC13
RC14
VDD
RG2
RG3
RF6
RF2
RF3
VDD
VSS
RB11
RB10
RB9
RB8
AVSS
AVDD
RB7
RB6
RB12
RB13
RB14
RB15
RF4
RF5
RD7
VCAP
N/C
RF0
RF1
RE0
RE1
RE2
RE3
RE4
RD6
RD5
RD4
RD3
RD2
RD1
PIC24FJXXXXGA606
mews
2015-2019 Microchip Technology Inc. DS30010074G-page 5
PIC24FJ1024GA610/GB610 FAMILY
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGA606 TQFP/QFN)
Pin Function Pin Function
1 IC4/CTED4/PMD5/RE5 33 RP16/RF3
2 SCL3/IC5/PMD6/RE6 34 RP30/RF2
3 SDA3/IC6/PMD7/RE7 35 INT0/RF6
4 C1IND/RP21/ICM1/OCM1A/PMA5/RG6 36 SDA1/RG3
5 C1INC/RP26/OCM1B/PMA4/RG7 37 SCL1/RG2
6 C2IND/RP19/ICM2/OCM2A/PMA3/RG8 38 VDD
7MCLR 39 OSCI/CLKI/RC12
8 C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/RG9 40 OSCO/CLKO/RC15
9V
SS 41 VSS
10 VDD 42 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
11 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5 43 RP4/PMACK2/RD9
12 PGED3/AN4/C1INB/RP28/OCM3B/RB4 44 RP3/PMA15/PMCS2/RD10
13 AN3/C2INA/RB3 45 RP12/PMA14/PMCS1/RD11
14 AN2/CTCMP/C2INB/RP13/CTED13/RB2 46 CLC3OUT/RP11/U6CTS/ICM6/RD0
15 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 47 SOSCI/C3IND/RC13
16 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/PMA6/RB0 48 SOSCO/C3INC/RPI37/PWRLCLK/RC14
17 PGEC2/AN6/RP6/RB6 49 RP24/U5TX/ICM4/RD1
18 PGED2/AN7/RP7/U6TX/RB7 50 RP23/PMACK1/RD2
19 AVDD 51 RP22/ICM7/PMBE0/RD3
20 AVSS 52 RP25/PMWR/PMENB/RD4
21 AN8/RP8/PWRGT/RB8 53 RP20/PMRD/PMWR/RD5
22 AN9/TMPR/RP9/T1CK/PMA7/RB9 54 C3INB/U5RX/OC4/RD6
23 TMS/CVREF/AN10/PMA13/RB10 55 C3INA/U5RTS/U5BCLK/OC5/RD7
24 TDO/AN11/REFI/PMA12/RB11 56 VCAP
25 VSS 57 N/C
26 VDD 58 U5CTS/OC6/RF0
27 TCK/AN12/U6RX/CTED2/PMA11/RB12 59 RF1
28 TDI/AN13/CTED1/PMA10/RB13 60 PMD0/RE0
29 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14 61 PMD1/RE1
30 AN15/RP29/CTED6/PMA0/PMALL/RB15 62 PMD2/RE2
31 RP10/SDA2/PMA9/RF4 63 CTED9/PMD3/RE3
32 RP17/SCL2/PMA8/RF5 64 HLVDIN/CTED8/PMD4/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
MCLR
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 6 2015-2019 Microchip Technology Inc.
Pin Diagrams(2) (Continued)
Legend: See Table 3 for a complete description of pin functions.
Note 1: It is recommended to connect the metal pad on the bottom of the 64-pin QFN package to VSS.
2: Gray shading indicates 5.5V tolerant input pins.
64-Pin TQFP
64-Pin QFN(1)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
22
44
24
25
26
27
28
29
30
31
32
1
46
45
23
43
42
41
40
39
63
62
61
59
60
58
57
56
54
55
53
52
51
49
50
38
37
34
36
35
33
17
19
20
21
18
64
VDD
VSS
RG9
MCLR
RG8
RG7
RG6
RE7
RE6
RE5
RB5
RB4
RB3
RB2
RB1
RB0
OSCI/RC12
OSCO/RC15
VSS
RD8
RD9
RD10
RD11
RD0
RC13
RC14
VDD
D+/RG2
D-/RG3
VUSB3V3
VBUS/RF7
RF3
VDD
VSS
RB11
RB10
RB9
RB8
AVSS
AVDD
RB7
RB6
RB12
RB13
RB14
RB15
RF4
RF5
RD7
VCAP
N/C
RF0
RF1
RE0
RE1
RE2
RE3
RE4
RD6
RD5
RD4
RD3
RD2
RD1
PIC24FJXXXXGB606
15
mews B/USBOEN
2015-2019 Microchip Technology Inc. DS30010074G-page 7
PIC24FJ1024GA610/GB610 FAMILY
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGB606 TQFP/QFN)
Pin Function Pin Function
1 IC4/CTED4/PMD5/RE5 33 RP16/USBID/RF3
2 SCL3/IC5/PMD6/RE6 34 VBUS/RF7
3 SDA3/IC6/PMD7/RE7 35 VUSB3V3
4 C1IND/RP21/ICM1/OCM1A/PMA5/RG6 36 D-/RG3
5 C1INC/RP26/OCM1B/PMA4/RG7 37 D+/RG2
6 C2IND/RP19/ICM2/OCM2A/PMA3/RG8 38 VDD
7MCLR 39 OSCI/CLKI/RC12
8 C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/RG9 40 OSCO/CLKO/RC15
9V
SS 41 VSS
10 VDD 42 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
11 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5 43 RP4/SDA1/PMACK2/RD9
12 PGED3/AN4/C1INB/RP28/USBOEN/OCM3B/RB4 44 RP3/SCL1/PMA15/PMCS2/RD10
13 AN3/C2INA/RB3 45 RP12/PMA14/PMCS1/RD11
14 AN2/CTCMP/C2INB/RP13/CTED13/RB2 46 CLC3OUT/RP11/U6CTS/ICM6/INT0/RD0
15 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 47 SOSCI/C3IND/RC13
16 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/PMA6/RB0 48 SOSCO/C3INC/RPI37/PWRLCLK/RC14
17 PGEC2/AN6/RP6/RB6 49 RP24/U5TX/ICM4/RD1
18 PGED2/AN7/RP7/U6TX/RB7 50 RP23/PMACK1/RD2
19 AVDD 51 RP22/ICM7/PMBE0/RD3
20 AVSS 52 RP25/PMWR/PMENB/RD4
21 AN8/RP8/PWRGT/RB8 53 RP20/PMRD/PMWR/RD5
22 AN9/TMPR/RP9/T1CK/PMA7/RB9 54 C3INB/U5RX/OC4/RD6
23 TMS/CVREF/AN10/PMA13/RB10 55 C3INA/U5RTS/U5BCLK/OC5/RD7
24 TDO/AN11/REFI/PMA12/RB11 56 VCAP
25 VSS 57 N/C
26 VDD 58 U5CTS/OC6/RF0
27 TCK/AN12/U6RX/CTED2/PMA11/RB12 59 RF1
28 TDI/AN13/CTED1/PMA10/RB13 60 PMD0/RE0
29 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14 61 PMD1/RE1
30 AN15/RP29/CTED6/PMA0/PMALL/RB15 62 PMD2/RE2
31 RP10/SDA2/PMA9/RF4 63 CTED9/PMD3/RE3
32 RP17/SCL2/PMA8/RF5 64 HLVDIN/CTED8/PMD4/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 8 2015-2019 Microchip Technology Inc.
Pin Diagrams(1) (Continued)
Legend: See Ta b le 4 for a complete description of pin functions.
Note 1: Gray shading indicates 5.5V tolerant input pins.
100-Pin TQFP
92
94
93
91
90
89
88
87
86
85
84
83
82
81
80
79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
28
29
30
31
32
33
34
35
36
37
38
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
96
98
97
99
27
46
47
48
49
50
55
54
53
52
51
100
RD5
RD4
RD13
RD12
RD3
RD2
RD1
RA7
RA6
RE2
RG13
RG12
RG14
RE1
RE0
RG0
RE4
RE3
RF0
VCAP
RC13
RD0
RD10
RD9
RD8
RD11
RA15
RA14
OSCO/RC15
OSCI/RC12
VDD
RG2
RF6
RF7
RF8
RG3
RF2
RF3
VSS
RC14
RA10
RA9
AVDD
AVSS
RB8
RB9
RB10
RB11
VDD
RF12
RF13
VSS
VDD
RD15
RD14
RB6
RB7
RF5
RF4
RE5
RE6
RE7
RC1
RC2
RC3
RC4
RG6
VDD
RA0
RE8
RE9
RB5
RB4
RB3
RB2
RG7
RG8
RB1
RB0
RG15
VDD
RG9
MCLR
RB12
RB13
RB14
RB15
RG1
RF1
RD7
RD6
RA5
RA3
RA2
VSS
VSS
VSS
N/C
RA4
RA1
PIC24FJXXXXGA610
mews
2015-2019 Microchip Technology Inc. DS30010074G-page 9
PIC24FJ1024GA610/GB610 FAMILY
TABLE 4: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGA610 TQFP)
Pin Function Pin Function
1 OCM1C/CTED3/RG15 51 RP16/RF3
2V
DD 52 RP30/RF2
3 IC4/CTED4/PMD5/RE5 53 RP15/RF8
4 SCL3/IC5/PMD6/RE6 54 RF7
5 SDA3/IC6/PMD7/RE7 55 INT0/RF6
6RPI38/OCM1D/RC1 56 SDA1/RG3
7RPI39/OCM2C/RC2 57 SCL1/RG2
8RPI40/OCM2D/RC3 58 PMPCS1/SCL2/RA2
9 AN16/RPI41/OCM3C/PMCS2/RC4 59 SDA2/PMA20/RA3
10 AN17/C1IND/RP21/ICM1/OCM1A/PMA5/RG6 60 TDI/PMA21/RA4
11 AN18/C1INC/RP26/OCM1B/PMA4/RG7 61 TDO/RA5
12 AN19/C2IND/RP19/ICM2/OCM2A/PMA3/RG8 62 VDD
13 MCLR 63 OSCI/CLKI/RC12
14 AN20/C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/RG9 64 OSCO/CLKO/RC15
15 VSS 65 VSS
16 VDD 66 RPI36/PMA22/RA14
17 TMS/OCM3D/RA0 67 RPI35/PMBE1/RA15
18 RPI33/PMCS1/RE8 68 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
19 AN21/RPI34/PMA19/RE9 69 RP4/PMACK2/RD9
20 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5 70 RP3/PMA15/PMCS2/RD10
21 PGED3/AN4/C1INB/RP28/OCM3B/RB4 71 RP12/PMA14/PMCS1/RD11
22 AN3/C2INA/RB3 72 CLC3OUT/RP11/U6CTS/ICM6/RD0
23 AN2/CTCMP/C2INB/RP13/CTED13/RB2 73 SOSCI/C3IND/RC13
24 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 74 SOSCO/C3INC/RPI37/PWRLCLK/RC14
25 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/RB0 75 VSS
26 PGEC2/AN6/RP6/RB6 76 RP24/U5TX/ICM4/RD1
27 PGED2/AN7/RP7/U6TX/RB7 77 RP23/PMACK1/RD2
28 CVREF-/VREF-/PMA7/RA9 78 RP22/ICM7/PMBE0/RD3
29 CVREF+/VREF+/PMA6/RA10 79 RPI42/OCM3E/PMD12/RD12
30 AVDD 80 OCM3F/PMD13/RD13
31 AVSS 81 RP25/PMWR/PMENB/RD4
32 AN8/RP8/PWRGT/RB8 82 RP20/PMRD/PMWR/RD5
33 AN9/TMPR/RP9/T1CK/RB9 83 C3INB/U5RX/OC4/PMD14/RD6
34 CVREF/AN10/PMA13/RB10 84 C3INA/U5RTS/U5BCLK/OC5/PMD15/RD7
35 AN11/REFI/PMA12/RB11 85 VCAP
36 VSS 86 N/C
37 VDD 87 U5CTS/OC6/PMD11/RF0
38 TCK/RA1 88 PMD10/RF1
39 RP31/RF13 89 PMD9/RG1
40 RPI32/CTED7/PMA18/RF12 90 PMD8/RG0
41 AN12/U6RX/CTED2/PMA11/RB12 91 AN23/OCM1E/RA6
42 AN13/CTED1/PMA10/RB13 92 AN22/OCM1F/PMA17/RA7
43 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14 93 PMD0/RE0
44 AN15/RP29/CTED6/PMA0/PMALL/RB15 94 PMD1/RE1
45 VSS 95 CTED11/PMA16/RG14
46 VDD 96 OCM2E/RG12
47 RPI43/RD14 97 OCM2F/CTED10/RG13
48 RP5/RD15 98 PMD2/RE2
49 RP10/PMA9/RF4 99 CTED9/PMD3/RE3
50 RP17/PMA8/RF5 100 HLVDIN/CTED8/PMD4/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 10 2015-2019 Microchip Technology Inc.
Pin Diagrams(1) (Continued)
Legend: See Ta b le 5 for a complete description of pin functions.
Note 1: Gray shading indicates 5.5V tolerant input pins.
100-Pin TQFP
92
94
93
91
90
89
88
87
86
85
84
83
82
81
80
79
78
20
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
65
64
63
62
61
60
59
26
56
45
44
43
42
41
40
39
28
29
30
31
32
33
34
35
36
37
38
17
18
19
21
22
95
1
76
77
72
71
70
69
68
67
66
75
74
73
58
57
24
23
25
96
98
97
99
27
46
47
48
49
50
55
54
53
52
51
100
RD5
RD4
RD13
RD12
RD3
RD2
RD1
RA7
RA6
RE2
RG13
RG12
RG14
RE1
RE0
RG0
RE4
RE3
RF0
V
CAP
RC13
RD0
RD10
RD9
RD8
RD11
RA15
RA14
OSCO/RC15
OSCI/RC12
V
DD
D+/RG2
V
USB3V3
V
BUS
/RF7
RF8
D-/RG3
RF2
RF3
V
SS
RC14
RA10
RA9
AV
DD
AV
SS
RB8
RB9
RB10
RB11
V
DD
RF12
RF13
V
SS
V
DD
RD15
RD14
RB6
RB7
RF5
RF4
RE5
RE6
RE7
RC1
RC2
RC3
RC4
RG6
V
DD
RA0
RE8
RE9
RB5
RB4
RB3
RB2
RG7
RG8
RB1
RB0
RG15
V
DD
RG9
MCLR
RB12
RB13
RB14
RB15
RG1
RF1
RD7
RD6
RA5
RA3
RA2
V
SS
V
SS
V
SS
N/C
RA4
RA1
PIC24FJXXXXGB610
B/USBOEN
2015-2019 Microchip Technology Inc. DS30010074G-page 11
PIC24FJ1024GA610/GB610 FAMILY
TABLE 5: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGB610 TQFP)
Pin Function Pin Function
1 OCM1C/CTED3/RG15 51 RP16/USBID/RF3
2V
DD 52 RP30/RF2
3 IC4/CTED4/PMD5/RE5 53 RP15/RF8
4 SCL3/IC5/PMD6/RE6 54 VBUS/RF7
5 SDA3/IC6/PMD7/RE7 55 VUSB3V3
6RPI38/OCM1D/RC1 56 D-/RG3
7RPI39/OCM2C/RC2 57 D+/RG2
8RPI40/OCM2D/RC3 58 PMPCS1/SCL2/RA2
9 AN16/RPI41/OCM3C/PMCS2/RC4 59 SDA2/PMA20/RA3
10 AN17/C1IND/RP21/ICM1/OCM1A/PMA5/RG6 60 TDI/PMA21/RA4
11 AN18/C1INC/RP26/OCM1B/PMA4/RG7 61 TDO/RA5
12 AN19/C2IND/RP19/ICM2/OCM2A/PMA3/RG8 62 VDD
13 MCLR 63 OSCI/CLKI/RC12
14 AN20/C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/RG9 64 OSCO/CLKO/RC15
15 VSS 65 VSS
16 VDD 66 RPI36/SCL1/PMA22/RA14
17 TMS/OCM3D/RA0 67 RPI35/SDA1/PMBE1/RA15
18 RPI33/PMCS1/RE8 68 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
19 AN21/RPI34/PMA19/RE9 69 RP4/PMACK2/RD9
20 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5 70 RP3/PMA15/PMCS2/RD10
21 PGED3/AN4/C1INB/RP28/USBOEN/OCM3B/RB4 71 RP12/PMA14/PMCS1/RD11
22 AN3/C2INA/RB3 72 CLC3OUT/RP11/U6CTS/ICM6/INT0/RD0
23 AN2/CTCMP/C2INB/RP13/CTED13/RB2 73 SOSCI/C3IND/RC13
24 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 74 SOSCO/C3INC/RPI37/PWRLCLK/RC14
25 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/RB0 75 VSS
26 PGEC2/AN6/RP6/RB6 76 RP24/U5TX/ICM4/RD1
27 PGED2/AN7/RP7/U6TX/RB7 77 RP23/PMACK1/RD2
28 CVREF-/VREF-/PMA7/RA9 78 RP22/ICM7/PMBE0/RD3
29 CVREF+/VREF+/PMA6/RA10 79 RPI42/OCM3E/PMD12/RD12
30 AVDD 80 OCM3F/PMD13/RD13
31 AVSS 81 RP25/PMWR/PMENB/RD4
32 AN8/RP8/PWRGT/RB8 82 RP20/PMRD/PMWR/RD5
33 AN9/TMPR/RP9/T1CK/RB9 83 C3INB/U5RX/OC4/PMD14/RD6
34 CVREF/AN10/PMA13/RB10 84 C3INA/U5RTS/U5BCLK/OC5/PMD15/RD7
35 AN11/REFI/PMA12/RB11 85 VCAP
36 VSS 86 N/C
37 VDD 87 U5CTS/OC6/PMD11/RF0
38 TCK/RA1 88 PMD10/RF1
39 RP31/RF13 89 PMD9/RG1
40 RPI32/CTED7/PMA18/RF12 90 PMD8/RG0
41 AN12/U6RX/CTED2/PMA11/RB12 91 AN23/OCM1E/RA6
42 AN13/CTED1/PMA10/RB13 92 AN22/OCM1F/PMA17/RA7
43 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14 93 PMD0/RE0
44 AN15/RP29/CTED6/PMA0/PMALL/RB15 94 PMD1/RE1
45 VSS 95 CTED11/PMA16/RG14
46 VDD 96 OCM2E/RG12
47 RPI43/RD14 97 OCM2F/CTED10/RG13
48 RP5/RD15 98 PMD2/RE2
49 RP10/PMA9/RF4 99 CTED9/PMD3/RE3
50 RP17/PMA8/RF5 100 HLVDIN/CTED8/PMD4/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
0.0.0.00... OOOOOOOOOOO 0000000000. 0000000000. 0.0.0.0.... 0000000000 00000000... 0000000000. 0000000000. 00000.00... 00000.00...
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 12 2015-2019 Microchip Technology Inc.
Pin Diagrams(1) (Continued)
Legend: See Ta b le 6 for a complete description of pin functions.
Note 1: Gray shading indicates 5.5V tolerant input pins.
PIC24FJXXXGA610 121-Pin BGA
RE4 RE3 RG13 RE0 RG0 RF1 RD12 RD2 RD1
RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14
RE6 VDD RG12 RG14 RA6 RD7 RD4 RC13 RD11
RC1 RE7 RE5 RD6 RD13 RD0 RD10
RC4 RC3 RG6 RC2 RG1 RA15 RD8 RD9 RA14
MCLR RG8 RG9 RG7 VSS VDD RC12 VSS RC15
RE8 RE9 RA0 VDD VSS VSS RA5 RA3 RA4
RB5 RB4 VDD RF7 RF6 RG2 RA2
RB3 RB2 RB7 AVDD RB11 RA1 RB12 RF8 RG3
RB1 RB0 RA10 RB8 RF12 RB14 VDD RD15 RF3 RF2
RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5
1234567891011
A
B
C
D
E
F
G
H
J
K
L
N/C N/C
N/C
N/C
N/CN/CN/C
N/C N/C
N/C
N/C
N/C N/C
N/C N/C
N/C N/C N/C
N/C N/C
N/C
N/C
mews
2015-2019 Microchip Technology Inc. DS30010074G-page 13
PIC24FJ1024GA610/GB610 FAMILY
TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGA610 BGA)
Pin Full Pin Name Pin Full Pin Name
A1 HLVDIN/CTED8/PMD4/RE4 E1 AN16/RPI41/OCM3C/PMCS2/RC4
A2 CTED9/PMD3/RE3 E2 RPI40/OCM2D/RC3
A3 OCM2F/CTED10/RG13 E3 AN17/C1IND/RP21/ICM1/OCM1A/PMA5/RG6
A4 PMD0/RE0 E4 RPI39/OCM2C/RC2
A5 PMD8/RG0 E5 N/C
A6 PMD10/RF1 E6 PMD9/RG1
A7 N/C E7 N/C
A8 N/C E8 RPI35/PMBE1/RA15
A9 RPI42/OCM3E/PMD12/RD12 E9 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
A10 RP23/PMACK1/RD2 E10 RP4/PMACK2/RD9
A11 RP24/U5TX/ICM4/RD1 E11 RPI36/PMA22/RA14
B1 N/C F1 MCLR
B2 OCM1C/CTED3/RG15 F2 AN19/C2IND/RP19/ICM2/OCM2A/PMA3/RG8
B3 PMD2/RE2 F3 AN20/C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/
RG9
B4 PMD1/RE1 F4 AN18/C1INC/RP26/OCM1B/PMA4/RG7
B5 AN22/OCM1F/PMA17/RA7 F5 VSS
B6 U5CTS/OC6/PMD11/RF0 F6 N/C
B7 VCAP F7 N/C
B8 RP20/PMRD/PMWR/RD5 F8 VDD
B9 RP22/ICM7/PMBE0/RD3 F9 OSCI/CLKI/RC12
B10 VSS F10 VSS
B11 SOSCO/C3INC/RPI37/PWRLCLK/RC14 F11 OSCO/CLKO/RC15
C1 SCL3/IC5/PMD6/RE6 G1 RPI33/PMCS1/RE8
C2 VDD G2 AN21/RPI34/PMA19/RE9
C3 OCM2E/RG12 G3 TMS/OCM3D/RA0
C4 CTED11/PMA16/RG14 G4 N/C
C5 AN23/OCM1E/RA6 G5 VDD
C6 N/C G6 VSS
C7 C3INA/U5RTS/U5BCLK/OC5/PMD15/RD7 G7 VSS
C8 RP25/PMWR/PMENB/RD4 G8 N/C
C9 N/C G9 TDO/RA5
C10 SOSCI/C3IND/RC13 G10 SDA2/PMA20/RA3
C11 RP12/PMA14/PMCS1/RD11 G11 TDI/PMA21/RA4
D1 RPI38/OCM1D/RC1 H1 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5
D2 SDA3/IC6/PMD7/RE7 H2 PGED3/AN4/C1INB/RP28/OCM3B/RB4
D3 IC4/CTED4/PMD5/RE5 H3 N/C
D4 N/C H4 N/C
D5 N/C H5 N/C
D6 N/C H6 VDD
D7 C3INB/U5RX/OC4/PMD14/RD6 H7 N/C
D8 OCM3F/PMD13/RD13 H8 RF7
D9 CLC3OUT/RP11/U6CTS/ICM6/RD0 H9 INT0/RF6
D10 N/C H10 SCL1/RG2
D11 RP3/PMA15/PMCS2/RD10 H11 PMPCS1/SCL2/RA2
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 14 2015-2019 Microchip Technology Inc.
J1 AN3/C2INA/RB3 K7 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14
J2 AN2/CTCMP/C2INB/RP13/CTED13/RB2 K8 VDD
J3 PGED2/AN7/RP7/U6TX/RB7 K9 RP5/RD15
J4 AVDD K10 RP16/RF3
J5 AN11/REFI/PMA12/RB11 K11 RP30/RF2
J6 TCK/RA1 L1 PGEC2/AN6/RP6/RB6
J7 AN12/U6RX/CTED2/PMA11/RB12 L2 CVREF-/VREF-/PMA7/RA9
J8 N/C L3 AVSS
J9 N/C L4 AN9/TMPR/RP9/T1CK/RB9
J10 RP15/RF8 L5 CVREF/AN10/PMA13/RB10
J11 SDA1/RG3 L6 RP31/RF13
K1 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 L7 AN13/CTED1/PMA10/RB13
K2 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/RB0 L8 AN15/RP29/CTED6/PMA0/PMALL/RB15
K3 CVREF+/VREF+/PMA6/RA10 L9 RPI43/RD14
K4 AN8/RP8/PWRGT/RB8 L10 RP10/PMA9/RF4
K5 N/C L11 RP17/PMA8/RF5
K6 RPI32/CTED7/PMA18/RF12
TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGA610 BGA) (CONTINUED)
Pin Full Pin Name Pin Full Pin Name
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
0.0.0.00... OOOOOOOOOOO 0000000000. 0000000000. 0.0.0.0.... 0000000000 0000000000. 0000000000. 00000000000 00000.00... 00000.00...
2015-2019 Microchip Technology Inc. DS30010074G-page 15
PIC24FJ1024GA610/GB610 FAMILY
Pin Diagrams(1) (Continued)
Legend: See Ta b le 7 for a complete description of pin functions.
Note 1: Gray shading indicates 5.5V tolerant input pins.
PIC24FJXXXGB610 121-Pin BGA
RE4 RE3 RG13 RE0 RG0 RF1 RD12 RD2 RD1
RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14
RE6 VDD RG12 RG14 RA6 RD7 RD4 RC13 RD11
RC1 RE7 RE5 RD6 RD13 RD0 RD10
RC4 RC3 RG6 RC2 RG1 RA15 RD8 RD9 RA14
MCLR RG8 RG9 RG7 VSS VDD RC12 VSS RC15
RE8 RE9 RA0 VDD VSS VSS RA5 RA3 RA4
RB5 RB4 VDD VBUS/RF7 VUSB3V3 D+/RG2 RA2
RB3 RB2 RB7 AVDD RB11 RA1 RB12 RF8 D-/RG3
RB1 RB0 RA10 RB8 RF12 RB14 VDD RD15 RF3 RF2
RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5
1234567891011
A
B
C
D
E
F
G
H
J
K
L
N/C N/C
N/C
N/C
N/CN/CN/C
N/C N/C
N/C
N/C
N/C N/C
N/C N/C
N/C N/C N/C
N/C N/C
N/C
N/C
/UGCTS
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 16 2015-2019 Microchip Technology Inc.
TABLE 7: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGB610 BGA)
Pin Full Pin Name Pin Full Pin Name
A1 HLVDIN/CTED8/PMD4/RE4 E1 AN16/RPI41/OCM3C/PMCS2/RC4
A2 CTED9/PMD3/RE3 E2 RPI40/OCM2D/RC3
A3 OCM2F/CTED10/RG13 E3 AN17/C1IND/RP21/ICM1/OCM1A/PMA5/RG6
A4 PMD0/RE0 E4 RPI39/OCM2C/RC2
A5 PMD8/RG0 E5 N/C
A6 PMD10/RF1 E6 PMD9/RG1
A7 N/C E7 N/C
A8 N/C E8 RPI35/SDA1/PMBE1/RA15
A9 RPI42/OCM3E/PMD12/RD12 E9 CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8
A10 RP23/PMACK1/RD2 E10 RP4/PMACK2/RD9
A11 RP24/U5TX/ICM4/RD1 E11 RPI36/SCL1/PMA22/RA14
B1 N/C F1 MCLR
B2 OCM1C/CTED3/RG15 F2 AN19/C2IND/RP19/ICM2/OCM2A/PMA3/RG8
B3 PMD2/RE2 F3 AN20/C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/
RG9
B4 PMD1/RE1 F4 AN18/C1INC/RP26/OCM1B/PMA4/RG7
B5 AN22/OCM1F/PMA17/RA7 F5 VSS
B6 U5CTS/OC6/PMD11/RF0 F6 N/C
B7 VCAP F7 N/C
B8 RP20/PMRD/PMWR/RD5 F8 VDD
B9 RP22/ICM7/PMBE0/RD3 F9 OSCI/CLKI/RC12
B10 VSS F10 VSS
B11 SOSCO/C3INC/RPI37/PWRLCLK/RC14 F11 OSCO/CLKO/RC15
C1 SCL3/IC5/PMD6/RE6 G1 RPI33/PMCS1/RE8
C2 VDD G2 AN21/RPI34/PMA19/RE9
C3 OCM2E/RG12 G3 TMS/OCM3D/RA0
C4 CTED11/PMA16/RG14 G4 N/C
C5 AN23/OCM1E/RA6 G5 VDD
C6 N/C G6 VSS
C7 C3INA/U5RTS/U5BCLK/OC5/PMD15/RD7 G7 VSS
C8 RP25/PMWR/PMENB/RD4 G8 N/C
C9 N/C G9 TDO/RA5
C10 SOSCI/C3IND/RC13 G10 SDA2/PMA20/RA3
C11 RP12/PMA14/PMCS1/RD11 G11 TDI/PMA21/RA4
D1 RPI38/OCM1D/RC1 H1 PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5
D2 SDA3/IC6/PMD7/RE7 H2 PGED3/AN4/C1INB/RP28/USBOEN/OCM3B/RB4
D3 IC4/CTED4/PMD5/RE5 H3 N/C
D4 N/C H4 N/C
D5 N/C H5 N/C
D6 N/C H6 VDD
D7 C3INB/U5RX/OC4/PMD14/RD6 H7 N/C
D8 OCM3F/PMD13/RD13 H8 VBUS/RF7
D9 CLC3OUT/RP11/U6CTS/ICM6/INT0/RD0 H9 VUSB3V3
D10 N/C H10 D+/RG2
D11 RP3/PMA15/PMCS2/RD10 H11 PMPCS1/SCL2/RA2
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
2015-2019 Microchip Technology Inc. DS30010074G-page 17
PIC24FJ1024GA610/GB610 FAMILY
J1 AN3/C2INA/RB3 K7 AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14
J2 AN2/CTCMP/C2INB/RP13/CTED13/RB2 K8 VDD
J3 PGED2/AN7/RP7/U6TX/RB7 K9 RP5/RD15
J4 AVDD K10 RP16/USBID/RF3
J5 AN11/REFI/PMA12/RB11 K11 RP30/RF2
J6 TCK/RA1 L1 PGEC2/AN6/RP6/RB6
J7 AN12/U6RX/CTED2/PMA11/RB12 L2 CVREF-/VREF-/PMA7/RA9
J8 N/C L3 AVSS
J9 N/C L4 AN9/TMPR/RP9/T1CK/RB9
J10 RP15/RF8 L5 CVREF/AN10/PMA13/RB10
J11 D-/RG3 L6 RP31/RF13
K1 PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 L7 AN13/CTED1/PMA10/RB13
K2 PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/RB0 L8 AN15/RP29/CTED6/PMA0/PMALL/RB15
K3 CVREF+/VREF+/PMA6/RA10 L9 RPI43/RD14
K4 AN8/RP8/PWRGT/RB8 L10 RP10/PMA9/RF4
K5 N/C L11 RP17/PMA8/RF5
K6 RPI32/CTED7/PMA18/RF12
TABLE 7: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJXXXGB610 BGA) (CONTINUED)
Pin Full Pin Name Pin Full Pin Name
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 18 2015-2019 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 21
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 41
3.0 CPU ........................................................................................................................................................................................... 47
4.0 Memory Organization ................................................................................................................................................................. 53
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 81
6.0 Flash Program Memory.............................................................................................................................................................. 89
7.0 Resets ........................................................................................................................................................................................ 97
8.0 Interrupt Controller ................................................................................................................................................................... 105
9.0 Oscillator Configuration ............................................................................................................................................................ 117
10.0 Power-Saving Features............................................................................................................................................................ 137
11.0 I/O Ports ................................................................................................................................................................................... 149
12.0 Timer1 ...................................................................................................................................................................................... 185
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 187
14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 193
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 199
16.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................. 209
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 227
18.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 247
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 255
20.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 265
21.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 299
22.0 Real-Time Clock and Calendar with Timestamp ...................................................................................................................... 311
23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 331
24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 337
25.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 347
26.0 Triple Comparator Module........................................................................................................................................................ 363
27.0 Comparator Voltage Reference................................................................................................................................................ 369
28.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 371
29.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 381
30.0 Special Features ..................................................................................................................................................................... 383
31.0 Development Support............................................................................................................................................................... 401
32.0 Instruction Set Summary .......................................................................................................................................................... 403
33.0 Electrical Characteristics .......................................................................................................................................................... 411
34.0 Packaging Information.............................................................................................................................................................. 443
Appendix A: Revision History............................................................................................................................................................. 457
Index ................................................................................................................................................................................................. 459
The Microchip Website....................................................................................................................................................................... 465
Customer Change Notification Service .............................................................................................................................................. 465
Customer Support .............................................................................................................................................................................. 465
Product Identification System............................................................................................................................................................. 467
2015-2019 Microchip Technology Inc. DS30010074G-page 19
PIC24FJ1024GA610/GB610 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 20 2015-2019 Microchip Technology Inc.
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
CPU with Extended Data Space (EDS)” (www.microchip.com/DS39732)
“Data Memory with Extended Data Space (EDS)” (www.microchip.com/DS39733)
“Direct Memory Access Controller (DMA)” (www.microchip.com/DS30009742)
“PIC24F Flash Program Memory” (www.microchip.com/DS30009715)
“Reset” (www.microchip.com/DS39712)
“Interrupts” (www.microchip.com/DS70000600)
“Oscillator” (www.microchip.com/DS39700)
“Power-Saving Features” (www.microchip.com/DS39698)
“I/O Ports with Interrupt-on-Change (IOC)” (www.microchip.com/DS70005186)
“Timers” (www.microchip.com/DS39704)
”Input Capture with Dedicated Timer” (www.microchip.com/DS70000352)
“Output Compare with Dedicated Timer” (www.microchip.com/DS70005159)
“Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/DS30003035A)
“Serial Peripheral Interface (SPI) with Audio Codec Support” (www.microchip.com/DS70005136)
“Inter-Integrated Circuit (I2C) (www.microchip.com/DS70000195)
“UART” (www.microchip.com/DS39708)
“USB On-The-Go (OTG)” (www.microchip.com/DS39721)
“Enhanced Parallel Master Port (EPMP)” (www.microchip.com/DS39730)
“RTCC with Timestamp” (www.microchip.com/DS70005193)
“RTCC with External Power Control” (www.microchip.com/DS39745)
“32-Bit Programmable Cyclic Redundancy Check (CRC)” (www.microchip.com/DS30009729)
“12-Bit A/D Converter with Threshold Detect” (www.microchip.com/DS39739)
“Scalable Comparator Module” (www.microchip.com/DS39734)
“Dual Comparator Module” (www.microchip.com/DS39710)
“Charge Time Measurement Unit (CTMU) and CTMU Operation with Threshold Detect”
(www.microchip.com/DS30009743)
“High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725)
“Watchdog Timer (WDT)” (www.microchip.com/DS39697)
“CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182)
“High-Level Device Integration” (www.microchip.com/DS39719)
“Programming and Diagnostics” (www.microchip.com/DS39716)
“Dual Partition Flash Program Memory” (www.microchip.com/DS70005156)
“Configurable Logic Cell (CLC)” (www.microchip.com/DS70005298)
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC24FJ1024GA610/GB610 product
page of the Microchip website
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
2015-2019 Microchip Technology Inc. DS30010074G-page 21
PIC24FJ1024GA610/GB610 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The PIC24FJ1024GA610/GB610 family introduces many
new analog features to the extreme low-power
Microchip devices. This is a 16-bit microcontroller family
with a broad peripheral feature set and enhanced
computational performance. This family also offers a
new migration option for those high-performance appli-
cations which may be outgrowing their 8-bit platforms,
but do not require the numerical processing power of a
Digital Signal Processor (DSP).
Table 1-3 lists the functions of the various pins shown
in the pinout diagrams.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such
as:
16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
A 16-element Working register array with built-in
software stack support
A 17 x 17 hardware multiplier with support for
integer math
Hardware support for 32 by 16-bit division
An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
The PIC24FJ1024GA610/GB610 family of devices
includes Retention Sleep, a low-power mode with
essential circuits being powered from a separate
low-voltage regulator.
This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.
Aside from this new feature, PIC24FJ1024GA610/GB610
family devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and the Sleep modes
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ1024GA610/GB610
family offer six different oscillator options, allowing
users a range of choices in developing application
hardware. These include:
Two Crystal modes
Two External Clock (EC) modes
A Phase-Locked Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
A Digitally Controlled Oscillator (DCO) with
multiple frequencies and fast wake-up time
A Fast Internal Oscillator (FRC), a nominal 8 MHz
output, with multiple frequency divider options
A separate Low-Power Internal RC Oscillator
(LPRC), 31 kHz nominal, for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
• PIC24FJ1024GB610 • PIC24FJ1024GA610
• PIC24FJ512GB610 • PIC24FJ512GA610
• PIC24FJ256GB610 • PIC24FJ256GA610
• PIC24FJ128GB610 • PIC24FJ128GA610
• PIC24FJ1024GB606 • PIC24FJ1024GA606
• PIC24FJ512GB606 • PIC24FJ512GA606
• PIC24FJ256GB606 • PIC24FJ256GA606
• PIC24FJ128GB606 • PIC24FJ128GA606
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 22 2015-2019 Microchip Technology Inc.
1.2 DMA Controller
PIC24FJ1024GA610/GB610 family devices have a Direct
Memory Access (DMA) Controller. This module acts in
concert with the CPU, allowing data to move between
data memory and peripherals without the intervention of
the CPU, increasing data throughput and decreasing exe-
cution time overhead. Eight independently programmable
channels make it possible to service multiple peripherals
at virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
1.3 Other Special Features
Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
Configurable Logic Cell: The Configurable
Logic Cell (CLC) module allows the user to
specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins.
Timing Modules: The PIC24FJ1024GA610/GB610
family provides five independent, general purpose,
16-bit timers (four of which can be combined
into two 32-bit timers). The devices also include
three multiple output and four single output
advanced Capture/Compare/PWM/Timer
peripherals, and six independent legacy
Input Capture and six independent legacy
Output Compare modules.
Communications: The PIC24FJ1024GA610/GB610
family incorporates a range of serial communication
peripherals to handle a range of application require-
ments. There are three independent I2C modules
that support both Master and Slave modes of
operation. Devices also have, through the
PPS feature, six independent UARTs with built-in
IrDA® encoders/decoders and three SPI modules.
Analog Features: All members of the
PIC24FJ1024GA610/GB610 family include the
new 12-bit A/D Converter (A/D) module and a
triple comparator module. The A/D module incor-
porates a range of new features that allow the
converter to assess and make decisions on
incoming data, reducing CPU overhead for
routine A/D conversions. The comparator module
includes three analog comparators that are
configurable for a wide range of operations.
CTMU Interface: In addition to their other analog
features, members of the PIC24FJ1024GA610/
GB610 family include the CTMU interface module.
This provides a convenient method for precision
time measurement and pulse generation, and can
serve as an interface for capacitive sensors.
Enhanced Parallel Master/Parallel Slave Port:
This module allows rapid and transparent access
to the microcontroller data bus, and enables the
CPU to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of 4, 8 or 16 bits and
address widths of up to 23 bits in Master modes.
Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
1.4 Details on Individual Family
Members
Devices in the PIC24FJ1024GA610/GB610 family are
available in 64-pin, 100-pin and 121-pin packages. The
general block diagram for all devices is shown in
Figure 1-1.
The devices are differentiated from each other in
six ways:
1. Flash program memory (128 Kbytes for
PIC24FJ128GX6XX devices, 256 Kbytes for
PIC24FJ256GX6XX devices, 512 Kbytes for
PIC24FJ512GX6XX devices and 1024 Kbytes
for PIC24FJ1024GX6XX devices).
2. Available I/O pins and ports (53 pins on six ports
for 64-pin devices and 85 pins on seven ports for
100-pin and 121-pin devices).
3. Available interrupt-on-change (IOC) notification
inputs (53 on 64-pin devices and 85 on 100-pin
and 121-pin devices).
4. Available remappable pins (29 pins on 64-pin
devices, 44 pins on 100-pin and 121-pin
devices).
5. Available USB peripheral (available on
PIC24FJXXXGB6XX devices; not available on
PIC24FJXXXGA6XX devices).
6. Analog input channels (16 channels for 64-pin
devices and 24 channels for 100-pin and 121-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1, Tab l e 1-2 and
Table 1-3.
A list of the pin features available on the
PIC24FJ1024GA610/GB610 family devices, sorted
by function, is shown in Ta b l e 1 - 3 . Note that this table
shows the pin location of individual peripheral features
and not how they are multiplexed on the same pin. This
information is provided in the pinout diagrams in the
beginning of this data sheet. Multiplexed features are
sorted by the priority given to a feature, with the highest
priority peripheral being listed first.
2015-2019 Microchip Technology Inc. DS30010074G-page 23
PIC24FJ1024GA610/GB610 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ1024GA606/GB606: 64-PIN DEVICES
Features PIC24FJ128GX606 PIC24FJ256GX606 PIC24FJ512GX606 PIC24FJ1024GX606
Operating Frequency DC – 32 MHz
Program Memory (bytes) 128K 256K 512K 1024K
Program Memory (instructions) 44,032 88,064 176,128 352,256
Data Memory (bytes) 32K
Interrupt Sources (soft vectors/
NMI traps)
103 (97/6)
I/O Ports Ports B, C, D, E, F, G
Total I/O Pins 53
Remappable Pins 29 (28 I/O, 1 input only)
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers) 2
Input Capture Channels 6(1)
Output Compare/PWM Channels 6(1)
Input Change Notification Interrupt 53
Serial Communications:
6(1)
UART
SPI (3-wire/4-wire) 3(1)
I2C 3
Configurable Logic Cell (CLC) 4(1)
Parallel Communications
(EPMP/PSP)
Yes
Capture/Compare/PWM/Timer
Modules
3 Multiple Outputs and 4 Single Outputs
JTAG Boundary Scan Yes
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
16
Analog Comparators 3
CTMU Interface Yes
Universal Serial Bus Controller Yes (PIC24FJ1024GB606 devices only)
Resets (and Delays) Core POR, VDD POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 64-Pin TQFP and QFN
Note 1: Some peripherals are accessible through remappable pins.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 24 2015-2019 Microchip Technology Inc.
TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ1024GX610: 100-PIN AND 121-PIN DEVICES
Features PIC24FJ128GX610 PIC24FJ256GX610 PIC24FJ512GX610 PIC24FJ1024GX610
Operating Frequency DC – 32 MHz
Program Memory (bytes) 128K 256K 512K 1024K
Program Memory (instructions) 44,032 88,064 176,128 352,256
Data Memory (bytes) 32K
Interrupt Sources
(soft vectors/NMI traps)
103 (97/6)
I/O Ports Ports A, B, C, D, E, F, G
Total I/O Pins 85
Remappable Pins 44 (32 I/O, 12 input only)
Timers:
5(1)
Total Number (16-bit)
32-Bit (from paired 16-bit timers) 2
Capture/Compare/PWM/Timer
Modules
3 Multiple Outputs and 4 Single Outputs
Input Capture Channels 6(1)
Output Compare/PWM Channels 6(1)
Input Change Notification Interrupt 85
Serial Communications:
6(1)
UART
SPI (3-wire/4-wire) 3(1)
I2C 3
Configurable Logic Cell (CLC 4
Parallel Communications
(EPMP/PSP)
Yes
JTAG Boundary Scan Yes
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
24
Analog Comparators 3
CTMU Interface Yes
Universal Serial Bus Controller Yes (PIC14FJ1024GB610 devices only)
Resets (and delays) Core POR, VDD POR, BOR, RESET Instruction,
MCLR, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 100-Pin TQFP and 121-Pin BGA
Note 1: Some peripherals are accessible through remappable pins.
24 4——> I:
2015-2019 Microchip Technology Inc. DS30010074G-page 25
PIC24FJ1024GA610/GB610 FAMILY
FIGURE 1-1: PIC24FJ1024GA610/GB610 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
EDS and
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
VDD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
HLVD &
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulators
Voltage
VCAP
PORTA(1)
PORTC(1)
(12 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Tab l e 1 - 3 for specific implementations by pin count
.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
3:
Some peripheral I/Os are only accessible through remappable pins.
PORTD(1)
(16 I/O)
Comparators(3)
Timer2/3(3)
Timer1 RTCC
IC
A/D
12-Bit
OC/PWM SPI I2C
Timer4/5(3)
EPMP/PSP
1-6(3) IOCs(1) UART
REFO
PORTE(1)
PORTG(1)
(10 I/O)
(12 I/O)
PORTF(1)
(11 I/O)
1-3(3) 1-3 1-6(3)
1-6(3) CTMU USB
Driver
Space
Program Memory/
CLC1-4(1)
DMA
Controller
Data
DMA
Data Bus
16
Tab le Da ta
Access Control
MCCP1/2/3
SCCP4/5/6/7
PCL
BOR
(2)
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 26 2015-2019 Microchip Technology Inc.
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
AN0 16 16 25 25 K2 K2 I ANA A/D Analog Inputs
AN1 15 15 24 24 K1 K1 I ANA
AN2 14 14 23 23 J2 J2 I ANA
AN3 13 13 22 22 J1 J1 I ANA
AN4 12 12 21 21 H2 H2 I ANA
AN5 11 11 20 20 H1 H1 I ANA
AN6 17 17 26 26 L1 L1 I ANA
AN7 18 18 27 27 J3 J3 I ANA
AN8 21 21 32 32 K4 K4 I ANA
AN9 22 22 33 33 L4 L4 I ANA
AN10 23 23 34 34 L5 L5 I ANA
AN11 24 24 35 35 J5 J5 I ANA
AN12 27 27 41 41 J7 J7 I ANA
AN13 28 28 42 42 L7 L7 I ANA
AN14 29 29 43 43 K7 K7 I ANA
AN15 30 30 44 44 L8 L8 I ANA
AN16 9 9 E1 E1 I ANA
AN17 10 10 E3 E3 I ANA
AN18 11 11 F4 F4 I ANA
AN19 12 12 F2 F2 I ANA
AN20 14 14 F3 F3 I ANA
AN21 19 19 G2 G2 I ANA
AN22 92 92 B5 B5 I ANA
AN23 91 91 C5 C5 I ANA
AVDD 19 19 30 30 J4 J4 P Positive Supply for Analog
modules
AVSS 20 20 31 31 L3 L3 P Ground Reference for Analog
modules
C1INA 11 11 20 20 H1 H1 I ANA Comparator 1 Input A
C1INB 12 12 21 21 H2 H2 I ANA Comparator 1 Input B
C1INC 5,8 5,8 11,14 11,14 F4,F3 F4,F3 I ANA Comparator 1 Input C
C1IND 4 4 10 10 E3 E3 I ANA Comparator 1 Input D
C2INA 13 13 22 22 J1 J1 I ANA Comparator 2 Input A
C2INB 14 14 23 23 J2 J2 I ANA Comparator 2 Input B
C2INC 8 8 14 14 F3 F3 I ANA Comparator 2 Input C
C2IND 6 6 12 12 F2 F2 I ANA Comparator 2 Input D
C3INA 55 55 84 84 C7 C7 I ANA Comparator 3 Input A
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 27
PIC24FJ1024GA610/GB610 FAMILY
C3INB 54 54 83 83 D7 D7 I ANA Comparator 3 Input B
C3INC 8,48 8,48 14,74 14,74 F3,B11 F3,B11 I ANA Comparator 3 Input C
C3IND 47 47 73 73 C10 C10 I ANA Comparator 3 Input D
CLC3OUT 46 46 72 72 D9 D9 O DIG CLC3 Output
CLC4OUT 42 42 68 68 E9 E9 O DIG CLC4 Output
CLKI 39 39 63 63 F9 F9 Main Clock Input Connection
CLKO 40 40 64 64 F11 F11 O DIG System Clock Output
CTCMP 14 14 23 23 J2 J2 O ANA CTMU Comparator 2 Input
(Pulse mode)
CTED1 28 28 42 42 L7 L7 I ST CTMU External Edge Inputs
CTED2 27 27 41 41 J7 J7 I ST
CTED3 1 1 B2 B2 I ST
CTED4 1 1 3 3 D3 D3 I ST
CTED5 29 29 43 43 K7 K7 I ST
CTED6 30 30 44 44 L8 L8 I ST
CTED7 40 40 K6 K6 I ST
CTED8 64 64 100 100 A1 A1 I ST
CTED9 63 63 99 99 A2 A2 I ST
CTED10 97 97 A3 A3 I ST
CTED11 95 95 C4 C4 I ST
CTED12 15 15 24 24 K1 K1 I ST
CTED13 14 14 23 23 J2 J2 I ST
CTPLS 29 29 43 43 K7 K7 O DIG CTMU Pulse Output
CVREF 23 23 34 34 L5 L5 O ANA Comparator Voltage Reference
Output
CVREF+ 16 16 25,29 25,29 K2,K3 K2,K3 I ANA Comparator Voltage Reference
(high) Input
CVREF- 15 15 24,28 24,28 K1,L2 K1,L2 I ANA Comparator Voltage Reference
(low) Input
D+ 37 57 H10 I/O XCVR USB Signaling
D- 36 56 J11 I/O XCVR
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 28 2015-2019 Microchip Technology Inc.
IC4 1 1 3 3 D3 D3 I ST Input Capture
IC5 2 2 4 4 C1 C1 I ST
IC6 3 3 5 5 D2 D2 I ST
ICM1 4 4 10 10 12 12 I ST MCCP1 Input Capture
ICM2 6 6 12 12 14 14 I ST MCCP2 Input Capture
ICM3 11 11 20 20 23 23 I ST MCCP3 Input Capture
ICM4 49 49 76 76 91 91 I ST SCCP4 Input Capture
ICM5 42 42 68 68 80 80 I ST SCCP5 Input Capture
ICM6 46 46 72 72 86 86 I ST SCCP6 Input Capture
ICM7 51 51 78 78 93 93 I ST SCCP7 Input Capture
INT0 35 46 55 72 H9 D9 I ST External Interrupt Input 0
IOCA0 17 17 G3 G3 I ST PORTA Interrupt-on-Change
IOCA1 38 38 J6 J6 I ST
IOCA2 58 58 H11 H11 I ST
IOCA3 59 59 G10 G10 I ST
IOCA4 60 60 G11 G11 I ST
IOCA5 61 61 G9 G9 I ST
IOCA6 91 91 C5 C5 I ST
IOCA7 92 92 B5 B5 I ST
IOCA9 28 28 L2 L2 I ST
IOCA10 29 29 K3 K3 I ST
IOCA14 66 66 E11 E11 I ST
IOCA15 67 67 E8 E8 I ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 29
PIC24FJ1024GA610/GB610 FAMILY
IOCB0 16 16 25 25 K2 K2 I ST PORTB Interrupt-on-Change
IOCB1 15 15 24 24 K1 K1 I ST
IOCB2 14 14 23 23 J2 J2 I ST
IOCB3 13 13 22 22 J1 J1 I ST
IOCB4 12 12 21 21 H2 H2 I ST
IOCB5 11 11 20 20 H1 H1 I ST
IOCB6 17 17 26 26 L1 L1 I ST
IOCB7 18 18 27 27 J3 J3 I ST
IOCB8 21 21 32 32 K4 K4 I ST
IOCB9 22 22 33 33 L4 L4 I ST
IOCB10 23 23 34 34 L5 L5 I ST
IOCB11 24 24 35 35 J5 J5 I ST
IOCB12 27 27 41 41 J7 J7 I ST
IOCB13 28 28 42 42 L7 L7 I ST
IOCB14 29 29 43 43 K7 K7 I ST
IOCB15 30 30 44 44 L8 L8 I ST
IOCC1 6 6 D1 D1 I ST PORTC Interrupt-on-Change
IOCC2 7 7 E4 E4 I ST
IOCC3 8 8 E2 E2 I ST
IOCC4 9 9 E1 E1 I ST
IOCC12 39 39 63 63 F9 F9 I ST
IOCC13 47 47 73 73 C10 C10 I ST
IOCC14 48 48 74 74 B11 B11 I ST
IOCC15 40 40 64 64 F11 F11 I ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 30 2015-2019 Microchip Technology Inc.
IOCD0 46 46 72 72 D9 D9 I ST PORTD Interrupt-on-Change
IOCD1 49 49 76 76 A11 A11 I ST
IOCD2 50 50 77 77 A10 A10 I ST
IOCD3 51 51 78 78 B9 B9 I ST
IOCD4 52 52 81 81 C8 C8 I ST
IOCD5 53 53 82 82 B8 B8 I ST
IOCD6 54 54 83 83 D7 D7 I ST
IOCD7 55 55 84 84 C7 C7 I ST
IOCD8 42 42 68 68 E9 E9 I ST
IOCD9 43 43 69 69 E10 E10 I ST
IOCD10 44 44 70 70 D11 D11 I ST
IOCD11 45 45 71 71 C11 C11 I ST
IOCD12 79 79 A9 A9 I ST
IOCD13 80 80 D8 D8 I ST
IOCD14 47 47 L9 L9 I ST
IOCD15 48 48 K9 K9 I ST
IOCE0 60 60 93 93 A4 A4 I ST PORTE Interrupt-on-Change
IOCE1 61 61 94 94 B4 B4 I ST
IOCE2 62 62 98 98 B3 B3 I ST
IOCE3 63 63 99 99 A2 A2 I ST
IOCE4 64 64 100 100 A1 A1 I ST
IOCE5 1 1 3 3 D3 D3 I ST
IOCE6 2 2 4 4 C1 C1 I ST
IOCE7 3 3 5 5 D2 D2 I ST
IOCE8 18 18 G1 G1 I ST
IOCE9 19 19 G2 G2 I ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 31
PIC24FJ1024GA610/GB610 FAMILY
IOCF0 58 58 87 87 B6 B6 I ST PORTF Interrupt-on-Change
IOCF1 59 59 88 88 A6 A6 I ST
IOCF2 34 52 52 K11 K11 I ST
IOCF3 33 33 51 51 K10 K10 I ST
IOCF4 31 31 49 49 L10 L10 I ST
IOCF5 32 32 50 50 L11 L11 I ST
IOCF6 35 55 H9 I ST
IOCF7 34 54 54 H8 H8 I ST
IOCF8 53 53 J10 J10 I ST
IOCF12 40 40 K6 K6 I ST
IOCF13 39 39 L6 L6 I ST
IOCG0 90 90 A5 A5 I ST PORTG Interrupt-on-Change
IOCG1 89 89 E6 E6 I ST
IOCG2 37 37 57 57 H10 H10 I ST
IOCG3 36 36 56 56 J11 J11 I ST
IOCG6 4 4 10 10 E3 E3 I ST
IOCG7 5 5 11 11 F4 F4 I ST
IOCG8 6 6 12 12 F2 F2 I ST
IOCG9 8 8 14 14 F3 F3 I ST
IOCG12 96 96 C3 C3 I ST
IOCG13 97 97 A3 A3 I ST
IOCG14 95 95 C4 C4 I ST
IOCG15 1 1 B2 B2 I ST
HLVDIN 64 64 100 100 A1 A1 I ANA High/Low-Voltage Detect Input
MCLR 7 7 13 13 F1 F1 I ST Master Clear (device Reset)
Input. This line is brought low to
cause a Reset.
OC4 54 54 83 83 D7 D7 O DIG Output Compare Outputs
OC5 55 55 84 84 C7 C7 O DIG
OC6 58 58 87 87 B6 B6 O DIG
OCM1A 4 4 10 10 E3 E3 O DIG MCCP1 Outputs
OCM1B 5 5 11 11 F4 F4 O DIG
OCM1C 1 1 B2 B2 O DIG
OCM1D 6 6 D1 D1 O DIG
OCM1E 91 91 C5 C5 O DIG
OCM1F 92 92 B5 B5 O DIG
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 32 2015-2019 Microchip Technology Inc.
OCM2A 6 6 12 12 F2 F2 O DIG MCCP2 Outputs
OCM2B 8 8 14 14 F3 F3 O DIG
OCM2C 7 7 E4 E4 O DIG
OCM2D 8 8 E2 E2 O DIG
OCM2E 96 96 C3 C3 O DIG
OCM2F 97 97 A3 A3 O DIG
OCM3A 11 11 20 20 H1 H1 O DIG MCCP3 Outputs
OCM3B 12 12 21 21 H2 H2 O DIG
OCM3C 9 9 E1 E1 O DIG
OCM3D 17 17 G3 G3 O DIG
OCM3E 79 79 A9 A9 O DIG
OCM3F 80 80 D8 D8 O DIG
OSCI 39 39 63 63 F9 F9 I ANA/
ST
Main Oscillator Input Connection
OSCO 40 40 64 64 F11 F11 O ANA Main Oscillator Output
Connection
PGEC1 15 15 24 24 K1 K1 I ST ICSP™ Programming Clock
PGEC2 17 17 26 26 L1 L1 I ST
PGEC3 11 11 20 20 H1 H1 I ST
PGED1 16 16 25 25 K2 K2 I/O DIG/ST ICSP Programming Data
PGED2 18 18 27 27 J3 J3 I/O DIG/ST
PGED3 12 12 21 21 H2 H2 I/O DIG/ST
PMA0/
PMALL
30 30 44 44 L8 L8 I/O DIG/
ST/TTL
Parallel Master Port Address[0]/
Address Latch Low
PMA1/
PMALH
29 29 43 43 K7 K7 I/O DIG/
ST/TTL
Parallel Master Port Address[1]/
Address Latch High
PMA14/
PMCS1
45 45 71 71 C11 C11 I/O DIG/
ST/TTL
Parallel Master Port Address[14]/
Slave Chip Select/Chip Select 1
Strobe
PMA15/
PMCS2
44 44 70 70 D11 D11 I/O DIG/
ST/TTL
Parallel Master Port Address[15]/
Chip Select 2 Strobe
PMA6 16 16 29 29 K3 K3 O DIG Parallel Master Port Address
PMA7 22 22 28 28 L2 L2 O DIG
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 33
PIC24FJ1024GA610/GB610 FAMILY
PMA8 32 32 50 50 L11 L11 I/O DIG/
ST/TTL
Parallel Master Port Address
(Demultiplexed Master mode) or
Address/Data (Multiplexed
Master modes)
PMA9 31 31 49 49 L10 L10 I/O DIG/
ST/TTL
PMA10 28 28 42 42 L7 L7 I/O DIG/
ST/TTL
PMA11 27 27 41 41 J7 J7 I/O DIG/
ST/TTL
PMA12 24 24 35 35 J5 J5 I/O DIG/
ST/TTL
PMA13 23 23 34 34 L5 L5 I/O DIG/
ST/TTL
PMA16 95 95 C4 C4 O DIG
PMA17 92 92 B5 B5 O DIG
PMA18 40 40 K6 K6 O DIG
PMA19 19 19 G2 G2 O DIG
PMA2/
PMALU
8 8 14 14 F3 F3 O DIG Parallel Master Port Address[2]/
Address Latch Upper
PMA3 6 6 12 12 F2 F2 O DIG Parallel Master Port Address
PMA4 5 5 11 11 F4 F4 O DIG
PMA5 4 4 10 10 E3 E3 O DIG
PMA20 59 59 G10 G10 O DIG Parallel Master Port Address
(Demultiplexed Master mode) or
Address/Data (Multiplexed
Master modes)
PMA21 60 60 G11 G11 O DIG
PMA22 66 66 E11 E11 O DIG
PMACK1 50 50 77 77 A10 A10 I ST/TTL Parallel Master Port
Acknowledge Input 1
PMACK2 43 43 69 69 E10 E10 I ST/TTL Parallel Master Port
Acknowledge Input 2
PMBE0 51 51 78 78 B9 B9 O DIG Parallel Master Port Byte
Enable 0 Strobe
PMBE1 67 67 E8 E8 O DIG Parallel Master Port Byte
Enable 1 Strobe
PMCS1 18 18 G1 G1 O DIG Parallel Master Port Chip
Select 1 Strobe
PMCS2 9 9 E1 E1 O DIG Parallel Master Port Chip
Select 2 Strobe
PMPCS1 58 58 H11 H11 O DIG Parallel Master Port Chip
Select 1
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 34 2015-2019 Microchip Technology Inc.
PMD0 60 60 93 93 A4 A4 I/O DIG/
ST/TTL
Parallel Master Port Data
(Demultiplexed Master mode) or
Address/Data (Multiplexed
Master modes)
PMD1 61 61 94 94 B4 B4 I/O DIG/
ST/TTL
PMD2 62 62 98 98 B3 B3 I/O DIG/
ST/TTL
PMD3 63 63 99 99 A2 A2 I/O DIG/
ST/TTL
PMD4 64 64 100 100 A1 A1 I/O DIG/
ST/TTL
PMD5 1 1 3 3 D3 D3 I/O DIG/
ST/TTL
PMD6 2 2 4 4 C1 C1 I/O DIG/
ST/TTL
PMD7 3 3 5 5 D2 D2 I/O DIG/
ST/TTL
PMD8 90 90 A5 A5 I/O DIG/
ST/TTL
PMD9 89 89 E6 E6 I/O DIG/
ST/TTL
PMD10 88 88 A6 A6 I/O DIG/
ST/TTL
PMD11 87 87 B6 B6 I/O DIG/
ST/TTL
PMD12 79 79 A9 A9 I/O DIG/
ST/TTL
PMD13 80 80 D8 D8 I/O DIG/
ST/TTL
PMD14 83 83 D7 D7 I/O DIG/
ST/TTL
PMD15 84 84 C7 C7 I/O DIG/
ST/TTL
PMRD/
PMWR
53 53 82 82 B8 B8 I/O DIG/
ST/TTL
Parallel Master Port Read
Strobe/Write Strobe
PMWR/
PMENB
52 52 81 81 C8 C8 I/O DIG/
ST/TTL
Parallel Master Port Write
Strobe/Enable Strobe
PWRGT 21 21 32 32 K4 K4 O DIG Real-Time Clock Power Control
Output
PWRLCLK 48 48 74 74 B11 B11 I ST Real-Time Clock 50/60 Hz Clock
Input
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 35
PIC24FJ1024GA610/GB610 FAMILY
RA0 17 17 G3 G3 I/O DIG/ST PORTA Digital I/Os
RA1 38 38 J6 J6 I/O DIG/ST
RA2 58 58 H11 H11 I/O DIG/ST
RA3 59 59 G10 G10 I/O DIG/ST
RA4 60 60 G11 G11 I/O DIG/ST
RA5 61 61 G9 G9 I/O DIG/ST
RA6 91 91 C5 C5 I/O DIG/ST
RA7 92 92 B5 B5 I/O DIG/ST
RA9 28 28 L2 L2 I/O DIG/ST
RA10 29 29 K3 K3 I/O DIG/ST
RA14 66 66 E11 E11 I/O DIG/ST
RA15 67 67 E8 E8 I/O DIG/ST
RB0 16 16 25 25 K2 K2 I/O DIG/ST PORTB Digital I/Os
RB1 15 15 24 24 K1 K1 I/O DIG/ST
RB2 14 14 23 23 J2 J2 I/O DIG/ST
RB3 13 13 22 22 J1 J1 I/O DIG/ST
RB4 12 12 21 21 H2 H2 I/O DIG/ST
RB5 11 11 20 20 H1 H1 I/O DIG/ST
RB6 17 17 26 26 L1 L1 I/O DIG/ST
RB7 18 18 27 27 J3 J3 I/O DIG/ST
RB8 21 21 32 32 K4 K4 I/O DIG/ST
RB9 22 22 33 33 L4 L4 I/O DIG/ST
RB10 23 23 34 34 L5 L5 I/O DIG/ST
RB11 24 24 35 35 J5 J5 I/O DIG/ST
RB12 27 27 41 41 J7 J7 I/O DIG/ST
RB13 28 28 42 42 L7 L7 I/O DIG/ST
RB14 29 29 43 43 K7 K7 I/O DIG/ST
RB15 30 30 44 44 L8 L8 I/O DIG/ST
RC1 6 6 D1 D1 I/O DIG/ST PORTC Digital I/Os
RC2 7 7 E4 E4 I/O DIG/ST
RC3 8 8 E2 E2 I/O DIG/ST
RC4 9 9 E1 E1 I/O DIG/ST
RC12 39 39 63 63 F9 F9 I/O DIG/ST
RC13 47 47 73 73 C10 C10 I/O DIG/ST
RC14 48 48 74 74 B11 B11 I/O DIG/ST
RC15 40 40 64 64 F11 F11 I/O DIG/ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 36 2015-2019 Microchip Technology Inc.
RD0 46 46 72 72 D9 D9 I/O DIG/ST PORTD Digital I/Os
RD1 49 49 76 76 A11 A11 I/O DIG/ST
RD2 50 50 77 77 A10 A10 I/O DIG/ST
RD3 51 51 78 78 B9 B9 I/O DIG/ST
RD4 52 52 81 81 C8 C8 I/O DIG/ST
RD5 53 53 82 82 B8 B8 I/O DIG/ST
RD6 54 54 83 83 D7 D7 I/O DIG/ST
RD7 55 55 84 84 C7 C7 I/O DIG/ST
RD8 42 42 68 68 E9 E9 I/O DIG/ST
RD9 43 43 69 69 E10 E10 I/O DIG/ST
RD10 44 44 70 70 D11 D11 I/O DIG/ST
RD11 45 45 71 71 C11 C11 I/O DIG/ST
RD12 79 79 A9 A9 I/O DIG/ST
RD13 80 80 D8 D8 I/O DIG/ST
RD14 47 47 L9 L9 I/O DIG/ST
RD15 48 48 K9 K9 I/O DIG/ST
RE0 60 60 93 93 A4 A4 I/O DIG/ST PORTE Digital I/Os
RE1 61 61 94 94 B4 B4 I/O DIG/ST
RE2 62 62 98 98 B3 B3 I/O DIG/ST
RE3 63 63 99 99 A2 A2 I/O DIG/ST
RE4 64 64 100 100 A1 A1 I/O DIG/ST
RE5 1 1 3 3 D3 D3 I/O DIG/ST
RE6 2 2 4 4 C1 C1 I/O DIG/ST
RE7 3 3 5 5 D2 D2 I/O DIG/ST
RE8 18 18 G1 G1 I/O DIG/ST
RE9 19 19 G2 G2 I/O DIG/ST
REFI 24 24 35 35 J5 J5 I ST Reference Clock Input
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 37
PIC24FJ1024GA610/GB610 FAMILY
RF0 58 58 87 87 B6 B6 I/O DIG/ST PORTF Digital I/Os
RF1 59 59 88 88 A6 A6 I/O DIG/ST
RF2 34 52 52 K11 K11 I/O DIG/ST
RF3 33 33 51 51 K10 K10 I/O DIG/ST
RF4 31 31 49 49 L10 L10 I/O DIG/ST
RF5 32 32 50 50 L11 L11 I/O DIG/ST
RF6 35 55 H9 I/O DIG/ST
RF7 34 54 54 H8 H8 I/O DIG/ST
RF8 53 53 J10 J10 I/O DIG/ST
RF12 40 40 K6 K6 I/O DIG/ST
RF13 39 39 L6 L6 I/O DIG/ST
RG0 90 90 A5 A5 I/O DIG/ST PORTG Digital I/Os
RG1 89 89 E6 E6 I/O DIG/ST
RG2 37 37 57 57 H10 H10 I/O DIG/ST
RG3 36 36 56 56 J11 J11 I/O DIG/ST
RG6 4 4 10 10 E3 E3 I/O DIG/ST
RG7 5 5 11 11 F4 F4 I/O DIG/ST
RG8 6 6 12 12 F2 F2 I/O DIG/ST
RG9 8 8 14 14 F3 F3 I/O DIG/ST
RG12 96 96 C3 C3 I/O DIG/ST
RG13 97 97 A3 A3 I/O DIG/ST
RG14 95 95 C4 C4 I/O DIG/ST
RG15 1 1 B2 B2 I/O DIG/ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 38 2015-2019 Microchip Technology Inc.
RP0 16 16 25 25 K2 K2 I/O DIG/ST Remappable Peripherals
(input or output)
RP1 15 15 24 24 K1 K1 I/O DIG/ST
RP2 42 42 68 68 E9 E9 I/O DIG/ST
RP3 44 44 70 70 D11 D11 I/O DIG/ST
RP4 43 43 69 69 E10 E10 I/O DIG/ST
RP5 48 48 K9 K9 I/O DIG/ST
RP6 17 17 26 26 L1 L1 I/O DIG/ST
RP7 18 18 27 27 J3 J3 I/O DIG/ST
RP8 21 21 32 32 K4 K4 I/O DIG/ST
RP9 22 22 33 33 L4 L4 I/O DIG/ST
RP10 31 31 49 49 L10 L10 I/O DIG/ST
RP11 46 46 72 72 D9 D9 I/O DIG/ST
RP12 45 45 71 71 C11 C11 I/O DIG/ST
RP13 14 14 23 23 J2 J2 I/O DIG/ST
RP14 29 29 43 43 K7 K7 I/O DIG/ST
RP15 53 53 J10 J10 I/O DIG/ST
RP16 33 33 51 51 K10 K10 I/O DIG/ST
RP17 32 32 50 50 L11 L11 I/O DIG/ST
RP18 11 11 20 20 H1 H1 I/O DIG/ST
RP19 6 6 12 12 F2 F2 I/O DIG/ST
RP20 53 53 82 82 B8 B8 I/O DIG/ST
RP21 4 4 10 10 E3 E3 I/O DIG/ST
RP22 51 51 78 78 B9 B9 I/O DIG/ST
RP23 50 50 77 77 A10 A10 I/O DIG/ST
RP24 49 49 76 76 A11 A11 I/O DIG/ST
RP25 52 52 81 81 C8 C8 I/O DIG/ST
RP26 5 5 11 11 F4 F4 I/O DIG/ST
RP27 8 8 14 14 F3 F3 I/O DIG/ST
RP28 12 12 21 21 H2 H2 I/O DIG/ST
RP29 30 30 44 44 L8 L8 I/O DIG/ST
RP30 34 52 52 K11 K11 I/O DIG/ST
RP31 39 39 L6 L6 I/O DIG/ST
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
2015-2019 Microchip Technology Inc. DS30010074G-page 39
PIC24FJ1024GA610/GB610 FAMILY
RPI32 40 40 K6 K6 I DIG/ST Remappable Peripherals
(input only)
RPI33 18 18 G1 G1 I DIG/ST
RPI34 19 19 G2 G2 I DIG/ST
RPI35 67 67 E8 E8 I DIG/ST
RPI36 66 66 E11 E11 I DIG/ST
RPI37 48 48 74 74 B11 B11 I DIG/ST
RPI38 6 6 D1 D1 I DIG/ST
RPI39 7 7 E4 E4 I DIG/ST
RPI40 8 8 E2 E2 I DIG/ST
RPI41 9 9 E1 E1 I DIG/ST
RPI42 79 79 A9 A9 I DIG/ST
RPI43 47 47 L9 L9 I DIG/ST
SCL1 37 44 57 66 H10 E11 I/O I2C I2C1 Synchronous Serial Clock
Input/Output
SCL2 32 32 58 58 H11 H11 I/O I2C I2C2 Synchronous Serial Clock
Input/Output
SCL3 2 2 4 4 C1 C1 I/O I2C I2C3 Synchronous Serial Clock
Input/Output
SDA1 36 43 56 67 J11 E8 I/O I2C I2C1 Data Input/Output
SDA2 31 31 59 59 G10 G10 I/O I2C I2C2 Data Input/Output
SDA3 3 3 5 5 D2 D2 I/O I2C I2C3 Data Input/Output
SOSCI 47 47 73 73 C10 C10 I ANA/
ST
Secondary Oscillator/Timer1
Clock Input
SOSCO 48 48 74 74 B11 B11 O ANA Secondary Oscillator/Timer1
Clock Output
T1CK 22 22 33 33 L4 L4 I ST Timer1 Clock
TCK 27 27 38 38 J6 J6 I ST JTAG Test Clock/Programming
Clock Input
TDI 28 28 60 60 G11 G11 I ST JTAG Test Data/Programming
Data Input
TDO 24 24 61 61 G9 G9 O DIG JTAG Test Data Output
TMPR 22 22 33 33 L4 L4 I ST Tamper Detect Input
TMS 23 23 17 17 G3 G3 I ST JTAG Test Mode Select Input
U5CTS 58 58 87 87 B6 B6 I ST UART5 CTS Output
U5RTS/
U5BCLK
55 55 84 84 C7 C7 O DIG UART5 RTS Input
U5RX 54 54 83 83 D7 D7 I ST UART5 Receive Input
U5TX 49 49 76 76 A11 A11 O DIG UART5 Transmit Output
U6CTS 46 46 72 72 D9 D9 I ST UART6 CTS Output
U6RTS/
U6BCLK
42 42 68 68 E9 E9 O DIG UART6 RTS Input
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 40 2015-2019 Microchip Technology Inc.
U6RX 27 27 41 41 J7 J7 I ST UART6 Receive Input
U6TX 18 18 27 27 J3 J3 O DIG UART6 Transmit Output
USBID 33 51 K10 I ST USB OTG ID Input
USBOEN 12 21 H2 O DIG USB Output Enable (active-low)
VBUS —3454H8IVBUS Supply Detect
VCAP 56 56 85 85 B7 B7 P External Filter Capacitor
Connection (regulator enabled)
VDD 10,26,38 10,26,38 2,16,37,
46,62
2,16,37,
46,62
C2,F8,
G5,H6,
K8
C2,F8,
G5,H6,
K8
P Positive Supply for Peripheral
Digital Logic and I/O Pins
VREF+ 16 16 25,29 25,29 K2,K3 K2,K3 I ANA Comparator and A/D Reference
Voltage (high) Input
VREF- 15 15 24,28 24,28 K1,L2 K1,L2 I ANA Comparator and A/D Reference
Voltage (low) Input
VSS 9,25,41 9,25,41 15,36,45,
65,75
15,36,45,
65,75
B10,F5,
F10,G6,
G7
B10,F5,
F10,G6,
G7
P Ground Reference for
Peripheral Digital Logic and I/O
Pins
VUSB3V3 —3555H9P3.3V VUSB
TABLE 1-3: PIC24FJ1024GA610/GB610 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
I/O Input
Buffer Description
GA606
64-Pin
QFN/TQFP/
QFP
GB606
64-Pin QFN/
TQFP/QFP
GA610
100-Pin
TQFP/
QFP
GB610
100-Pin
TQFP/
QFP
GA612
121-Pin
BGA
GB612
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C = I2C/SMBus input buffer
DIG = Digital input/output XCVR = Dedicated Transceiver
M w H? NHL W W
2015-2019 Microchip Technology Inc. DS30010074G-page 41
PIC24FJ1024GA610/GB610 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC24FJ1024GA610/GB610
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
The following pins must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Power Supply Pins”)
The USB transceiver supply, VUSB3V3, regardless
of whether or not the USB module is used
(see Section 2.2 “Power Supply Pins”)
•All AV
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
MCLR
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
•V
CAP pin (PIC24F J devices only)
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
These pins must also be connected if they are being
used in the end application:
PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
PIC24FJXXXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
VDD
MCLR VCAP
R2
C7
C2(2)
C3(2)
C4(2)
C5(2)
C6(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 50V ceramic
C7: 10 F, 16V or greater, ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pin
(VCAP)” for an explanation of voltage
regulator pin connections.
2: The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)
MCLR MCLR MCLR MCLR WHH
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 42 2015-2019 Microchip Technology Inc.
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: A 0.1 µF (100 nF),
16V-50V capacitor is recommended. The
capacitor should be a low-ESR device with a
self-resonance frequency in the range of 200 MHz
and higher. Ceramic capacitors are
recommended.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic-type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 µF in parallel with 0.001 µF).
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 µF to 47 µF.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
device Reset, and device programming and debug-
ging. If programming and debugging are not required
in the end application, a direct connection to VDD
may be all that is required. The addition of other
components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented
depending on the application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and debug-
ging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of a MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
PIC24FJXXXX
JP
2015-2019 Microchip Technology Inc. DS30010074G-page 43
PIC24FJ1024GA610/GB610 FAMILY
2.4 Voltage Regulator Pin (VCAP)
Refer to Section 30.3 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
A low-ESR (< 5Ω) capacitor is required on the VCAP pin
to stabilize the voltage regulator output voltage. The
VCAP pin must not be connected to VDD and must use a
capacitor of 10 µF connected to ground. The type can be
ceramic or tantalum. Suitable examples of capacitors
are shown in Table 2-1. Capacitors with equivalent
specifications can be used.
Designers may use Figure 2-3 to evaluate the ESR
equivalence of candidate devices.
The placement of this capacitor should be close to VCAP.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 33.0 “Electrical
Characteristics” for additional information.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
.
Note: This section applies only to PIC24FJ
devices with an on-chip voltage regulator.
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
ESR ()
Note: Typical data measurement at +25°C, 0V DC bias.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS (0805 CASE SIZE)
Make Part # Nominal
Capacitance Base Tolerance Rated Voltage
TDK C2012X5R1E106K085AC 10 µF ±10% 25V
TDK C2012X5R1C106K085AC 10 µF ±10% 16V
Kemet C0805C106M4PACTU 10 µF ±10% 16V
Murata GRM21BR61E106KA3L 10 µF ±10% 25V
Murata GRM21BR61C106KE15 10 µF ±10% 16V
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 44 2015-2019 Microchip Technology Inc.
2.4.1 CONSIDERATIONS FOR CERAMIC
CAPACITORS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
Ceramic capacitors are suitable for use with the inter-
nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance
specifications for these types of capacitors are often
specified as ±10% to ±20% (X5R and X7R) or -20%/
+80% (Y5V). However, the effective capacitance that
these capacitors provide in an application circuit will also
vary based on additional factors, such as the applied DC
bias voltage and the temperature. The total in-circuit tol-
erance is, therefore, much wider than the initial tolerance
specification.
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.
FIGURE 2-4: DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
a minimum of 16V for the 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits, and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” pins (i.e., PGECx/PGEDx),
programmed into the device, match the physical
connections for the ICSP to the Microchip debugger/
emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 31.0 “Development Support”.
-80
-70
-60
-50
-40
-30
-20
-10
0
10
5 1011121314151617
DC Bias Voltage (VDC)
Capacitance Change (%)
01234 6789
16V Capacitor
10V Capacitor
6.3V Capacitor
_ sc0\ MM —> ENE
2015-2019 Microchip Technology Inc. DS30010074G-page 45
PIC24FJ1024GA610/GB610 FAMILY
2.6 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency Primary Oscillator and a
low-frequency Secondary Oscillator (refer to
Section 9.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times
and other similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):
AN943, “Practical PICmicro® Oscillator Analysis
and Design”
AN949, “Making Your Oscillator Work
AN1798, “Crystal Selection for Low-Power
Secondary Oscillator”
FIGURE 2-5: SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
GND
`
`
`
OSCI
OSCO
SOSCO
SOSC I
Copper Pour Primary Oscillator
Crystal
Secondary
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
Sec Oscillator: C1 Sec Oscillator: C2
(tied to ground)
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
Oscillator
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 46 2015-2019 Microchip Technology Inc.
2.7 Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debug-
ger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by setting all bits in the ADxPCFG
register(s) or clearing all bits in the ANSx registers.
All PIC24F devices will have either one or more
ADxPCFG registers, or several ANSx registers (one for
each port); no device will have both. Refer to
Section 11.2 “Configuring Analog Port Pins
(ANSx)” for more specific information.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
For devices with an ADxPCFG register, clear the
bits corresponding to the pin(s) to be configured
as analog. Do not change any other bits, particu-
larly those corresponding to the PGECx/PGEDx
pair, at any time.
For devices with ANSx registers, set the bits
corresponding to the pin(s) to be configured as
analog. Do not change any other bits, particularly
those corresponding to the PGECx/PGEDx pair,
at any time.
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ADxPCFG or ANSx registers.
Automatic initialization of these registers is only done
during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic 0’, which may affect user
application functionality.
2.8 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
2015-2019 Microchip Technology Inc. DS30010074G-page 47
PIC24FJ1024GA610/GB610 FAMILY
3.0 CPU
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen, 16-bit Working registers
in the programmer’s model. Each of the Working
registers can act as a Data, Address or Address Offset
register. The 16th Working register (W15) operates as
a Software Stack Pointer (SSP) for interrupts and calls.
The lower 32 Kbytes of the Data Space (DS) can be
accessed linearly. The upper 32 Kbytes of the Data
Space are referred to as Extended Data Space (EDS),
to which the extended data RAM, EPMP memory
space or program memory can be mapped.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil-
ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct Addressing modes along with
three groups of addressing modes. All modes support
Register Direct and various Register Indirect modes.
Each group offers up to seven addressing modes.
Instructions are associated with predefined addressing
modes depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a Working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
A high-speed, 17-bit x 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit x 16-bit or
8-bit x 8-bit, integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or 16-bit),
divided by 16-bit, integer signed and unsigned division.
All divide operations require 19 cycles to complete but
are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
A block diagram of the CPU is shown in Figure 3-1.
3.1 Programmers Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory-mapped and can be manipulated directly by
instructions.
A description of each register is provided in Tab le 3-1 .
All registers associated with the programmer’s model
are memory-mapped.
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
CPU, refer to “CPU with Extended
Data Space (EDS)” (www.microchip.com/
DS39732)
in the “dsPIC33/PIC24 Family
Reference Manual”, which is available from
the Microchip website (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 48 2015-2019 Microchip Technology Inc.
FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
TABLE 3-1: CPU CORE REGISTERS
Register(s) Name Description
W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
RCOUNT REPEAT Loop Counter Register
CORCON CPU Control Register
DISICNT Disable Interrupt Count Register
DSRPAG Data Space Read Page Register
DSWPAG Data Space Write Page Register
Instruction
Decode and
Control
PCH
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
Divide
Support
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
8
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory/
Data Latch
Address Bus
16
Literal Data
16 16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
Up to 0x7FFF
Extended Data
Space
PCL
16 x 16
W Register Array
EDS and Table
Data Access
Control Block
2015-2019 Microchip Technology Inc. DS30010074G-page 49
PIC24FJ1024GA610/GB610 FAMILY
FIGURE 3-2: PROGRAMMERS MODEL
N OV Z C
TBLPAG
22 0
7 0
015
Program Counter
Table Memory Page
ALU STATUS Register (SR)
Working/Address
Registers
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer
Stack Pointer
RA
0
RCOUNT
15 0REPEAT Loop Counter
SPLIM Stack Pointer Limit
SRL
0
0
15 0
CPU Control Register (CORCON)
SRH
W14
W15
DC
IPL
2
1
0
PC
Divider Working Registers
Multiplier Registers
15 0
Value Register
Address Register
Register
Data Space Read Page Register
Data Space Write Page Register
Disable Interrupt Count Register
13 0
DISICNT
90
DSRPAG
80
DSWPAG
IPL3 ———
Registers or bits are shadowed for PUSH.S and POP.S instructions.
————————————
——
[1) (1) [1) [1) 1 12) [1) /Borrow
PIC24FJ1024GA610/GB610 FAMILY
DS30010074G-page 50 2015-2019 Microchip Technology Inc.
3.2 CPU Control/Status Registers
REGISTER 3-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — —DC
bit 15 bit 8
R/W-0(1)R/W-0(1)R/W-0(1)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2(2)IPL1(2)IPL0(2)RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as0
bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5 IPL[2:0]: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit
1 = Result was negative
0 = Result was not negative (zero or positive)
bit 2 OV: ALU Overflow bit
1 = Overflow occurred for signed (two’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1 Z: ALU Zero bit
1 = An operation, which affects the Z bit, has set it at some time in the past
0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow bit
1 = A carry out from the Most Significant bit (MSb) of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1.
2: The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
PSV‘Z)
2015-2019 Microchip Technology Inc. DS30010074G-page 51
PIC24FJ1024GA610/GB610 FAMILY
REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0
————IPL3
(1)PSV(2)— —
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as0
bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 PSV: Program Space Visibility (PSV) in Data Space Enable
1 = Program space is visible in Data Space
0 = Program space is not visible in Data Space
bit 1-0 Unimplemented: Read as0
Note 1: The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see
Register 3-1 for bit description.
2: If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of
reading from the PSV section of program memory. This bit is not individually addressable.
Borrow Digi‘ Borrow
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3.3 Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addi-
tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
3.3.1 MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.3.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.3.3 MULTIBIT SHIFT SUPPORT
The PIC24F ALU supports both single bit and single-
cycle, multibit arithmetic and logic shifts. Multibit shifts
are implemented using a shifter block, capable of
performing up to a 15-bit arithmetic right shift, or up to
a 15-bit left shift, in a single cycle. All multibit shift
instructions only support Register Direct Addressing for
both the operand source and result destination.
A full summary of instructions that use the shift
operation is provided in Table 3-2.
TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTIBIT SHIFT OPERATION
Instruction Description
ASR Arithmetic Shift Right Source register by one or more bits.
SL Shift Left Source register by one or more bits.
LSR Logical Shift Right Source register by one or more bits.
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4.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space during
code execution.
4.1 Program Memory Space
The program address memory space of the
PIC24FJ1024GA610/GB610 family devices is 4M
instructions. The space is addressable by a 24-bit value
derived from either the 23-bit Program Counter (PC)
during program execution, or from table operation or
Data Space remapping, as described in Section 4.3
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG[7] to permit access to
the Configuration bits and customer OTP sections of
the configuration memory space.
The PIC24FJ1024GA610/GB610 family of devices
supports a Single Partition mode and two Dual Partition
modes. The Dual Partition modes allow the device to
be programmed with two separate applications to facil-
itate bootloading or to allow an application to be
programmed at run time without stalling the CPU.
Memory maps for the PIC24FJ1024GA610/GB610
family of devices are shown in Figure 4-1.
FBOOT
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FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ1024GA610/GB610 FAMILY
DEVICES
TABLE 4-1: PROGRAM MEMORY SIZES AND BOUNDARIES(1)
Device
Program Memory Upper Boundary (Instruction Words)
Write
Blocks(2)
Erase
Blocks(2)
Single Partition
Mode
Dual Partition Mode
Active Partition Inactive Partition
PIC24FJ1024GX6XX 0ABFFEh (352K) 055FFEh (176K) 455FFEh (176K) 2752 344
PIC24FJ512GX6XX 055FFEh (176K) 02AFFEh (88k) 42AFFEh (88k) 1376 172
PIC24FJ256GX6XX 02AFFEh (88K) 0157FEh (44k) 4157FEh (44k) 688 86
PIC24FJ128GX6XX 015FFEh (44K) 00AFFEh (22k) 40AFFEh (22k) 352 44
Note 1: Includes Flash Configuration Words.
2: 1 Write Block = 128 Instruction Words; 1 Erase Block = 1024 Instruction Words.
000000h
FA00FEh
FA0100h
FEFFFEh
FFFFFFh
Configuration Memory Space User Memory Space
Flash Write Latches
DEVID (2)
Reserved
FF0000h
F9FFFEh
FA0000h
800000h
7FFFFFh
Reserved
Flash Config Words
0xxx00h(1)
0xxxFEh(1)
Unimplemented
Read ‘0
User Flash Program Memory
FBOOT 801802h
801800h
Reserved
FF0004h
Reserved
Executive Code Memory 800FFEh
800100h
Customer OTP Memory 8017FEh
801700h
Reserved 801000h
801804h
8016FEh
Single Partition Mode
000000h
Configuration Memory Space User Memory Space
800000h
7FFFFFh
Reserved
Flash Config Words
0xxx00h(1)
0xxxFEh(1)
Unimplemented
Read ‘0
User Flash Program Memory
FBOOT 801802h
801800h
Reserved
Executive Code Memory 800FFEh
800100h
Customer OTP Memory 8017FEh
801700h
Reserved 801000h
801804h
8016FEh
400000h
Flash Config Words
User Flash Program Memory
4xxx00h(1)
4xxxFEh(1)
Unimplemented
Read ‘0
FA00FEh
FA0100h
FEFFFEh
FFFFFFh
Flash Write Latches
DEVID(2)
Reserved
FF0000h
F9FFFEh
FA0000h
FF0004h
Reserved
Legend: Memory areas are not shown to scale.
Note 1: Exact boundary addresses are determined by the size of the implemented program memory (Table 4-1).
Dual Partition Mode
\ocaled allhe address, (BSLIM[12.0]
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4.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-3).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
In Single Partition mode, user program memory is
arranged in a contiguous block starting at address,
000000h.
4.1.2 DUAL PARTITION FLASH PROGRAM
MEMORY ORGANIZATION
In the Dual Partition modes, the device’s memory is
divided evenly into two physical sections, known as
Partition 1 and Partition 2. Each of these partitions con-
tains its own program memory and Configuration
Words. During program execution, the code on only
one of these panels is executed; this is the Active
Partition. The other partition, or the Inactive Partition, is
not used, but can be programmed.
The Active Partition is always mapped to logical
address, 000000h, while the Inactive Partition will
always be mapped to logical address, 400000h. Note
that even when the code partitions are switched
between Active and Inactive by the user, the address of
the Active Partition will still be at 000000h and the
address of the Inactive Partition will still be at 400000h.
The Boot Sequence Configuration Word (FBTSEQ)
determines whether Partition 1 or Partition 2 will be active
after Reset. If the part is operating in Dual Partition mode,
the partition with the lower Boot Sequence Number will
operate as the Active Partition (FBTSEQ is unused in
Single Partition mode). The partitions can be switched
between Active and Inactive by reprogramming their
Boot Sequence Numbers, but the Active Partition will not
change until a device Reset is performed. If both Boot
Sequence Numbers are the same, or if both are
corrupted, the part will use Partition 1 as the Active Parti-
tion. If only one Boot Sequence Number is corrupted, the
device will use the partition without a corrupted Boot
Sequence Number as the Active Partition.
Should a Boot Sequence Number be invalid (or
unprogrammed), it will be overridden to value, 0x000FFF
(i.e., the highest possible Boot Sequence Number).
The user can also change which partition is active at run
time using the BOOTSWP instruction. Issuing a BOOTSWP
instruction does not affect which partition will be the
Active Partition after a Reset. Figure 4-2 demonstrates
how the relationship between Partitions 1 and 2, shown
in red and blue respectively, and the Active and Inactive
Partitions are affected by reprogramming the Boot
Sequence Number or issuing a BOOTSWP instruction.
The P2ACTIV bit (NVMCON[10]) can be used to deter-
mine which physical partition is the Active Partition. If
P2ACTIV = 1, Partition 2 is active; if P2ACTIV = 0,
Partition 1 is active.
4.1.3 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the PC
on a device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
The PIC24FJ1024GA610/GB610 devices can have up to
two Interrupt Vector Tables (IVT). The first is located from
addresses, 000004h to 0000FFh. The Alternate Interrupt
Vector Table (AIVT) can be enabled by the AIVTDIS Con-
figuration bit if the Boot Segment (BS) is present. If the
user has configured a Boot Segment, the AIVT will be
located at the address, (BSLIM[12:0] – 1) x 0x800. These
vector tables allow each of the many device interrupt
sources to be handled by separate ISRs. A more detailed
discussion of the Interrupt Vector Tables is provided in
Section 8.1 “Interrupt Vector Table”.
4.1.4 CONFIGURATION BITS OVERVIEW
The Configuration bits are stored in the last page loca-
tion of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system oper-
ation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
Table 4-2 lists the Configuration register address range
for each device in Single and Dual Partition modes.
Table 4-2 lists all of the Configuration bits found in the
PIC24FJ1024GA610/GB610 family devices, as well as
their Configuration register locations. Refer to
Section 30.0 “Special Features” in this data sheet for
the full Configuration register description for each
specific device.
PIC24FJ1024GA610/GB610 FAMILY
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FIGURE 4-2: RELATIONSHIP BETWEEN PARTITIONS 1/2 AND ACTIVE/INACTIVE PARTITIONS
Active Partition
Active Partition
Inactive Partition
Inactive Partition
Partition 1
BSEQ = 10
Partition 2
BSEQ = 15
Partition 2
BSEQ = 15
Partition 1
BSEQ = 10
Partition 1
BSEQ = 10
Partition 2
BSEQ = 15
Partition 1
BSEQ = 10
Partition 2
BSEQ = 15
Partition 1
BSEQ = 10
Partition 2
BSEQ = 5
Partition 2
BSEQ = 5
Partition 1
BSEQ = 10
000000h
400000h
000000h
400000h
000000h
400000h
000000h
400000h
000000h
400000h
000000h
400000h
Reset
BOOTSWP
Instruction
Reprogram BSEQ
Reset
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TABLE 4-2: CONFIGURATION WORD ADDRESSES
Configuration
Register
Single Partition Mode
PIC24FJ1024GX6XX PIC24FJ512GX6XX PIC24FJ256GX6XX PIC24FJ128GX6XX
FSEC 0ABF00h 055F00h 02AF00h 015F00h
FBSLIM 0ABF10h 055F10h 02AF10h 015F10h
FSIGN 0ABF14h 055F14h 02AF14h 015F14h
FOSCSEL 0ABF18h 055F18h 02AF18h 015F18h
FOSC 0ABF1Ch 055F1Ch 02AF1Ch 015F1Ch
FWDT 0ABF20h 055F20h 02AF20h 015F20h
FPOR 0ABF24h 055F24h 02AF24h 015F24h
FICD 0ABF28h 055F28h 02AF28h 015F28h
FDEVOPT1 0ABF2Ch 055F2Ch 02AF2Ch 015F2Ch
FBOOT 801800h
Dual Partition Modes(1)
FSEC(2)055F00h/455F00h 02AF00h/42AF00h 015700h/415700h 00AF00h/40AF00h
FBSLIM(2)055F10h/455F10h 02AF10h/42AF10h 015710h/415710h 00AF10h/40AF10h
FSIGN(2)055F14h/455F14h 02AF14h/42AF14h 015714h/415714h 00AF14h/40AF14h
FOSCSEL 055F18h/455F18h 02AF18h/42AF18h 015718h/415718h 00AF18h/40AF18h
FOSC 055F1Ch/455F1Ch 02AF1Ch/42AF1Ch 01571Ch/41571Ch 00AF1Ch/40AF1Ch
FWDT 055F20h/455F20h 02AF20h/42AF20h 015720h/415720h 00AF20h/40AF20h
FPOR 055F24h/455F24h 02AF24h/42AF24h 015724h/415724h 00AF24h/40AF24h
FICD 055F28h/455F28h 02AF28h/42AF28h 015728h/415728h 00AF28h/40AF28h
FDEVOPT1 055F2Ch/455F2Ch 02AF2Ch/42AF2Ch 01572Ch/41572Ch 00AF2Ch/40AF2Ch
FBTSEQ(3)055FFCh/455FFCh 02AFFCh/42AFFCh 0157FCh/4157FCh 00AFFCh/40AFFCh
FBOOT 801800h
Note 1: Addresses shown for Dual Partition modes are for the Active/Inactive Partitions, respectively.
2: Changes to these Inactive Partition Configuration Words affect how the Active Partition accesses the
Inactive Partition.
3: FBTSEQ is a 24-bit Configuration Word, using all three bytes of the program memory width.
PIC24FJ1024GA610/GB610 FAMILY
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4.1.5 CODE-PROTECT CONFIGURATION
BITS
The device implements intermediate security features
defined by the FSEC register. The Boot Segment (BS)
is the higher privilege segment and the General Seg-
ment (GS) is the lower privilege segment. The total
user code memory can be split into BS or GS. The size
of the segments is determined by the BSLIM[12:0] bits.
The relative location of the segments within user space
does not change, such that BS (if present) occupies the
memory area just after the Interrupt Vector Table (IVT)
and the GS occupies the space just after the BS.
The Configuration Segment (CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that are loaded by the NVM Controller during the
Reset sequence.
4.1.6 CUSTOMER OTP MEMORY
PIC24FJ1024GA610/GB610 family devices provide
256 bytes of One-Time-Programmable (OTP) mem-
ory, located at addresses, 801700h through 8017FEh.
This memory can be used for persistent storage of
application-specific information that will not be erased
by reprogramming the device. This includes many
types of information, such as (but not limited to):
Application Checksums
Code Revision Information
Product Information
Serial Numbers
System Manufacturing Dates
Manufacturing Lot Numbers
Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data are not cleared by a chip erase.
Do not write the OTP memory more than one time.
Writing to the OTP memory more than once may result
in a permanent ECC Double-Bit Error (ECCDBE) trap.
Therefore, writing to OTP memory should only be done
after the firmware is debugged and the part is
programmed in a production environment.
4.1.7 DUAL PARTITION CONFIGURATION
WORDS
In Dual Partition modes, each partition has its own set of
Flash Configuration Words. The full set of Configuration
registers in the Active Partition is used to determine the
device’s configuration; the Configuration Words in the
Inactive Partition are used to determine the device’s
configuration when that partition becomes active. How-
ever, some of the Configuration registers in the Inactive
Partition (FSEC, FBSLIM and FSIGN) may be used to
determine how the Active Partition is able or allowed to
access the Inactive Partition.
\—v—)Lv—j\ gr—J
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4.2 Data Memory Space
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-3.
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 32 Kbytes or 16K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS).
The lower half of DS is compatible with previous PIC24F
microcontrollers without EDS. All PIC24FJ1024GA610/
GB610 family devices implement 30 Kbytes of data
RAM in the lower half of DS, from 0800h to 7FFF.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data are aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ1024GA610/GB610 FAMILY DEVICES
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to “Data Memory with Extended Data
Space (EDS)” (www.microchip.com/
DS39733) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
Note: Memory areas not shown to scale.
0000h
07FEh
FFFEh
LSB
Address
LSBMSB
MSB
Address
0001h
07FFh
1FFFh
FFFFh
8001h 8000h
7FFFh
0801h 0800h
2001h
Near
1FFEh
SFR
2000h
7FFEh
EDS Window
Space
Data Space
Upper 32 Kbytes
Data Space
Lower 32 Kbytes
Data Space
30 Kbytes Data RAM
SFR Space
EDS Page 0x1
(2 Kbytes implemented)
EDS Page 0x2
EDS Page 0x1FF
EDS Page 0x200
EDS Page 0x2FF
EDS Page 0x300
EDS Page 0x3FF
Internal Extended
Data RAM (2 Kbytes)
EPMP Memory Space
Program Space Visibility
Area to Access Lower
Word of Program Memory
Program Space Visibility
Area to Access Upper
Word of Program Memory
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4.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCUs and
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to deter-
mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow-
ing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
A Sign-Extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register by executing a Zero-Extend
(ZE) instruction on the appropriate address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3 NEAR DATA SPACE
The 8-Kbyte area bet