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PIC16(L)F18855/75 Datasheet by Microchip Technology

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6‘ ‘ MICRDCHIP P|C16(L)F18855/75
2015-2018 Microchip Technology Inc. DS40001802F-page 1
PIC16(L)F18855/75
Description
PIC16(L)F18855/75 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 14 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC2) extensions for automated signal analysis to reduce the complexity of the
application.
Core Features
C Compiler Optimized RISC Architecture
Only 49 Instructions
Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
Interrupt Capability
16-Level Deep Hardware Stack
Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT) Extensions
Four 16-Bit Timers (TMR0/1/3/5)
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRTE)
Brown-out Reset (BOR) with Fast Recovery
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
Programmable Code Protection
Memory
Up to 14 KB Flash Program Memory
Up to 1 KB Data SRAM
256B of EEPROM
Direct, Indirect and Relative Addressing modes
Operating Characteristics
Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18855/75)
- 2.3V to 5.5V (PIC16F18855/75)
Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
DOZE mode: Ability to run the CPU core slower
than the system clock
IDLE mode: Ability to halt CPU core while internal
peripherals continue operating
Sleep mode: Lowest Power Consumption
Peripheral Module Disable (PMD):
- Ability to disable hardware module to
minimize power consumption of unused
peripherals
eXtreme Low-Power (XLP) Features
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
-8 A @ 32 kHz, 1.8V, typical
-32 A/MHz @ 1.8V, typical
Digital Peripherals
Four Configurable Logic Cells (CLC):
- Integrated combinational and sequential logic
Three Complementary Waveform Generators
(CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
Five Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
10-bit PWM:
- Two 10-bit PWMs
Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
Two Signal Measurement Timers (SMT):
- 24-bit Signal Measurement Timer
- Up to 12 different Acquisition modes
Full-Featured 28/40/44-Pin Microcontrollers
2015-2018 Microchip Technology Inc. DS40001802F-page 2
PIC16(L)F18855/75
Digital Peripherals (Cont.)
Cyclical Redundancy Check (CRC/SCAN):
- 16-bit CRC
- Scans memory for NVM integrity
• Communication:
- EUSART, RS-232, RS-485, LIN compatible
-Two SPI
-Two I
2C, SMBus, PMBus™ compatible
Up to 36 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
- Current mode enable
Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
Data Signal Modulator (DSM)
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
Analog Peripherals
Analog-to-Digital Converter with Computation
(ADC2):
- 10-bit with up to 35 external channels
- Automated post-processing
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
Two Comparators (COMP):
- Fixed Voltage Reference at (non) inverting
input(s)
- Comparator outputs externally accessible
5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
Flexible Oscillator Structure
High-Precision Internal Oscillator:
- Software selectable frequency range up to 32
MHz, ±1% typical
x2/x4 PLL with Internal and External Sources
Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator
resources
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2015-2018 Microchip Technology Inc. DS40001802F-page 3
PIC16(L)F18855/75
PIC16(L)F188XX Family Types
Device
Data Sheet Index
Program Flash
Memory (Words)
Program Flash
Memory (KB)
EEPROM
(bytes)
Data SRAM
(bytes)
I/O Pins(1)
10-Bit ADC2 (ch)
5-Bit DAC
Comparator
8-Bit (with HLT)/
16-Bit Timers
SMT
Windowed
Watchdog Timer
CRC and Memory Scan
CCP/10-Bit PWM
Zero-Cross Detect
CWG
NCO
CLC
DSM
EUSART/I2C/SPI
Peripheral Pin Select
Peripheral Module
Disable
PIC16(L)F18854 (1) 4096 7256 512 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18855 (2) 8192 14 256 1024 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18856 (3) 16384 28 256 2048 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18857 (4) 32768 56 256 4096 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18875 (2) 8192 14 256 1024 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18876 (3) 16384 28 256 2048 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18877 (4) 32768 56 256 4096 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
Note 1: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document)
1: DS40001826 PIC16(L)F18854 Data Sheet, 28-Pin, Full-Featured 8-bit Microcontrollers
2: DS40001802 PIC16(L)F18855/75 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
3: DS40001824 PIC16(L)F18856/76 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
4: DS40001825 PIC16(L)F18857/77 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
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2015-2018 Microchip Technology Inc. DS40001802F-page 4
PIC16(L)F18855/75
PIN DIAGRAMS
TABLE 1: PACKAGES
Packages (S)PDIP SOIC SSOP QFN
(6x6)
UQFN
(4x4) TQFP QFN
(8x8)
UQFN
(5x5)
PIC16(L)F18855 
PIC16(L)F18875 
Note: Pin details are subject to change.
Note 1: See Table 2 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins
to float may result in degraded electrical performance or non-functionality.
PIC16(L)F18855
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
11
12
13
14 15
16
17
18
19
20
28
27
26
25
24
23
22
21
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RC5
RC4
RC7
RC6
RB7
28-pin SPDIP, SOIC, SSOP
jjjjjjjjjjjjjjjjjjjj DDDDDDDDDDDDDDDDDDDD
2015-2018 Microchip Technology Inc. DS40001802F-page 5
PIC16(L)F18855/75
Note 1: See Table 2 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
2
3
6
1
18
19
20
21
15
7
16
17
RC0
5
4
RB7
RB6
RB5
RB4
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RE3/MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC1
RC2
RC3
9
10
13
8
14
12
11
27
26
23
28
22
24
25
RB3
RB2
RB1
PIC16(L)F18855
28-pin QFN (6x6), UQFN (4x4)
Note 1: See Table 3 for location of all peripheral function.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
PIC16(L)F18875
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
RB6/ICSPCLK
RB5
RB4
RB0
VDD
VSS
RD2
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
RC5
RC4
RD3
RD4
RC7
RC6
RD7
RD6
RD5
RB7/ICSPDAT
1
RB3
RB2
RB1
40-pin PDIP
2015-2018 Microchip Technology Inc. DS40001802F-page 6
PIC16(L)F18855/75
Note 1: See Table 3 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA1
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
PIC16(L)F18875
RA3
RA2
40-pin UQFN (5x5)
Note 1: See Table 3 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC16(L)F18875
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA1
AN0/RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC
RA3
RA2
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RA6
RA7
VSS
NC
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
44-pin TQFP (10x10)
MCLR
2015-2018 Microchip Technology Inc. DS40001802F-page 7
PIC16(L)F18855/75
Note 1: See Table 3 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA0
VPP/MCLR/RE3
RB3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
NC RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
RA6
RA7
NC
VSS
NC
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
NC
RB0
RB1
RB2
PIC16(L)F18875
RA3
RA2
RA1
44-pin QFN (8x8)
2015-2018 Microchip Technology Inc. DS40001802F-page 14
PIC16(L)F18855/75
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 16
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 33
3.0 Memory Organization ................................................................................................................................................................. 35
4.0 Device Configuration .................................................................................................................................................................. 91
5.0 Resets ...................................................................................................................................................................................... 100
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 109
7.0 Interrupts .................................................................................................................................................................................. 128
8.0 Power-Saving Operation Modes .............................................................................................................................................. 154
9.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 161
10.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 169
11.0 Cyclic Redundancy Check (CRC) Module ............................................................................................................................... 187
12.0 I/O Ports ................................................................................................................................................................................... 199
13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 234
14.0 Peripheral Module Disable ....................................................................................................................................................... 244
15.0 Interrupt-On-Change ................................................................................................................................................................ 251
16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 259
17.0 Temperature Indicator Module ................................................................................................................................................. 262
18.0 Comparator Module.................................................................................................................................................................. 264
19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 274
20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 281
21.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 305
22.0 Configurable Logic Cell (CLC).................................................................................................................................................. 311
23.0 Analog-to-Digital Converter With Computation (ADC2) Module............................................................................................... 328
24.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 366
25.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 376
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 381
27.0 Timer0 Module ......................................................................................................................................................................... 394
28.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 400
29.0 Timer2/4/6 Module ................................................................................................................................................................... 414
30.0 Capture/Compare/PWM Modules ............................................................................................................................................ 435
31.0 Master Synchronous Serial Port (MSSP) Modules .................................................................................................................. 448
32.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 499
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 544
34.0 Reference Clock Output Module .............................................................................................................................................. 572
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 576
36.0 Instruction Set Summary .......................................................................................................................................................... 578
37.0 Electrical Specifications............................................................................................................................................................ 592
38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 622
39.0 Development Support............................................................................................................................................................... 638
40.0 Packaging Information.............................................................................................................................................................. 642
Appendix A: Data Sheet Revision History ......................................................................................................................................... 665
2015-2018 Microchip Technology Inc. DS40001802F-page 15
PIC16(L)F18855/75
TO OUR VALUED CUSTOMERS
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2015-2018 Microchip Technology Inc. DS40001802F-page 16
PIC16(L)F18855/75
1.0 DEVICE OVERVIEW
The PIC16(L)F18855/75 are described within this data
sheet. The PIC16(L)F18855 devices are available in
28-pin SPDIP, SSOP, SOIC, and UQFN packages. The
PIC16(L)F18875 devices are available in 40-pin PDIP
and UQFN and 44-pin TQFP and QFN packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F18855/75 devices. Ta ble 1 - 2 and Table 1-3
show the pinout descriptions.
Reference Ta ble 1- 1 for peripherals available per device.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F18855
PIC16(L)F18855
Analog-to-Digital Converter with Computation (ADC2)●●
Cyclic Redundancy Check (CRC) ●●
Digital-to-Analog Converter (DAC) ●●
Fixed Voltage Reference (FVR) ●●
Enhanced Universal Synchronous/Asynchronous Receiver/
Transmitter (EUSART1)
●●
Digital Signal Modulator (DSM) ●●
Numerically Controlled Oscillator (NCO1) ●●
Temperature Indicator ●●
Zero-Cross Detect (ZCD) ●●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ●●
CCP2 ●●
CCP3 ●●
CCP4 ●●
CCP5 ●●
Comparators
C1 ●●
C2 ●●
Configurable Logic Cell (CLC)
CLC1 ●●
CLC2 ●●
CLC3 ●●
CLC4 ●●
Complementary Waveform Generator (CWG)
CWG1 ●●
CWG2 ●●
CWG3 ●●
Master Synchronous Serial Ports
MSSP1 ●●
MSSP2 ●●
Pulse-Width Modulator (PWM)
PWM6 ●●
PWM7 ●●
Signal Measure Timer (SMT)
SMT1 ●●
SMT2 ●●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
Timer3 ●●
Timer4 ●●
Timer5 ●●
Timer6 ●●
2015-2018 Microchip Technology Inc. DS40001802F-page 17
PIC16(L)F18855/75
1.1 Register and Bit naming
conventions
1.1.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.1.2 BIT NAMES
There are two variants for bit names:
Short name: Bit function abbreviation
Long name: Peripheral abbreviation + short name
1.1.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis-
ter can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly pro-
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.1.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
Example 2:
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
1.1.3 REGISTER AND BIT NAMING
EXCEPTIONS
1.1.3.1 Status, Interrupt, and Mirror Bits
Status, interrupt enables, interrupt flags, and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique so there is no prefix or short name variant.
1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
2015-2018 Microchip Technology Inc. DS40001802F-page 19
PIC16(L)F18855/75
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION
Name Function Input
Type Output Type Description
RA0/ANA0/C1IN0-/C2IN0-/CLCIN0(1)/
IOCA0
RA0 TTL/ST CMOS/OD General purpose I/O.
ANA0 AN ADC Channel A0 input.
C1IN0- AN Comparator negative input.
C2IN0- AN Comparator negative input.
CLCIN0(1) TTL/ST Configurable Logic Cell source input.
IOCA0 TTL/ST Interrupt-on-change input.
RA1/ANA1/C1IN1-/C2IN1-/CLCIN1(1)/
IOCA1
RA1 TTL/ST CMOS/OD General purpose I/O.
ANA1 AN ADC Channel A1 input.
C1IN1- AN Comparator negative input.
C2IN1- AN Comparator negative input.
CLCIN1(1) TTL/ST Configurable Logic Cell source input.
IOCA1 TTL/ST Interrupt-on-change input.
RA2/ANA2/C1IN0+/C2IN0+/VREF-/
DAC1OUT1/IOCA2
RA2 TTL/ST CMOS/OD General purpose I/O.
ANA2 AN ADC Channel A2 input.
C1IN0+ AN Comparator positive input.
C2IN0+ AN Comparator positive input.
VREF- AN External ADC and/or DAC negative reference input.
DAC1OUT1 AN Digital-to-Analog Converter output.
IOCA2 TTL/ST Interrupt-on-change input.
RA3/ANA3/C1IN1+/VREF+/MDCARL(1)/
IOCA3
RA3 TTL/ST CMOS/OD General purpose I/O.
ANA3 AN ADC Channel A3 input.
C1IN1+ AN Comparator positive input.
VREF+ AN External ADC and/or DAC positive reference input.
MDCARL(1) TTL/ST Modular Carrier input 1.
IOCA3 TTL/ST Interrupt-on-change input.
RA4/ANA4/MDCARH(1)/T0CKI(1)/
CCP5(1)/IOCA4
RA4 TTL/ST CMOS/OD General purpose I/O.
ANA4 AN ADC Channel A4 input.
MDCARH(1) TTL/ST Modular Carrier input 2.
T0CKI(1) TTL/ST Timer0 clock input.
CCP5(1) TTL/ST CMOS/OD Capture/compare/PWM5 (default input location for capture
function).
IOCA4 TTL/ST Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
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RA5/ANA5/SS1(1)/MDSRC(1)/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.
ANA5 AN ADC Channel A5 input.
SS1(1) TTL/ST MSSP1 SPI slave select input.
MDSRC(1) TTL/ST Modulator Source input.
IOCA5 TTL/ST Interrupt-on-change input.
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
ANA6 AN ADC Channel A6 input.
OSC2 XTAL External Crystal/Resonator (LP, XT, HS modes) driver output.
CLKOUT CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).
IOCA6 TTL/ST Interrupt-on-change input.
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
ANA7 AN ADC Channel A7 input.
OSC1 XTAL External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST External digital clock input.
IOCA7 TTL/ST Interrupt-on-change input.
RB0/ANB0/C2IN1+/ZCD/SS2(1)/
CCP4(1)/CWG1IN(1)/INT(1)/IOCB0
RB0 TTL/ST CMOS/OD General purpose I/O.
ANB0 AN ADC Channel B0 input.
C2IN1+ AN Comparator positive input.
ZCD AN AN Zero-cross detect input pin.
SS2(1) TTL/ST MSSP2 SPI slave select input.
CCP4(1) TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
function).
CWG1IN(1) TTL/ST Complementary Waveform Generator 1 input.
INT(1) TTL/ST External interrupt request input.
IOCB0 TTL/ST Interrupt-on-change input.
RB1/ANB1/C1IN3-/C2IN3-/SCL2(3,4)/
SCK2(1)/CWG2IN(1)/IOCB1
RB1 TTL/ST CMOS/OD General purpose I/O.
ANB1 AN ADC Channel B1 input.
C1IN3- AN Comparator negative input.
C2IN3- AN Comparator negative input.
SCL2(3,4) I2C/
SMBus
OD MSSP2 I2C clock input/output.
SCK2(1) TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a PPS
remappable input and output).
CWG2IN(1) TTL/ST Complementary Waveform Generator 2 input.
IOCB1 TTL/ST Interrupt-on-change input.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 21
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RB2/ANB2/SDA2(3,4)/SDI2(1)/
CWG3IN(1)/IOCB2
RB2 TTL/ST CMOS/OD General purpose I/O.
ANB2 AN ADC Channel B2 input.
SDA2(3,4) I2C/
SMBus
OD MSSP2 I2C serial data input/output.
SDI2(1) TTL/ST MSSP2 SPI serial data input.
CWG3IN(1) TTL/ST Complementary Waveform Generator 3 input.
IOCB2 TTL/ST Interrupt-on-change input.
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.
ANB3 AN ADC Channel B3 input.
C1IN2- AN Comparator negative input.
C2IN2- AN Comparator negative input.
IOCB3 TTL/ST Interrupt-on-change input.
RB4/ANB4/ADCACT(1)/T5G(1)/
SMTWIN2(1)/IOCB4
RB4 TTL/ST CMOS/OD General purpose I/O.
ANB4 AN ADC Channel B4 input.
ADCACT(1) TTL/ST ADC Auto-Conversion Trigger input.
T5G(1) TTL/ST Timer5 gate input.
SMTWIN2(1) TTL/ST Signal Measurement Timer 2 (SMT2) window input.
IOCB4 TTL/ST Interrupt-on-change input.
RB5/ANB5/T1G(1)/SMTSIG2(1)/
CCP3(1)/IOCB5
RB5 TTL/ST CMOS/OD General purpose I/O.
ANB5 AN ADC Channel B5 input.
T1G(1) TTL/ST Timer1 gate input.
SMTSIG2(1) TTL/ST Signal Measurement Timer 2 (SMT2) signal input.
CCP3(1) TTL/ST CMOS/OD Capture/compare/PWM3 (default input location for capture
function).
IOCB5 TTL/ST Interrupt-on-change input.
RB6/ANB6/CLCIN2(1)/IOCB6/ICSPCLK RB6 TTL/ST CMOS/OD General purpose I/O.
ANB6 AN ADC Channel B6 input.
CLCIN2(1) TTL/ST Configurable Logic Cell source input.
IOCB6 TTL/ST Interrupt-on-change input.
ICSPCLK ST In-Circuit Serial Programming™ and debugging clock input.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 22
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RB7/ANB7/DAC1OUT2/T6IN(1)/
CLCIN3(1)/IOCB7/ICSPDAT
RB7 TTL/ST CMOS/OD General purpose I/O.
ANB7 AN ADC Channel B7 input.
DAC1OUT2 AN Digital-to-Analog Converter output.
T6IN(1) TTL/ST Timer6 external digital clock input.
CLCIN3(1) TTL/ST Configurable Logic Cell source input.
IOCB7 TTL/ST Interrupt-on-change input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/out-
put.
RC0/ANC0/T1CKI(1)/T3CKI(1)/T3G(1)/
SMTWIN1(1)/IOCC0/SOSCO
RC0 TTL/ST CMOS/OD General purpose I/O.
ANC0 AN ADC Channel C0 input.
T1CKI(1) TTL/ST Timer1 external digital clock input.
T3CKI(1) TTL/ST Timer3 external digital clock input.
T3G(1) TTL/ST Timer3 gate input.
SMTWIN1(1) TTL/ST Signal Measurement Timer1 (SMT1) input.
IOCC0 TTL/ST Interrupt-on-change input.
SOSCO AN 32.768 kHz secondary oscillator crystal driver output.
RC1/ANC1/SMTSIG1(1)/CCP2(1)/
IOCC1/SOSCI
RC1 TTL/ST CMOS/OD General purpose I/O.
ANC1 AN ADC Channel C1 input.
SMTSIG1(1) TTL/ST Signal Measurement Timer1 (SMT1) signal input.
CCP2(1) TTL/ST CMOS/OD Capture/compare/PWM2 (default input location for capture
function).
IOCC1 TTL/ST Interrupt-on-change input.
SOSCI AN 32.768 kHz secondary oscillator crystal driver input.
RC2/ANC2/T5CKI(1)/CCP1(1)/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.
ANC2 AN ADC Channel C2 input.
T5CKI(1) TTL/ST Timer5 external digital clock input.
CCP1(1) TTL/ST CMOS/OD Capture/compare/PWM1 (default input location for capture
function).
IOCC2 TTL/ST Interrupt-on-change input.
RC3/ANC3/SCL1(3,4)/SCK1(1)/T2IN(1)/
IOCC3
RC3 TTL/ST CMOS/OD General purpose I/O.
ANC3 AN ADC Channel C3 input.
SCL1(3,4) I2C/
SMBus
OD MSSP1 I2C clock input/output.
SCK1(1) TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1 is a
PPS remappable input and output).
T2IN(1) TTL/ST Timer2 external input.
IOCC3 TTL/ST Interrupt-on-change input.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
MCLR
2015-2018 Microchip Technology Inc. DS40001802F-page 23
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RC4/ANC4/SDA1(3,4)/SDI1(1)/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.
ANC4 AN ADC Channel C4 input.
SDA1(3,4) I2C/
SMBus
OD MSSP1 I2C serial data input/output.
SDI1(1) TTL/ST MSSP1 SPI serial data input.
IOCC4 TTL/ST Interrupt-on-change input.
RC5/ANC5/T4IN(1)/IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.
ANC5 AN ADC Channel C5 input.
T4IN(1) TTL/ST Timer4 external input.
IOCC5 TTL/ST Interrupt-on-change input.
RC6/ANC6/CK(3)/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.
ANC6 AN ADC Channel C6 input.
CK(3) TTL/ST CMOS/OD EUSART synchronous mode clock input/output.
IOCC6 TTL/ST Interrupt-on-change input.
RC7/ANC7/RX(1)/DT(3)/IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
ANC7 AN ADC Channel C7 input.
RX(1) TTL/ST EUSART Asynchronous mode receiver data input.
DT(3) TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
IOCC7 TTL/ST Interrupt-on-change input.
RE3/IOCE3/MCLR/VPP RE3 TTL/ST General purpose input only (when MCLR is disabled by the
Configuration bit).
IOCE3 TTL/ST Interrupt-on-change input.
MCLR ST Master clear input with internal weak pull up resistor.
VPP HV ICSP™ High-Voltage Programming mode entry input.
VDD VDD Power Positive supply voltage input.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 24
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VSS VSS Power Ground reference.
OUT(2) ADGRDA CMOS/OD ADC Guard Ring A output.
ADGRDB CMOS/OD ADC Guard Ring B output.
C1OUT CMOS/OD Comparator 1 output.
C2OUT CMOS/OD Comparator 2 output.
SDO1 CMOS/OD MSSP1 SPI serial data output.
SCK1 CMOS/OD MSSP1 SPI serial clock output.
SDO2 CMOS/OD MSSP2 SPI serial data output.
SCK2 CMOS/OD MSSP2 SPI serial clock output.
TX CMOS/OD EUSART Asynchronous mode transmitter data output.
CK(3) CMOS/OD EUSART Synchronous mode clock output.
DT(3) CMOS/OD EUSART Synchronous mode data output.
DSM CMOS/OD Data Signal Modulator output.
TMR0 CMOS/OD Timer0 output.
CCP1 CMOS/OD Capture/Compare/PWM1 output (compare/PWM functions).
CCP2 CMOS/OD Capture/Compare/PWM2 output (compare/PWM functions).
CCP3 CMOS/OD Capture/Compare/PWM3 output (compare/PWM functions).
CCP4 CMOS/OD Capture/Compare/PWM4 output (compare/PWM functions).
CCP5 CMOS/OD Capture/Compare/PWM5 output (compare/PWM functions).
PWM6OUT CMOS/OD PWM6 output.
PWM7OUT CMOS/OD PWM7 output.
CWG1A CMOS/OD Complementary Waveform Generator 1 output A.
CWG1B CMOS/OD Complementary Waveform Generator 1 output B.
CWG1C CMOS/OD Complementary Waveform Generator 1 output C.
CWG1D CMOS/OD Complementary Waveform Generator 1 output D.
CWG2A CMOS/OD Complementary Waveform Generator 2 output A.
CWG2B CMOS/OD Complementary Waveform Generator 2 output B.
CWG2C CMOS/OD Complementary Waveform Generator 2 output C.
CWG2D CMOS/OD Complementary Waveform Generator 2 output D.
CWG3A CMOS/OD Complementary Waveform Generator 3 output A.
CWG3B CMOS/OD Complementary Waveform Generator 3 output B.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 25
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OUT(2) CWG3C CMOS/OD Complementary Waveform Generator 3 output C.
CWG3D CMOS/OD Complementary Waveform Generator 3 output D.
CLC1OUT CMOS/OD Configurable Logic Cell 1 output.
CLC2OUT CMOS/OD Configurable Logic Cell 2 output.
CLC3OUT CMOS/OD Configurable Logic Cell 3 output.
CLC4OUT CMOS/OD Configurable Logic Cell 4 output.
NCO1 CMOS/OD Numerically Controller Oscillator output.
CLKR CMOS/OD Clock Reference module output.
TABLE 1-2: PIC16F18855 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
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TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/ANA0/C1IN0-/C2IN0-/
CLCIN0(1)/IOCA0
RA0 TTL/ST CMOS/OD General purpose I/O.
ANA0 AN ADC Channel A0 input.
C1IN0- AN Comparator negative input.
C2IN0- AN Comparator negative input.
CLCIN0(1) TTL/ST Configurable Logic Cell source input.
IOCA0 TTL/ST Interrupt-on-change input.
RA1/ANA1/C1IN1-/C2IN1-/
CLCIN1(1)/IOCA1
RA1 TTL/ST CMOS/OD General purpose I/O.
ANA1 AN ADC Channel A1 input.
C1IN1- AN Comparator negative input.
C2IN1- AN Comparator negative input.
CLCIN1(1) TTL/ST Configurable Logic Cell source input.
IOCA1 TTL/ST Interrupt-on-change input.
RA2/ANA2/C1IN0+/C2IN0+/VREF-/
DAC1OUT1/IOCA2
RA2 TTL/ST CMOS/OD General purpose I/O.
ANA2 AN ADC Channel A2 input.
C1IN0+ AN Comparator positive input.
C2IN0+ AN Comparator positive input.
VREF- AN External ADC and/or DAC negative reference input.
DAC1OUT1 AN Digital-to-Analog Converter output.
IOCA2 TTL/ST Interrupt-on-change input.
RA3/ANA3/C1IN1+/VREF+/
MDCARL(1)/IOCA3
RA3 TTL/ST CMOS/OD General purpose I/O.
ANA3 AN ADC Channel A3 input.
C1IN1+ AN Comparator positive input.
VREF+ AN External ADC and/or DAC positive reference input.
MDCARL(1) TTL/ST Modular Carrier input 1.
IOCA3 TTL/ST Interrupt-on-change input.
RA4/ANA4/MDCARH(1)/T0CKI(1)/
CCP5(1)/IOCA4
RA4 TTL/ST CMOS/OD General purpose I/O.
ANA4 AN ADC Channel A4 input.
MDCARH(1) TTL/ST Modular Carrier input 2.
T0CKI(1) TTL/ST Timer0 clock input.
CCP5(1) TTL/ST CMOS/OD Capture/compare/PWM5 (default input location for capture
function).
IOCA4 TTL/ST Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
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RA5/ANA5/SS1(1)/MDSRC(1)/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.
ANA5 AN ADC Channel A5 input.
SS1(1) TTL/ST MSSP1 SPI slave select input.
MDSRC(1) TTL/ST Modulator Source input.
IOCA5 TTL/ST Interrupt-on-change input.
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
ANA6 AN ADC Channel A6 input.
OSC2 XTAL External Crystal/Resonator (LP, XT, HS modes) driver out-
put.
CLKOUT CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).
IOCA6 TTL/ST Interrupt-on-change input.
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
ANA7 AN ADC Channel A7 input.
OSC1 XTAL External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST External digital clock input.
IOCA7 TTL/ST Interrupt-on-change input.
RB0/ANB0/C2IN1+/ZCD/SS2(1)/
CCP4(1)/CWG1IN(1)/INT(1)/IOCB0
RB0 TTL/ST CMOS/OD General purpose I/O.
ANB0 AN ADC Channel B0 input.
C2IN1+ AN Comparator positive input.
ZCD AN AN Zero-cross detect input pin.
SS2(1) TTL/ST MSSP2 SPI slave select input.
CCP4(1) TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
function).
CWG1IN(1) TTL/ST Complementary Waveform Generator 1 input.
INT(1) TTL/ST External interrupt request input.
IOCB0 TTL/ST Interrupt-on-change input.
RB1/ANB1/C1IN3-/C2IN3-/SCL2(3,4)/
SCK2(1)/CWG2IN(1)/IOCB1
RB1 TTL/ST CMOS/OD General purpose I/O.
ANB1 AN ADC Channel B1 input.
C1IN3- AN Comparator negative input.
C2IN3- AN Comparator negative input.
SCL2(3,4) I2C/SMBus OD MSSP2 I2C clock input/output.
SCK2(1) TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a
PPS remappable input and output).
CWG2IN(1) TTL/ST Complementary Waveform Generator 2 input.
IOCB1 TTL/ST Interrupt-on-change input.
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 28
PIC16(L)F18855/75
RB2/ANB2/SDA2(3,4)/SDI2(1)/
CWG3IN(1)/IOCB2
RB2 TTL/ST CMOS/OD General purpose I/O.
ANB2 AN ADC Channel B2 input.
SDA2(3,4) I2C/SMBus OD MSSP2 I2C serial data input/output.
SDI2(1) TTL/ST MSSP2 SPI serial data input.
CWG3IN(1) TTL/ST Complementary Waveform Generator 3 input.
IOCB2 TTL/ST Interrupt-on-change input.
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.
ANB3 AN ADC Channel B3 input.
C1IN2- AN Comparator negative input.
C2IN2- AN Comparator negative input.
IOCB3 TTL/ST Interrupt-on-change input.
RB4/ANB4/ADCACT(1)/T5G(1)/
SMTWIN2(1)/IOCB4
RB4 TTL/ST CMOS/OD General purpose I/O.
ANB4 AN ADC Channel B4 input.
ADCACT(1) TTL/ST ADC Auto-Conversion Trigger input.
T5G(1) TTL/ST Timer5 gate input.
SMTWIN2(1) TTL/ST Signal Measurement Timer2 (SMT2) window input.
IOCB4 TTL/ST Interrupt-on-change input.
RB5/ANB5/T1G(1)/SMTSIG2(1)/
CCP3(1)/IOCB5
RB5 TTL/ST CMOS/OD General purpose I/O.
ANB5 AN ADC Channel B5 input.
T1G(1) TTL/ST Timer1 gate input.
SMTSIG2(1) TTL/ST Signal Measurement Timer2 (SMT2) signal input.
CCP3(1) TTL/ST CMOS/OD Capture/compare/PWM3 (default input location for capture
function).
IOCB5 TTL/ST Interrupt-on-change input.
RB6/ANB6/CLCIN2(1)/IOCB6/
ICSPCLK
RB6 TTL/ST CMOS/OD General purpose I/O.
ANB6 AN ADC Channel B6 input.
CLCIN2(1) TTL/ST Configurable Logic Cell source input.
IOCB6 TTL/ST Interrupt-on-change input.
ICSPCLK ST In-Circuit Serial Programming™ and debugging clock input.
RB7/ANB7/DAC1OUT2/T6IN(1)/
CLCIN3(1)/IOCB7/ICSPDAT
RB7 TTL/ST CMOS/OD General purpose I/O.
ANB7 AN ADC Channel B7 input.
DAC1OUT2 AN Digital-to-Analog Converter output.
T6IN(1) TTL/ST Timer6 external digital clock input.
CLCIN3(1) TTL/ST Configurable Logic Cell source input.
IOCB7 TTL/ST Interrupt-on-change input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/
output.
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 29
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RC0/ANC0/T1CKI(1)/T3CKI(1)/T3G(1)/
SMTWIN1(1)/IOCC0/SOSCO
RC0 TTL/ST CMOS/OD General purpose I/O.
ANC0 AN ADC Channel C0 input.
T1CKI(1) TTL/ST Timer1 external digital clock input.
T3CKI(1) TTL/ST Timer3 external digital clock input.
T3G(1) TTL/ST Timer3 gate input.
SMTWIN1(1) TTL/ST Signal Measurement Timer1 (SMT1) input.
IOCC0 TTL/ST Interrupt-on-change input.
SOSCO AN 32.768 kHz secondary oscillator crystal driver output.
RC1/ANC1/SMTSIG1(1)/CCP2(1)/
IOCC1/SOSCI
RC1 TTL/ST CMOS/OD General purpose I/O.
ANC1 AN ADC Channel C1 input.
SMTSIG1(1) TTL/ST Signal Measurement Timer1 (SMT1) signal input.
CCP2(1) TTL/ST CMOS/OD Capture/compare/PWM2 (default input location for capture
function).
IOCC1 TTL/ST Interrupt-on-change input.
SOSCI AN 32.768 kHz secondary oscillator crystal driver input.
RC2/ANC2/T5CKI(1)/CCP1(1)/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.
ANC2 AN ADC Channel C2 input.
T5CKI(1) TTL/ST Timer5 external digital clock input.
CCP1(1) TTL/ST CMOS/OD Capture/compare/PWM1 (default input location for capture
function).
IOCC2 TTL/ST Interrupt-on-change input.
RC3/ANC3/SCL1(3,4)/SCK1(1)/
T2IN(1)/IOCC3
RC3 TTL/ST CMOS/OD General purpose I/O.
ANC3 AN ADC Channel C3 input.
SCL1(3,4) I2C/SMBus OD MSSP1 I2C clock input/output.
SCK1(1) TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1
is a PPS remappable input and output).
T2IN(1) TTL/ST Timer2 external input.
IOCC3 TTL/ST Interrupt-on-change input.
RC4/ANC4/SDA1(3,4)/SDI1(1)/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.
ANC4 AN ADC Channel C4 input.
SDA1(3,4) I2C/SMBus OD MSSP1 I2C serial data input/output.
SDI1(1) TTL/ST MSSP1 SPI serial data input.
IOCC4 TTL/ST Interrupt-on-change input.
RC5/ANC5/T4IN(1)/IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.
ANC5 AN ADC Channel C5 input.
T4IN(1) TTL/ST Timer4 external input.
IOCC5 TTL/ST Interrupt-on-change input.
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
MCLR
2015-2018 Microchip Technology Inc. DS40001802F-page 30
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RC6/ANC6/CK(3)/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.
ANC6 AN ADC Channel C6 input.
CK(3) TTL/ST CMOS/OD EUSART synchronous mode clock input/output.
IOCC6 TTL/ST Interrupt-on-change input.
RC7/ANC7/RX(1)/DT(3)/IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
ANC7 AN ADC Channel C7 input.
RX(1) TTL/ST EUSART Asynchronous mode receiver data input.
DT(3) TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
IOCC7 TTL/ST Interrupt-on-change input.
RD0 RD0 TTL/ST CMOS/OD General purpose I/O.
AND0 AN ADC Channel D0 input.
RD1 RD1 TTL/ST CMOS/OD General purpose I/O.
AND1 AN ADC Channel D1 input.
RD2 RD2 TTL/ST CMOS/OD General purpose I/O.
AND2 AN ADC Channel D2 input.
RD3 RD3 TTL/ST CMOS/OD General purpose I/O.
AND3 AN ADC Channel D3 input.
RD4 RD4 TTL/ST CMOS/OD General purpose I/O.
AND4 AN ADC Channel D4 input.
RD5 RD5 TTL/ST CMOS/OD General purpose I/O.
AND5 AN ADC Channel D5 input.
RD6 RD6 TTL/ST CMOS/OD General purpose I/O.
AND6 AN ADC Channel D6 input.
RD7 RD7 TTL/ST CMOS/OD General purpose I/O.
AND7 AN ADC Channel D7 input.
RE0 RE0 TTL/ST CMOS/OD General purpose I/O.
ANE0 AN ADC Channel E0 input.
RE1 RE1 TTL/ST CMOS/OD General purpose I/O.
ANE1 AN ADC Channel E1 input.
RE2 RE2 TTL/ST CMOS/OD General purpose I/O.
ANE2 AN ADC Channel E2 input.
RE3/IOCE3/MCLR/VPP RE3 TTL/ST General purpose input-only (when MCLR is disabled by
config bit).
IOCE3 TTL/ST Interrupt-on-change input.
MCLR ST Master clear input with internal weak pull-up resistor.
VPP HV ICSP™ high voltage programming mode entry input.
VDD VDD Power Positive supply voltage input.
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 31
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VSS VSS Power Ground reference.
OUT(2) ADGRDA CMOS/OD ADC Guard Ring A output.
ADGRDB CMOS/OD ADC Guard Ring B output.
C1OUT CMOS/OD Comparator 1 output.
C2OUT CMOS/OD Comparator 2 output.
SDO1 CMOS/OD MSSP1 SPI serial data output.
SCK1 CMOS/OD MSSP1 SPI serial clock output.
SDO2 CMOS/OD MSSP2 SPI serial data output.
SCK2 CMOS/OD MSSP2 SPI serial clock output.
TX CMOS/OD EUSART Asynchronous mode transmitter data output.
CK(3) CMOS/OD EUSART Synchronous mode clock output.
DT(3) CMOS/OD EUSART Synchronous mode data output.
DSM CMOS/OD Data Signal Modulator output.
TMR0 CMOS/OD Timer0 output.
CCP1 CMOS/OD Capture/Compare/PWM1 output (compare/PWM functions).
CCP2 CMOS/OD Capture/Compare/PWM2 output (compare/PWM functions).
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
2015-2018 Microchip Technology Inc. DS40001802F-page 32
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OUT(2) CCP3 CMOS/OD Capture/Compare/PWM3 output (compare/PWM functions).
CCP4 CMOS/OD Capture/Compare/PWM4 output (compare/PWM functions).
CCP5 CMOS/OD Capture/Compare/PWM5 output (compare/PWM functions).
PWM6OUT CMOS/OD PWM6 output.
PWM7OUT CMOS/OD PWM7 output.
CWG1A CMOS/OD Complementary Waveform Generator 1 output A.
CWG1B CMOS/OD Complementary Waveform Generator 1 output B.
CWG1C CMOS/OD Complementary Waveform Generator 1 output C.
CWG1D CMOS/OD Complementary Waveform Generator 1 output D.
CWG2A CMOS/OD Complementary Waveform Generator 2 output A.
CWG2B CMOS/OD Complementary Waveform Generator 2 output B.
CWG2C CMOS/OD Complementary Waveform Generator 2 output C.
CWG2D CMOS/OD Complementary Waveform Generator 2 output D.
CWG3A CMOS/OD Complementary Waveform Generator 3 output A.
CWG3B CMOS/OD Complementary Waveform Generator 3 output B.
CWG3C CMOS/OD Complementary Waveform Generator 3 output C.
CWG3D CMOS/OD Complementary Waveform Generator 3 output D.
CLC1OUT CMOS/OD Configurable Logic Cell 1 output.
CLC2OUT CMOS/OD Configurable Logic Cell 2 output.
CLC3OUT CMOS/OD Configurable Logic Cell 3 output.
CLC4OUT CMOS/OD Configurable Logic Cell 4 output.
NCO CMOS/OD Numerically Controller Oscillator output.
CLKR CMOS/OD Clock Reference module output.
TABLE 1-3: PIC16F18875 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
in 4U :7/ 5% © a, 1% g: @ ® 5
2015-2018 Microchip Technology Inc. DS40001802F-page 33
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2.0 ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16-levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
Automatic Interrupt Context Saving
16-level Stack with Overflow and Underflow
File Select Registers
Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
12
Addr MUX
FSR reg
STATUS reg
MUX
ALU
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
VDD
8
8
Brown-out
Reset
12
3
VSS
Internal
Oscillator
Block
Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
Addr MUX
FSR reg
STATUS reg
MUX
ALU
W reg
Instruction
Decode &
Control
Timing
Generation
VDD
8
8
3
VSS
Internal
Oscillator
Block
15 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
16-Level Stack
(15-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR0 Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
VDD
8
8
3
VSS
Internal
Oscillator
Block
RAM
FSR regFSR reg
FSR1 Reg
15
15
MUX
15
Program Memory
Read (PMR)
12
FSR regFSR reg
BSR Reg
5
ConfigurationConfigurationConfiguration
Nonvolatile
Memory
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2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.
2.2 16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled, will
cause a software Reset. See Section 3.4 “Stack” for
more details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 36.0 “Instruction Set Summary” for more
details.
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3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
Program Memory
- Configuration Words
-Device ID
-User ID
- Program Flash Memory
Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
- Data EEPROM Memory
The following features are associated with access and
control of program memory and data memory:
PCL and PCLATH
•Stack
Indirect Addressing
NVMREG access
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 3-1).
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory Size (Words) Last Program Memory Address
PIC16(L)F18855/75 8192 1FFFh
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3.1.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, the older
table read method must be used because the BRW
instruction is not available in some devices.
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F18855/75
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
0000h
0004h
0005h
0FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
1000h
7FFFh
1FFFh
2000h
3FFFh
4000h
Rev. 10-000040H
8/23/2016
Unimplemented
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
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3.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The HIGH directive will set bit 7 if a label points to a
location in the program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
3.2 Data Memory Organization
The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 3-2):
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing”” for more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
3.2.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-12.
TABLE 3-2: CORE REGISTERS
constants
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
Dow (11
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3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
the arithmetic status of the ALU
the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (refer to Section 3.0 “Memory
Organization).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
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3.2.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.2.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2: BANKED MEMORY
PARTITIONING
3.2.5 DEVICE MEMORY MAPS
The memory maps are as shown in Tab l e 3-3 through
Table 3-13.
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
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TABLE 3-8: PIC16(L)F18855/75 MEMORY MAP, BANK 28
Bank 28
E0Ch
E0Dh
E0Eh
E0Fh CLCDATA
E10h CLC1CON
E11h CLC1POL
E12h CLC1SEL0
E13h CLC1SEL1
E14h CLC1SEL2
E15h CLC1SEL3
E16h CLC1GLS0
E17h CLC1GLS1
E18h CLC1GLS2
E19h CLC1GLS3
E1Ah CLC2CON
E1Bh CLC2POL
E1Ch CLC2SEL0
E1Dh CLC2SEL1
E1Eh CLC2SEL2
E1Fh CLC2SEL3
E20h CLC2GLS0
E21h CLC2GLS1
E22h CLC2GLS2
E23h CLC2GLS3
E24h CLC3CON
E25h CLC3POL
E26h CLC3SEL0
E27h CLC3SEL1
E28h CLC3SEL2
E29h CLC3SEL3
E2Ah CLC3GLS0
E2Bh CLC3GLS1
E2Ch CLC3GLS2
E2Dh CLC3GLS3
Legend: = Unimplemented data memory locations, read as ‘0’.
Bank 28
E2Eh CLC4CON
E2Fh CLC4POL
E30h CLC4SEL0
E31h CLC4SEL1
E32h CLC4SEL2
E33h CLC4SEL3
E34h CLC4GLS0
E35h CLC4GLS1
E36h CLC4GLS2
E37h CLC4GLS3
E38h
E6Fh
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TABLE 3-9: PIC16(L)F18855/75 MEMORY MAP, BANK 29
Bank 29
E8Ch
E8Dh
E8Eh
E8Fh PPSLOCK
E90h INTPPS
E91h T0CKIPPS
E92h T1CKIPPS
E93h T1GPPS
E94h T3CKIPPS
E95h T3GPPS
E96h T5CKIPPS
E97h T5GPPS
E98h
E99h
E9Ah
E9Bh
E9Ch T2AINPPS
E9Dh T4AINPPS
E9Eh T6AINPPS
E9Fh
EA0h
EA1h CCP1PPS
EA2h CCP2PPS
EA3h CCP3PPS
EA4h CCP4PPS
EA5h CCP5PPS
EA6h
EA7h
EA8h
EA9h SMT1WINPPS
EAAh SMT1SIGPPS
EABh SMT2WINPPS
EACh SMT2SIGPPS
EADh
EAEh
EAFh
EB0h
Legend: = Unimplemented data memory locations, read as ‘0’.
Bank 29
EB1h CWG1PPS
EB2h CWG2PPS
EB3h CWG3PPS
EB4h
EB5h
EB6h
EB7h
EB8h MDCARLPPS
EB9h MDCARHPPS
EBAh MDSRCPPS
EBBh CLCIN0PPS
EBCh CLCIN1PPS
EBDh CLCIN2PPS
EBEh CLCIN3PPS
EBFh
EC0h
EC1h
EC2h
EC3h ADCACTPPS
EC4h
EC5h SSP1CLKPPS
EC6h SSP1DATPPS
EC7h SSP1SSPPS
EC8h SSP2CLKPPS
EC9h SSP2DATPPS
ECAh SSP2SSPPS
ECBh RXPPS
ECCh TXPPS
ECDh
EEFh
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TABLE 3-10: PIC16(L)F18855 MEMORY MAP, BANK 30
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h RA0PPS
F11h RA1PPS
F12h RA2PPS
F13h RA3PPS
F14h RA4PPS
F15h RA5PPS
F16h RA6PPS
F17h RA7PPS
F18h RB0PPS
F19h RB1PPS
F1Ah RB2PPS
F1Bh RB3PPS
F1Ch RB4PPS
F1Dh RB5PPS
F1Eh RB6PPS
F1Fh RB7PPS
F20h RC0PPS
F21h RC1PPS
F22h RC2PPS
F23h RC3PPS
F24h RC4PPS
F25h RC5PPS
F26h RC6PPS
F27h RC7PPS
F28h
F37h
F38h ANSELA
F39h WPUA
F3Ah ODCONA
F3Bh SLRCONA
F3Ch INLVLA
F3Dh IOCAP
F3Eh IOCAN
F3Fh IOCAF
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Reserved, maintain as ‘0’.
Bank 30
F40h (1)
F41h (1)
F42h
F43h ANSELB
F44h WPUB
F45h ODCONB
F46h SLRCONB
F47h INLVLB
F48h IOCBP
F49h IOCBN
F4Ah IOCBF
F4Bh (1)
F4Ch (1)
F4Dh
F4Eh ANSELC
F4Fh WPUC
F50h ODCONC
F51h SLRCONC
F52h INLVLC
F53h IOCCP
F54h IOCCN
F55h IOCCF
F56h (1)
F57h (1)
F58h
F64h
F65h WPUE
F66h
F67h
F68h INLVLE
F69h IOCEP
F6Ah IOCEN
F6Bh IOCEF
F6Ch
F6Dh
F6Eh
F6Fh
Re
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TABLE 3-11: PIC16(L)F18875 MEMORY MAP, BANK 30
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Reserved, read as ‘0’.
Bank 30
F0Ch
F0Dh
F0Eh
F0Fh
F10h RA0PPS
F11h RA1PPS
F12h RA2PPS
F13h RA3PPS
F14h RA4PPS
F15h RA5PPS
F16h RA6PPS
F17h RA7PPS
F18h RB0PPS
F19h RB1PPS
F1Ah RB2PPS
F1Bh RB3PPS
F1Ch RB4PPS
F1Dh RB5PPS
F1Eh RB6PPS
F1Fh RB7PPS
F20h RC0PPS
F21h RC1PPS
F22h RC2PPS
F23h RC3PPS
F24h RC4PPS
F25h RC5PPS
F26h RC6PPS
F27h RC7PPS
F28h
F37h
F38h ANSELA
F39h WPUA
F3Ah ODCONA
F3Bh SLRCONA
F3Ch INLVLA
F3Dh IOCAP
F3Eh IOCAN
F3Fh IOCAF
Bank 30
F40h (1)
F41h (1)
F42h
F43h ANSELB
F44h WPUB
F45h ODCONB
F46h SLRCONB
F47h INLVLB
F48h IOCBP
F49h IOCBN
F4Ah IOCBF
F4Bh (1)
F4Ch (1)
F4Dh
F4Eh ANSELC
F4Fh WPUC
F50h ODCONC
F51h SLRCONC
F52h INLVLC
F53h IOCCP
F54h IOCCN
F55h IOCCF
F56h (1)
F57h (1)
F58h
F59h ANSELD
F5Ah WPUD
F5Bh ODCOND
F5Ch SLRCOND
F5Dh INLVLD
F5Eh
F5Fh
F60h
F61h (1)
F62h (1)
F63h
Bank 30
F64h ANSELE
F65h WPUE
F66h ODCONE
F67h SLRCONE
F68h INLVLE
F69h IOCEP
F6Ah IOCEN
F6Bh IOCEF
F6Ch (1)
F6Dh (1)
F6Eh
F6Fh
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TABLE 3-12: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (ALL BANKS)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
Resets
All Banks
000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a
physical register)
xxxx xxxx xxxx xxxx
001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a
physical register)
xxxx xxxx xxxx xxxx
002h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
003h STATUS — — —TOPD ZDCC---1 1000 ---q quuu
004h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
005h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
006h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
007h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
008h BSR — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
009h WREG Working Register 0000 0000 uuuu uuuu
00Ah PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
00Bh INTCON GIE PEIE — — — — —INTEDG00-- ---1 00-- ---1
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations
unimplemented, read as ‘0’.
Note 1: These Registers can be accessed from any bank