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Z8F640x/480x/320x/240x/160x Specification Datasheet by Zilog

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Product Specification
Z8F640x, Z8F480x, Z8F320x,
Z8F240x, and Z8F160x
Z8 Encore!
Microcontrollers
with Flash Memory and 10-Bit
A/D Converter
PS017610-0404
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Z W ZILDG 0m
PS017610-0404
This publication is subject to replacement by a later edition. To determine whether
a later edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other
products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered
by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of
Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the
express written approval of ZiLOG, use of information, devices, or technology as critical components
of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this
document under any intellectual property rights.
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
iii
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . 4
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
System and Short Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
iv
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stop Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . 29
Stop Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . 30
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port A-H Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port A-H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port A-H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A-H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Assertion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . 51
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . 52
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . 53
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Port Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
v
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 66
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . 67
Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . 69
Timer 0-3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . 73
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . 74
Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . 75
Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . 75
Watch-Dog Timer Reload Upper, High and Low Byte Registers . 76
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . 80
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . 81
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . 82
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . 82
Receiving Data using the Direct Memory Access
Controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Multiprocessor (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
UARTx Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
UARTx Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UARTx Status 0 and Status 1 Registers . . . . . . . . . . . . . . . . . . . . . 87
UARTx Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . 89
UARTx Baud Rate High and Low Byte Registers . . . . . . . . . . . . . 91
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
vi
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . 98
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . 102
Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . 110
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I
2
C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Writing a Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . 112
Writing a Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . 114
Reading a Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . 115
Reading a Transaction with a 10-Bit Address . . . . . . . . . . . . . . . 116
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . 121
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DMA0 and DMA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . 123
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
vii
DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . 124
DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DMAx Address High Nibble Register . . . . . . . . . . . . . . . . . . . . . 126
DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . 127
DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . 128
DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Flash Operation Timing Using the Flash Frequency Registers . . 141
Flash Code Protection Against External Access . . . . . . . . . . . . . . 141
Flash Code Protection Against Accidental Program and Erasure 141
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . 147
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
viii
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . 148
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . 149
Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . 150
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . 154
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Watchpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . 161
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
OCD Watchpoint Control Register . . . . . . . . . . . . . . . . . . . . . . . . 163
OCD Watchpoint Address Register . . . . . . . . . . . . . . . . . . . . . . . 164
OCD Watchpoint Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 164
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
20MHz Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . 173
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . 176
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . 177
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . 182
PS017610-0404 Table of Contents
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
ix
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
PS017610-0404 List of Figures
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xiv
List of Figures
Figure 1. Z8 Encore!
®
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8Fxx01 in 40-Pin Dual Inline Package (DIP) . . . . . . . . . . 7
Figure 3. Z8Fxx01 in 44-Pin Plastic Leaded Chip Carrier (PLCC) . . 8
Figure 4. Z8Fxx01 in 44-Pin Low-Profile Quad Flat Package (LQFP) 9
Figure 5. Z8Fxx02 in 64-Pin Low-Profile Quad Flat Package (LQFP) 10
Figure 6. Z8Fxx02 in 68-Pin Plastic Leaded Chip Carrier (PLCC) . 11
Figure 7. Z8Fxx03 in 80-Pin Quad Flat Package (QFP) . . . . . . . . . . 12
Figure 8. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . 28
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . 46
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 14. UART Asynchronous Data Format without Parity . . . . . . 80
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . 80
Figure 16. UART Asynchronous Multiprocessor (9-bit) Mode
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 17. Infrared Data Communication System Block Diagram . . . 95
Figure 18. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 19. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 20. SPI Configured as a Master in a Single Master,
Single Slave System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 21. SPI Configured as a Master in a Single Master,
Multiple Slave System . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 22. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 23. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . 103
Figure 24. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . 104
Figure 25. 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . 113
Figure 26. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . 114
Figure 27. Receive Data Transfer Format for a 7-Bit
Addressed Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 28. Receive Data Format for a 10-Bit Addressed Slave . . . . 116
Figure 29. Analog-to-Digital Converter Block Diagram . . . . . . . . . 133
Figure 30. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . 139
PS017610-0404 List of Figures
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xv
Figure 31. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . 140
Figure 32. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . 151
Figure 33. Interfacing the On-Chip Debugger’s DBG Pin with an
RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 34. Interfacing the On-Chip Debugger’s DBG Pin with an
RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 35. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 36. Recommended Crystal Oscillator Configuration
(20MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 37. Nominal ICC Versus System Clock Frequency . . . . . . . 170
Figure 38. Nominal Halt Mode ICC Versus System
Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 39. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 40. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 41. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 42. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 43. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 44. I
2
C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 45. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 46. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . 202
Figure 47. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 48. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . 205
Figure 49. 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . 206
Figure 50. 44-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . 207
Figure 51. 44-Lead Plastic Lead Chip Carrier Package (PLCC) . . . 207
Figure 52. 64-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . 208
Figure 53. 68-Lead Plastic Lead Chip Carrier Package (PLCC) . . . 209
Figure 54. 80-Lead Quad-Flat Package (QFP) . . . . . . . . . . . . . . . . . 210
PS017610-0404 List of Tables
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
x
List of Tables
Table 1. Z8F640x Family Part Selection Guide . . . . . . . . . . . . . . . . 2
Table 2. Z8F640x Family Package Options . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Pin Characteristics of the Z8F640x family . . . . . . . . . . . . 15
Table 5. Z8F640x Family Program Memory Maps . . . . . . . . . . . . . 18
Table 6. Z8F640x Family Data Memory Maps . . . . . . . . . . . . . . . . 19
Table 7. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Reset and STOP Mode Recovery Characteristics
and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . 26
Table 10. STOP Mode Recovery Sources and Resulting Action . . . 29
Table 11. Port Availability by Device and Package Type . . . . . . . . . 33
Table 12. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . 35
Table 13. Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . 37
Table 14. GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . 37
Table 15. Port A-H Control Registers (PxCTL) . . . . . . . . . . . . . . . . 38
Table 16. Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . 39
Table 17. Port A-H Alternate Function Sub-Registers . . . . . . . . . . . 39
Table 18. Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . 40
Table 19. Port A-H High Drive Enable Sub-Registers . . . . . . . . . . . 41
Table 20. Port A-H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . 42
Table 21. Port A-H STOP Mode Recovery Source Enable
Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . 43
Table 23. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . 45
Table 24. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . 48
Table 25. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . 49
Table 26. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . 50
Table 27. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 51
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . 51
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . 52
Table 30. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 52
Table 31. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . 53
PS017610-0404 List of Tables
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xi
Table 32. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . 53
Table 33. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . 53
Table 34. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . 54
Table 35. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . 54
Table 36. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . 55
Table 37. Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . 55
Table 38. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . 56
Table 39. Timer 0-3 High Byte Register (TxH) . . . . . . . . . . . . . . . . 67
Table 40. Timer 0-3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . 67
Table 41. Timer 0-3 Reload High Byte Register (TxRH) . . . . . . . . . 68
Table 42. Timer 0-3 Reload Low Byte Register (TxRL) . . . . . . . . . . 68
Table 43. Timer 0-3 PWM High Byte Register (TxPWMH) . . . . . . 69
Table 44. Timer 0-3 PWM Low Byte Register (TxPWML) . . . . . . . 69
Table 45. Timer 0-3 Control Register (TxCTL) . . . . . . . . . . . . . . . . 70
Table 46. Watch-Dog Timer Approximate Time-Out Delays . . . . . . 73
Table 47. Watch-Dog Timer Control Register (WDTCTL) . . . . . . . 75
Table 48. Watch-Dog Timer Reload Upper Byte Register (WDTU) 76
Table 49. Watch-Dog Timer Reload High Byte Register (WDTH) . 76
Table 50. Watch-Dog Timer Reload Low Byte Register (WDTL) . . 77
Table 51. UARTx Transmit Data Register (UxTXD) . . . . . . . . . . . . 86
Table 52. UARTx Receive Data Register (UxRXD) . . . . . . . . . . . . . 87
Table 53. UARTx Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . 87
Table 54. UARTx Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . 89
Table 55. UARTx Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . 89
Table 56. UARTx Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . 90
Table 57. UARTx Baud Rate High Byte Register (UxBRH) . . . . . . 91
Table 58. UARTx Baud Rate Low Byte Register (UxBRL) . . . . . . . 92
Table 59. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 60. SPI Clock Phase (PHASE) and Clock Polarity
(CLKPOL) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 61. SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . 106
Table 62. SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . 107
Table 63. SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . 108
Table 64. SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . 109
Table 65. SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . 110
Table 66. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . 110
PS017610-0404 List of Tables
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xii
Table 67. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . 118
Table 68. I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . 118
Table 69. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . 119
Table 70. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . 121
Table 71. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . 121
Table 72. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . 124
Table 73. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . 126
Table 74. DMAx Address High Nibble Register (DMAxH) . . . . . . 126
Table 75. DMAx End Address Low Byte Register (DMAxEND) . 128
Table 76. DMAx Start/Current Address Low Byte Register
(DMAxSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 77. DMA_ADC Register File Address Example . . . . . . . . . . 129
Table 78. DMA_ADC Address Register (DMAA_ADDR) . . . . . . 129
Table 79. DMA_ADC Control Register (DMAACTL) . . . . . . . . . . 130
Table 80. DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . 131
Table 81. ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . 135
Table 82. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . 137
Table 83. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . 137
Table 84. Z8F640x family Flash Memory Configurations . . . . . . . 138
Table 85. Flash Code Protection Using the Option Bits . . . . . . . . . 142
Table 86. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . 144
Table 87. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . 145
Table 88. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . 146
Table 89. Flash Frequency High Byte Register (FFREQH) . . . . . . 147
Table 90. Flash Frequency Low Byte Register (FFREQL) . . . . . . . 147
Table 91. Option Bits At Program Memory Address 0000H . . . . . 149
Table 92. Options Bits at Program Memory Address 0001H . . . . . 150
Table 93. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 94. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . 156
Table 95. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . 161
Table 96. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . 162
Table 97. OCD Watchpoint Control/Address (WPTCTL) . . . . . . . 163
Table 98. OCD Watchpoint Address (WPTADDR) . . . . . . . . . . . . 164
Table 99. OCD Watchpoint Data (WPTDATA) . . . . . . . . . . . . . . . 164
Table 100. Recommended Crystal Oscillator Specifications
(20MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
PS017610-0404 List of Tables
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xiii
Table 101. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 167
Table 102. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 103. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 104. Power-On Reset and Voltage Brown-Out Electrical
Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . 173
Table 105. Flash Memory Electrical Characteristics and Timing . . . 173
Table 106. Watch-Dog Timer Electrical Characteristics and Timing 174
Table 107. Analog-to-Digital Converter Electrical Characteristics
and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 108. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 109. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 110. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . 178
Table 111. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 112. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 113. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 114. Assembly Language Syntax Example 1 . . . . . . . . . . . . . 183
Table 115. Assembly Language Syntax Example 2 . . . . . . . . . . . . . 183
Table 116. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 117. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 118. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 119. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 120. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . 188
Table 121. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . 188
Table 122. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 123. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 124. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 125. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . 190
Table 126. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . 191
Table 127. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . 191
Table 128. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . 203
Table 129. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
PS017610-0404 Manual Objectives
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xvi
Manual Objectives
This Product Specification provides detailed operating information for the Z8F640x,
Z8F480x, Z8F320x, Z8F240x, and Z8F160x devices within the Z8 Encore!
TM
Microcon-
troller (MCU) family of products. Within this document, the Z8F640x, Z8F480x,
Z8F320x, Z8F240x, and Z8F160x are referred to collectively as Z8 Encore!
TM
or the
Z8F640x family unless specifically stated otherwise.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before
setting up and using the product. However, we recognize that there are different styles of
learning. Therefore, we have designed this Product Specification to be used either as a
how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with
microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Courier typeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is pre-
sented in upper case.
Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
Example: R1 is set to F8H.
Brackets
The square brackets, [ ], indicate a register or bus.
Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant
bit, and R1[0] is the least significant bit.
PS017610-0404 Manual Objectives
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xvii
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some com-
bination of smaller registers, buses, or individual bits.
Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the
contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical may not be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least sig-
nificant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text.
Example 1: Stop mode.
Example 2: The receiver forces the SCL line to Low.
The Master can generate a Stop condition to abort the transfer.
ZiLOé; Inc.
PS017610-0404 Manual Objectives
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
xviii
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states and commands.
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization sequence.
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that all users understand the following safety terms, which are defined here.
Indicates a procedure or file may become corrupted if the user does not fol-
low directions.
Trademarks
ZiLOG, eZ8, Z8 Encore!, and Z8 are trademarks of ZiLOG, Inc. in the U.S.A. and other
countries. All other trademarks are the property of their respective corporations.
Caution:
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
PS017610-0404 Introduction
1
Introduction
The Z8 Encore!
®
MCU family of products are the first in a line of ZiLOG microcontroller
products based upon the new 8-bit eZ8 CPU. The Z8F640x/Z8F480x/Z8F320x/Z8F240x/
Z8F160x products are referred to collectively as either Z8 Encore!
®
or the Z8F640x fam-
ily. The Z8F640x family of products introduce Flash memory to ZiLOG’s extensive line
of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster
development time and program changes in the field. The new eZ8 CPU is upward compat-
ible with existing Z8 instructions. The rich peripheral set of the Z8F640x family makes it
suitable for a variety of applications including motor control, security systems, home
appliances, personal electronic devices, and sensors.
Features
eZ8 CPU, 20 MHz operation
12-channel, 10-bit analog-to-digital converter (ADC)
3-channel DMA
Up to 64KB Flash memory with in-circuit programming capability
Up to 4KB register RAM
Serial communication protocols
Serial Peripheral Interface
–I
2
C
Two full-duplex 9-bit UARTs
24 interrupts with programmable priority
Three or four 16-bit timers with capture, compare, and PWM capability
Single-pin On-Chip Debugger
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders integrated
with the UARTs
Watch-Dog Timer (WDT) with internal RC oscillator
Up to 60 I/O pins
Voltage Brown-out Protection (VBO)
PS017610-0404 Introduction
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
2
Power-On Reset (POR)
3.0-3.6V operating voltage with 5V-tolerant inputs
0° to +70°C standard temperature and -40° to +105°C extended temperature operating
ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8F640x family product line.
Table 1. Z8F640x Family Part Selection Guide
Part
Number Flash
(KB) RAM
(KB) I/O 16-bit Timers
with PWM ADC
Inputs UARTs
with IrDA I
2
CSPI40/44-pin
packages 64/68-pin
packages 80-pin
package
Z8F1601 16 2 31 3 8 2 1 1 X
Z8F1602 16 2 46 4 12 2 1 1 X
Z8F2401 24 2 31 3 8 2 1 1 X
Z8F2402 24 2 46 4 12 2 1 1 X
Z8F3201 32 2 31 3 8 2 1 1 X
Z8F3202 32 2 46 4 12 2 1 1 X
Z8F4801 48 4 31 3 8 2 1 1 X
Z8F4802 48 4 46 4 12 2 1 1 X
Z8F4803 48 4 60 4 12 2 1 1 X
Z8F6401 64 4 31 3 8 2 1 1 X
Z8F6402 64 4 46 4 12 2 1 1 X
Z8F6403 64 4 60 4 12 2 1 1 X
WW < w”="" r="" ,="" 4="" '="" ltv="" t,="" ¢¢¢¢="" hm="" ljwh="" h="" ¢="" :="">
PS017610-0404 Introduction
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
3
Block Diagram
Figure 55 illustrates the block diagram of the architecture of the Z8 Encore!
TM.
Figure 55. Z8 Encore!
®
Block Diagram
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8, ZiLOG’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8 instruction set. The eZ8 CPU features include:
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory
GPIO
IrDA
UARTs I
2
CTimers SPI ADC
Flash
Flash
Controller
RAM
RAM
Controller
Memory
Interrupt
Controller
On-Chip
Debugger
eZ8
CPU WDT with
RC Oscillator
POR/VBO
& Reset
Controller
XTAL / RC
Oscillator
Register Bus
Memory Busses
System
Clock
DMA
Z ww zilog om
PS017610-0404 Introduction
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
4
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail-
able for download at www.zilog.com.
General Purpose I/O
The Z8 Encore!
®
features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for
general purpose I/O (GPIO). Each pin is individually programmable.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes and selectable parity.
I
2
C
The inter-integrated circuit (I
2
C
®
) controller makes the Z8 Encore!
®
compatible with the
I
2
C protocol. The I
2
C controller consists of two bidirectional bus lines, a serial data (SDA)
line and a serial clock (SCL) line.
PS017610-0404 Introduction
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
5
Serial Peripheral Interface
The serial peripheral interface (SPI) allows the Z8 Encore!
®
to exchange data between
other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is
a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and oper-
ate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM
modes. Only 3 timers (Timers 0-2) are available in the 40- and 44-pin packages.
Interrupt Controller
The Z8F640x family products support up to 24 interrupts. These interrupts consist of 12
internal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable
interrupt priority.
Reset Controller
The Z8F640x family can be reset using the RESET pin, power-on reset, Watch-Dog Timer
(WDT), Stop mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore!
®
features an integrated On-Chip Debugger (OCD). The OCD provides a
rich set of debugging capabilities, such as reading and writing registers, programming the
Flash, setting breakpoints and executing code. A single-pin interface provides communi-
cation to the OCD.
DMA Controller
The Z8F640x family features three channels of DMA. Two of the channels are for register
RAM to and from I/O operations. The third channel automatically controls the transfer of
data from the ADC to the memory.
ZiLOG
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
PS017610-0404 Signal and Pin Descriptions
6
Signal and Pin Descriptions
Overview
The Z8F640x family products are available in a variety of packages styles and pin config-
urations. This chapter describes the signals and available pin configurations for each of the
package styles. For information regarding the physical package specifications, please refer
to the chapter Packaging on page 206.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8F640x
family product line.
Table 2. Z8F640x family Package Options
Part Number 40-pin
PDIP 44-pin
LQFP 44-pin
PLCC 64-pin
LQFP 68-pin
PLCC 80-pin
QFP
Z8F1601 XXX
Z8F1602 X X
Z8F2401 XXX
Z8F2402 X X
Z8F3201 XXX
Z8F3202 X X
Z8F4801 XXX
Z8F4802 X X
Z8F4803 X
Z8F6401 XXX
Z8F6402 X X
Z8F6403 X
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
7
Pin Configurations
Figures 56 through 61 illustrate the pin configurations for all of the packages available in
the Z8 Encore!
®
MCU family. Refer to Table 2 for a description of the signals.
Figure 56. Z8Fxx01 in 40-Pin Dual Inline Package (DIP)
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
PD4/RXD1
PD3
PC5 / MISO
PA3 / CTS0
PA2
PA1 / T0OUT
PA0 / T0IN
PC2 / SS
140
VDD
RESET
PC6 / T2IN *
DBG
PC1 / T1OUT
VSS
PD1
PD0
PC0 / T1INXOUT
AVSSXIN
VREFAVDD
PB2 / ANA2
PB3 / ANA3
PB7 / ANA7
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
20 21 PB6 / ANA6PB5 / ANA5
5
10
15
35
30
25
VDD
* T2OUT is not supported.
Note: Timer 3 is not supported.
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
8
Figure 57. Z8Fxx01 in 44-Pin Plastic Leaded Chip Carrier (PLCC)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
VDD
VSS
PC7 / T2OUT
PC6 / T2IN
DBG
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
VSS
VDD
PD1
PD0
739
PC1 / T1OUT
XOUT
PC0 / T1IN
XIN
PA1 / T0OUT
PA2
PA3 / CTS0
PC5 / MISO
PD3
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
AVDD
PB6 / ANA6
PB5 / ANA5
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB7 / ANA7
VREF
PB2 / ANA2
PB3 / ANA3
AVSS
6401
17 29
2818
12
23
34
Note: Timer 3 is not supported.
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
9
Figure 58. Z8Fxx01 in 44-Pin Low-Profile Quad Flat Package (LQFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
VDD
VSS
PC7 / T2OUT
PC6 / T2IN
DBG
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
VSS
VDD
PD1
PD0
34 22
PC1 / T1OUT
XOUT
PC0 / T1IN
XIN
PA1 / T0OUT
PA2
PA3 / CTS0
PC5 / MISO
PD3
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
AVDD
PB6 / ANA6
PB5 / ANA5
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB7 / ANA7
VREF
PB2 / ANA2
PB3 / ANA3
AVSS
33 23
44 12
111
28
39 17
6
Note: Timer 3 is not supported.
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
10
Figure 59. Z8Fxx02 in 64-Pin Low-Profile Quad Flat Package (LQFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
PE7
VDD
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
PE4
PE3
VSS
PE2
49 32
PG3PE1
VDD
PE0
PA1 / T0OUT
PA2
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PH1 / ANA9
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
48
1
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
17
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
16
VSS
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN 64
PD3
VDD
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
33
VSS
56
40
25
8
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
11
Figure 60. Z8Fxx02 in 68-Pin Plastic Leaded Chip Carrier (PLCC)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
PE7
VDD
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
PE4
PE3
VSS
PE2
10 60
PG3PE1
VDD
PE0
PA1 / T0OUT
PA2
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
9
27
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
VSS
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
PD3
VSS
PA4 / RXD0
PA5 / TXD0
VDD
PH1 / ANA9
PA6 / SCL
61
VSS
44
AVSS
43
XIN 26
1
VDD
18
35
52
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
12
Figure 61. Z8Fxx03 in 80-Pin Quad Flat Package (QFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
PG0
VSS
PG1
PG2
PE5
PA0 / T0IN
PD2
PC2 / SS
PF6
RESET
VDD
PF5
PF4
PF3
164
PE6PE4
PE7
PE3
PA1 / T0OUT
PA2
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4/MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
80
25
VDD
PG3
PG4
PG5
PG6
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
VSS
PE2
PE1
PE0
VSS
PD3
VDD
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
VSS
PH1 / ANA9
65
VDD
40
PF2
PG7
PF1
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
PF0
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
VSS
41
XIN 24
5
10
15
20
30 35
45
50
55
60
70
75
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
13
Signal Descriptions
Table 2 describes the Z8F640x family signals. Refer to the section Pin Configurations on
page 7 to determine the signals available for the specific package styles.
Table 2. Signal Descriptions
Signal Mnemonic I/O Description
General-Purpose I/O Ports A-H
PA[7:0] I/O Port A[7:0]. These pins are used for general-purpose I/O.
PB[7:0] I/O Port B[7:0]. These pins are used for general-purpose I/O.
PC[7:0] I/O Port C[7:0]. These pins are used for general-purpose I/O.
PD[7:0] I/O Port D[7:0]. These pins are used for general-purpose I/O.
PE[7:0] I/O Port E[7:0]. These pins are used for general-purpose I/O.
PF[7:0] I/O Port F[7:0]. These pins are used for general-purpose I/O.
PG[7:0] I/O Port G[7:0]. These pins are used for general-purpose I/O.
PH[3:0] I/O Port H[3:0]. These pins are used for general-purpose I/O.
I
2
C Controller
SCL O Serial Clock. This is the output clock for the I
2
C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA I/O Serial Data. This open-drain pin is used to transfer data between the I
2
C and a
slave. This pin is multiplexed with a general-purpose I/O pin. When the general-
purpose I/O pin is configured for alternate function to enable the SDA function,
this pin is open-drain.
SPI Controller
SS I/O Slave Select. This signal can be an output or an input. If the Z8 Encore! is the SPI
master, this pin may be configured as the Slave Select output. If the Z8 Encore! is
the SPI slave, this pin is the input slave select. It is multiplexed with a general-
purpose I/O pin.
SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! is the SPI
master, this pin is an output. If the Z8 Encore! is the SPI slave, this pin is an
input. It is multiplexed with a general-purpose I/O pin.
MOSI I/O Master Out Slave In. This signal is the data output from the SPI master device and
the data input to the SPI slave device. It is multiplexed with a general-purpose I/O
pin.
MISO I/O Master In Slave Out. This pin is the data input to the SPI master device and the
data output from the SPI slave device. It is multiplexed with a general-purpose I/O
pin.
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
14
UART Controllers
TXD0 / TXD1 O Transmit Data. These signals are the transmit outputs from the UARTs. The TXD
signals are multiplexed with general-purpose I/O pins.
RXD0 / RXD1 I Receive Data. These signals are the receiver inputs for the UARTs and IrDAs. The
RXD signals are multiplexed with general-purpose I/O pins.
CTS0 / CTS1 I Clear To Send. These signals are control inputs for the UARTs. The CTS signals
are multiplexed with general-purpose I/O pins.
Timers (Timer 3 is unavailable in the 40-and 44-pin packages)
T0OUT / T1OUT/
T2OUT / T3OUT O Timer Output 0-3. These signals are output pins from the timers. The Timer
Output signals are multiplexed with general-purpose I/O pins. T2OUT is not
supported in the 40-pin package. T3OUT is not supported in the 40- and 44-pin
packages.
T0IN / T1IN/
T2IN / T3IN I Timer Input 0-3. These signals are used as the capture, gating and counter inputs.
The Timer Input signals are multiplexed with general-purpose I/O pins. T3IN is
not supported in the 40- and 44-pin packages.
Analog
ANA[11:0] I Analog Input. These signals are inputs to the analog-to-digital converter (ADC).
The ADC analog inputs are multiplexed with general-purpose I/O pins.
VREF I Analog-to-digital converter reference voltage input. The VREF pin should be left
unconnected (or capacitively coupled to analog ground) if the internal voltage
reference is selected as the ADC reference voltage.
Oscillators
XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can
be connected between it and the XOUT pin to form the oscillator.
XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal
can be connected between it and the XIN pin to form the oscillator. When the
system clock is referred to in this manual, it refers to the frequency of the signal at
this pin.
RCOUT O RC Oscillator Output. This signal is the output of the RC oscillator. It is
multiplexed with a general-purpose I/O pin.
On-Chip Debugger
DBG I/O Debug. This pin is the control and data input and output to and from the On-Chip
Debugger. For operation of the On-chip debugger, all power pins (V
DD
and AV
DD
must be supplied with power, and all ground pins (V
SS
and AV
SS
must be
grounded. This pin is open-drain and must have an external pull-up resistor to
ensure proper operation.
Table 2. Signal Descriptions (Continued)
Signal Mnemonic I/O Description
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
15
Pin Characteristics
Table 3 provides detailed information on the characteristics for each pin available on the
Z8F640x family products. Data in Table 3 is sorted alphabetically by the pin symbol mne-
monic.
Reset
RESET I RESET. Generates a Reset when asserted (driven Low).
Power Supply
VDD I Power Supply.
AVDD I Analog Power Supply.
VSS I Ground.
AVSS I Analog Ground.
Table 3. Pin Characteristics of the Z8F640x family
Symbol
Mnemonic Direction Reset
Direction
Active Low
or
Active High Tri-State
Output
Internal
Pull-up or
Pull-down
Schmitt
Trigger
Input Open Drain
Output
AVSS N/A N/A N/A N/A No No N/A
AVDD N/A N/A N/A N/A No No N/A
DBG I/O I N/A Yes No Yes Yes
VSS N/A N/A N/A N/A No No N/A
PA[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PB[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PC[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PD[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PE7:0] I/O I N/A Yes No Yes Yes,
Programmable
x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer
Table 2. Signal Descriptions (Continued)
Signal Mnemonic I/O Description
PS017610-0404 Signal and Pin Descriptions
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
16
PF[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PG[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PH[3:0] I/O I N/A Yes No Yes Yes,
Programmable
RESET I I Low N/A Pull-up Yes N/A
VDD N/A N/A N/A N/A No No N/A
XIN I I N/A N/A No No N/A
XOUT O O N/A Yes, in
Stop mode No No No
Table 3. Pin Characteristics of the Z8F640x family
Symbol
Mnemonic Direction Reset
Direction
Active Low
or
Active High Tri-State
Output
Internal
Pull-up or
Pull-down
Schmitt
Trigger
Input Open Drain
Output
x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer
ZiLOG
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
PS017610-0404 Address Space
17
Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable
code and/or data.
The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore!
®
is 4KB (4096 bytes). The Register File
is composed of two sections—control registers and general-purpose registers. When
instructions are executed, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not recom-
mended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
Z8F640x family products contain 2KB to 4KB of on-chip RAM depending upon the
device. Reading from Register File addresses outside the available RAM addresses (and
not within in the control register address space) returns an undefined value. Writing to
these Register File addresses produces no effect. Refer to the Part Selection Guide sec-
tion of the Introduction chapter to determine the amount of RAM available for the spe-
cific Z8F640x family device.
PS017610-0404 Address Space
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
18
Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8F640x family
devices contain 16KB to 64KB of on-chip Flash memory in the Program Memory address
space. Reading from Program Memory addresses outside the available Flash memory
addresses returns FFH. Writing to these unemployments Program Memory addresses pro-
duces no effect. Table 4 describes the Program Memory Maps for the Z8F640x family
products.
Table 4. Z8F640x Family Program Memory Maps
Program Memory Address (Hex) Function
Z8F160x Products
0000-0001 Flash Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-3FFFH Program Memory
Z8F240x Products
0000-0001 Flash Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-5FFFH Program Memory
Z8F320x Products
0000-0001 Flash Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-7FFFH Program Memory
* See Table 22 on page 45 for a list of the interrupt vectors.
PS017610-0404 Address Space
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
19
Data Memory
The Z8F640x family devices contain 128 bytes of read-only memory at the top of the eZ8
CPU’s 64KB Data Memory address space. The eZ8 CPU’s LDE and LDEI instructions
provide access to the Data Memory information. Table 5 describes the Z8F640x family’s
Data Memory Map.
Z8F480x Products
0000-0001 Flash Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-BFFFH Program Memory
Z8F640x Products
0000-0001 Flash Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-FFFFH Program Memory
Table 5. Z8F640x family Data Memory Maps
Data Memory Address (Hex) Function
0000H-FFBFH Reserved
FFC0H-FFD3H Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FFD4H-FFFFH Reserved
Table 4. Z8F640x Family Program Memory Maps (Continued)
Program Memory Address (Hex) Function
* See Table 22 on page 45 for a list of the interrupt vectors.
ZiLOG
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
PS017610-0404 Register File Address Map
20
Register File Address Map
Table 6 provides the address map for the Register File of the Z8F640x family of products.
Not all devices and package styles in the Z8F640x family support Timer 3 and all of the
GPIO Ports. Consider registers for unimplemented peripherals as Reserved.
Table 6. Register File Address Map
Address (Hex) Register Description Mnemonic Reset (Hex) Page #
General Purpose RAM
000-EFF General-Purpose Register File RAM XX
Timer 0
F00 Timer 0 High Byte T0H 00 66
F01 Timer 0 Low Byte T0L 01 66
F02 Timer 0 Reload High Byte T0RH FF 67
F03 Timer 0 Reload Low Byte T0RL FF 67
F04 Timer 0 PWM High Byte T0PWMH 00 69
F05 Timer 0 PWM Low Byte T0PWML 00 69
F06 Reserved — XX
F07 Timer 0 Control T0CTL 00 70
Timer 1
F08 Timer 1 High Byte T1H 00 66
F09 Timer 1 Low Byte T1L 01 66
F0A Timer 1 Reload High Byte T1RH FF 67
F0B Timer 1 Reload Low Byte T1RL FF 67
F0C Timer 1 PWM High Byte T1PWMH 00 69
F0D Timer 1 PWM Low Byte T1PWML 00 69
F0E Reserved — XX
F0F Timer 1 Control T1CTL 00 70
Timer 2
F10 Timer 2 High Byte T2H 00 66
F11 Timer 2 Low Byte T2L 01 66
F12 Timer 2 Reload High Byte T2RH FF 67
F13 Timer 2 Reload Low Byte T2RL FF 67
F14 Timer 2 PWM High Byte T2PWMH 00 69
F15 Timer 2 PWM Low Byte T2PWML 00 69
F16 Reserved — XX
F17 Timer 2 Control T2CTL 00 70
XX=Undefined
PS017610-0404 Register File Address Map
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
21
Timer 3 (not available in 40- and 44- Pin Packages)
F18 Timer 3 High Byte T3H 00 66
F19 Timer 3 Low Byte T3L 01 66
F1A Timer 3 Reload High Byte T3RH FF 67
F1B Timer 3 Reload Low Byte T3RL FF 67
F1C Timer 3 PWM High Byte T3PWMH 00 69
F1D Timer 3 PWM Low Byte T3PWML 00 69
F1E Reserved — XX
F1F Timer 3 Control T3CTL 00 70
F20-F3F Reserved XX
UART 0
F40 UART0 Transmit Data U0TXD XX 86
UART0 Receive Data U0RXD XX 87
F41 UART0 Status 0 U0STAT0 0000011Xb 87
F42 UART0 Control 0 U0CTL0 00 89
F43 UART0 Control 1 U0CTL1 00 89
F44 UART0 Status 1 U0STAT1 00 87
F45 Reserved — XX
F46 UART0 Baud Rate High Byte U0BRH FF 91
F47 UART0 Baud Rate Low Byte U0BRL FF 91
UART 1
F48 UART1 Transmit Data U1TXD XX 86
UART1 Receive Data U1RXD XX 87
F49 UART1 Status 0 U1STAT0 0000011Xb 87
F4A UART1 Control 0 U1CTL0 00 89
F4B UART1 Control 1 U1CTL1 00 89
F4C UART1 Status 1 U1STAT1 00 87
F4D Reserved XX
F4E UART1 Baud Rate High Byte U1BRH FF 91
F4F UART1 Baud Rate Low Byte U1BRL FF 91
I
2
C
F50 I
2
C Data I2CDATA 00 118
F51 I
2
C Status I2CSTAT 80 118
F52 I
2
C Control I2CCTL 00 119
F53 I
2
C Baud Rate High Byte I2CBRH FF 121
F54 I
2
C Baud Rate Low Byte I2CBRL FF 121
F55-F5F Reserved XX
Serial Peripheral Interface (SPI)
F60 SPI Data SPIDATA XX 106
F61 SPI Control SPICTL 00 107
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page #
XX=Undefined
PS017610-0404 Register File Address Map
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
22
F62 SPI Status SPISTAT 01 108
F63 SPI Mode SPIMODE 00 109
F64-F65 Reserved XX
F66 SPI Baud Rate High Byte SPIBRH FF 110
F67 SPI Baud Rate Low Byte SPIBRL FF 110
F68-F69 Reserved XX
Analog-to-Digital Converter (ADC)
F70 ADC Control ADCCTL 20 135
F71 Reserved — XX
F72 ADC Data High Byte ADCD_H XX 137
F73 ADC Data Low Bits ADCD_L XX 137
F74-FAF Reserved XX
DMA 0
FB0 DMA0 Control DMA0CTL 00 124
FB1 DMA0 I/O Address DMA0IO XX 125
FB2 DMA0 End/Start Address High Nibble DMA0H XX 126
FB3 DMA0 Start Address Low Byte DMA0START XX 127
FB4 DMA0 End Address Low Byte DMA0END XX 128
DMA 1
FB8 DMA1 Control DMA1CTL 00 124
FB9 DMA1 I/O Address DMA1IO XX 125
FBA DMA1 End/Start Address High Nibble DMA1H XX 126
FBB DMA1 Start Address Low Byte DMA1START XX 127
FBC DMA1 End Address Low Byte DMA1END XX 128
DMA ADC
FBD DMA_ADC Address DMAA_ADDR XX 128
FBE DMA_ADC Control DMAACTL 00 130
FBF DMA_ADC Status DMAASTAT 00 131
Interrupt Controller
FC0 Interrupt Request 0 IRQ0 00 48
FC1 IRQ0 Enable High Bit IRQ0ENH 00 51
FC2 IRQ0 Enable Low Bit IRQ0ENL 00 51
FC3 Interrupt Request 1 IRQ1 00 49
FC4 IRQ1 Enable High Bit IRQ1ENH 00 52
FC5 IRQ1 Enable Low Bit IRQ1ENL 00 52
FC6 Interrupt Request 2 IRQ2 00 50
FC7 IRQ2 Enable High Bit IRQ2ENH 00 53
FC8 IRQ2 Enable Low Bit IRQ2ENL 00 53
FC9-FCC Reserved XX
FCD Interrupt Edge Select IRQES 00 54
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page #
XX=Undefined
PS017610-0404 Register File Address Map
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
23
FCE Interrupt Port Select IRQPS 00 55
FCF Interrupt Control IRQCTL 00 56
GPIO Port A
FD0 Port A Address PAADDR 00 37
FD1 Port A Control PACTL 00 38
FD2 Port A Input Data PAIN XX 42
FD3 Port A Output Data PAOUT 00 43
GPIO Port B
FD4 Port B Address PBADDR 00 37
FD5 Port B Control PBCTL 00 38
FD6 Port B Input Data PBIN XX 42
FD7 Port B Output Data PBOUT 00 43
GPIO Port C
FD8 Port C Address PCADDR 00 37
FD9 Port C Control PCCTL 00 38
FDA Port C Input Data PCIN XX 42
FDB Port C Output Data PCOUT 00 43
GPIO Port D
FDC Port D Address PDADDR 00 37
FDD Port D Control PDCTL 00 38
FDE Port D Input Data PDIN XX 42
FDF Port D Output Data PDOUT 00 43
GPIO Port E
FE0 Port E Address PEADDR 00 37
FE1 Port E Control PECTL 00 38
FE2 Port E Input Data PEIN XX 42
FE3 Port E Output Data PEOUT 00 43
GPIO Port F
FE4 Port F Address PFADDR 00 37
FE5 Port F Control PFCTL 00 38
FE6 Port F Input Data PFIN XX 42
FE7 Port F Output Data PFOUT 00 43
GPIO Port G
FE8 Port G Address PGADDR 00 37
FE9 Port G Control PGCTL 00 38
FEA Port G Input Data PGIN XX 42
FEB Port G Output Data PGOUT 00 43
GPIO Port H
FEC Port H Address PHADDR 00 37
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page #
XX=Undefined
PS017610-0404 Register File Address Map
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
24
FED Port H Control PHCTL 00 38
FEE Port H Input Data PHIN XX 42
FEF Port H Output Data PHOUT 00 43
Watch-Dog Timer (WDT)
FF0 Watch-Dog Timer Control WDTCTL XXX00000b 75
FF1 Watch-Dog Timer Reload Upper Byte WDTU FF 76
FF2 Watch-Dog Timer Reload High Byte WDTH FF 76
FF3 Watch-Dog Timer Reload Low Byte WDTL FF 76
FF4--FF7 Reserved XX
Flash Memory Controller
FF8 Flash Control FCTL 00 144
FF8 Flash Status FSTAT 00 145
FF9 Flash Page Select FPS 00 146
FFA Flash Programming Frequency High Byte FFREQH 00 147
FFB Flash Programming Frequency Low Byte FFREQL 00 147
eZ8 CPU
FFC Flags XX Refer to the eZ8
CPU User
Manual
FFD Register Pointer RP XX
FFE Stack Pointer High Byte SPH XX
FFF Stack Pointer Low Byte SPL XX
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page #
XX=Undefined
PS017610-0404 Reset and Stop Mode Recovery
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
25
Reset and Stop Mode Recovery
Overview
The Reset Controller within the Z8F640x family devices controls Reset and STOP Mode
Recovery operation. In typical operation, the following events cause a Reset to occur:
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate
a reset)
External RESET pin assertion
On-Chip Debugger initiated Reset (OCDCTL[1] set to 1)
When the Z8F640x family device is in Stop mode, a Stop Mode Recovery is initiated by
either of the following:
Watch-Dog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The Z8F640x family provides several different types of Reset operation. Stop Mode
Recovery is considered a form of Reset. The type of Reset is a function of both the current
operating mode of the Z8F640x family device and the source of the Reset. Table 7 lists the
types of Reset and their operating characteristics. The System Reset is longer than the
Short Reset to allow additional time for external oscillator start-up.
Table 7. Reset and Stop Mode Recovery Characteristics and Latency
Reset Type
Reset Characteristics and Latency
Control Registers eZ8 CPU Reset Latency (Delay)
System Reset Reset (as applicable) Reset 514 WDT Oscillator cycles + 16 System Clock cycles
Short Reset Reset (as applicable) Reset 66 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode Recovery Unaffected, except
WDT_CTL register Reset 514 WDT Oscillator cycles + 16 System Clock cycles
PS017610-0404 Reset and Stop Mode Recovery
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
26
System and Short Resets
During a System Reset, the Z8F640x family device is held in Reset for 514 cycles of the
Watch-Dog Timer oscillator followed by 16 cycles of the system clock (crystal oscillator).
A Short Reset differs from a System Reset only in the number of Watch-Dog Timer oscil-
lator cycles required to exit Reset. A Short Reset requires only 66 Watch-Dog Timer oscil-
lator cycles. Unless specifically stated otherwise, System Reset and Short Reset are
referred to collectively as Reset.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins oper-
ating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Reset Sources
Table 8 lists the reset sources and type of Reset as a function of the Z8F640x family
device operating mode. The text following provides more detailed information on the indi-
vidual Reset sources. Please note that Power-On Reset / Voltage Brown-Out events always
have priority over all other possible reset sources to insure a full system reset occurs.
Table 8. Reset Sources and Resulting Reset Type
Operating Mode Reset Source Reset Type
Normal or Halt modes Power-On Reset / Voltage Brown-Out System Reset
Watch-Dog Timer time-out
when configured for Reset Short Reset
RESET pin assertion Short Reset
On-Chip Debugger initiated Reset
(OCDCTL[1] set to 1) System Reset except the On-Chip Debugger is
unaffected by the reset
Stop mode Power-On Reset / Voltage Brown-Out System Reset
RESET pin assertion System Reset
DBG pin driven Low System Reset
whim-“mm
PS017610-0404 Reset and Stop Mode Recovery
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
27
Power-On Reset
The Z8F640x family products contain an internal Power-On Reset (POR) circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (V
POR
), the POR Counter is enabled and counts 514 cycles of the
Watch-Dog Timer oscillator. After the POR counter times out, the XTAL Counter is
enabled to count a total of 16 system clock pulses. The Z8F640x family device is held in
the Reset state until both the POR Counter and XTAL counter have timed out. After the
device exits the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following
Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register
is set to 1.
Figure 62 illustrates Power-On Reset operation. Refer to the Electrical Characteristics
chapter for the POR threshold voltage (V
POR
).
Figure 62. Power-On Reset Operation (not to scale)
Voltage Brown-Out Reset
The devices in the Z8F640x family provide low Voltage Brown-Out (VBO) protection.
The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO
VCC = 0.0V
VCC = 3.3V
V
POR
V
VBO
Crystal Oscillator
XOUT
Internal RESET
signal
Program
Execution
Oscillator
Start-up
XTAL
WDT Clock
POR counter delaycounter delay
wmm
PS017610-0404 Reset and Stop Mode Recovery
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
28
threshold voltage, V
VBO
) and forces the device into the Reset state. While the supply volt-
age remains below the Power-On Reset voltage threshold (V
POR
), the VBO block holds
the Z8F640x family
device in the Reset state.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the
Z8F640x family device progresses through a full System Reset sequence, as described in
the Power-On Reset section. Following Power-On Reset, the POR status bit in the Watch-
Dog Timer Control (WDTCTL) register is set to 1. Figure 63 illustrates Voltage Brown-
Out operation. Refer to the Electrical Characteristics chapter for the VBO and POR
threshold voltages (V
VBO
and V
POR
).
Stop mode disables the Voltage Brown-Out detector.
Figure 63. Voltage Brown-Out Reset Operation (not to scale)
Watch-Dog Timer Reset
If the device is in normal or Halt mode, the Watch-Dog Timer can initiate a System Reset
at time-out if the WDT_RES Option Bit is set to 1. This is the default (unprogrammed) set-
ting of the WDT_RES Option Bit. The WDT status bit in the WDT Control register is set to
signify that the reset was initiated by the Watch-Dog Timer.
VCC = 3.3V
V
POR
V
VBO
Internal RESET
signal
Program
Execution
Program
Execution Voltage
Brownout
VCC = 3.3V
Crystal Oscillator
XOUT
WDT Clock
XTALPOR counter delaycounter delay
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External Pin Reset
The RESET pin has a Schmitt-triggered input and an internal pull-up. Once the RESET
pin is asserted, the device progresses through the Short Reset sequence. While the RESET
input pin is asserted Low, the Z8F640x family device continues to be held in the Reset
state. If the RESET pin is held Low beyond the Short Reset time-out, the device exits the
Reset state immediately following RESET pin deassertion. Following a Short Reset initi-
ated by the external RESET pin, the EXT status bit in the Watch-Dog Timer Control
(WDTCTL) register is set to 1.
Stop Mode Recovery
Stop mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the
Low-Power Modes chapter for detailed Stop mode information. During Stop Mode
Recovery, the Z8F640x family device is held in reset for 514 cycles of the Watch-Dog
Timer oscillator followed by 16 cycles of the system clock (crystal oscillator). Stop Mode
Recovery does not affect any values in the Register File, including the Stack Pointer, Reg-
ister Pointer, Flags and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop Mode Recovery, the STOP bit in the Watch-Dog Timer Con-
trol Register is set to 1. Table 9 lists the Stop Mode Recovery sources and resulting
actions. The text following provides more detailed information on each of the Stop Mode
Recovery sources.
Stop Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during Stop mode, the Z8F640x family device under-
goes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the
WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an inter-
rupt upon time-out and the device is configured to respond to interrupts, the Z8F640x fam-
ily device services the Watch-Dog Timer interrupt request following the normal Stop
Mode Recovery sequence.
Table 9. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source Action
Stop mode Watch-Dog Timer time-out
when configured for Reset Stop Mode Recovery
Watch-Dog Timer time-out
when configured for interrupt Stop Mode Recovery followed by interrupt (if
interrupts are enabled)
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery source Stop Mode Recovery
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Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recover source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. In the Watch-Dog
Timer Control register, the STOP bit is set to 1.
In Stop mode, the GPIO Port Input Data registers (PxIN) are disabled. The
Port Input Data registers record the Port transition only if the signal stays
on the Port pin through the end of the STOP Mode Recovery delay. Thus,
short pulses on the Port pin can initiate STOP Mode Recovery without be-
ing written to the Port Input Data register or without initiating an interrupt
(if enabled for that pin).
Caution:
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PS017610-0404 Low-Power Modes
31
Low-Power Modes
Overview
The Z8F640x family products contain power-saving features. The highest level of power
reduction is provided by Stop mode. The next level of power reduction is provided by the
Halt mode.
Stop Mode
Execution of the eZ8 CPU’s STOP instruction places the Z8F640x family device into Stop
mode. In Stop mode, the operating characteristics are:
Primary crystal oscillator is stopped
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate
If enabled, the Watch-Dog Timer continues to operate
All other on-chip peripherals are idle
To minimize current in Stop mode, all GPIO pins that are configured as digital inputs must
be driven to one of the supply rails (V
CC
or GND). The Z8F640x family device can be
brought out of Stop mode using Stop Mode Recovery. For more information on STOP
Mode Recovery refer to the Reset and Stop Mode Recovery chapter.
Halt Mode
Execution of the eZ8 CPU’s HALT instruction places the Z8F640x family device into Halt
mode. In Halt mode, the operating characteristics are:
Primary crystal oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is idle
Program counter (PC) stops incrementing
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Watch-Dog Timer’s internal RC oscillator continues to operate
If enabled, the Watch-Dog Timer continues to operate
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of Halt mode by any of the following operations:
Interrupt
Watch-Dog Timer time-out (interrupt or reset)
Power-on reset
Voltage-brown out reset
External RESET pin assertion
To minimize current in Halt mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (V
CC
or GND).
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PS017610-0404 General-Purpose I/O
33
General-Purpose I/O
Overview
The Z8F640x family products support a maximum of seven 8-bit ports (Ports A-G) and
one 4-bit port (Port H) for general-purpose input/output (I/O) operations. Each port con-
tains control and data registers. The GPIO control registers are used to determine data
direction, open-drain, output drive current and alternate pin functions. Each port pin is
individually programmable.
GPIO Port Availability By Device
Not all Z8F640x family products support all 8 ports (A-H). Table 10 lists the port pins
available with each device and package type.
Table 10. Port Availability by Device and Package Type
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
Z8F1601 40-pin [7:0] [7:0] [6:0] [6:3, 1:0] - - - -
Z8F1601 44-pin [7:0] [7:0] [7:0] [6:0]
Z8F1602 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8F2401 40-pin [7:0] [7:0] [6:0] [6:3, 1:0] - - - -
Z8F2401 44-pin [7:0] [7:0] [7:0] [6:0] - - - -
Z8F2402 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8F3201 40-pin [7:0] [7:0] [6:0] [6:3, 1:0] - - - -
Z8F3201 44-pin [7:0] [7:0] [7:0] [6:0] - - - -
Z8F3202 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8F4801 40-pin [7:0] [7:0] [6:0] [6:3, 1:0] - - - -
Z8F4801 44-pin [7:0] [7:0] [7:0] [6:0] - - - -
Z8F4802 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8F4803 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Z8F6401 40-pin [7:0] [7:0] [6:0] [6:3, 1:0] - - - -
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Architecture
Figure 64 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength are not
illustrated.
Figure 64. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A-H Alternate Function sub-registers configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
Z8F6401 44-pin [7:0] [7:0] [7:0] [6:0] - - - -
Z8F6402 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8F6403 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Table 10. Port Availability by Device and Package Type (Continued)
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
DQ
DQ
DQ
GND
VDD
Port Output Control
Port Data Direction
Port Output
Data Register
Port Input
Data Register
Port
Pin
DATA
Bus
System
Clock
System
Clock
Schmitt Trigger
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of the port pin direction (input/output) is passed from the Port A-H Data Direction regis-
ters to the alternate function assigned to this pin. Table 11 lists the alternate functions asso-
ciated with each port pin.
Table 11. Port Alternate Function Mapping
Port Pin Mnemonic Alternate Function Description
Port A
PA0 T0IN Timer 0 Input
PA1 T0OUT Timer 0 Output
PA2 N/A No alternate function
PA3 CTS0 UART 0 Clear to Send
PA4 RXD0 / IRRX0 UART 0 / IrDA 0 Receive Data
PA5 TXD0 / IRTX0 UART 0 / IrDA 0 Transmit Data
PA6 SCL I
2
C Clock (automatically open-drain)
PA7 SDA I
2
C Data (automatically open-drain)
Port B
PB0 ANA0 ADC Analog Input 0
PB1 ANA1 ADC Analog Input 1
PB2 ANA2 ADC Analog Input 2
PB3 ANA3 ADC Analog Input 3
PB4 ANA4 ADC Analog Input 4
PB5 ANA5 ADC Analog Input 5
PB6 ANA6 ADC Analog Input 6
PB7 ANA7 ADC Analog Input 7
Port C
PC0 T1IN Timer 1 Input
PC1 T1OUT Timer 1 Output
PC2 SS SPI Slave Select
PC3 SCK SPI Serial Clock
PC4 MOSI SPI Master Out Slave In
PC5 MISO SPI Master In Slave Out
PC6 T2IN Timer 2 In
PC7 T2OUT Timer 2 Out (not available in 40-pin packages)
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GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). Refer to the Interrupt Controller chapter for more information on
interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 12 lists these Port registers. Use the Port A-H Address and Control registers together
to provide access to sub-registers for Port configuration and control.
Port D
PD0 T3IN Timer 3 In (not available in 40- and 44-pin packages)
PD1 T3OUT Timer 3 Out (not available in 40- and 44-pin packages)
PD2 N/A No alternate function
PD3 N/A No alternate function
PD4 RXD1 / IRRX1 UART 1 / IrDA 1 Receive Data
PD5 TXD1 / IRTX1 UART 1 / IrDA 1 Transmit Data
PD6 CTS1 UART 1 Clear to Send
PD7 RCOUT Watch-Dog Timer RC Oscillator Output
Port E
PE[7:0] N/A No alternate functions
Port F
PF[7:0] N/A No alternate functions
Port G
PG[7:0] N/A No alternate functions
Port H
PH0 ANA8 ADC Analog Input 8
PH1 ANA9 ADC Analog Input 9
PH2 ANA10 ADC Analog Input 10
PH3 ANA11 ADC Analog Input 11
Table 11. Port Alternate Function Mapping (Continued)
Port Pin Mnemonic Alternate Function Description
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Port A-H Address Registers
The Port A-H Address registers select the GPIO Port functionality accessible through the
Port A-H Control registers. The Port A-H Address and Control registers combine to pro-
vide access to all GPIO Port control (Table 13).
Table 12. GPIO Port Registers and Sub-Registers
Port Register Mnemonic Port Register Name
PxADDR Port A-H Address Register
(Selects sub-registers)
PxCTL Port A-H Control Register
(Provides access to sub-registers)
PxIN Port A-H Input Data Register
PxOUT Port A-H Output Data Register
Port Sub-Register Mnemonic Port Register Name
PxDD Data Direction
PxAF Alternate Function
PxOC Output Control (Open-Drain)
PxHDE High Drive Enable
PxSMRE STOP Mode Recovery Source
Enable
Table 13. Port A-H GPIO Address Registers (PxADDR)
BITS 76543210
FIELD PADDR[7:0]
RESET 00H
R/W R/W
ADDR FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
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PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
Port A-H Control Registers
The Port A-H Control registers set the GPIO port operation. The value in the correspond-
ing Port A-H Address register determines the control sub-registers accessible using the
Port A-H Control register (Table 14).
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
PADDR[7:0] Port Control sub-register accessible using the Port A-H Control Registers
00H No function. Provides some protection against accidental Port reconfiguration.
01H Data Direction
02H Alternate Function
03H Output Control (Open-Drain)
04H High Drive Enable
05H Stop Mode Recovery Source Enable.
06H-FFH No function.
Table 14. Port A-H Control Registers (PxCTL)
BITS 76543210
FIELD PCTL
RESET 00H
R/W R/W
ADDR FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
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Port A-H Data Direction Sub-Registers
The Port A-H Data Direction sub-register is accessed through the Port A-H Control regis-
ter by writing 01H to the Port A-H Address register (Table 15).
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A-H Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A-H Input Data Reg-
ister. The output driver is tri-stated.
Port A-H Alternate Function Sub-Registers
The Port A-H Alternate Function sub-register (Table 16) is accessed through the Port A-H
Control register by writing 02H to the Port A-H Address register. The Port A-H Alternate
Function sub-registers select the alternate functions for the selected pins. Refer to the
GPIO Alternate Functions section to determine the alternate function associated with
each port pin.
Do not enable alternate function for GPIO port pins which do not have an
associated alternate function. Failure to follow this guideline may result in
unpredictable operation.
Table 15. Port A-H Data Direction Sub-Registers
BITS 76543210
FIELD DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
RESET 11111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR If 01H in Port A-H Address Register, accessible via Port A-H Control Register
Table 16. Port A-H Alternate Function Sub-Registers
BITS 76543210
FIELD AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR If 02H in Port A-H Address Register, accessible via Port A-H Control Register
Caution:
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AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDx bit in the Port A-H Data Direction sub-
register determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the alternate
function.
Port A-H Output Control Sub-Registers
The Port A-H Output Control sub-register (Table 17) is accessed through the Port A-H
Control register by writing 03H to the Port A-H Address register. Setting the bits in the
Port A-H Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate func-
tions are also affected.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and disables the drains if set
to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Table 17. Port A-H Output Control Sub-Registers
BITS 76543210
FIELD POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR If 03H in Port A-H Address Register, accessible via Port A-H Control Register
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Port A-H High Drive Enable Sub-Registers
The Port A-H High Drive Enable sub-register (Table 18) is accessed through the Port A-H
Control register by writing 04H to the Port A-H Address register. Setting the bits in the
Port A-H High Drive Enable sub-registers to 1 configures the specified port pins for high
current output drive operation. The Port A-H High Drive Enable sub-register affects the
pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A-H Stop Mode Recovery Source Enable Sub-Registers
The Port A-H STOP Mode Recovery Source Enable sub-register (Table 19) is accessed
through the Port A-H Control register by writing 05H to the Port A-H Address register.
Setting the bits in the Port A-H STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
Table 18. Port A-H High Drive Enable Sub-Registers
BITS 76543210
FIELD PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR If 04H in Port A-H Address Register, accessible via Port A-H Control Register
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PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during Stop mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during Stop mode initiates STOP Mode Recovery.
Port A-H Input Data Registers
Reading from the Port A-H Input Data registers (Table 20) returns the sampled values
from the corresponding port pins. The Port A-H Input Data registers are Read-only.
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Table 19. Port A-H STOP Mode Recovery Source Enable Sub-Registers
BITS 76543210
FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR If 05H in Port A-H Address Register, accessible via Port A-H Control Register
Table 20. Port A-H Input Data Registers (PxIN)
BITS 76543210
FIELD PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET XXXXXXXX
R/W RRRRRRRR
ADDR FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
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Port A-H Output Data Register
The Port A-H Output Data register (Table 21) writes output data to the pins.
POUT[7:0]—Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alter-
nate function operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by set-
ting the corresponding Port Output Control register bit to 1.
Table 21. Port A-H Output Data Register (PxOUT)
BITS 76543210
FIELD POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
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PS017610-0404 Interrupt Controller
44
Interrupt Controller
Overview
The interrupt controller on the Z8F640x family device prioritizes the interrupt requests
from the on-chip peripherals and the GPIO port pins. The features of the interrupt control-
ler on the Z8F640x family device include the following:
24 unique interrupt vectors:
12 GPIO port pin interrupt sources
12 on-chip peripheral interrupt sources
Flexible GPIO interrupts
8 selectable rising and falling edge GPIO interrupts
4 dual-edge interrupts
3 levels of individually programmable interrupt priority
Watch-Dog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for
more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man-
ual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 22 lists all of the interrupts available on the Z8F640x family device in order of pri-
ority. The interrupt vector is stored with the most significant byte (MSB) at the even Pro-
gram Memory address and the least significant byte (LSB) at the following odd Program
Memory address.
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Table 22. Interrupt Vectors in Order of Priority
Priority Program Memory
Vector Address Interrupt Source Interrupt Assertion Type
Highest 0002h Reset (not an interrupt) Not applicable
0004h Watch-Dog Timer Continuous assertion
0006h Illegal Instruction Trap (not an interrupt) Not applicable
0008h Timer 2 Single assertion (pulse)
000Ah Timer 1 Single assertion (pulse)
000Ch Timer 0 Single assertion (pulse)
000Eh UART 0 receiver Continuous assertion
0010h UART 0 transmitter Continuous assertion
0012h I
2
C Continuous assertion
0014h SPI Continuous assertion
0016h ADC Single assertion (pulse)
0018h Port A7 or Port D7, rising or falling input edge Single assertion (pulse)
001Ah Port A6 or Port D6, rising or falling input edge Single assertion (pulse)
001Ch Port A5 or Port D5, rising or falling input edge Single assertion (pulse)
001Eh Port A4 or Port D4, rising or falling input edge Single assertion (pulse)
0020h Port A3 or Port D3, rising or falling input edge Single assertion (pulse)
0022h Port A2 or Port D2, rising or falling input edge Single assertion (pulse)
0024h Port A1 or Port D1, rising or falling input edge Single assertion (pulse)
0026h Port A0 or Port D0, rising or falling input edge Single assertion (pulse)
0028h Timer 3 (not available in 40/44-pin packages) Single assertion (pulse)
002Ah UART 1 receiver Continuous assertion
002Ch UART 1 transmitter Continuous assertion
002Eh DMA Single assertion (pulse)
0030h Port C3, both input edges Single assertion (pulse)
0032h Port C2, both input edges Single assertion (pulse)
0034h Port C1, both input edges Single assertion (pulse)
Lowest 0036h Port C0, both input edges Single assertion (pulse)
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Architecture
Figure 65 illustrates a block diagram of the interrupt controller.
Figure 65. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
Writing a 1 to the IRQE bit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
Execution of a DI (Disable Interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller
Writing a 0 to the IRQE bit in the Interrupt Control register
Reset
Vector
IRQ Request
High
Priority
Medium
Priority
Low
Priority
Priority
Mux
Interrupt Request Latches and Control
Port Interrupts
Internal Interrupts
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47
Execution of a Trap instruction
Illegal instruction trap
Interrupt Vectors and Priority
The Z8F640x family device interrupt controller supports three levels of interrupt priority.
Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the
lowest priority. If all of the interrupts were enabled with identical interrupt priority (all as
Level 2 interrupts, for example), then interrupt priority would be assigned from highest to
lowest as specified in Table 22. Level 3 interrupts always have higher priority than Level 2
interrupts which, in turn, always have higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 22.
Reset, Watch-Dog Timer interrupt (if enabled), and Illegal Instruction Trap always have
highest (Level 3) priority.
Interrupt Assertion Types
Two types of interrupt assertion - single assertion (pulse) and continuous assertion - are
used within the Z8F640x family device. The type of interrupt assertion for each interrupt
source is listed in Table 22.
Single Assertion (Pulse) Interrupt Sources
Some interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corre-
sponding bit in the Interrupt Request register is cleared until the next interrupt occurs.
Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the
interrupt request.
Continuous Assertion Interrupt Sources
Other interrupt sources continuously assert their interrupt requests until cleared at the
source. For these continuous assertion interrupt sources, interrupt acknowledgement by
the eZ8 CPU does not clear the corresponding bit in the Interrupt Request register. Writing
a 0 to the corresponding bit in the Interrupt Request register only clears the interrupt for a
single clock cycle. Since the source is continuously asserting the interrupt request, the
interrupt request bit is set to 1 again during the next clock cycle.
The only way to clear continuous assertion interrupts is at the source of the interrupt (for
example, in the UART or SPI peripherals). The source of the interrupt must be cleared
first. After the interrupt is cleared at the source, the corresponding bit in the Interrupt
Request register must also be cleared to 0. Both the interrupt source and the IRQ register
must be cleared.
PS017610-0404 Interrupt Controller
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
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Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 23) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
Table 23. Interrupt Request 0 Register (IRQ0)
BITS 76543210
FIELD T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC0H
PS017610-0404 Interrupt Controller
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
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I
2
CI— I
2
C Interrupt Request
0 = No interrupt request is pending for the I
2
C.
1 = An interrupt request from the I
2
C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 24) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
PADxI—Port A or Port D Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
where x indicates the specific GPIO Port pin number (0 through 7). For each pin, only 1 of
either Port A or Port D can be enabled for interrupts at any one time. Port selection (A or
D) is determined by the values in the Interrupt Port Select Register.
Table 24. Interrupt Request 1 Register (IRQ1)
BITS 76543210
FIELD PAD7I PAD6I PAD5I PAD4I PAD3I PAD2I PAD1I PAD0I
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC3H
PS017610-0404 Interrupt Controller
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Z8 Encore!
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Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 25) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
T3I—Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
U1RXI—UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
U1TXI—UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
DMAI—DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
PCxI—Port C Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
where x indicates the specific GPIO Port C pin number (0 through 3).
Table 25. Interrupt Request 2 Register (IRQ2)
BITS 76543210
FIELD T3I U1RXI U1TXI DMAI PC3I PC2I PC1I PC0I
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC6H
PS017610-0404 Interrupt Controller
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Z8 Encore!
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IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 27 and 28) form a priority encoded
enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting
bits in each register. Table 26 describes the priority control for IRQ0.
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I
2
C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 26. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority Description
0 0 Disabled Disabled
01Level 1Low
1 0 Level 2 Nominal
1 1 Level 3 High
where x indicates the register bits from 0 through 7.
Table 27. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS 76543210
FIELD T2ENH T1ENH T0ENH U0RENH U0TENH I2CENH SPIENH ADCENH
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC1H
PS017610-0404 Interrupt Controller
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T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I
2
C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 30 and 31) form a priority encoded
enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting
bits in each register. Table 29 describes the priority control for IRQ1.
Table 28. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS 76543210
FIELD T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC2H
Table 29. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority Description
0 0 Disabled Disabled
01Level 1Low
1 0 Level 2 Nominal
1 1 Level 3 High
where x indicates the register bits from 0 through 7.
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PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the
interrupt source.
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the
interrupt source.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (Tables 33 and 34) form a priority encoded
enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting
bits in each register. Table 32 describes the priority control for IRQ2.
Table 30. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS 76543210
FIELD PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC4H
Table 31. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS 76543210
FIELD PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC5H
Table 32. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority Description
0 0 Disabled Disabled
01Level 1Low
1 0 Level 2 Nominal
1 1 Level 3 High
where x indicates the register bits from 0 through 7.
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T3ENH—Timer 3 Interrupt Request Enable High Bit
U1RENH—UART 1 Receive Interrupt Request Enable High Bit
U1TENH—UART 1 Transmit Interrupt Request Enable High Bit
DMAENH—DMA Interrupt Request Enable High Bit
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
T3ENL—Timer 3 Interrupt Request Enable Low Bit
U1RENL—UART 1 Receive Interrupt Request Enable Low Bit
U1TENL—UART 1 Transmit Interrupt Request Enable Low Bit
DMAENL—DMA Interrupt Request Enable Low Bit
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 35) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
Table 33. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS 76543210
FIELD T3ENH U1RENH U1TENH DMAENH C3ENH C2ENH C1ENH C0ENH
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC7H
Table 34. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS 76543210
FIELD T3ENL U1RENL U1TENL DMAENL C3ENL C2ENL C1ENL C0ENL
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FC8H
PS017610-0404 Interrupt Controller
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
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Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
IESx—Interrupt Edge Select x
where x indicates the specific GPIO Port pin number (0 through 7). The pulse width
should be greater than 1 system clock to guarantee capture of the edge triggered interrupt.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 36) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as inter-
rupts. The Interrupt Edge Select register controls the active interrupt edge.
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
Table 35. Interrupt Edge Select Register (IRQES)
BITS 76543210
FIELD IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FCDH
Table 36. Interrupt Port Select Register (IRQPS)
BITS 76543210
FIELD PAD7S PAD6S PAD5S PAD4S PAD3S PAD2S PAD1S PAD0S
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR FCEH
PS017610-0404 Interrupt Controller
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
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Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 37) contains the master enable bit for all
interrupts.
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved
These bits must be 0.
Table 37. Interrupt Control Register (IRQCTL)
BITS 76543210
FIELD IRQE Reserved
RESET 00000000
R/W R/WRRRRRRR
ADDR FCFH
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
PS017610-0404 Timers
57
Timers
Overview
The Z8F640x family products contain three to four 16-bit reloadable timers that can be
used for timing, event counting, or generation of pulse-width modulated (PWM) signals.
The timers’ features include:
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I
2
C peripherals may also be used to provide basic timing function-
ality. Refer to the respective serial communication peripheral chapters for information on
using the Baud Rate Generators as timers. Timer 3 is unavailable in the 40- and 44-pin
packages.
Architecture
Figure 66 illustrates the architecture of the timers.
PS017610-0404 Timers
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Figure 66. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
One-Shot Mode
In One-Shot mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and
stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is desired to have the Timer Output make a permanent state change upon One-Shot time-
16-Bit
PWM / Compare
16-Bit Counter
with Prescaler
16-Bit
Reload Register
Timer
Control
Compare Compare
Interrupt,
PWM,
and
Timer Output
Control
Timer
Timer
Timer Block
System
Timer
Data
Block
Interrupt
Output
Control
Bus
Clock
Input
Gate
Input
Capture
Input
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out, first set the TPOL bit in the Timer Control Register to the start value before beginning
One-Shot mode. Then, after starting the timer, set TPOL to the opposite bit value.
The steps for configuring a timer for One-Shot mode and initiating the count are as fol-
lows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for One-Shot mode.
Set the prescale value.
If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In One-Shot mode, the system clock always provides the timer input. The timer period is
given by the following equation:
Continuous Mode
In Continuous mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt, the count value in the Timer High and
Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output
alternate function is enabled, the Timer Output pin changes state (from Low to High or
from High to Low) upon timer Reload.
The steps for configuring a timer for Continuous mode and initiating the count are as fol-
lows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for Continuous mode.
Set the prescale value.
One-Shot Mode Time-Out Period (s) Reload Value Start Value()Prescale×
System Clock Frequency (Hz)
------------------------------------------------------------------------------------------------------=
PS017610-0404 Timers
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If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This only affects the first pass in Continuous mode. After the first timer
Reload in Continuous mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In Continuous mode, the system clock always provides the timer input. The timer period is
given by the following equation:
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first time-out period.
Counter Mode
In Counter mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer
Control Register selects whether the count occurs on the rising edge or the falling edge of
the Timer Input signal. In Counter mode, the prescaler is disabled.
The input frequency of the Timer Input signal must not exceed one-fourth
the system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
The steps for configuring a timer for Counter mode and initiating the count are as follows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for Counter mode.
Continuous Mode Time-Out Period (s) Reload Value Prescale×
System Clock Frequency (Hz)
----------------------------------------------------------------------------=
Caution:
PS017610-0404 Timers
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Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter mode. After the first timer Reload in Counter
mode, counting always begins at the reset value of 0001H. Generally, in Counter
mode the Timer High and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control register to enable the timer.
In Counter mode, the number of Timer Input transitions since the timer start is given by
the following equation:
PWM Mode
In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16-
bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as
a High (1) and then transitions to a Low (0) when the timer value matches the PWM value.
The Timer Output signal returns to a High (1) after the timer reaches the Reload value and
is reset to 0001H.
If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as
a Low (0) and then transitions to a High (1) when the timer value matches the PWM value.
The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and
is reset to 0001H.
The steps for configuring a timer for PWM mode and initiating the PWM operation are as
follows:
1. Write to the Timer Control register to:
Counter Mode Timer Input Transitions Current Count Value Start Value=
PS017610-0404 Timers
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Disable the timer
Configure the timer for PWM mode.
Set the prescale value.
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is given by the following equation:
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by:
Capture Mode
In Capture mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control register determines if the Capture occurs on a rising edge or a falling edge of the
PWM Period (s) Reload Value Prescale×
System Clock Frequency (Hz)
----------------------------------------------------------------------------=
PWM Output High Time Ratio (%) Reload Value PWM Value
Reload Value
------------------------------------------------------------------------100×=
PWM Output High Time Ratio (%) PWM Value
Reload Value
---------------------------------- 100×=
PS017610-0404 Timers
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Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting.
The steps for configuring a timer for Capture mode and initiating the count are as follows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for Capture mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000H after the
interrupt, then the interrupt was generated by a Reload.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In Capture mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
Compare Mode
In Compare mode, the timer counts up to the 16-bit maximum Compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon Com-
pare.
Capture Elapsed Time (s) Capture Value Start Value()Prescale×
System Clock Frequency (Hz)
---------------------------------------------------------------------------------------------------------=
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If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
The steps for configuring a timer for Compare mode and initiating the count are as fol-
lows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for Compare mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In Compare mode, the system clock always provides the timer input. The Compare time is
given by the following equation:
Gated Mode
In Gated mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
The steps for configuring a timer for Gated mode and initiating the count are as follows:
1. Write to the Timer Control register to:
Disable the timer
Compare Mode Time (s) Compare Value Start Value()Prescale×
System Clock Frequency (Hz)
------------------------------------------------------------------------------------------------------------=
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Configure the timer for Gated mode.
Set the prescale value.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Gated mode. After the first timer reset in Gated mode,
counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
Capture/Compare Mode
In Capture/Compare mode, the timer begins counting on the first external Timer Input
transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the
Timer Control Register. The timer input is the system clock.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte registers is reset to 0001H, and counting resumes.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes.
The steps for configuring a timer for Capture/Compare mode and initiating the count are
as follows:
1. Write to the Timer Control register to:
Disable the timer
Configure the timer for Capture/Compare mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
PS017610-0404 Timers
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5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In Capture/Compare mode, the elapsed time from timer start to Capture event can be cal-
culated using the following equation:
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte reg-
ister is read, the contents of the Timer Low Byte register are placed in a holding register. A
subsequent read from the Timer Low Byte register returns the value in the holding register.
This operation allows accurate reads of the full 16-bit timer count value while enabled.
When the timers are not enabled, a read from the Timer Low Byte register returns the
actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
Timers 0–2 are available in all packages. Timer 3 is available only in the 64-, 68- and 80-
pin packages.
Timer 0-3 High and Low Byte Registers
The Timer 0-3 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the
current 16-bit timer count value. When the timer is enabled, a read from TxH causes the
value in TxL to be stored in a temporary holding register. A read from TMRL always
returns this temporary register when the timers are enabled. When the timer is disabled,
reads from the TMRL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
Capture Elapsed Time (s) Capture Value Start Value()Prescale×
System Clock Frequency (Hz)
---------------------------------------------------------------------------------------------------------
=
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written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
TH and TL—Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-3 Reload High and Low Byte (TxRH and TxRL) registers (Tables 40 and 41)
store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload
High Byte register are stored in a temporary holding register. When a write to the Timer
Reload Low Byte register occurs, the temporary holding register value is written to the
Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer
Reload value.
In Compare mode, the Timer Reload High and Low Byte registers store the 16-bit Com-
pare value.
In single-byte DMA transactions to the Timer Reload High Byte register, the temporary
holding register is bypassed and the value is written directly to the register. If the DMA is
Table 38. Timer 0-3 High Byte Register (TxH)
BITS 76543210
FIELD TH
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F00H, F08H, F10H, F18H
Table 39>. Timer 0-3 Low Byte Register (TxL)
BITS 76543210
FIELD TL
RESET 00000001
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F01H, F09H, F11H, F19H
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set to 2-byte transfers, the temporary holding register for the Timer Reload High Byte is
not bypassed.
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value is used
to set the maximum count value which initiates a timer reload to 0001H. In Compare
mode, these two byte form the 16-bit Compare value.
Table 40. Timer 0-3 Reload High Byte Register (TxRH)
BITS 76543210
FIELD TRH
RESET 11111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F02H, F0AH, F12H, F1AH
Table 41. Timer 0-3 Reload Low Byte Register (TxRL)
BITS 76543210
FIELD TRL
RESET 11111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F03H, F0BH, F13H, F1BH
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Timer 0-3 PWM High and Low Byte Registers
The Timer 0-3 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 42
and 43) are used for Pulse-Width Modulator (PWM) operations. These registers also store
the Capture values for the Capture and Capture/Compare modes.
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL) register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in Capture or Capture/Compare modes.
Table 42. Timer 0-3 PWM High Byte Register (TxPWMH)
BITS 76543210
FIELD PWMH
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F04H, F0CH, F14H, F1CH
Table 43. Timer 0-3 PWM Low Byte Register (TxPWML)
BITS 76543210
FIELD PWML
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F05H, F0DH, F15H, F1DH
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Timer 0-3 Control Registers
The Timer 0-3 Control (TxCTL) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
One-Shot mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Continuous mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Counter mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
Table 44. Timer 0-3 Control Register (TxCTL)
BITS 76543210
FIELD TEN TPOL PRES TMODE
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F07H, F0FH, F17H, F1FH
PS017610-0404 Timers
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Capture mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
Compare mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Gated mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
Capture/Compare mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
PRES—Prescale value.
The timer input clock is divided by 2
PRES
, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE—Timer mode
000 = One-Shot mode
001 = Continuous mode
010 = Counter mode
011 = PWM mode
100 = Capture mode
101 = Compare mode
110 = Gated mode
111 = Capture/Compare mode
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PS017610-0404 Watch-Dog Timer
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Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which may place the Z8 Encore!
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into unsuitable
operating states. The Watch-Dog Timer includes the following features:
On-chip RC oscillator
A selectable time-out response: Short Reset or interrupt
24-bit programmable time-out value
Operation
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
Z8F640x family device when the WDT reaches its terminal count. The Watch-Dog Timer
uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer
has only two modes of operation—on and off. Once enabled, it always counts and must be
refreshed to prevent a time-out. An enable can be performed by executing the WDT
instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog
Timer to operate all the time, even if a WDT instruction has not been executed.
The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
given by the following equation:
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator
frequency is 50kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H.
The WDT Reload Value must not be set to values below 000004H. Table 45 provides
WDT Time-out Period (ms) WDT Reload Value
50
--------------------------------------------------
=
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information on approximate time-out delays for the minimum and maximum WDT reload
values.
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 000000H unless a
WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes
the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog
Timer Reload registers. Counting resumes following the reload operation.\
When the Z8F640x family device is operating in Debug Mode (via the On-Chip Debug-
ger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog
Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the
Watch-Dog Timer generates either an interrupt or a Short Reset. The WDT_RES Option Bit
determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chap-
ter for information regarding programming of the WDT_RES Option Bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watch-Dog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter
rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog
Timer counter is not automatically returned to its Reload Value.
WDT Interrupt in Stop Mode
If configured to generate an interrupt when a time-out occurs and the Z8F640x family
device is in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode
Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in
the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP
Table 45. Watch-Dog Timer Approximate Time-Out Delays
WDT Reload Value WDT Reload Value Approximate Time-Out Delay
(with 50kHz typical WDT oscillator frequency)
(Hex) (Decimal) Typical Description
000004 4 80µs Minimum time-out delay
FFFFFF 16,777,215 335.5s Maximum time-out delay
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mode. Refer to the Reset and Stop Mode Recovery chapter for more information on
STOP Mode Recovery.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and
executing code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
Z8F640x family device into the Short Reset state. The WDT status bit in the Watch-Dog
Timer Control register is set to 1. Refer to the Reset and Stop Mode Recovery chapter for
more information on Short Reset.
WDT Reset in Stop Mode
If configured to generate a Reset when a time-out occurs and the Z8F640x family device is
in STOP mode, the Watch-Dog Timer initiates a Stop Mode Recovery. Both the WDT sta-
tus bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following
WDT time-out in STOP mode. Refer to the Reset and Stop Mode Recovery chapter for
more information.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer Control register (WDTCTL)
unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL)
to allow changes to the time-out period. These write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the Reload registers. The follow sequence is required to unlock
the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write
access.
1. Write 55H to the Watch-Dog Timer Control register (WDTCTL)
2. Write AAH to the Watch-Dog Timer Control register (WDTCTL)
3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU)
4. Write the Watch-Dog Timer Reload High Byte register (WDTH)
5. Write the Watch-Dog Timer Reload Low Byte register (WDTL)
All three Watch-Dog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur, unless the sequence
is restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter
when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.
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Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 46, is a Read-Only
register that indicates the source of the most recent Reset event, indicates a Stop Mode
Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets
the upper four bits to 0.
Writing the 55H, AAH unlock sequence to the Watch-Dog Timer Control (WDTCTL) reg-
ister address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH,
and WDTL) to allow changes to the time-out period. These write operations to the
WDTCTL register address produce no effect on the bits in the WDTCTL register. The
locking mechanism prevents spurious writes to the Reload registers.
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-
out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both
set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1
and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This
bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP
mode. Reading this register also resets this bit.
WDT—Watch-Dog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A Stop
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Table 46. Watch-Dog Timer Control Register (WDTCTL)
BITS 76543210
FIELD POR STOP WDT EXT Reserved
RESET XXX00000
R/W RRRRRRRR
ADDR FF0
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Reserved
These bits are reserved and must be 0.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-
isters (Tables 47 through 49) form the 24-bit reload value that is loaded into the Watch-
Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]. Writing to these registers sets the desired Reload Value. Read-
ing from these registers returns the current Watch-Dog Timer count value.
The 24-bit WDT Reload Value must not be set to a value less than
000004H or unpredictable behavior may result.
WDTU—WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
WDTH—WDT Reload High Byte
Table 47. Watch-Dog Timer Reload Upper Byte Register (WDTU)
BITS 76543210
FIELD WDTU
RESET 11111111
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF1H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
Table 48. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS 7 6 5 4 3 2 1 0
FIELD WDTH
RESET 11111111
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF2H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
Caution:
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Middle byte, Bits[15:8], of the 24-bit WDT reload value.
WDTL—WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
Table 49. Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS 7 6 5 4 3 2 1 0
FIELD WDTL
RESET 11111111
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF3H
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
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PS017610-0404 UART
78
UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communica-
tion channel capable of handling asynchronous data transfers. The Z8F640x family device
contains two fully independent UARTs. The UART uses a single 8-bit data mode with
selectable parity. Features of the UART include:
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two Stop bits
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
Separate transmit and receive enables
Selectable 9-bit multiprocessor (9-bit) mode
16-bit Baud Rate Generator (BRG)
Architecture
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate
generator. The UART’s transmitter and receiver function independently, but employ the
same baud rate and data format. Figure 67 illustrates the UART architecture.
PS017610-0404 UART
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Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits.
Figure 67. UART Block Diagram
Receive Shifter
Receive Data
Transmit Data
Transmit Shift
TXD
RXD
System Bus
Parity Checker
Parity Generator
Receiver Control
Control Register
Transmitter Control
CTS
Status Register
Register
Register
Register
Baud Rate
Generator
Z
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Figures 68 and 69 illustrates the asynchronous data format employed by the UART with-
out parity and with parity, respectively.
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions,
if desired.
4. Write to the UART Control 0 register to:
Set the transmit enable bit (TEN) to enable the UART for data transmission
Enable parity, if desired, and select either even or odd parity.
Set or clear the CTSE bit to enable or disable control from the receiver using the
CTS pin.
Figure 68. UART Asynchronous Data Format without Parity
Figure 69. UART Asynchronous Data Format with Parity
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Data Field
lsb msb
Idle State
of Line
Stop Bit(s)
1
2
1
0
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity
Data Field
lsb msb
Idle State
of Line
Stop Bit(s)
1
2
1
0
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5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data
register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data
register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data register becomes available to receive new data.
6. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmit the data.
7. To transmit additional bits, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow these steps to configure the UART for interrupt-
driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the desired priority.
5. Write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions,
if desired.
6. Write to the UART Control 0 register to:
Set the transmit enable bit (TEN) to enable the UART for data transmission
Enable parity, if desired, and select either even or odd parity.
Set or clear the CTSE bit to enable or disable control from the receiver via the
CTS pin.
7. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data transmission. When the UART
Transmit interrupt is detected, the associated interrupt service routine (ISR) should per-
form the following:
8. Write the data byte to the UART Transmit Data register. The transmitter will
automatically transfer the data to the Transmit Shift register and transmit the data.
9. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
10. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
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Receiving Data using the Polled Method
Follow these steps to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions,
if desired.
4. Write to the UART Control 0 register to:
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired, and select either even or odd parity.
5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data
register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to Step 6. If the Receive Data register is empty (indicated by a
0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data register. If operating in Multiprocessor (9-bit)
mode, first read the Multiprocessor Receive flag (MPRX) to determine if the data was
directed to this UART before reading the data.
7. Return to Step 6 to receive additional data.
Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error con-
ditions). Follow these steps to configure the UART receiver for interrupt-driven operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the desired priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions,
if desired.
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7. Write to the UART Control 0 register to:
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired, and select either even or odd parity.
8. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) should per-
form the following:
9. Check the UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
10. If the interrupt was due to data available, read the data from the UART Receive Data
register. If operating in Multiprocessor (9-bit) mode, first read the Multiprocessor
Receive flag (MPRX) to determine if the data was directed to this UART before
reading the data.
11. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
12. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Receiving Data using the Direct Memory Access Controller (DMA)
The DMA and UART can coordinate automatic data transfer from the UART Receive
Data register to general-purpose Register File RAM. This reduces the eZ8 CPU process-
ing overhead required to support UART data reception. The UART Receiver interrupt
must then only notify the eZ8 CPU of error conditions. Follow these steps to configure the
UART and DMA for automatic data handling:
1. Write to the DMA control registers to configure the DMA to transfer data from the
UART Receive Data register to general-purpose Register File RAM.
2. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
3. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the desired priority.
5. Write to the UART Control 1 register to:
Enable Multiprocessor (9-bit) mode functions, if desired.
Disable the UART interrupt for received data by clearing RDAIRQ to 0.
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6. Write to the UART Control 0 register to:
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired, and select either even or odd parity.
The UART and DMA are now configured for data reception and automatic data transfer to
the Register File. When a valid data byte is received by the UART the following occurs:
7. The UART notifies the DMA Controller that a data byte is available in the UART
Receive Data register.
8. The DMA Controller requests control of the system bus from the eZ8 CPU.
9. The eZ8 CPU acknowledges the bus request.
10. The DMA Controller transfers the data from the UART Receive Data register to
another location in RAM and then return bus control back to the eZ8 CPU.
The UART and DMA can continue to transfer incoming data bytes without eZ8 CPU
intervention. When a UART error is detected, the UART Receiver interrupt is generated.
The associated interrupt service routine (ISR) should perform the following:
11. Check the UART Status 0 register to determine the source of the UART error or break
condition and then respond appropriately.
Multiprocessor (9-bit) mode
The UART has a Multiprocessor mode that uses an extra (9th) bit for selective communi-
cation when a number of processors share a common UART bus. In Multiprocessor (9-bit)
mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immedi-
ately following the 8-bits of data and immediately preceding the STOP bit(s) as illustrated
in Figure 70. The character format is:
In Multiprocessor (9-bit) mode, parity is not an option as the Parity bit location (9th bit)
becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers pro-
vide multiprocessor (9-bit) mode control and status information.
Figure 70. UART Asynchronous Multiprocessor (9-bit) Mode Data Format
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 MP
Data Field
lsb msb
Idle State
of Line
STOP Bit(s)
1
2
1
0
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UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates an interrupt anytime the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. Writing to the UART Transmit Data register clears the UART Transmit interrupt.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources.
A break is received.
An overrun is detected.
A data framing error is detected.
Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate
Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans-
mission. The input to the Baud Rate Generator is the system clock. The UARTx Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
UART Data Rate (bits/s) System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value×
----------------------------------------------------------------------------------------------
=
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3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the UARTx Control 1 register to 1.
UART Control Register Definitions
The UART control registers support both the UARTs and the associated Infrared Encoder/
Decoders. For more information on the infrared operation, refer to the Infrared Encoder/
Decoder chapter on page 95.
UARTx Transmit Data Register
Data bytes written to the UARTx Transmit Data register (Table 50) are shifted out on the
TXDx pin. The Write-only UARTx Transmit Data register shares a Register File address
with the Read-only UARTx Receive Data register.
TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
Table 50. UARTx Transmit Data Register (UxTXD)
BITS 76543210
FIELD TXD
RESET XXXXXXXX
R/W WWWWWWWW
ADDR F40H and F48H
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UARTx Receive Data Register
Data bytes received through the RXDx pin are stored in the UARTx Receive Data register
(Table 51). The Read-only UARTx Receive Data register shares a Register File address
with the Write-only UARTx Transmit Data register.
RXD—Receive Data
UART receiver data byte from the RXDx pin
UARTx Status 0 and Status 1 Registers
The UARTx Status 0 and Status 1 registers (Table 52 and 53) identify the current UART
operating configuration and status.
RDA—Receive Data Available
This bit indicates that the UART Receive Data register has received data. Reading the
UART Receive Data register clears this bit.
0 = The UART Receive Data register is empty.
1 = There is a byte in the UART Receive Data register.
PE—Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data regis-
ter clears this bit.
Table 51. UARTx Receive Data Register (UxRXD)
BITS 76543210
FIELD RXD
RESET XXXXXXXX
R/W RRRRRRRR
ADDR F40H and F48H
Table 52. UARTx Status 0 Register (UxSTAT0)
BITS 7 6 5 4 3 2 1 0
FIELD RDAPEOEFEBRKDTDRETXECTS
RESET 000001 1X
R/W RRRRRR R R
ADDR F41H and F49H
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0 = No parity error has occurred.
1 = A parity error has occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data register has not been read. If the RDA bit is reset to
0, then reading the UART Receive Data register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears
this bit.
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data register is empty and ready for additional
data. Writing to the UART Transmit Data register resets this bit.
0 = Do not write to the UART Transmit Data register.
1 = The UART Transmit Data register is ready to receive an additional byte to be transmit-
ted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS signal
When this bit is read it returns the level of the CTS signal.
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Reserved
These bits are reserved and must be 0.
MPRX—Multiprocessor Receive
This status bit is for the receiver and reflects the actual status of the last multiprocessor bit
received. Reading from the UART Data register resets this bit to 0.
UARTx Control 0 and Control 1 Registers
The UARTx Control 0 and Control 1 registers (Tables 54 and 55) configure the properties
of the UART’s transmit and receive operations. The UART Control registers must ben be
written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
Table 53. UARTx Status 1 Register (UxSTAT1)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved MPRX
RESET 000000 00
R/W RRRRRR R R
ADDR F44H and F4CH
Table 54. UARTx Control 0 Register (UxCTL0)
BITS 76543210
FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F42H and F4AH
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CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so insure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
BIRQ—Baud Rate Generator Interrupt Request
This bit sets an interrupt request when the Baud Rate Generator times out and is only set if
a UART is not enabled. The is bit produces no effect when the UART is enabled.
0 = Interrupts behave as set by UART control.
1 = The Baud Rate Generator generates a receive interrupt when it counts down to zero.
MPM—Multiprocessor (9-bit) mode Select
This bit is used to enable Multiprocessor (9-bit) mode.
Table 55. UARTx Control 1 Register (UxCTL1)
BITS 7 6 5 4 3 2 1 0
FIELD BIRQ MPM MPE MPBT Reserved RDAIRQ IREN
RESET 000000 00
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F43H and F4BH
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0 = Disable Multiprocessor mode.
1 = Enable Multiprocessor mode.
MPE—Multiprocessor Enable
0 = The UART processes all received data bytes.
1 = The UART processes only data bytes in which the multiprocessor data bit (9th bit) is
set to 1.
MPBT—Multiprocessor Bit Transmitter
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
Reserved
These bits are reserved and must be 0.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request. The associated DMA will still be notified that
received data is available.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
UARTx Baud Rate High and Low Byte Registers
The UARTx Baud Rate High and Low Byte registers (Tables 56 and 57) combine to create
a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud
rate) of the UART.
Table 56. UARTx Baud Rate High Byte Register (UxBRH)
BITS 76543210
FIELD BRH
RESET 11111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F46H and F4EH
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The UART data rate is calculated using the following equation:
For a given UART data rate, the integer baud rate divisor value is calculated using the fol-
lowing equation:
The baud rate error relative to the desired baud rate is calculated using the following equa-
tion:
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 58 provides information on data rate errors for popular baud rates and commonly
used crystal oscillator frequencies.
Table 57. UARTx Baud Rate Low Byte Register (UxBRL)
BITS 76543210
FIELD BRL
RESET 11111111
R/W R/W R/W R/W R/W R/W R/W R/W R/w
ADDR F47H and F4FH
UART Baud Rate (bits/s) System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value×
----------------------------------------------------------------------------------------------
=
UART Baud Rate Divisor Value (BRG) Round System Clock Frequency (Hz)
16 UART Data Rate (bits/s)×
----------------------------------------------------------------------------
=
UART Baud Rate Error (%) 100 Actual Data Rate Desired Data Rate
Desired Data Rate
-------------------------------------------------------------------------------------------------
⎝⎠
⎛⎞
×=
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Table 58. UART Baud Rates
20.0 MHz System Clock 18.432 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error
(kHz) (Decimal) (kHz) (%) (kHz) (Decimal) (kHz) (%)
1250.0 1 1250.0 0.00 1250.0 1 1152.0 -7.84%
625.0 2 625.0 0.00 625.0 2 576.0 -7.84%
250.0 5 250.0 0.00 250.0 5 230.4 -7.84%
115.2 11 113.6 -1.36 115.2 10 115.2 0.00
57.6 22 56.8 -1.36 57.6 20 57.6 0.00
38.4 33 37.9 -1.36 38.4 30 38.4 0.00
19.2 65 19.2 0.16 19.2 60 19.2 0.00
9.60 130 9.62 0.16 9.60 120 9.60 0.00
4.80 260 4.81 0.16 4.80 240 4.80 0.00
2.40 521 2.40 -0.03 2.40 480 2.40 0.00
1.20 1042 1.20 -0.03 1.20 960 1.20 0.00
0.60 2083 0.60 0.02 0.60 1920 0.60 0.00
0.30 4167 0.30 -0.01 0.30 3840 0.30 0.00
16.667 MHz System Clock 11.0592 MHz System Clock
Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error
(kHz) (Decimal) (kHz) (%) (kHz) (Decimal) (kHz) (%)
1250.0 1 1041.69 -16.67 1250.0 N/A N/A N/A
625.0 2 520.8 -16.67 625.0 1 691.2 10.59
250.0 4 260.4 4.17 250.0 3 230.4 -7.84
115.2 9 115.7 0.47 115.2 6 115.2 0.00
57.6 18 57.87 0.47 57.6 12 57.6 0.00
38.4 27 38.6 0.47 38.4 18 38.4 0.00
19.2 54 19.3 0.47 19.2 36 19.2 0.00
9.60 109 9.56 -0.45 9.60 72 9.60 0.00
4.80 217 4.80 -0.83 4.80 144 4.80 0.00
2.40 434 2.40 0.01 2.40 288 2.40 0.00
1.20 868 1.20 0.01 1.20 576 1.20 0.00
0.60 1736 0.60 0.01 0.60 1152 0.60 0.00
0.30 3472 0.30 0.01 0.30 2304 0.30 0.00
PS017610-0404 UART