EPC2110 Datasheet by EPC

RoHS (A @ Halogen-Free
eGaN® FET DATASHEET EPC2110
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
VDS , 120 V
RDS(on) , 110 mΩ
ID , 3.4 A
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EPC2110 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 1.35 mm x 1.35 mm
Applications
• Ultra High Frequency DC-DC Conversion
• Wireless Power Transfer
• Synchronous Rectification
Benefits
Ultra High Efficiency
Ultra Low RDS(on)
Ultra Low QG
Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2110.aspx
Maximum Ratings of Q1 & Q2
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 120 V
ID
Continuous (TA = 25°C, RθJA = 52°C/W) 3.4 A
Pulsed (25°C, TPULSE = 300 µs) 20
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage –4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Thermal Characteristics of Q1 & Q2
PARAMETER TYP UNIT
R
θ
JC Thermal Resistance, Junction-to-Case 3
°C/W
R
θ
JB Thermal Resistance, Junction-to-Board 25
R
θ
JA Thermal Resistance, Junction-to-Ambient (Note 1) 81
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
EPC2110 – Dual Common-Source
Enhancement-Mode GaN Power Transistor
Static Characteristics of Q1 & Q2 (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.3 mA 120 V
IDSS Drain-Source Leakage VDS = 96 V, VGS = 0 V 0.01 0.25 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.05 1 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.25 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.7 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 4 A 80 110
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
eGaN® FET DATASHEET EPC2110
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2
Dynamic Characteristics of Q1 & Q2 (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VDS = 60 V, VGS = 0 V
85 100
pF
CRSS Reverse Transfer Capacitance 1
COSS Output Capacitance 45 70
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 60 V, VGS = 0 V 54
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 67
RG Gate Resistance 0.6 Ω
QG Total Gate Charge VDS = 60 V, VGS = 5 V, ID = 4 A 0.8 1.1
nC
QGS Gate to Source Charge
VDS = 60 V, ID = 4 A
0.25
QGD Gate to Drain Charge 0.18
QG(TH) Gate Charge at Threshold 0.16
QOSS Output Charge VDS = 60 V, VGS = 0 V 4 6
QRR Source-Drain Recovery Charge 0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
EPC2110 – Detailed Schematic
1
4
5
6
2
3
8
9
D1 D2
G1 G2
S
Q1 Q2
7
Note: The EPC2110 can be connected in parallel or used as independent FETs with common source.
%/ E:
eGaN® FET DATASHEET EPC2110
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3
Capacitance (pF)
100
10
1
0.1
Figure 5b (Q1 & Q2): Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0 20 40 60 80 120100
Capacitance (pF)
0 20 40 60 80 120100
Figure 5a (Q1 & Q2): Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
150
100
50
0
R
DS(on)
Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 2.52.0 3.5 4.0 4.5 5.0
Figure 3 (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents
ID = 1 A
ID = 2A
ID = 4 A
ID = 8 A
300
200
100
0
300
200
100
03.02.52.0 3.5 4.0 4.5 5.0
Figure 4 (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 4 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
20
15
10
5
00 0.5 1.0 1.5 2.0 2.5 3.0
ID
Drain Current (A)
VDS Drain-to-Source Voltage (V)
Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
ID
Drain Current (A)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
VDS = 3 V
VGS – Gate-to-Source Voltage (V)
Figure 2 (Q1 & Q2): Transfer Characteristics
25˚C
125˚C
VDS = 3 V
20
15
10
5
0
Figure 9 (01 81 02): Figure 10 (01 & 02):
eGaN® FET DATASHEET EPC2110
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4
Figure 10 (Q1 & Q2):
Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 0.7 mA
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
20
15
10
5
0
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VGS = 0 V
Figure 9 (Q1 & Q2):
Normalized On-State Resistance vs. Temperature
ID = 4 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
0 0.2 0.4 0.6 0.8 1
Figure 7 (Q1 & Q2): Gate Charge
VGS Gate-to-Source Voltage (V)
QG – Gate Charge (pC)
ID = 4 A
VDS = 60 V
5
4
3
2
1
0
Figure 6a: Output Charge and COSS Stored Energy
QOSS Output Charge (nC)
EOSS COSS Stored Energy (μJ)
7
6
5
4
3
2
1
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0 20 40 60 80 100 120
VDS – Drain-to-Source Voltage (V)
Figure 6 (Q1 & Q2): Output Charge and COSS Stored Energy
Single Pulse fir T
eGaN® FET DATASHEET EPC2110
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Single Pulse
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
Figure 11a (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Board)
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
Single Pulse
tp, Rectangular Pulse Duration, seconds
0.5
0.05
0.02
Single Pulse
0.01
0.1
0.2
Duty Cycle:
10-5
10-6 10-4 10-3 10-2 10-1 1
ZθJC, Normalized Thermal Impedance
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
Figure 11b (Q1 & Q2): Transient Thermal Response Curves (Junction-to-Case)
1
0.1
0.01
0.001
100
10
1
0.1
0.1 1 10 100
1000
ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max rated, TC = +25°C, Single pulse
Limited by RDS(on)
100 µs
Pulse Width
1 ms
100 µs
10 µs
Figure 12 (Q1 & Q2): Safe Operating Area
i $EFELeE: flea Heflefl?‘ —— Dimensionmm) target mln max a 0.00 7.90 8.30 b 1.75 1,65 1.85 c (ssenma) 3.50 3,45 3.55 d 4.00 3,90 4.10 s 4.00 3,90 4.10 f(saannla) 2.00 1,95 2.05 g 1.5 1.5 1.6 5-!—
eGaN® FET DATASHEET EPC2110
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DIE MARKINGS
YYYY
2110
ZZZZ
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
a
d e f g
c
b
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
P1 is under
this corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
EPC2110 (note 1)
Pin 1 is under
this corner
2110
YYYY
ZZZZ EPC2110 2110 YYYY ZZZZ
Die orientation dot
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
Part
Number
Laser Markings
xxxxx
eGaN® FET DATASHEET EPC2110
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 7
DIE OUTLINE
Solder Bump View
Side View
B
A
d c
e
c
d c c
Pad 1 is Gate 1;
Pad 7 is Gate 2;
Pads 2, 3 are Drain 1;
Pads 8, 9 are Drain 2;
Pads 4, 6 are Source;
Pad 5 is Substrate*
*Substrate pin should be
connected to Source
369
258
147
165 +/-17
815 Max
(625)
Seating Plane
Information subject to
change without notice.
Revised August, 2019
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED
LAND PATTERN
(measurements in µm) The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
X9
1350
1350
2 5 8
3 6 9
1 4 7
225
225
450450
450450
200 +20 / - 10 (*)
* minimum 190
RECOMMENDED
STENCIL DRAWING
(measurements in µm) Recommended stencil should be 4 mil (100 µm) thick, must be
laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,reference 88.5%
metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
250
1350
1350
225
225
450450
450450
R60
DIM
Micrometers
MIN Nominal MAX
A1320 1350 1380
B1320 1350 1380
c450 450 450
d210 225 240
e187 208 229