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eGaN® FET DATASHEET EPC2001C
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EPC2001C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High-Frequency DC-DC Conversion
• Industrial Automation
• Synchronous Rectification
• Class-D Audio
• Low Inductance Motor Drives
Benefits
• Ultra High Efficiency
• Ultra Low Switching and Conduction Losses
• Zero QRR
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
EPC2001C – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 7 mΩ
ID , 36 A
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 100 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
ID
Continuous (TA = 25°C, RθJA = 7.3) 36 A
Pulsed (25°C, TPULSE = 300 µs) 150
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 1
°C/W RθJB Thermal Resistance, Junction-to-Board 2
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 54
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 μA 100 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 100 250 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 1 5 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.25
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 5 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 5.6 7 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
0.5 1,5 1 15 0.5 1 1,5 1 2.5 3 3.5 45 11-50 ta ,- e-to n tag 15 1.5 4 45 San ag
eGaN® FET DATASHEET EPC2001C
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ID – Drain Current (A)
VDS Drain-to-Source Voltage (V)
150
120
90
60
30
01 1.5 2 2.5 3
VGS
GS
GS
GS
= 5 V
V = 4 V
V = 3 V
V = 2 V
ID – Drain Current (A)
VGS Gate-to-Source Voltage (V)
150
120
90
60
30
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RDS(on) – Drain to Source Resistance (mΩ)
RDS(on) – Drain to Source Resistance (mΩ)
VGS Gate-to-Source Voltage (V)
20
25
15
10
5
02.5 2 3 3.5 4 4.5 5
VGS Gate-to-Source Voltage (V)
25
15
20
10
5
02.5 2 3 3.5 4 4.5 5
ID = 25 A
25˚C
125˚C
Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics
Figure 3: RDS(on) vs. VGS for Various Currents Figure 4: RDS(on) vs. VGS for Various Temperatures
0 0.5
ID = 10 A
ID = 20 A
ID = 40 A
ID = 80 A
VDS = 3 V
25°C
125°C
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 50 V, VGS = 0 V
770 900
pFCOSS
Output Capacitance
430 650
CRSS
Reverse Transfer Capacitance
10 15
RG
Gate Resistance
0.3 Ω
QG
Total Gate Charge
VDS = 50 V, VGS = 5 V, ID = 25 A 7.5 9
nC
QGS
Gate-to-Source Charge
VDS = 50 V, ID = 25 A
2.4
QGD
Gate-to-Drain Charge
1.2 2
QG(TH)
Gate Charge at Threshold
1.6
QOSS
Output Charge
VDS = 50 V, VGS = 0 V 31 45
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
t In an m :2” :5V 0,5 1 1 S 2 1,5 3 3.5 4 4.5 T, —Jumiun Temperature ( 'E)
eGaN® FET DATASHEET EPC2001C
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Normalized On-State Resistance – RDS(on)
TJ – Junction Temperature ( ˚C )
1.8
2
1.6
1.4
1.2
1
0.8
0.6
0 25 50 75 100 125 150
ID = 25 A
VGS = 5 V
Figure 8: Normalized On Resistance vs. Temperature
Normalized Threshold Voltage
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
0.6
0 25 50 75 100 125 150
ID = 5 mA
Figure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature ( ˚C )
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
ISD – Source to Drain Current (A)
VSD – Source-to-Drain Voltage (V)
12
24
36
48
60
72
25˚C
VGS = 0 V
125˚C
Figure 7: Reverse Drain-Source Characteristics
Capacitance (nF)
VDS – Drain-to-Source Voltage (V)
1.2
1
0.8
0.6
0.4
0.2
00 20 40 60 80 100
Figure 5a: Capacitance (Linear Scale)
Capacitance (nF)
VDS – Drain-to-Source Voltage (V)
0.01
0.1
1
0.001 0 20 40 60 80 100
Figure 5b: Capacitance (Log Scale)
VGS Gate to Source Voltage (V)
QG – Gate Charge (nC)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
00 1 2 3 4 6 5 7 8
ID = 25 A
VDS = 50 V
Figure 6: Gate Charge
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
l , Narmalixed Thermal ImpedarKe Single Pulse Single Pulse
eGaN® FET DATASHEET EPC2001C
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Figure 11: Transient Thermal Response Curves
0.001
0.01
0.1
1
10-5 10-4 10-3 10-2 10-1 1 10
Junction-to-Board
tp - Rectangular Pulse Duration [s]
ZθJB, Normalized Thermal Impedance
Duty Factors:
0.5
0.1
0.05
0.02
0.01
Single Pulse
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
tp
P
T
DM
0.0001
0.001
0.01
0.1
1
Junction-to-Case
Duty Factors:
0.5
0.1
0.05
0.02
0.01
Single Pulse
tp - Rectangular Pulse Duration [s]
Z
θC
, Normalized Thermal Impedance
0.2
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
tp
P
T
DM
10-5 10-4 10-3 10-2 10-1 1 10
IG – Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
25
20
15
10
5
00 1 2 3 4 5 6
25˚C
125˚C
Figure 10: Gate Current
eGaN® FET DATASHEET EPC2001C
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Figure 12: Safe Operating Area
0.1
1
10
100
0.1 1 10 100
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Pulse Width
100 ms
10 ms
1 ms
100 us
limited by RDS(on)
DIE MARKINGS
TAPE AND REEL CONFIGURATION
4 mm pitch, 12 mm wide tape on 7” reel
YYYY
2001
ZZZZ
7” reel
a
d e f g
c
b
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
DIM Dimension (mm)
EPC2001 (Note 1) Target MIN MAX
a12.00 11.90 12.30
b1.75 1.65 1.85
c (Note 2) 5.50 5.45 5.55
d4.00 3.90 4.10
e4.00 3.90 4.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2001C 2001 YYYY ZZZZ
2001
YYYY
ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
x2 VVVUVUVUVU 815 Max x2 x2 x9 I j \
eGaN® FET DATASHEET EPC2001C
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RECOMMENDED
LAND PATTERN
(measurements in µm) Pad no. 1 is Gate;
Pads no. 3, 5, 7, 9, 11 are Drain;
Pads no. 4, 6, 8, 10 are Source;
Pad no. 2 is Substrate.*
*Substrate pin should be connected to Source
The land pattern is solder mask defined.
RECOMMENDED
STENCIL DRAWING
(units in µm) Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
https://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
x2
3
4
5
7
6
9
8
10
11
x9
1
2
1362
1635
802
560
400
4105
400
x8
180 180
Information subject to
change without notice.
Revised April, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
DIE OUTLINE
Solder Bar View
Side View
Pad no. 1 is Gate;
Pads no. 3, 5, 7, 9, 11 are Drain;
Pads no. 4, 6, 8, 10 are Source;
Pad no. 2 is Substrate.*
*Substrate pin should be connected to Source
DIM MICROMETERS
MIN Nominal MAX
A4075 4105 4135
B1602 1635 1662
c1379 1382 1385
d577 580 583
e235 250 265
f195 200 205
g400 400 400
B
A
d
x2
c
e g
3
4
5
7
6
9
8
10
11
g
x8
f f
x9
2
1
815 Max
100 +/- 20
Seating Plane
(685)
x2
3
4 5
7
6
9
8
10
11
x9
1
2
1362
1635
560
400
4105
400
x8
180 180
R60

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