VTM48EH120x010B00 Datasheet by Vicor Corporation

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@ I®C€ [See AQthatmn Note AN:024 VICI-IIF’ High perfmmam ?cwer Mndu/es
VTM®Current Multiplier
High Efficiency, Sine Amplitude Converter™
S
NRTL
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VTM®Current Multiplier Rev 1.2 vicorpower.com
Page 1 of 16 08/2015 800 927.9474
FEATURES
48 Vdc to 12 Vdc 10 A current multiplier
- Operating from standard 48 V or 24 V PRM modules
High efficiency (> 95 %) reduces system power
consumption
High density ( 901 W /in3)
Half Chip ” VI Chip®package enables surface mount,
low impedance interconnect to system board
Contains built-in protection features against:
- Overvoltage
- Overcurrent
- Short Circuit
- Overtemperature
Provides enable / disable control, internal temperature
monitoring, current monitoring
ZVS / ZCS resonant Sine Amplitude Converter topology
Less than 50ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
High End Computing Systems
Automated Test Equipment
High Density Power Supplies
Communications Systems
0
DESCRIPTION
The VI Chip current multiplier is a high efficiency (> 95 %)
Sine Amplitude Converter™ (SAC™) operating from a
26 to 55 Vdc primary bus to deliver an isolated output.
The Sine Amplitude Converter offers a low AC impedance
beyond the bandwidth of most downstream regulators, which
means that capacitance normally at the load can be located
at the input to the Sine Amplitude Converter. Since the K factor
of the VTM48EH120T010B00 is 1/4 , that capacitance value can
be reduced by a factor of 16 , resulting in savings of board area,
materials and total system cost.
The VTM48EH120T010B00 is provided in a VI Chip package
compatible with standard pick-and-place and surface mount
assembly processes. The co-molded VI Chip package provides
enhanced thermal management due to large thermal interface
area and superior thermal conductivity. With high conversion
efficiency the VTM48EH120T010B00 increases overall system
efficiency and lowers operating costs compared to conventional
approaches.
The VTM48EH120T010B00 enables the utilization of Factorized
Power Architecture providing efficiency and size benefits by
lowering conversion and distribution losses and promoting high
density point of load conversion.
VIN
L
O
A
D
PR
PC
VC
TM
IL
OS
SG
PRM®
CD
-Out
+Out
-In
+In
PC
VTM®
IM
VC TM
-Out
+Out
-In
+In
Regulator Current Multiplier
Factorized Power Architecture™
VIN = 26 to 55 V
VOUT = 6.5 to 13.8 V(NO LOAD)
IOUT = 10 A(NOM)
K= 1/4
(See Application Note AN:024)
PART NUMBER PRODUCT GRADE
T= -40° to 125°C
M= -55° to 125°C
PART NUMBERING
For Storage and Operating Temperatures see Section 6.0 General Characteristics
120 x 010 B00
HVTM E 48
120 010 B00 x E H 48 VTM
2 E c _. E VlCII—IIP High Pellarmame PowerModu/e;
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120 010 B00 x E H 48 VTM
ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
Input Voltage Range VIN No external VC applied 26 55 VDC
VC applied 0 55
VIN Slew Rate dVIN /dt 1 V/µs
VIN UV Turn Off VIN_UV Module latched shutdown, 19.2 26.0 V
No external VC applied, IOUT = 10 A
No Load power dissipation PNL
VIN = 48 V 0.8 4.1
W
VIN = 26 V to 55 V 5
VIN = 48 V, TC= 25ºC 2.0 2.8
VIN = 26 V to 55 V, TC= 25ºC 4
Inrush current peak IINRP VC enable, VIN = 48 V COUT = 500 µF, 8 12 A
RLOAD = 1162 mΩ
DC input current IIN_DC 2.7 A
Transfer ratio K K = VOUT/V
IN, IOUT = 0 A 1/4 V/V
Output voltage VOUT VOUT = VIN K - IOUT ROUT, Section 11 V
Output current (average) IOUT_AVG 10 A
Output current (peak) IOUT_PK TPEAK < 10 ms, IOUT_AVG 10 A 12.5 A
Output power (average) POUT_AVG IOUT_AVG 10 A 135 W
VIN = 48 V, IOUT = 10 A 93.5 94.7
Efficiency (ambient) hAMB VIN = 26 V to 55 V, IOUT = 10 A 90.0 %
VIN = 48 V, IOUT = 5 A 94.0 94.9
Efficiency (hot) hHOT VIN = 48 V, TC= 100°C, IOUT = 10 A 92.6 94.1 %
Efficiency (Over load range) h20% 2 A < IOUT < 10 A 72.0 %
Output resistance (Cold) ROUT_COLD TC= -40°C, IOUT = 10 A 20.0 26.9 40.0 mΩ
Output resistance (Ambient) ROUT_AMB TC= 25°C, IOUT = 10 A 25 38.3 50.0 mΩ
Output resistance (Hot) ROUT_HOT TC= 100°C, IOUT = 10 A 30.0 47.1 60.0 mΩ
Switching frequency FSW 1.40 1.50 1.60 MHz
Output ripple frequency FSW_RP 2.80 3.00 3.20 MHz
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 10 A, VIN = 48 V, 200 400 mV
20 MHz BW, Section 12
Output inductance (parasitic) LOUT_PAR Frequency up to 30 MHz, 600 pH
Simulated J-lead model
Output capacitance (internal) COUT_INT VOUT = 12 V 20 µF
Output capacitance (external) COUT_EXT VTM Standalone Operation 500 µF
VIN pre-applied, VC enable
PROTECTION
OVLO VIN_OVLO+Module latched shutdown 55.1 58.7 60 V
Overvoltage lockout TOVLO Effective internal RC filter 2.4 µs
response time
Output overcurrent trip IOCP 12 19 24 A
Short circuit protection trip current ISCP 24 A
Output overcurrent response TOCP Effective internal RC filter (Integrative). 5.3 ms
time constant
Short circuit protection response time TSCP From detection to cessation 1 µs
of switching (Instantaneous)
Thermal shutdown setpoint TJ_OTP 125 130 135 ºC
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25ºC unless otherwise noted.
MIN MAX UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . . -1.0 60 VDC
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 7 VDC
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
MIN MAX UNIT
IM to - IN................................................. 0 3.15 VDC
+ IN / - IN to + OUT / - OUT (hipot)........ 2250 VDC
+ OUT to - OUT....................................... -1.0 16 VDC
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120 010 B00 x E H 48 VTM
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
External VC voltage VVC_EXT Required for startup, and operation
11.5 16.5 V
below 26 V. See Section 7.
VC current draw threshold VVC_TH Low VC current draw for VIN > 26 V 12 V
VC = 12 V, VIN = 0 V 71 150
Steady VC current draw IVC VC = 12 V, VIN > 26 V 21 mA
VC = 16.5 V, VIN > 26 V 75
VC internal resistor RVC-INT 2.05 kΩ
ANALOG Start Up VC slew rate dVC/dt Required for proper startup; 0.02 0.25 V/µs
INPUT VC inrush current IINR_VC VC = 16.5 V, dVC/dt = 0.25 V/µs 750 mA
VC output turn-on delay TON VIN pre-applied, PC floating, VC enable 500 µs
Transitional
CPC = 0 µF, COUT = 500 µF
VC to PC delay TVC_PC VC = 11.5 V to PC high, VIN = 0 V,
10 25 µs
dVC/dt = 0.25 V/µs
Internal VC capacitance CVC_INT VC = 0 V 2.2 µF
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
PC voltage VPC 4.7 5.0 5.3 V
ANALOG Steady PC source current IPC_OP 2 mA
OUTPUT PC resistance (internal) RPC_INT Internal pull down resistor 50 150 400 kΩ
Start Up
PC source current IPC_EN 50 100 300 µA
PC capacitance (internal) CPC_INT Section 7 588 pF
PC resistance (external) RPC_EXT 60 kΩ
Enable PC voltage (enable) VPC_EN 2 2.5 3 V
DIGITAL Disable PC voltage (disable) VPC_DIS 2 V
INPUT / OUTPUT
PC pull down current IPC_PD 5.1 mA
Transitional PC disable time TPC_DIS_T 4 µs
PC fault response time TFR_PC From fault to PC = 2 V 100 µs
Used to wake up powertrain circuit.
A minimum of 11.5 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
VC slew rate must be within range for a successful start.
•PRM
®VC can be used as valid wake-up signal source.
VC voltage may be continuously applied;
there will be minimal VC current drawn when VIN > 26 V and VC < 12 .
Internal resistance used in adaptive loop compensation
VTM CONTROL : VC
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25°C unless otherwise noted.
The PC pin enables and disables the VTM.
When held below 2 V, the VTM will be disabled.
PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
during fault mode given VIN > 26 V and VC > 11.5 V.
After successful start-up and under no fault condition, PC can be used as
a 5 V regulated voltage source with a 2 mA maximum current.
Module will shutdown when pulled low with an impedance
less than 400 Ω.
In an array of VTMs, connect PC pin to synchronize startup.
PC pin cannot sink current and will not disable other module
during fault mode.
PRIMARY CONTROL : PC
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
TM voltage VTM_AMB TJcontroller = 27°C 2.95 3.00 3.05 V
ANALOG TM source current ITM 100 µA
OUTPUT Steady TM gain ATM 10 mV/°C
TM voltage ripple VTM_PP CTM = 0 F, VIN = 48 V, 120 200 mV
IOUT = 10 A
Disable TM voltage VTM_DIS 0 V
DIGITAL OUTPUT TM resistance (internal) RTM_INT Internal pull down resistor 25 40 50 kΩ
Transitional TM capacitance (external) CTM_EXT 50 pF
(FAULT FLAG) TM fault response time TFR_TM From fault to TM = 1.5 V 10 µs
The TM pin monitors the internal temperature of the VTM controller IC
within an accuracy of ±5°C.
Can be used as a "Power Good" flag to verify that the VTM is operating.
The TM pin has a room temperature setpoint of 3 V (@27°C)
and approximate gain of 10 mV/ °C.
TEMPERATURE MONITOR : TM
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120 010 B00 x E H 48 VTM
4.0 TIMING DIAGRAM
12
7
VPRI
1. Initiated VC pulse
2. Controller start
3. VPRI ramp up
4. VPRI = VOVLO
5. VPRI ramp down no VC pulse
6. Overcurrent, Secondary
7. Start up on short circuit
8. PC driven low
VSEC
PC
3 V
VC
NL
5 V
VOVLO
TM
VTM-AMB
c
Notes:
– Timing and voltage is not to scale
– Error pulse width is load dependent
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: TOVLO_PIN
d: TOCP_SEC
e: Secondary turn on delay (TON)
f: PC disable time (TPC_DIS_T)
g: VC to PC delay (TVC_PC)
d
ISEC
ISEC
ISEC
VVC-EXT
345
6
a
b
8
g
ef
≥ 26 V
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
IM voltage (no load) VIM_NL TC= 25ºC, VIN = 48 V, IOUT = 0 A 0.06 0.38 0.5 V
IM voltage (50%) VIM_50% TC= 25ºC, VIN = 48 V, IOUT = 5 A 1.17 V
ANALOG Steady IM voltage (full load) VIM_FL TC= 25ºC, VIN = 48 V, IOUT = 10 A 2.03 V
OUTPUT IM gain AIM TC= 25ºC, VIN = 48 V, IOUT > 5 A 172 mV/A
IM resistance (external) RIM_EXT 2.5 MΩ
The nominal IM pin voltage varies between 0.38 V and 2.03 V
representing the output current within ±25% under all operating line
temperature conditions between 50% and 100%.
The IM pin provides a DC analog voltage proportional to
the output current of the VTM.
CURRENT MONITOR : IM
3.0 SIGNAL CHARACTERISTICS (CONT.)
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25°C unless otherwise noted.
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120 010 B00 x E H 48 VTM
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TC= 25ºC unless otherwise noted. See associated figures
for general trend data.
ATTRIBUTE SYMBOL CONDITIONS / NOTES TYP UNIT
No load power dissipation PNL VIN = 48 V 2.1 W
Efficiency (ambient) hAMB VIN = 48 V, IOUT = 10 A 94.5 %
Efficiency (hot) hHOT VIN = 48 V, IOUT = 10 A, TC= 100ºC 94.0 %
Output resistance (ambient) ROUT_AMB VIN = 48 V, IOUT = 10 A 50.1 mΩ
Output resistance (hot) ROUT_HOT VIN = 48 V, IOUT = 10 A, TC= 100ºC 57.4 mΩ
Output resistance (cold) ROUT_COLD VIN = 48 V, IOUT = 10 A, TC= -40ºC 40.7 mΩ
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 10 A, VIN = 48 V,
261 mV
20 MHz BW, Section 12
VOUT Transient (positive) VOUT_TRAN+IOUT_STEP = 0 A TO 10 A, VIN = 48 V,
100 mV
ISLEW > 10 A /us
VOUT Transient (negative) VOUT_TRAN-IOUT_STEP = 10 A to 0 A, VIN = 48 V
100 mV
ISLEW > 10 A /us
No Load Power Dissipation vs. Line
No Load Power Dissipation (W)
-40ºC 25ºC 100ºC
T :
CASE
26 29 32 36 39 42 45 49 52 55
Input Voltage (V)
0.5
1
1.5
2
2.5
3
3.5
4
Full Load Efficiency (%)
Case Temperature (C)
26 V 48 V 55 V
V :
IN
89
90
91
92
93
94
95
96
-40 -20 0 20 40 60 80 100
Full Load Efficiency vs. TCASE
80
84
88
92
96
012345678910
0
2
4
6
8
Efficiency (%)
Power Dissipation (W)
Efficiency & Power Dissipation -40°C Case
P
D
10
12
76
72
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Load Current (A)
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Efficiency and Power Dissipation 25ºC Case
Efficiency (%)
Power Dissipation (W)
Load Current (A)
80
84
88
92
96
012345678910
0
2
4
6
8
10
12
76
72
P
D
Figure 1 — No load power dissipation vs. VIN Figure 2 — Full load efficiency vs. temperature
Figure 3 — Efficiency and power dissipation at –40°C Figure 4 — Efficiency and power dissipation at 25°C
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120 010 B00 x E H 48 VTM
012345678910
-40ºC 25ºC 100ºC
IM Voltage vs. Load at VIN = 48 V
IM (V)
TCASE:
Load Current (A)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output voltage Ripple vs. Load
Ripple (mV pk-pk)
Load Current (A)
48 V 26 V 55 V
V :
IN
50
75
100
125
150
175
200
225
250
275
300
0 1 2 3 4 5 6 7 8 9 10
Figure 8 IM voltage vs. load
IM Voltage vs. Load 25°C Case
012345678910
26ºC 48ºC 55ºC
IM (V)
TCASE:
Load Current (A)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Figure 9 IM voltage vs. load
Figure 7 — VRIPPLE vs. IOUT ; No external COUT. Board mounted
module, scope setting: 20 MHz analog BW
TCASE (°C)
IM (V)
-40 -20 0 20 40 60 80 100
26 V 48 V 55 VVIN
IM Voltage vs. TCASE & Line
1
1.2
1.4
1.6
1.8
2
2.2
Load Current (A)
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Efficiency & Power Dissipation 100°C Case
Efficiency (%)
Power Dissipation (W)
80
84
88
92
96
012345678910
0
2
4
6
8
10
12
76
72
P
D
I :
OUT 10 A
Case Temperature (C)
Rout (m )
ROUT vs. TCASE at VIN = 48 V
-40 -20 0 20 40 60 80 100
25
30
35
40
45
50
55
60
Figure 5 — Efficiency and power dissipation at 100°C Figure 6 — ROUT vs. temperature
Figure 10 Full load IM voltage vs. TCASE
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120 010 B00 x E H 48 VTM
Figure 13 Start up from application of VIN ; VC pre-applied
COUT = 500 µF
Figure 16 — 10 A – 0 A transient response:
CIN = 100 µF, no external COUT
Figure 15 0 A – 10 A transient response:
CIN = 100 µF, no external COUT
0
2
4
6
8
10
12
14
16
18
20
02468101214
Safe Operating Area
Output Voltage (V)
Output Current (A)
10 ms Max
Continuous
Figure 11 Safe operating area Figure 12 Full load ripple, 100 µF CIN; No external COUT. Board
mounted module, scope setting : 20 MHz analog BW
Figure 14 — Start up from application of VC; VIN pre-applied
COUT = 500 µF
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120 010 B00 x E H 48 VTM
ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
MECHANICAL
Length L 21.7 / [ 0.85 ] 22.0 / [ 0.87 ] 22.3 / [ 0.88 ] mm/[in]
Width W 16.4 / [ 0.64 ] 16.5 / [ 0.65 ] 16.6 / [ 0.66 ] mm/[in]
Height H 6.48 / [ 0.255 ] 6.73 / [ 0.265 ] 6.98 / [ 0.275 ] mm/[in]
Volume Vol No heat sink 2.44 / [ 0.150 ]cm
3/[in3]
Weight W 8.0 / 0.28 g/[oz]
Nickel 0.51 2.03
Lead finish Palladium 0.02 0.15 µm
Gold 0.003 0.051
THERMAL
Operating temperature TJ VTM48EH120T010B00 (T-Grade) -40 125 °C
VTM48EH120M010B00 (M-Grade) -55 125 °C
Thermal capacity 5 Ws/°C
ASSEMBLY
Peak compressive force Supported by J-lead only 2.5 3 lbs
Applied to case (Z-axis)
Storage temperature TST VTM48EH120T010B00 (T-Grade) -40 125 °C
VTM48EH120M010B00 (M-Grade) -65 125 °C
ESDHBM
1500
ESD withstand
ESDMM
400
VDC
SOLDERING
Peak temperature during reflow MSL 4 (Datecode 1528 and later) 245 °C
Peak time above 217°C 60 90 s
Peak heating rate during reflow 1.5 3 °C/s
Peak cooling rate post reflow 1.5 6 °C/s
SAFETY
Isolation voltage (hipot) VHIPOT 2250 VDC
Isolation capacitance CIN_OUT Unpowered Unit 1350 1750 2150 pF
Isolation resistance RIN_OUT 10 MΩ
MTBF MIL HDBK 217, 25ºC, 5.0 MHrs
Ground Benign
cTÜVus
Agency approvals/ standards cURus
CE Marked for low voltage directive and RoHS recast directive, as applicable
Human Body Model,
"JEDEC JESD 22-A114C.01"
Machine Model,
"JEDEC JESD 22-A115-A"
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40ºC < TJ< 125ºC (T-Grade); All Other specifications are at TJ= 25°C unless otherwise noted.
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120 010 B00 x E H 48 VTM
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
The VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry when within the specified voltage range
of 11.5 V to 16.5 V. This voltage is required in order for the
VTM module to start, and must be applied as long as the input
is below 26 V. In order to ensure a proper start, the slew rate of
the applied voltage must be within the specified range.
Some additional notes on the using the VC pin:
In most applications, the VTM module will be powered
by an upstream PRM®which provides a 10 ms VC pulse
during startup. In these applications the VC pins of the PRM
and VTM should be tied together.
The VC voltage can be applied indefinitely allowing for
continuous operation down to 0 VIN.
The fault response of the VTM module is latching.
A positive edge on VC is required in order to restart the unit.
If VC is continuously applied the PC pin may be toggled
to restart the module.
Primary Control (PC) pin can be used to accomplish the
following functions:
Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 400 Ω.
Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
Current Monitor (IM) pin provides a voltage proportional to
the output current of the VTM module. The nominal voltage
will vary between 0.38 V and 2.03 V over the output current
range of the module (See Figures 8–10). The accuracy of the
IM pin will be within 25% under all line and temperature
conditions between 50% and 100% load.
8.0 STARTUP BEHAVIOR
Depending on the sequencing of the VC with respect to the
input voltage, the behavior during startup will vary as follows:
Normal Operation (VC applied prior to VIN): In this case the
controller is active prior to ramping the input. When the
input voltage is applied, the VTM output voltage will track
the input (See Figure 13). The inrush current is determined by
the input voltage rate of rise and output capacitance. If the
VC voltage is removed prior to the input reaching 26 V, the
VTM module may shut down.
Stand Alone Operation (VC applied after VIN): In this case the
module output will begin to rise upon the application of the
VC voltage (See Figure 14). The Adaptive Soft Start circuit
(See Section 10) may vary the ouput rate of rise in order to
limit the inrush current to it’s maximum level. When starting
into high capacitance, or a short, the output current will be
limited for a maximum of 900 µsec. After this period, the
adaptive soft start circuit will time out and the module
may shut down. No restart will be attempted until VC is
re-applied, or PC is toggled. The maximum output
capacitance is limited to 500 µF in this mode of operation
to ensure a sucessful start.
9.0 THERMAL CONSIDERATIONS
VI Chip®products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
VTM48EH120T010B00 case to less than 100ºC will keep all
junctions within the VI Chip below 125ºC for most
applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a VI Chip module for an
extended period of time at full load without proper heat
sinking.
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120 010 B00 x E H 48 VTM
+VOUT
-VOUT
Modulator
+VIN
Fast
current
limit
Slow
current
limit
Vref
PC
Enable
-VIN
2.5 V
100 uA
5 V
2 mA
150 K
40 K
560 pF
10.5 V
Gate
Drive
Supply
2.5 V
Primary Current
Sensing
PC Pull-Up
& Source
Temperature
dependent
voltage source
Overcurrent
Protection
Primary Stage &
Resonant Tank
1.5 k
VC
Buck
Regulator
Supply
Primary
Gate
Drive
Enable
Fault Logic
OVLO
UVLO
VIN
TM
Secondary
Gate Drive
Power
Transformer
Synchronous
Rectification
VREF
(130ºC ± 5°C)
Over
Temperature
Protection
Enable
Adaptive
Soft Start
Q1
Q2 C2
C1
Lr Cr
Q3 Q4
COUT
Enable
CIN
Rvc
18 V
IM
3 V max.
240 µA max.
10.0 VTM MODULE BLOCK DIAGRAM
‘44WW—‘ 004mg :3 44% VI CHIP High Pellarmams PowerModu/ex
VTM®Current Multiplier Rev 1.2 vicorpower.com
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11.0 SINE AMPLITUDE CONVERTER™ POINT OF LOAD CONVERSION
The Sine Amplitude Converter (SAC™) uses a high frequency
resonant tank to move energy from input to output. (The
resonant tank is formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM™ Module
Block Diagram. See Section 10). The resonant LC tank,
operated at high frequency, is amplitude modulated as
function of input voltage and output current. A small amount
of capacitance embedded in the input and output stages of
the module is sufficient for full functionality and is key to
achieving power density.
The VTM48EH120T010B00 SAC can be simplified into the
following model:
At no load:
VOUT = VIN K (1)
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
K= VOUT (2)
VIN
In the presence of load, VOUT is represented by:
VOUT = VIN K – IOUT ROUT (3)
and IOUT is represented by:
IOUT =IIN –I
Q(4)
K
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input and output MOSFETs and the winding
resistance of the power transformer. IQrepresents the
quiescent current of the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming for the moment that
ROUT = 0 Ωand IQ= 0 A, Eq. (3) now becomes Eq. (1) and is
essentially load independent. A resistor R is now placed in
series with VIN as shown in Figure 18.
The relationship between VIN and VOUT becomes:
VOUT = (VIN –I
IN R) K (5)
Substituting the simplified version of Eq. (4)
(IQis assumed = 0 A) into Eq. (5) yields:
VOUT = VIN K – IOUT R K2(6)
+
+
VOUT
COUT
VIN
V•I
K
+
+
CIN
IOUT
RCOUT
IQ
ROUT
RCIN
0.042 A
1/4 • IOUT 1/4 • VIN
38.3 mΩ
RCIN
6.3 mΩ
1040 pH
3125 mΩRCOUT
650 µΩ
20 µF
LOUT = 600 pH
900 nF
IQ
LIN = 3.7 nH IOUT ROUT
VIN VOUT
R
SAC
K = 1/32
Vin
Vout
+
VIN VOUT
R
SAC™
K = 1/32
Figure 18 — K = 1/32 Sine Amplitude Converter™
with series input resistor
Figure 17 — VI Chip®module AC model
COUT
CIN
Rom VlCII—IIP High Pelrannams Power Module:
VTM®Current Multiplier Rev 1.2 vicorpower.com
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120 010 B00 x E H 48 VTM
This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC™. However,
in this case a real R on the input side of the SAC is effectively
scaled by K2with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
side is 0.98 mΩ, with K = 1/32 as shown in Figure 18.
A similar exercise should be performed with the additon of a
capacitor, or shunt impedance, at the input to the SAC. A
switch in series with VIN is added to the circuit. This is depicted
in Figure 19.
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C dVIN (7)
dt
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC=I
OUT K (8)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =CdVOUT (9)
K2dt
Writing the equation in terms of the output has yielded a K2
scaling factor for C, this time in the denominator of the
equation. For a K factor less than unity, this results in an
effectively larger capacitance on the output when expressed in
terms of the input. With a K=1/32 as shown in Figure 19,
C=1 µF would effectively appear as C=1024 µF when viewed
from the output.
Low impedance is a key requirement for powering a high-
current, low-voltage load efficiently. A switching regulation
stage should have minimal impedance, while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit, scaling down series impedance
leading back to the source and scaling up shunt capacitance
(or energy storage) as a function of its K factor squared.
However, these benefits are not useful if the series impedance
of the SAC is too high. The impedance of the SAC must be low
well beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables magnetic
components to be small since magnetizing currents remain
low. Small magnetics mean small path lengths for turns. Use of
low loss core material at high frequencies reduces core losses
as well.
The two main terms of power loss in the VTM®module are:
-No load power dissipation (PNL): defined as the power
used to power up the module with an enabled power
train at no load.
-Resistive loss (ROUT): refers to the power loss across the
VTM current multiplier modeled as pure resistive impedance.
PDISSIPATED = PNL + PROUT (10)
Therefore,
POUT = PIN –P
DISSIPATED = PIN –P
NL –P
ROUT (11)
The above relations can be combined to calculate the overall
module efficiency:
h=POUT =PIN –P
NL –P
ROUT (12)
PIN PIN
=VIN IIN –P
NL –(I
OUT)2ROUT
VIN IIN
=1
(
PNL + (IOUT)2ROUT
)
VIN IIN
C
S
SAC
K = 1/32
Vin
Vout
+
VIN VOUT
C
SAC™
K = 1/32
Figure 19 — Sine Amplitude Converter™ with input capacitor
S
VICHIP High Perfmmante Pawn! Module:
VTM®Current Multiplier Rev 1.2 vicorpower.com
Page 13 of 16 08/2015 800 927.9474
120 010 B00 x E H 48 VTM
12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC™ system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM module dynamic
response, the impedance presented to its input terminals
must be low from DC to approximately 5 MHz. Input
capacitance may be added to improve transient
performance or compensate for high source impedance.
2.Further reduce input and /or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the module multiplied by its
K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The VI Chip®module input/output voltage ranges must
not be exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it.
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTER
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter™ on the
system as a whole. Both the capacitance value, and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the SAC
contains several terms:
Resonant tank impedance
Input lead inductance and internal capacitance
Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model but for
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM module reflect
back to the input of the module by the square of the K factor
(Eq. 9) with the impedance of the module appearing in series.
It is very important to keep this in mind when using a PRM™
regulator to power the VTM. Most PRM®regulators have a
limit on the maximum amount of capacitance that can be
applied to the output. This capacitance includes both the
regulator output capacitance and the current multiplier output
capacitance reflected back to the input. In PRM regulator remote
sense applications, it is important to consider the reflected value
of VTM current multiplier output capacitance when designing
and compensating the PRM regulator control loop.
Capacitance placed at the input of the VTM module appear to
the load reflected by the K factor, with the impedance of the
VTM module in series. In step-down VTM ratios, the effective
capacitance is increased by the K factor. The effective ESR of
the capacitor is decreased by the square of the K factor, but
the impedance of the VTM module appears in series. Still, in
most step-down VTM modules an electrolytic capacitor placed
at the input of the module will have a lower effective
impedance compared to an electrolytic capacitor placed at the
output. This is important to consider when placing capacitors
at the output of the current multiplier. Even though the
capacitor may be placed at the output, the majority of the AC
current will be sourced from the lower impedance, which in
most cases will be the VTM current multiplier. This should be
studied carefully in any system design using a VTM current
multiplier. In most cases, it should be clear that electrolytic
output capacitors are not necessary to design a stable, well-
bypassed system.
For further detar‘s see AN:016 Using BCMQ Bus Converters in Hrgh Power Arrays |:| _ , vW CI 43 VlCII—IIP High Pelrannams Power Module:
VTM®Current Multiplier Rev 1.2 vicorpower.com
Page 14 of 16 08/2015 800 927.9474
120 010 B00 x E H 48 VTM
VIN VOUT
+
DC
ZIN_EQ1
ZIN_EQ2
ZOUT_EQ1
ZOUT_EQ2
Load
VTM®1
RO_1
VTM®2
RO_2
VTM®n
RO_n
ZOUT_EQn
ZIN_EQn
Figure 20 — VTM module array
14.0 CURRENT SHARING
The SAC™ topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the VTM
module will inherently share the load current with parallel
units, according to the equivalent impedance divider that the
system implements from the power source to the point of load.
Some general recommendations to achieve matched array
impedances:
Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
Provide the PCB layout as symmetric as possible.
Apply same input / output filters (if present) to each unit.
For further details see AN:016 Using BCM® Bus Converters
in High Power Arrays.
15.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
VI Chip®products are not internally fused. Input line fusing of
VI Chip products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
Current rating (usually greater than maximum
VTM module current)
Maximum voltage rating (usually greater than the maximum
possible input voltage)
Ambient temperature
Nominal melting I2t
16.0 REVERSE OPERATION
The VTM48EH120T010B00 is capable of reverse operation.
If a voltage is present at the output which satisfies the
condition VOUT > VIN K at the time the VC voltage is applied,
or after the unit has started, then energy will be transferred
from secondary to primary. The input to output ratio will be
maintained. The VTM48EH120T010B00 will continue to
operate in reverse as long as the input and output are within
the specified limits. The VTM48EH120T010B00 has not been
qualified for continuous operation (>10 ms) in the reverse
direction.
TOP VIEW (COMPONENT SIDE) m was m ”71 Llassmm *‘xm fl ‘0‘ BUTTON VIEW 3 E a E \w\ m mm! A ‘\ m [mm a f m f [1711 ‘7‘ ”- E3 ;2\ an.“ n m ms 5— sEmNa ME 7 Hwy 1 ms [mum pa: :smom may mm mm A mm c ‘ m 5m: m 1 3m. m1 m n w FL ‘ a; my: U751} mm 125001015an LAND PATTERN (COMPONENT SIDE 511mm) i 3: 4L 1 7"“ A no a "(£12153 7”“ m FL. {:39} 2M k '0 am [my] ”a :1) PL mgr “571 m A1731, A252 522:] a n L E1 TM F2 vc m < ms="" mmw="" pa»="" [swam="" wzsr="" nswsm="" pc="" hz="" m="" mm="" a3433,="" aavda="" om="" j="" mba="" ma="" :weee="" mm="" 7:1“="" 1="" 3;:3';="" ¢="" vichip="" n/gh="" pellarmame="" power="" madu/ex="">
VTM®Current Multiplier Rev 1.2 vicorpower.com
Page 15 of 16 08/2015 800 927.9474
120 010 B00 x E H 48 VTM
inch
mm
NOTES:
.
DIMENSIONS ARE .
2.
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3.
PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
4
17.2 RECOMMENDED LAND PATTERN
17.1 MECHANICAL DRAWING
mm
(inch)
Notes:
1. Maintain 3.50 (0.138) Dia. keep-out zone
free of copper, all PCB layers.
2. (A) minimum recommended pitch is 24.00 (0.945)
this provides 7.50 (0.295) component
edge–to–edge spacing, and 0.50 (0.020)
clearance between Vicor heat sinks.
(B) Minimum recommended pitch is 25.50 (1.004).
This provides 9.00 (0.354) component
edge–to–edge spacing, and 2.00 (0.079)
clearance between Vicor heat sinks.
3. V•I Chip™ module land pattern shown
for reference only, actual land pattern may differ.
Dimensions from edges of land pattern
to push–pin holes will be the same for
all half size V•I Chip Products.
4. RoHS compliant per CST–0001 latest revision.
5. Unless otherwise specified:
Dimensions are mm (inches)
tolerances are:
x.x (x.xx) = ±0.13 (0.01)
x.xx (x.xxx) = ±0.13 (0.005)
6. Plated through holes for grounding clips (33855)
shown for reference. Heat sink orientation and
device pitch will dictate final grounding solution. (NO GROUNDING CLIPS) (WITH GROUNDING CLIPS)
17.3 RECOMMENDED HEAT SINK PUSH PIN LOCATION
PC
VC
TM
IM
Bottom View
4 3 2 1
+Out
-Out
+In
-In
A
B
C
D
J
K
L
M
E
F
G
H
A1-B1, A2-B2
L1-M1, L2-M2
E1
F2
G1
H2
A3-D3, A4-D4
J3-M3, J4-M4
Signal
Name Designation
+In
–In
IM
TM
VC
PC
+Out
–Out
Customer Service: (ustserv@vlcorgower,com Technica‘ Support: appsfivlcorgowemom VICI—IIP High Performams Power Module;
VTM®Current Multiplier Rev 1.2 vicorpower.com
Page 16 of 16 08/2015 800 927.9474
120 010 B00 x E H 48 VTM
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes
to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to
be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent
Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each
product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express
Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not
transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL
REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO
THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR
PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for
collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no
liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating
safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to
obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the
buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR
WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or
systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical
component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components in life
support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
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Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products
described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this
document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263;
7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965.
Vicor Corporation
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email
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