ADP7118 Datasheet by Analog Devices Inc.

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ANALOG DEVICES ADP7118 RRRRR uuuuuuuuuuuuuuuu 4-)

20 V, 200 mA, Low Noise,

CMOS LDO Linear Regulator

Data Sheet

ADP7118

Rev. F Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

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Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Low noise: 11 µV rms independent of fixed output voltage

PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,

VOUT ≤ 5 V, VIN = 7 V

Input voltage range: 2.7 V to 20 V

Maximum output current: 200 mA

Initial accuracy: ±0.8%

Accuracy over line, load, and temperature

−1.2% to +1.5%, TJ = −40°C to +85°C

±1.8%, TJ = −40°C to +125°C

Low dropout voltage: 200 mV (typical) at a 200 mA load,

VOUT = 5 V

User programmable soft start (LFCSP and SOIC only)

Low quiescent current, IGND = 50 μA (typical) with no load

Low shutdown current: 1.8 μA at VIN = 5 V, 3.0 μA at VIN = 20 V

Stable with a small 2.2 µF ceramic output capacitor

Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, 4.5 V, and 5.0 V

16 standard voltages between 1.2 V and 5.0 V are available

Adjustable output from 1.2 V to VIN – VDO, output can be

adjusted above initial set point

Precision enable

2 mm × 2 mm, 6-lead LFCSP, 8-Lead SOIC, 5-Lead TSOT

AEC-Q100 qualified for automotive applications

APPLICATIONS

Regulation to noise sensitive applications

ADC and DAC circuits, precision amplifiers, power for

VCO VTUNE control

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

Supported by ADIsimPower tool

TYPICAL APPLICATION CIRCUITS

GND

EN SS

VIN VOUT

ADP7118

OFF

VIN = 6V VOUT = 5V

SENSE/ADJ

CIN

2.2µF COUT

2.2µF

CSS

1nF

11849-001

Figure 1. ADP7118 with Fixed Output Voltage, 5 V

GND

EN SS

VIN VOUT

ADP7118

OFF

= 7V V

OUT

= 6V

SENSE/ADJ

2.2µF C

OUT

2.2µF

1nF

2kΩ

10kΩ

11849-002

Figure 2. ADP7118 with 5 V Output Adjusted to 6 V

GENERAL DESCRIPTION

The ADP7118 is a CMOS, low dropout (LDO) linear regulator

that operates from 2.7 V to 20 V and provides up to 200 mA of

output current. This high input voltage LDO is ideal for the

regulation of high performance analog and mixed-signal circuits

operating from 19 V down to 1.2 V rails. Using an advanced

proprietary architecture, the device provides high power supply

rejection, low noise, and achieves excellent line and load transient

response with a small 2.2 µF ceramic output capacitor. The

ADP7118 regulator output noise is 11 μV rms independent of

the output voltage for the fixed options of 5 V or less.

The ADP7118 is available in 16 fixed output voltage options.

The following voltages are available from stock: 1.2 V

(adjustable), 1.8 V, 2.5 V, 3.3 V, 4.5 V, and 5.0 V.

Additional voltages available by special order are 1.5 V, 1.85 V,

2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V.

Each fixed output voltage can be adjusted above the initial set

point with an external feedback divider. This allows the ADP7118

to provide an output voltage from 1.2 V to VIN − VDO with high

PSRR and low noise.

User programmable soft start with an external capacitor is

available in the LFCSP and SOIC packages.

The ADP7118 is available in a 6-lead, 2 mm × 2 mm LFCSP

making it not only a very compact solution, but it also provides

excellent thermal performance for applications requiring up to

200 mA of output current in a small, low profile footprint. The

ADP7118 is also available in a 5-lead TSOT and an 8-lead SOIC.

ADP7118 Data Sheet

Rev. F | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ...................................................................................... 1

Typical Application Circuits ........................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Input and Output Capacitance, Recommended Specifications .. 4

Absolute Maximum Ratings ........................................................... 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 13

Applications Information ............................................................. 14

ADIsimPower Design Tool ...................................................... 14

Capacitor Selection .................................................................... 14

Programable Precision Enable ................................................. 15

Soft Start ...................................................................................... 15

Noise Reduction of the ADP7118 in Adjustable Mode ........ 16

Effect of Noise Reduction on Start-Up Time ......................... 16

Current-Limit and Thermal Overload Protection ................ 17

Thermal Considerations ........................................................... 17

Printed Circuit Board Layout Considerations ........................... 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Automotive Products ................................................................ 24

REVISION HISTORY

9/2020—Rev. E to Rev. F

Change to General Description Section ........................................ 1

Changes to Shutdown Current Parameter, Table 1 ..................... 3

Change to Theory of Operation Section ..................................... 13

Change to Figure 50 ....................................................................... 16

Changes to Current-Limit and Thermal Overload

Protection Section .......................................................................... 17

Changes to Table 8 ......................................................................... 21

Changes to Ordering Guide .......................................................... 23

9/2019—Rev. D to Rev. E

Changes to Features Section ........................................................... 1

Change to Package Column, Table 9 ........................................... 21

Changes to Ordering Guide .......................................................... 23

Added Automotive Products Section .......................................... 24

4/2018—Rev. C to Rev. D

Changes to Features Section ........................................................... 1

Updated Outline Dimensions ....................................................... 22

Changes to Ordering Guide .......................................................... 23

11/2016—Rev. B to Rev. C

Changes to Features Section and General Description Section ....... 1

Changes to Ordering Guide ................................................................... 23

7/2016—Rev. A to Rev. B

Change to Table 5 .............................................................................. 6

Change to Figure 42 ....................................................................... 13

Changes to Programmable Precision Enable Section and Soft

Start Section .................................................................................... 15

Added Effect of Noise Reduction on Start-Up Time Section .. 16

12/2014—Rev. 0 to Rev. A

Changes to Figure 36 to Figure 41 ............................................... 12

Changes to Figure 44 ..................................................................... 14

9/2014—Revision 0: Initial Version

Data Sheet ADP7118

Rev. F | Page 3 of 24

SPECIFICATIONS

VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, EN = VIN, IOUT = 10 mA, CIN = COUT = 2.2 µF, CSS = 0 pF, TA = 25°C for typical

specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE VIN 2.7 20 V

OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 50 140 µA

IOUT = 10 mA 80 190 µA

IOUT = 200 mA 180 320 µA

SHUTDOWN CURRENT IGND-SD EN = GND 1.8 µA

EN = GND, VIN = 20 V 3.0 10 µA

OUTPUT VOLTAGE ACCURACY

Output Voltage Accuracy VOUT IOUT = 10 mA, TJ = 25°C –0.8 +0.8 %

100 μA < I

OUT

< 200 mA, V

= (V

OUT

+ 1 V) to 20 V,

TJ = −40°C to +85°C

–1.2 +1.5 %

100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V –1.8 +1.8 %

LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V –0.015 +0.015 %/V

LOAD REGULATION1 ∆VOUT/∆IOUT IOUT = 100 μA to 200 mA 0.002 0.004 %/mA

SENSE INPUT BIAS CURRENT SENSEI-BIAS 100 μA < IOUT < 200 mA VIN = (VOUT + 1 V) to 20 V 10 1000 nA

DROPOUT VOLTAGE2 VDROPOUT IOUT = 10 mA 30 60 mV

IOUT = 200 mA 200 420 mV

START-UP TIME3 tSTART-UP VOUT = 5 V 380 µs

SOFT START SOURCE CURRENT SSI-SOURCE SS = GND 1.15 µA

CURRENT-LIMIT THRESHOLD4 ILIMIT 250 360 460 mA

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD TJ rising 150 °C

Thermal Shutdown Hysteresis TSSD-HYS 15 °C

UNDERVOLTAGE THRESHOLDS

Input Voltage Rising UVLORISE 2.69 V

Input Voltage Falling UVLOFALL 2.2 V

Hysteresis UVLOHYS 230 mV

PRECISION EN INPUT 2.7 V ≤ VIN ≤ 20 V

Logic High ENHIGH 1.15 1.22 1.30 V

Logic Low ENLOW 1.06 1.12 1.18 V

Logic Hysteresis ENHYS 100 mV

Leakage Current IEN-LKG EN = VIN or GND 0.04 1 µA

Delay Time tEN-DLY From EN rising from 0 V to VIN to 0.1 × VOUT 80 μs

OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, all output voltage options 11 µV rms

POWER SUPPLY REJECTION RATIO PSRR 1 MHz, VIN = 7 V, VOUT = 5 V 50 dB

100 kHz, VIN = 7 V, VOUT = 5 V 68 dB

10 kHz, VIN = 7 V, VOUT = 5 V 88 dB

1 Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 7 for typical load regulation performance for loads less than 1 mA.

2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages above 2.7 V.

3 Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of the nominal value.

4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.

ADP7118 Data Sheet

Rev. F | Page 4 of 24

INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT AND OUTPUT CAPACITANCE

Minimum Capacitance1 CMIN TA = −40°C to +125°C 1.5 µF

Capacitor Effective Series Resistance (ESR) RESR TA = −40°C to +125°C 0.001 0.3 Ω

1 The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,

while Y5V and Z5U capacitors are not recommended for use with any LDO.

Am ESD (elutmsntit discharge) sensi ve device. Charged dewces and (Hum board: (an dmhavge wimom daemon. Nmough ms product feamves palenlgd av pmpnmyy pvmedlon mum, damage may cum on devues subjecled «7 mm enevgy ESD Thevefove, proper ESD pvecaunons Shou‘d be \aken m avoid performance degradalmn m ‘05; of (unmanahty

Data Sheet ADP7118

Rev. F | Page 5 of 24

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND –0.3 V to +24 V

VOUT to GND –0.3 V to VIN

EN to GND –0.3 V to +24 V

SENSE/ADJ to GND –0.3 V to +6 V

SS to GND –0.3 V to VIN or

+6 V (whichever is

less)

Storage Temperature Range –65°C to +150°C

Junction Temperature (TJ) 150°C

Operating Ambient Temperature (TA)

Range

–40°C to +125°C

Soldering Conditions JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADP7118 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that TJ is within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

In applications with moderate power dissipation and low

printed circuit board (PCB) thermal resistance, the maximum

ambient temperature can exceed the maximum limit as long as

the junction temperature is within specification limits. The

junction temperature of the device is dependent on the ambient

temperature, the power dissipation (PD) of the device, and the

junction-to-ambient thermal resistance of the package (θJA).

Maximum TJ is calculated from the TA and PD using the

formula

TJ = TA + (PD × θJA) (1)

θJA of the package is based on modeling and calculation using a

4-layer board. The θJA is highly dependent on the application

and board layout. In applications where high maximum power

dissipation exists, close attention to thermal board design is

required. The value of θJA may vary, depending on PCB material,

layout, and environmental conditions. The specified values of θJA

are based on a 4-layer, 4 inches × 3 inches circuit board. See

JESD51-7 and JESD51-9 for detailed information on the board

construction.

ΨJB is the junction-to-board thermal characterization parameter

with units of °C/W. The ΨJB of the package is based on

modeling and calculation using a 4-layer board. The JESD51-12,

Guidelines for Reporting and Using Electronic Package Thermal

Information, states that thermal characterization parameters are

not the same as thermal resistances. ΨJB measures the component

power flowing through multiple thermal paths rather than a

single path as in thermal resistance (θJB). Therefore, ΨJB thermal

paths include convection from the top of the package as well as

radiation from the package, factors that make ΨJB more useful

in real-world applications. Maximum TJ is calculated from the

board temperature (TB) and PD using the formula

TJ = TB + (PD × ΨJB) (2)

See JESD51-8 and JESD51-12 for more detailed information

about ΨJB.

THERMAL RESISTANCE

θJA, θJC, and ΨJB are specified for the worst-case conditions, that

is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θJC ΨJB Unit

6-Lead LFCSP 72.1 42.3 47.1 °C/W

8-Lead SOIC 52.7 41.5 32.7 °C/W

5-Lead TSOT 170 N/A1 43 °C/W

1 N/A means not applicable.

ESD CAUTION

UN DE 3333 CECE

ADP7118 Data Sheet

Rev. F | Page 6 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

3GND

1VOUT

2SENSE/ADJ

4 EN

6 VIN

5 SS

ADP7118

TOP VIEW

(Not to Scale)

EXPOSED PAD

NOTES

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE

ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

11849-003

Figure 3. 6-Lead LFCSP Pin Configuration

ADP7118

TOP VIEW

(Not to Scale)

VIN

GND

VOUT

SENSE/ADJ

11849-104

Figure 4. 5-Lead TSOT Pin Configuration

ADP7118

TOP VIEW

(Not to Scale)

VOUT

SENSE/ADJ

GND

VIN

NOTES

1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE

ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE

PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED

PAD CONNECT TO THE GROUND PLANE ON THE BOARD.

11849-105

Figure 5. 8-Lead SOIC Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

6-Lead LFCSP 8-Lead SOIC 5-Lead TSOT Mnemonic Description

1 1, 2 5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or greater

capacitor.

2 3 4 SENSE/ADJ Sense Input (SENSE). Connect to load. An external resistor divider may

also set the output voltage higher than the fixed output voltage (ADJ).

3 4 2 GND Ground.

4 5 3 EN The enable pin controls the operation of the LDO. Drive EN high to turn

on the regulator. Drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.

5 6 Not applicable SS Soft Start. An external capacitor connected to this pin determines the

soft-start time. Leave this pin open for a typical 380 μs start-up time. Do

not ground this pin.

6 7, 8 1 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater

capacitor.

Not applicable EP Exposed Pad. The exposed pad on the bottom of the package enhances

thermal performance and is electrically connected to GND inside the

package. It is recommended that the exposed pad connect to the

ground plane on the board.

5.n5 3m) 5.n5 20:2 5415 am:

Data Sheet ADP7118

Rev. F | Page 7 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 2.2 µF, TA = 25°C, unless otherwise noted.

–40 –5 25 85 125

OUT

(V)

JUNCTION TEMPERATURE (°C)

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05 LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-004

Figure 6. Output Voltage (VOUT) vs. Junction Temperature

0.1 110 100 1000

OUT

(V)

LOAD

(mA)

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

11849-005

Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD)

510 15 20

OUT

(V)

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05 LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-006

Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN)

–40 –5 25 85 125

GROUND CURRENT (µA)

JUNCTION TEMPERATURE (°C)

100

150

200

250

300 LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-007

Figure 9. Ground Current vs. Junction Temperature

0.1 110 100 1000

GROUND CURRENT (µA)

LOAD

(mA)

100

120

140

160

180

200

11849-008

Figure 10. Ground Current vs. Load Current (ILOAD)

510 15 20

GROUND CURRENT (µA)

(V)

100

150

200

250

300 LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-009

Figure 11. Ground Current vs. Input Voltage (VIN)

mun 22 ;: as zsn 3.35 5.05

ADP7118 Data Sheet

Rev. F | Page 8 of 24

2.5

2.0

1.5

1.0

0.5

–50 –25 025 50 75 100 125

SHUTDOWN CURRENT (µA)

TEMPERATURE (°C)

= 2.7V

= 3V

= 5V

= 6V

= 10V

= 20V

11849-010

Figure 12. Shutdown Current vs. Temperature at Various Input Voltages

110 100 1000

DROPOUT (mV)

LOAD

(mA)

100

150

200

250

11849-011

Figure 13. Dropout Voltage vs. Load Current (ILOAD), VOUT = 5 V

4.8 5.0 5.4 5.65.2

OUT

(V)

4.60

4.65

4.70

4.75

4.80

4.85

4.90

4.95

5.00

5.05

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

11849-012

Figure 14. Output Voltage(VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V

4.8 5.0 5.4 5.65.2

GROUND CURRENT (µA)

(V)

100

200

300

400

500

600

700

800

1000

900

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

11849-013

Figure 15. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 5 V

–40 –5 25 85 125

OUT

(V)

JUNCTION TEMPERATURE (°C)

3.25

3.35

3.33

3.31

3.29

3.27

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-014

Figure 16. Output Voltage (VOUT) vs. Junction Temperature, VOUT = 3.3 V

0.1 110 100 1000

OUT

(V)

LOAD

(mA)

3.25

3.27

3.29

3.31

3.33

3.35

11849-015

Figure 17. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V

3.35 m m 3.:

Data Sheet ADP7118

Rev. F | Page 9 of 24

010 20515

OUT

(V)

3.25

3.27

3.29

3.31

3.33

3.35 LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-016

Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 3.3 V

–40 –5 25 85 125

GROUND CURRENT (µA)

JUNCTION TEMPERATURE (°C)

300

250

200

150

100

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-017

Figure 19. Ground Current vs. Junction Temperature, VOUT = 3.3 V

0.1 110 100 1000

GROUND CURRENT (µA)

LOAD

(mA)

120

160

200

100

140

180

11849-018

Figure 20. Ground Current vs. Load Current (ILOAD), VOUT = 3.3 V

010 20515

GROUND CURRENT (µA)

(V)

300

250

200

150

100

LOAD = 100µA

LOAD = 1mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 200mA

11849-019

Figure 21. Ground Current vs. Input Voltage (VIN), VOUT = 3.3 V

110 100 1000

DROPOUT (mV)

LOAD

(mA)

100

150

200

300

250

11849-020

Figure 22. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3.3 V

3.1 3.3 3.73.5 3.9

OUT

(V)

2.8

2.9

3.0

3.1

3.2

3.4

3.3

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

11849-021

Figure 23. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,

VOUT = 3.3 V

3m)

ADP7118 Data Sheet

Rev. F | Page 10 of 24

3.1 3.3 3.73.5 3.9

GROUND CURRENT (µA)

(V)

100

200

300

400

700

500

600

LOAD = 5mA

LOAD = 10mA

LOAD = 50mA

LOAD = 100mA

LOAD = 150mA

LOAD = 200mA

11849-022

Figure 24. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V

–40 –5 25 85 125

SS CURRENT (µA)

TEMPERATURE (°C)

300

250

200

150

100

= 2.7V

= 5.0V

= 10V

= 20V

11849-023

Figure 25. Soft Start (SS) Current vs. Temperature, Multiple Input Voltages,

VOUT = 5 V

110M1M100k10k1k10010

PSRR (dB)

FREQUENCY (Hz)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

700mV

600mV

11849-024

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 1.8 V,

for Various Headroom Voltages

0.2 3.02.62.21.8

1.41.0

0.6

PSRR (dB)

HEADROOM VOLTAGE (V)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

11849-025

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

VOUT = 1.8 V,for Different Frequencies

10 10M1M100k10k1k100

PSRR (dB)

FREQUENCY (Hz)

–120

–100

–80

–60

–40

–20

3.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

11849-026

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3.3 V,

for Various Headroom Voltages

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

PSRR (dB)

HEADROOM VOLTAGE (V)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

010Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

11849-027

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

VOUT = 3.3 V, for Different Frequencies

32>... Emzun impounm “ma: .nz:>.._>=mzun 25.3% umaz 32>... Emzun 25.3% $6: 2n

Data Sheet ADP7118

Rev. F | Page 11 of 24

10 10M1M100k10k1k100

PSRR (dB)

FREQUENCY (Hz)

–120

–100

–80

–60

–40

–20

3.0V

2.0V

1.6V

1.4V

1.2V

1.0V

800mV

700mV

600mV

500mV

11849-028

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 5 V,

for Various Headroom Voltages

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

PSRR (dB)

HEADROOM VOLTAGE (V)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

010Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

11849-029

Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

VOUT = 5 V, for Different Frequencies

110 100 1000

RMS OUTPUT NOISE (µV rms)

LOAD CURRENT (mA)

20 10Hz TO 100kHz

100Hz TO 100kHz

11849-030

Figure 32. RMS Output Noise vs. Load Current

NOISE SPECTRAL DENSITY (nV/√Hz)

FREQUENCY (Hz)

10M

110 100 1k 10k 100k 1M

100

10k

11849-031

Figure 33. Output Noise Spectral Density vs. Frequency, ILOAD = 10 mA

NOISE SPECTRAL DENSITY (nV/√Hz)

FREQUENCY (Hz)

10M110 100 1k 10k 100k 1M

100

10k

100k 100µA

1mA

10mA

100mA

200mA

11849-032

Figure 34. Output Noise Spectral Density vs. Frequency, for Different Loads

NOISE SPECTRAL DENSITY (nV/√Hz)

FREQUENCY (Hz)

10M110 100 1k 10k 100k 1M

100

10k

100k 1.8V

3.3V

5.0V

11849-033

Figure 35. Output Noise Spectral Density vs. Frequency for

Different Output Voltages

ADP7118 Data Sheet

Rev. F | Page 12 of 24

11849-034

CH1 200mA Ω

CH2 20mV

M20µs A CH1 1000mA

T 10.2%

Figure 36. Load Transient Response, ILOAD = 1 mA to 200 mA,

VOUT = 5 V, VIN = 7 V, CH1 Load Current, CH2 VOUT

11849-035

CH1 2V

CH2 2mV

M4.0µs A CH4 1.84V

T 10.2%

Figure 37. Line Transient Response, ILOAD = 200 mA,

VOUT = 5 V, CH1 VIN, CH2 VOUT

11849-036

CH1 200mA Ω

CH2 20mV

M20µs A CH1 148mA

T 10.4%

Figure 38. Load Transient Response, ILOAD = 1 mA to 200 mA,

VOUT = 3.3 V, VIN = 5 V, CH1 Load Current, CH2 VOUT

11849-037

CH1 1V

CH2 2mV

M4µs A CH4 1.84V

T 10.2%

Figure 39. Line Transient Response, ILOAD = 200 mA,

VOUT = 3.3 V, CH1 VIN, CH2 VOUT

11849-038

CH1 200mA Ω

M20µs A CH1 84mA

T 10.2%

CH2 20mV

Figure 40. Load Transient Response, ILOAD = 1 mA to 200 mA,

VOUT = 1.8 V, VIN = 3 V, CH1 Load Current, CH2 VOUT

11849-039

CH1 1V

M4.0µs A CH4 2.08V

T 93.4%

CH2 5mV

Figure 41. Line Transient Response, ILOAD = 200 mA,

VOUT = 1.8 V, CH1 VIN, CH2 VOUT

Data Sheet ADP7118

Rev. F | Page 13 of 24

THEORY OF OPERATION

The ADP7118 is a low quiescent current, LDO linear regulator

that operates from 2.7 V to 20 V and provides up to 200 mA of

output current. Drawing a low 180 μA of quiescent current

(typical) at full load makes the ADP7118 ideal for portable

equipment. Typical shutdown current consumption is less than

3 µA at room temperature.

Optimized for use with small 2.2 µF ceramic capacitors, the

ADP7118 provides excellent transient performance.

VOUT

SENSE/

ADJ

GND

SHORT-CIRCUIT,

THERMAL

PROTECTION

REFERENCE

SHUTDOWN

VIN

11849-040

Figure 42. Internal Block Diagram

Internally, the ADP7118 consists of a reference, an error

amplifier, and a PMOS pass transistor. Output current is

delivered via the PMOS pass device, which is controlled by the

error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the

reference voltage, the gate of the PMOS device is pulled lower,

allowing more current to pass and increasing the output

voltage. If the feedback voltage is higher than the reference

voltage, the gate of the PMOS device is pulled higher, allowing

less current to pass and decreasing the output voltage.

The ADP7118 is available in 16 fixed output voltage options,

ranging from 1.2 V to 5.0 V. The ADP7118 architecture allows

any fixed output voltage to be set to a higher voltage with an

external voltage divider. For example, a fixed 5 V output can be

set to a 6 V output according to the following equation:

VOUT = 5 V(1 + R1/R2) (3)

where R1 and R2 are the resistors in the output voltage divider

shown in Figure 43.

To set the output voltage of the adjustable ADP7118, replace

5 V in Equation 3 with 1.2 V.

VOUT

SENSE/ADJ

VIN

ADP7118

GND SS CSS

1nF

CIN

2.2µF COUT

2.2µF

OFF

VIN = 7V VOUT = 6V

2kΩ

10kΩ

11849-041

Figure 43. Typical Adjustable Output Voltage Application Schematic

It is recommended that the R2 value be less than 200 kΩ to

minimize errors in the output voltage caused by the SENSE/ADJ

pin input current. For example, when R1 and R2 each equal

200 kΩ and the default output voltage is 1.2 V, the adjusted output

voltage is 2.4 V. The output voltage error introduced by the

SENSE/ADJ pin input current is 1 mV or 0.04%, assuming a

typical SENSE/ADJ pin input current of 10 nA at 25°C.

The ADP7118 uses the EN pin to enable and disable the

VOUT pin under normal operating conditions. When EN is

high, VOUT turns on, and when EN is low, VOUT turns off.

For automatic startup, EN can be tied to VIN.

ADP7118 Data Sheet

Rev. F | Page 14 of 24

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADP7118 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials, and

calculate performance in minutes. ADIsimPower can optimize

designs for cost, area, efficiency, and parts count, taking into

consideration the operating conditions and limitations of the IC

and all real external components. For more information about,

and to obtain ADIsimPower design tools, visit

www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Output Capacitor

The ADP7118 is designed for operation with small, space-saving

ceramic capacitors, but functions with general-purpose capacitors

as long as care is taken with regard to the effective series resistance

(ESR) value. The ESR of the output capacitor affects the stability

of the LDO control loop. A minimum of 2.2 µF capacitance with

an ESR of 0.3 Ω or less is recommended to ensure the stability of

the ADP7118. Transient response to changes in load current is

also affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the ADP7118 to

large changes in load current. Figure 44 shows the transient

responses for an output capacitance value of 2.2 µF.

11849-042

CH1 200mA Ω

M20µs A CH1 100mA

T 10.2%

CH2 20mV

Figure 44. Output Transient Response, VOUT = 5 V, COUT = 2.2 µF, CH1 Load

Current, CH2 VOUT

Input Bypass Capacitor

Connecting a 2.2 µF capacitor from VIN to GND reduces the

circuit sensitivity to the PCB layout, especially when long input

traces or high source impedance is encountered. If greater than

2.2 µF of output capacitance is required, increase the input

capacitor to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7118, as long as they meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manufactured

with a variety of dielectrics, each with different behavior over

temperature and applied voltage. Capacitors must have a dielectric

adequate to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V to 100 V are recommended. Y5V

and Z5U dielectrics are not recommended, due to their poor

temperature and dc bias characteristics.

Figure 45 depicts the capacitance vs. voltage bias characteristic

of an 0805, 2.2 µF, 10 V, X5R capacitor. The voltage stability of

a capacitor is strongly influenced by the capacitor size and

voltage rating. In general, a capacitor in a larger package or

higher voltage rating exhibits better stability. The temperature

variation of the X5R dielectric is ~±15% over the −40°C to

+85°C temperature range and is not a function of package or

voltage rating.

CAPACITANCE (µF)

DC BIAS VOLTAGE (V)

121086420

0.5

1.0

1.5

2.0

2.5

11849-043

Figure 45. Capacitance vs. Voltage Characteristic

Use Equation 1 to determine the worst-case capacitance

accounting for capacitor variation over temperature, component

tolerance, and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (4)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and CBIAS is 2.09 μF at 5 V, as shown in Figure 45.

These values in Equation 1 yield

CEFF = 2.09 μF × (1 − 0.15) × (1 − 0.1) = 1.59 μF (5)

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temper-

ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7118, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

/ f

Data Sheet ADP7118

Rev. F | Page 15 of 24

PROGRAMABLE PRECISION ENABLE

The ADP7118 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. As shown in Figure 46,

when a rising voltage on EN crosses the upper threshold,

nominally 1.2 V, VOUT turns on. When a falling voltage on EN

crosses the lower threshold, nominally 1.1 V, VOUT turns off.

The hysteresis of the EN threshold is approximately 100 mV.

OUT

(V)

1.301.251.201.151.101.05

0.5

1.0

1.5

2.0

2.5

3.5

3.0

–40°C

+25°C

+125°C

11849-044

Figure 46. Typical VOUT Response to EN Pin Operation

The upper and lower thresholds are user programmable and

can be set higher than the nominal 1.2 V threshold by using

two resistors. The resistance values, REN1 and REN2, can be

determined from the following:

REN2 = nominally 10 kΩ to 100 kΩ (6)

REN1 = REN2 × (VIN − 1.2 V)/1.2 V (7)

where:

VIN is the desired turn-on voltage.

The hysteresis voltage increases by the factor (REN1 + REN2)/REN2.

For the example shown in Figure 47, the enable threshold is

3.6 V with a hysteresis of 300 mV.

VOUT

SENSE/ADJ

VIN

ADP7118

GND

2.2µF C

OUT

2.2µF

OFF

= 8V V

OUT

= 6V

10kΩ

20kΩ

EN1

200kΩ

EN2

100kΩ

11849-045

Figure 47. Typical EN Pin Voltage Divider

Figure 46 shows the typical hysteresis of the EN pin. This pre-

vents on/off oscillations that can occur due to noise on the

EN pin as it passes through the threshold points.

SOFT START

The ADP7118 uses an internal soft start (SS pin open) to limit the

inrush current when the output is enabled. The start-up time for

the 3.3 V option is approximately 380 µs from the time the EN

active threshold is crossed to when the output reaches 90% of

the final value. As shown in Figure 48, the start-up time is

independent on the output voltage setting.

OUT

(V)

TIME (ms)

1.00.9

0.80.70.60.5

0.40.30.2

0.10

OUT

= 1.8V

OUT

= 3.3V

OUT

= 5.0V

11849-046

Figure 48. Typical Start-Up Behavior

An external capacitor connected to the SS pin determines the

soft start time. This SS pin can be left open for a typical 380 µs

start-up time. Do not ground this pin. When an external soft

start capacitor (CSS) is used, the soft start time is determined by

the following equation:

SSTIME (sec) = tSTART-UP at 0 pF + (0.6 × CSS)/ISS (8)

where:

tSTART-UP at 0 pF is the start-up time at CSS = 0 pF (typically 380 µs).

CSS is the soft start capacitor (F).

ISS is the soft start current (typically 1.15 µA).

OUT

(V)

TIME (ms)

109876543210

0.5

1.0

2.0

3.0

3.5

1.5

2.5

NO SS CAP

1nF

2nF

4.7nF

6.8nF

10nF

11849-047

Figure 49. Typical Soft Start Behavior, Different CSS

°_l_ nENSnvlnv/mz) muss srzmm max

ADP7118 Data Sheet

Rev. F | Page 16 of 24

NOISE REDUCTION OF THE ADP7118 IN

ADJUSTABLE MODE

The ultralow output noise of the ADP7118 is achieved by keeping

the LDO error amplifier in unity gain and setting the reference

voltage equal to the output voltage. This architecture does not

work for an adjustable output voltage LDO in the conventional

sense. However, the ADP7118 architecture allows any fixed

output voltage to be set to a higher voltage with an external

voltage divider. For example, a fixed 5 V output can be set to a

10 V output according to Equation 3 (see Figure 50):

VOUT = 5 V(1 + R1/R2)

The disadvantage in using the ADP7118 in this manner is that

the output voltage noise is proportional to the output voltage.

Therefore, it is best to choose a fixed output voltage that is close

to the target voltage to minimize the increase in output noise.

The adjustable LDO circuit can be modified to reduce the

output voltage noise to levels close to that of the fixed output

ADP7118. The circuit shown in Figure 50 adds two additional

components to the output voltage setting resistor divider. CNR

and RNR are added in parallel with R1 to reduce the ac gain of

the error amplifier. RNR is chosen to be small with respect to R2.

If RNR is 1% to 10% of the value of R2, the minimum ac gain of

the error amplifier is approximately 0.1 dB to 0.8 dB. The actual

gain is determined by the parallel combination of RNR and R1.

This gain ensures that the error amplifier always operates at

slightly greater than unity gain.

CNR is chosen by setting the reactance of CNR equal toR1 − RNR

at a frequency between 1 Hz and 50 Hz. This setting places the

frequency where the ac gain of the error amplifier is 3 dB down

from the dc gain.

OUT

= 10V

= 12V VOUTVIN

GND

SENSE/ADJ

100kΩ

200kΩ

OUT

2.2µF

OFF

10kΩ

100kΩ

++ R1

100kΩC

1µF

11849-048

Figure 50. Noise Reduction Modification

The noise of the adjustable LDO is found by using the

following formula, assuming the noise of a fixed output LDO is

approximately 11 μV.

Noise = 11 μV × (RPAR + R2)/R2 (9)

where RPAR is a parallel combination of R1 and RNR.

Based on the component values shown in Figure 50, the ADP7118

has the following characteristics:

• DC gain of 10 (20 dB)

• 3 dB roll-off frequency of 1.75 Hz

• High frequency ac gain of 1.099 (0.82 dB)

• Theoretical noise reduction factor of 9.1 (19.2 dB)

• Measured rms noise of the adjustable LDO without noise

reduction is 70 µV rms

• Measured rms noise of the adjustable LDO with noise

reduction is 12 µV rms

• Measured noise reduction of approximately 15.3 dB

Note that the measured noise reduction is less than the theoretical

noise reduction. Figure 51 shows the noise spectral density of an

adjustable ADP7118 set to 6 V and 12 V with and without the

noise reduction network. The output noise with the noise

reduction network is approximately the same for both voltages,

especially beyond 100 Hz. The noise of the 6 V and 12 V outputs

without the noise reduction network differs by a factor of 2 up to

approximately 20 kHz. Above 40 kHz, the closed loop gain of

the error amplifier is limited by the open loop gain characteristic.

Therefore, the noise contribution from 20 kHz to 100 kHz is

less than what it is if the error amplifier had infinite bandwidth.

This is also the reason why the noise is less than what might be

expected simply based on the dc gain, that is, 70 µV rms vs.

110 µV rms.

NOISE SPECTRAL DENSITY (nV/√Hz)

FREQUENCY (Hz)

10M1M100k10k1k100101

100

10k

100k

11849-100

12V NOISE REDUCTION

12V NO NOISE REDUCTION

6V NOISE REDUCTION

6V NO NOISE REDUCTION

Figure 51. 6 V and 12 V Output Voltage with and Without Noise Reduction

Network

EFFECT OF NOISE REDUCTION ON START-UP TIME

The start-up time of the ADP7118 is affected by the noise

reduction network and must be considered in applications

where power supply sequencing is critical.

The noise reduction circuit adds a pole in the feedback loop,

slowing down the start-up time. To approximate the start-up time

for an adjustable model with a noise reduction network using the

following equation:

SSNRTIME (sec) = 5.5 × CNR × (RNR + RFB1)

For a CNR, RNR, and R1 combination of 1 µF, 10 kΩ, and 100 kΩ,

as shown in Figure 50, the start-up time is approximately 0.6 sec.

When SSNRTIME is greater than SSTIME, SSNRTIME dictates the

length of the start-up time instead of the soft start capacitor.

Data Sheet ADP7118

Rev. F | Page 17 of 24

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7118 is protected against damage due to excessive

power dissipation by current and thermal overload protection

circuits. The ADP7118 is designed to current limit when the

output load reaches 360 mA (typical). When the output load

exceeds 360 mA, the output voltage is reduced to maintain a

constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and/or

high power dissipation) when the junction temperature starts

to rise above 150°C, the output is turned off, reducing the

output current to zero. When the junction temperature drops

below 135°C, the output is turned on again, and output current

is restored to the operating value.

Consider the case where a hard short from VOUT to ground

occurs. At first, the ADP7118 current limits, so that only 360 mA

is conducted into the short. If self heating of the junction is

great enough to cause the temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to zero. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

360 mA into the short, again causing the junction

temperature to rise above 150°C. This thermal oscillation

between 135°C and 150°C causes a current oscillation

between 360 mA and 0 mA that continues as long as the short

remains at the output.

Current and thermal limit protections protect the device

against accidental overload conditions. For reliable operation,

device power dissipation must be externally limited so that the

junction temperature does not exceed 125°C.

THERMAL CONSIDERATIONS

In applications with a low input-to-output voltage differential,

the ADP7118 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package may become large

enough to cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. It recovers only after the junction

temperature has decreased below 135°C to prevent any permanent

damage. Therefore, thermal analysis for the chosen application is

very important to guarantee reliable performance over all

conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 2.

To guarantee reliable operation, the junction temperature of

the ADP7118 must not exceed 125°C. To ensure that the

junction temperature stays below this maximum value, the user

must be aware of the parameters that contribute to junction

temperature changes. These parameters include ambient

temperature, power dissipation in the power device, and

thermal resistances between the junction and ambient air (θJA).

The θJA number is dependent on the package assembly

compounds that are used and the amount of copper used to

solder the package GND pins to the PCB.

Table 6 shows typical θJA values of the 8-lead SOIC, 6-lead LFCSP,

and 5-lead TSOT packages for various PCB copper sizes. Table 7

shows the typical ΨJB values of the 8-lead SOIC, 6-lead LFCSP,

and 5-lead TSOT.

Table 6. Typical θJA Values

Copper Size (mm2)

θJA (°C/W)

LFCSP SOIC TSOT

251 182.8 N/A2 N/A2

50 N/A2 181.4 152

100 142.6 145.4 146

500 83.9 89.3 131

1000 71.7 77.5 N/A2

6400 57.4 63.2 N/A2

1 Device soldered to minimum size pin traces.

2 N/A means not applicable.

Table 7. Typical ΨJB Values

Model ΨJB (°C/W)

6-Lead LFCSP 24

8-Lead SOIC 38.8

5-Lead TSOT 43

To calculate the junction temperature of the ADP7118, use

Equation 1.

TJ = TA + (PD × θJA)

where:

TA is the ambient temperature.

PD is the power dissipation in the die, given by

PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (10)

where:

VIN and VOUT are input and output voltages, respectively.

ILOAD is the load current.

IGND is the ground current.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to the following:

TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (11)

As shown in Equation 4, for a given ambient temperature, input-

to-output voltage differential, and continuous load current,

there exists a minimum copper size requirement for the PCB

to ensure that the junction temperature does not rise above 125°C.

Figure 52 to Figure 60 show junction temperature calculations

for different ambient temperatures, power dissipation, and

areas of PCB copper.

1w \\

ADP7118 Data Sheet

Rev. F | Page 18 of 24

105

115

125

135

145

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

6400mm

500mm

25mm

MAX

11849-049

Figure 52. LFCSP, TA = 25°C

100

110

120

130

140

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

6400mm

500mm

25mm

MAX

11849-050

Figure 53. LFCSP, TA = 50°C

100

110

120

130

140

00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

6400mm

500mm

25mm

MAX

11849-051

Figure 54. LFCSP, TA = 85°C

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

100

120

140

00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

= 25°C

= 50°C

= 65°C

= 85°C

MAX

11849-052

Figure 55. SOIC, TA = 25°C

100

110

120

130

140

00.2 0.4 0.6 0.8 1.0 1.2

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

6400mm

500mm

50mm

MAX

11849-155

Figure 56. SOIC, TA = 50°C

145

135

125

115

105

00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

6400mm

500mm

50mm

MAX

11849-156

Figure 57. SOIC, TA = 85°C

Data Sheet ADP7118

Rev. F | Page 19 of 24

105

115

125

135

145

00.1 0.2 0.3 0.4 0.5 0.6 0.8 1.0

0.7 0.9

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

500mm

100mm

50mm

MAX

11849-157

Figure 58. TSOT, TA = 25°C

140

130

120

110

100

00.1 0.2 0.3 0.4 0.5 0.6 0.7

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

500mm

100mm

50mm

MAX

11849-158

Figure 59. TSOT, TA = 50°C

145

105

115

125

135

00.400.350.300.250.200.150.10

0.05

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

500mm2

100mm2

50mm2

TJ MAX

11849-159

Figure 60. TSOT, TA = 85°C

In the case where the board temperature is known, use the thermal

characterization parameter, ΨJB, to estimate the junction

temperature rise (see Figure 61, Figure 62, and Figure 63).

Calculate the maximum junction temperature by using

Equation 2.

TJ = TB + (PD × ΨJB)

The typical value of ΨJB is 24°C/W for the 8-lead LFCSP package,

38.8°C/W for the 8-lead SOIC package, and 43°C/W for the 5-lead

TSOT package.

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

100

120

140

00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

= 25°C

= 50°C

= 65°C

= 85°C

MAX

11849-160

Figure 61. LFCSP Junction Temperature Rise, Different Board Temperatures

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

100

120

140

00.5 1.0 1.5 2.0 2.5 3.0

= 25°C

= 50°C

= 65°C

= 85°C

MAX

11849-161

Figure 62. SOIC Junction Temperature Rise, Different Board Temperatures

JUNCTION TEMPERATURE (°C)

TOTAL POWER DISSIPATION (W)

100

120

140

00.5 1.0 1.5 2.0 2.5

= 25°C

= 50°C

= 65°C

= 85°C

MAX

11849-162

Figure 63. TSOT Junction Temperature Rise, Different Board Temperatures

31. ,\,1. \:\J\z\1 (El/,2,» \J\J\I\.l {3? av» NIIKIQJ (Lax/six

ADP7118 Data Sheet

Rev. F | Page 20 of 24

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing

the amount of copper attached to the pins of the ADP7118.

However, as listed in Table 6, a point of diminishing returns is

eventually reached, beyond which an increase in the copper size

does not yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Use of 0805 or 1206 size capacitors and

resistors achieves the smallest possible footprint solution on

boards where area is limited.

11849-263

Figure 64. Example LFCSP PCB Layout

11849-164

Figure 65. Example SOIC PCB Layout

6ND ANALOG 00 DEVICES .. ADP7142/71187EVALZ J1 C1 00 o. o. 0. EB VIN JP1|§| EJPZVOUT SENSE/ADJ EN 0. .. J2 QGND .. .0 N to

Data Sheet ADP7118

Rev. F | Page 21 of 24

11849-165

Figure 66. Example TSOT PCB Layout

Table 8. Recommended LDOs for Very Low Noise Operation

Device

Number

VIN

Range (V)

VOUT

Fixed (V)

VOUT

Adjust

(V)

IOUT

(mA)

IQ at

IOUT

(µA)

IGND-SD

Max

(µA)

Soft

Start PGOOD

Noise

(Fixed)

10 Hz to

100 kHz

(µV rms)

PSRR

100 kHz

(dB)

PSRR

1 MHz Package

ADP7102 3.3 to 20 1.5 to 9 1.22 to

300 750 75 No Yes 15 60 40 dB 3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7104 3.3 to 20 1.5 to 9 1.22 to

500 900 75 No Yes 15 60 40 dB 3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7105 3.3 to 20 1.8, 3.3, 5 1.22 to

500 900 75 Yes Yes 15 60 40 dB 3 mm × 3 mm

8-lead LFCSP,

8-lead SOIC

ADP7112 2.7 to 20 1.2 to 5 1.2 to 19 200 180 10 Yes No 11 68 50 dB 1 mm ×

1.2 mm

6-ball WLCSP

ADP7118 2.7 to 20 1.2 to 5 1.2 to 19 200 180 10 Yes No 11 68 50 dB 2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142 2.7 to 40 1.2 to 5 1.2 to 39 200 180 10 Yes No 11 68 50 dB 2 mm × 2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7182 −2.7 to

−28

−1.8 to

−5

−1.22 to

−27

−200 −650 −8 No No 18 45 45 dB 2 mm × 2 mm

6-lead LFCSP,

3 mm × 3 mm

8-lead LFCSP,

5-lead TSOT

Table 9. Related Devices

Model Input Voltage (V) Output Current (mA) Package

ADP7142ACP 2.7 to 40 200 6-Lead LFCSP

ADP7142ARD 2.7 to 40 200 8-Lead SOIC

ADP7142AUJ 2.7 to 40 200 5-Lead TSOT

ADP7112ACB 2.7 to 20 200 6-Ball WLCSP

‘p w \ 1 *Lﬂ m ‘in r :Dﬁfg’ /' *JL T

ADP7118 Data Sheet

Rev. F | Page 22 of 24

OUTLINE DIMENSIONS

1.70

1.60

1.50

0.425

0.350

0.275

TOP VIEW

0.35

0.30

0.25

BOTTOM VIE W

PIN 1 INDEX

AREA

0.60

0.55

0.50

1.10

1.00

0.90

0.20 REF

0.05 MAX

0.02 NOM

0.65 BSC

EXPOSED

PAD

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

2.10

2.00 SQ

1.90

0.15 MIN

08-17-2018-D

SEATING

PLANE

PIN 1

IND ICATO R AR E A OP TIO N S

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

PKG-003581

Figure 67. 6-Lead Lead Frame Chip Scale Package [LFCSP]

2.00 mm × 2.00 mm Body and 0.55 mm Package Height

(CP-6-3)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-012-AA

06-02-2011-B

1.27

0.40

1.75

1.35

2.29

0.356

0.457

4.00

3.90

3.80

6.20

6.00

5.80

5.00

4.90

4.80

0.10 MAX

0.05 NOM

3.81 REF

0.25

0.17

8°

0°

0.50

0.25

45°

COPLANARITY

0.10

1.04 REF

1.27 BSC

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.51

0.31

1.65

1.25

Figure 68. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-1)

Dimensions shown in millimeters

A ﬁlm am ET ,: 7r 7‘: gm

Data Sheet ADP7118

Rev. F | Page 23 of 24

COMPLIANT TO JEDEC STANDARDS MO-193-AB

0.95 BSC

1.90 REF

0.90

0.70

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

1.00 MAX

5 4

1 2 3

END VIEW

TOP VIEW

SIDE VIEW

04-05-2017-B

PKG-000882

3.05

2.90

2.75

3.05

2.80

2.55

1.75

1.60

1.45

SEATING

PLANE

Figure 69. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Output Voltage (V)3, 4 Package Description Package Option Marking Code

ADP7118ACPZN-R7 −40°C to +125°C Adjustable (1.2 V) 6-Lead LFCSP CP-6-3 LP9

ADP7118ACPZN1.8-R7 −40°C to +125°C 1.8 6-Lead LFCSP CP-6-3 LPA

ADP7118ACPZN2.5-R7 −40°C to +125°C 2.5 6-Lead LFCSP CP-6-3 LPB

ADP7118ACPZN3.3-R7 −40°C to +125°C 3.3 6-Lead LFCSP CP-6-3 LPC

ADP7118ACPZN5.0-R7 −40°C to +125°C 5 6-Lead LFCSP CP-6-3 LPD

ADP7118ARDZ −40°C to +125°C Adjustable (1.2 V) 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-R7 −40°C to +125°C Adjustable (1.2 V) 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-1.8 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-2.5 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-2.5-R7 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-3.3 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-5.0 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-1

ADP7118ARDZ-5.0-R7

−40°C to +125°C

8-Lead SOIC_N_EP

RD-8-1

ADP7118AUJZ-R2 −40°C to +125°C Adjustable (1.2 V) 5-Lead TSOT UJ-5 LP9

ADP7118AUJZ-R7 −40°C to +125°C Adjustable (1.2 V) 5-Lead TSOT UJ-5 LP9

ADP7118AUJZ-1.8-R7 −40°C to +125°C 1.8 5-Lead TSOT UJ-5 LPA

ADP7118AUJZ-2.5-R7 −40°C to +125°C 2.5 5-Lead TSOT UJ-5 LPB

ADP7118AUJZ-3.3-R7 −40°C to +125°C 3.3 5-Lead TSOT UJ-5 LPC

ADP7118AUJZ-4.5-R7 −40°C to +125°C 4.5 5-Lead TSOT UJ-5 LUU

ADP7118AUJZ-5.0-R7 −40°C to +125°C 5 5-Lead TSOT UJ-5 LPD

ADP7118WAUJZ-1.8-R7 −40°C to +125°C 1.8 5-Lead TSOT UJ-5 LVL

ADP7118WAUJZ-2.5-R7 −40°C to +125°C 2.5 5-Lead TSOT UJ-5 LVM

ADP7118WAUJZ-3.3-R7 −40°C to +125°C 3.3 5-Lead TSOT UJ-5 LVN

ADP7118WAUJZ-5.0-R7 −40°C to +125°C 5 5-Lead TSOT UJ-5 LV8

ADP7118UJ-EVALZ TSOT Evaluation Board

ADP7118CP-EVALZ LFCSP Evaluation Board

ADP7118RD-EVALZ SOIC Evaluation Board

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

3 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.

4 The evaluation boards are preconfigured with an adjustable ADP7118.

ANALOG DEVICES www.analug.cum

ADP7118 Data Sheet

Rev. F | Page 24 of 24

AUTOMOTIVE PRODUCTS

The ADP7118W model is available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.

D11849-9/20(F)

ADP7118 Datasheet by Analog Devices Inc.

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