TSA7887 Datasheet by Touchstone Semiconductor

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TSA7887
Page 1
© 2014 Silicon Laboratories, Inc. All rights reserved.
FEATURES
Alternate Source for AD7887
Single-supply Operation: +2.7V to +5.25V
INL: ±1LSB - TSA7887B
±2LSBs - TSA7887A
One or Two Single-ended Analog Inputs
Internal Wide-bandwidth Track-and-Hold
Internal +2.5-V Reference
Flexible Power/Throughput-Rate Management
0.85mA at 125ksps (Internal VREF ON)
0.7mA at 125ksps (Internal VREF OFF)
Shutdown-mode Supply Current: 1A (max)
SPI®/QSPI™/MICROWIRE™/DSP-Compatible
Serial Interfaces
1
Operating Temperature Range:
-40ºC to +125ºC
8-pin SOIC and MSOP Packaging
APPLICATIONS
Instrumentation and Control Systems
High-Speed Modems
Battery-powered systems:
Personal Digital Assistants, Medical
Instruments, Mobile Communications
1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National
Semiconductor Corporation
DESCRIPTION
The TSA7887 – an alternate source for the AD7887 -
is a self-contained, 2-channel, high-speed,
micropower, 12-bit analog-to-digital converter (ADC)
that operates from a single +2.7V to +5.25V power
supply. The TSA7887 is capable of a 125-ksps
throughput rate with an external 2MHz serial clock
and draws 0.85mA supply current.
The wideband input track-and-hold acquires signals
in 500ns and features a single-ended sampling
topology. Output data coding is straight binary and
the ADC is capable of converting full power signals
up to 2.5 MHz. The ADC also contains an integrated
2.5V reference or the VREF pin can be overdriven by
an external reference.
The TSA7887’s provides one or two analog inputs
each with an analog input range from 0 to V
REF
. In
two-channel operation, the analog input range is 0V
to VDD. Efficient circuit design ensures low power
consumption of 2mW (typical) for normal operation
and 3W in power-down operation.
The TSA7887 is fully specified from -40ºC to +125ºC
and is available in 8-pin SOIC and MSOP packages.
A Micro
p
ower
,
2-channel
,
125-ks
p
s
,
Serial-Out
p
ut 12-bit SAR
A
DC
FUNCTIONAL BLOCK DIAGRAM
W SILIEDN LABS TOP VIEW (78E 0 VDDE GNDE A|N1NREFE TSA7887 ESCLK 3 DOUT EDIN E] AINO 8-pin sonc R-B Package TOP VIEW (TSE 0 VDDE GNDE AIMNREFE TSA7887 ESCLK fl DOUT EDIN E] AIND 8-pm MSOP RM-B Package
TSA7887
Page 2 TSA7887 Rev. 1.0
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND ................................................................ 0.3V to +7V
Analog Input Voltage (AIN0, AIN1) to AGND .... 0.3V to V
DD
+ 0.3V
Digital Input Voltage to AGND........................... 0.3V to V
DD
+ 0.3V
Digital Output Voltage to AGND ........................ 0.3V to V
DD
+ 0.3V
REFIN/REFOUT to AGND ................................ 0.3V to V
DD
+ 0.3V
Input Current to Any Pin Except Supplies
1
............................. ±10mA
Operating Temperature Range
A, B Versions ..................................................... 40°C to +125°C
Storage Temperature Range ................................. 65°C to +150°C
Junction Temperature ........................................................... +150°C
SOIC/MSOP Package Power Dissipation ............................. 450mW
JA
Thermal Impedance ..................................... 157°C/W (SOIC)
205.9°C/W (MSOP)
JC
Thermal Impedance ....................................... 56°C/W (SOIC)
43.74°C/W (MSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) ........................................................ 215°C
Infrared (15 sec) ................................................................ 220°C
Pb-Free Temperature, Soldering Reflow ............................. 260(0)°C
ESD ............................................................................................. 4kV
Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections
of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and
lifetime.
PACKAGE/ORDERING INFORMATION
ORDER NUMBER PART MARKING CARRIER QUANTITY
TSA7887ARZ TS7887A TUBE 97
TSA7887ARZ-REEL Tape & Reel 2500
TSA7887BRZ TS7887B TUBE 97
TSA7887BRZ-REEL Tape & Reel 2500
ORDER NUMBER PART MARKING CARRIER QUANTITY
TSA7887ARMZ TAAV TUBE 50
TSA7887ARMZ-REEL Tape & Reel 2500
Lead-free Program: Silicon Labs supplies only lead-free packaging.
Consult Silicon Labs for products specified with wider operating temperature ranges.
SILIEEIN LABS
TSA7887
TSA7887 Rev. 1.0 Page 3
ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.25V; VREF = 2.5V External/Internal Reference unless otherwise noted; fSCLK = 2 MHz;
TA = TMIN to TMAX, unless otherwise noted.
Parameter A Version1 B Version1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio (SNR)2 71 71 dB (typ) fIN = 10 kHz sine wave, fSAMPLE = 125 ksps
Total Harmonic Distortion (THD) 80 80 dB (typ) fIN = 10 kHz sine wave, fSAMPLE = 125 ksps
Peak Harmonic or Spurious Noise –80 80 db (typ) fIN = 10 kHz sine wave, fSAMPLE = 125 ksps
Intermodulation Distortion (IMD)
Second-Order Terms 80 80 dB (typ) f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 125 ksps
Third-Order Terms 80 80 dB (typ) f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 125 ksps
Channel-to-Channel Isolation 80 80 dB (typ) fIN = 25 kHz
Full-Power Bandwidth 2.5 2.5 MHz (typ) Measured at 3 dB down
DC ACCURACY(Any channel)
Resolution 12 12 Bits
Integral Nonlinearity ±2 ±1 LSB (max)
Differential Nonlinearity ±2 ±1 LSB (max) Guaranteed no missing codes to 11 bits (A Grade)
Offset Error
±3 ±3 LSB (max) VDD = 5V, dual-channel mode
±4 ±4 LSB (max) VDD = 3V, dual-channel mode
±6 ±6 LSB (typ) Single-channel mode
Offset Error Match 0.5 0.5 LSB (max)
Gain Error
±2 ±2 LSB (typ) Dual-channel mode
±1 ±1 LSB (max) Single-channel mode, external reference
±6 ±6 LSB (typ) Single-channel mode, internal reference
Gain Error Match 2 2 LSB (max)
ANALOG INPUT
Input Voltage Ranges 0 to VREF 0 to VREF V
Leakage Current ±5 ±5 A (max)
Input Capacitance 10 10 pF (typ)
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range 2.5/VDD 2.5/VDD V (min/max) Functional from 1.2V
Input Impedance 10 10 k (typ) Very high impedance if internal reference disabled
REFOUT Output Voltage 2.45/2.55 2.45/2.55 V (min/max)
REFOUT Temperature Coefficient ±50 ±50 ppm/°C (typ)
LOGIC INPUTS
Input High Voltage, VINH 2.4 2.4 V (min) VDD = 4.75V to 5.25V
2.1 2.1 V (min) VDD = 2.7V to 3.6V
Input Low Voltage, VINL 0.8 0.8 V (max) VDD = 2.7 V to 5.25 V
Input Current, IIN ±1 ±1 A (max) Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN3 10 10 pF (max)
LOGIC OUTPUTS
Output High Voltage, VOH I
SOURCE = 200 A
VDD 0.5 VDD 0.5 V (min) VDD = 2.7V to 5.25V
Output Low Voltage, VOL 0.4 0.4 V (max) ISINK = 200 A
Floating-State Leakage Current ±1 ±1 A (max)
Floating-State Output Capacitance4 10 10 pF (max)
Output Coding Straight (Natural) Binary
CONVERSION RATE
Throughput Time 16 16 SCLK cycles Conversion time plus acquisition time is 125 ksps,
with 2 MHz Clock
Track-and-Hold Acquisition Time 1.5 1.5 SCLK cycles
Conversion Time 14.5 14.5 SCLK cycles 7.25 s (2 MHz Clock)
SILIEEIN LABS
TSA7887
Page 4 TSA7887 Rev. 1.0
RTFDS
ELECTRICAL SPECIFICATIONS (continued)
VDD = +2.7V to +5.25V; VREF = 2.5V External/internal reference unless otherwise noted; fSCLK = 2 MHz;
TA = TMIN to TMAX, unless otherwise noted.
Parameter A Version1 B Version1 Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD +2.7/+5.25 +2.7/+5.25 V (min/max)
IDD
Normal Mode4 (PM Mode 2)
Static 700 700 A (max)
Operational (fSAMPLE = 125 kSPS) 850 850 A (typ) Internal reference enabled
700 700 A (typ) Internal reference disabled
Using Standby Mode (PM Mode 4) 450 450 A (typ) fSAMPLE = 50 ksps
Using Shutdown Mode
(PM Modes 1 and 3)
120 120 A (typ) fSAMPLE = 10 ksps
12 12 A (typ) fSAMPLE = 1 ksps
Standby Mode5 210 210 A (max) VDD = 2.7V to 5.25V
Shutdown Mode5 1 1 A (max) VDD = 2.7V to 3.6V
2 2 A (max) VDD = 4.75V to 5.25V
Normal Mode Power Dissipation 3.5 3.5 mW (max) VDD = 5 V
2.1 2.1 mW (max) VDD = 3 V
Shutdown Power Dissipation 5 5 W (max) VDD = 5 V
3 3 W (max) VDD = 3 V
Standby Power Dissipation 1.05 1.05 mW (max) VDD = 5 V
630 630 W (max) VDD = 3 V
Note 1: The TSA7887’s temperature range is –40°C to +125°C for both A and B versions.
Note 2: SNR calculation includes distortion and noise components.
Note 3: Sample tested at TA = 25°C to ensure compliance.
Note 4: All digital inputs at GND except for CS at VDD. All digital outputs are unloaded. Analog inputs are connected to GND.
Note 5: SCLK is at GND when SCLK is off. All digital inputs are at GND except for CS at VDD. All digital outputs are unloaded. Analog inputs
are connected to GND.
SILIEEIN LABS TO OUTPUT PIN +16V c 532$:D I zoom
TSA7887
TSA7887 Rev. 1.0 Page 5
TIMING SPECIFICATIONS
1
Parameter
Limit at T
MIN
, T
MAX
Unit Description
(A, B Versions)
4.75V to 5.25V 2.7V to 3.6V
f
SCLK2
2 2 MHz (max)
t
CONVERT
14.5 × t
SCLK
14.5 × t
SCLK
t
ACQ
1.5 × t
SCLK
1.5 × t
SCLK
Throughput time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
t
1
10 10 ns (min)
CS to SCLK setup time
t
23
30 60 ns (max)
Delay from CS until DOUT three-state disabled
t
33
75 100 ns (max)
Data access time after SCLK falling edge
t
4
20 20 ns (min) Data setup time prior to SCLK rising edge
t
5
20 20 ns (min) Data valid to SCLK hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns (min) SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns (min) SCLK low pulse width
t
84
80 80 ns (max)
CS rising edge to DOUT high-Z
t
9
5 5 s (typ) Power-up time from shutdown
Note 1: Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of
VDD) and timed relative to a voltage level of 1.6V.
Note 2: The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details.
Note 3: Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V.
Note 4: Timing specification t
8
is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown
below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This
means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish time of the TSA7887 and is independent of bus
loading.
Load Circuit Used for TSA7887’s Digital Output Timing
Specifications.
7 . SILICON LABS AFMVV
TSA7887
Page 6 TSA7887 Rev. 1.0
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Rejection vs Frequency
POWER SUPPLY REJECTION - dB
-97
-93
-89
-85
-77
FREQUENCY - kHz
-81
2.65 23.2 33.7 43.9
12.9 54.4 64.2
VDD = 2.7V/5.5V
REFIN (External) = 2.488V
100mVPP Sine Wave on VDD
VDD = 5V
REFIN
(
External
)
= 5V
Signal-to-Noise Ratio vs Frequency
SIGNAL-TO-NOISE RATIO - dB
70
70.5
71
72
71.5
0.7 21.4 31.8 42.1
11
FREQUENCY - kHz
Dynamic Performance vs Frequency
FFT RESULTS - dB
-140
-100
-80
-60
-40
0
FREQUENCY - kHz
-20
0 20 30 40
10 50
-120
60
4096-point FFT
125kHz Sampling Rate
10kHz Fundamental
SILIEEIN LAB"1
TSA7887
TSA7887 Rev. 1.0 Page 7
PIN FUNCTIONS
PIN LABEL DESCRIPTION
1 CS
Chip Select: As an active low logic input signal, the CS input provides the dual function of
initiating TSA7887 conversions as well as framing the serial data transfer. When the
TSA7887 is operated in Mode 1(its default power management mode), the CS pin also
acts as the shutdown pin in that the TSA7887 is powered-down when the CS pin is logic
high.
2 VDD
Power Supply Voltage: The TSA7887’s VDD range +2.7V to +5.25V. In two-channel
operation, the VDD pin also serves as the TSA7887’s voltage reference source during
conversions. For optimal performance, the VDD pin should be bypassed to GND with a
10-µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor.
3 GND
Analog Ground Pin: The GND pin is the ground reference point for all TSA7887 internal
circuitry. In systems with separate AGND and DGND planes, the TSA7887’s GND pin
should be connected to the AGND plane.
4 AIN1/VREF
Analog Input Channel 1/External VREF Input: In single-channel mode, the AIN1/VREF pin
is configured as VREFIN/OUT. In this mode, the TSA7887’s internal 2.5V reference can be
accessed or an external reference can be applied to this pin thereby overriding the internal
reference. The reference voltage range for an externally-applied reference is 1.2V to VDD.
In two-channel mode, the AIN1/VREF pin operates as a second analog input channel,
AIN1. The input voltage range on AIN1 is 0 to VDD.
5 AIN0
Analog Input Channel 0: In single-channel operation, AIN0 is the TSA7887’s analog input
with an input voltage range of 0V to VREF. In two-channel operation, the AIN0 pin exhibits
an analog input range of 0V to VDD.
6 DIN
Serial Data Input: Serial data to be loaded into the TSA7887’s control register is applied at
the DIN pin. Serial data is loaded into the ADC from the host processor on low-to-high
SCLK transitions (see the Control Register section for additional information). Configuring
the TSA7887 as a single-channel, read-only ADC can be achieved by hard-wiring the DIN
pin to GND or by applying a logic LOW at all times at the DIN pin.
7 DOUT
Serial Data Output: The TSA7887’s conversion result is available on this pin. Serial data is
transferred out of the TS7887 on high-to low transitions of SCLK. The 12-bit conversion
result is comprised of four leading zeros followed by the 12 bits of conversion data
formatted MSB first. Thus, a total of 16 SCLK high-to-low transitions transfers the
conversion result to the host processor as shown in the corresponding timing diagram of
Figure 14.
8 SCLK
Serial-Clock Input: SCLK is used for (3) purposes: a) to load serial data from the host
processor into the TSA7887’s control register on low-to-high SCLK transitions; b) to
transfer the 12-bit conversion result to the host processor on high-to-low SCLK transitions;
and c) to control the TSA7887’s conversion process.
qILIEElN LABS
TSA7887
Page 8 TSA7887 Rev. 1.0
TSA7887 CONTROL REGISTER DESCRIPTION
The TSA7887’s write-only control register is 8-bits
wide. Serial ADC configuration data is uploaded
from the host processor at the TSA7887’s DIN pin
on low-to-high SCLK transitions. Serial input data is
uploaded to the TSA7887 simultaneously as the
conversion result is transferred out of the TSA7887.
All serial data transfers require 16 serial clocks
transitions. After a high-to-low CS transition signal,
serial data available on the first eight low-to-high
SCLK transitions is transferred into the control
register. The first bit in the serial data stream is
always interpreted as the MSB. Upon initial power-
up, the TSA7887’s default control register bit is
cleared to all zeros (all “0”s). Table 1 lists the
functions of the Control Register’s 8 bits.
Table 1. TSA7887’s 8-Bit Control Register Content Description
DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)
DONTC ZERO REF SIN/DUAL CH ZERO PM1 PM0
DBx Label Comment
7 DONTC Control Register DB7: Bit status of DB7 is “Don’t Care.” In other words, the DB7 bit can be a “0” or a “1”.
6 ZERO
Control Register DB6: To ensure correct TS7887 operation, Control Register DB6 status must always be a “zero”
(“0”).
5 REF
Control Register DB5 – Internal Voltage Reference Configuration: The status of DB5 determines whether the
TSA7887’s internal voltage reference is enabled or disabled. A “0” in the DB5 location will enable the TSA7887’s
internal voltage reference (default condition). To disable the TSA7887’s internal voltage reference, a “1” must be
written into DB5’s register location.
4 SIN/DUAL
Control Register DB4 - Single-Channel/Dual-Channel Configuration. Control Register DB4 configures the TSA7887 as
a single-channel or two-channel ADC. Loading a “zero” (“0”) into this register location configures the TSA7887 for
single-channel operation with the AIN1/VREF pin configured to for internal VREF operation (default configuration). In
this case, the analog input signal range is 0V to VREF. Loading a “one” (“1”) into this register location configures the
TSA7887 for two-channel operation with the AIN1/VREF pin configured to its AIN1 function as the second analog
input. In addition, the conversion process’s reference voltage is internally connected to VDD. In this case, the analog
input signal range is 0V to VDD. To obtain best performance from the TSA7887 in two-channel operation, the ADC’s
internal reference should be disabled; that is, a “1” should be loaded into DB5’s register location.
3 CH
Control Register DB3 - Channel Select Bit: The bit status of DB3 determines on which channel the TSA7887 is
converting. When the ADC is configured for dual-channel operation, DB3 determines which channel is converted on
the next conversion cycle. When DB3 is a “zero” (a “0”), the AIN0 input is selected and, when DB3 is a “one” (a “1”),
the AIN1 input is selected. DB3 should be a “zero” (“0”) when the TSA7887 is configured for single-channel operation.
2 ZERO
Control Register DB2: To ensure correct TS7887 operation, Control Register DB2 status must always be a “zero”
(“0”).
1 PM1
Control Register DB1 and DB0 - Power Management Operating Modes: DB1 and DB0 are decoded to configure the
TSA7887 into one of four operating modes as shown in Table 2.
0 PM0
Table 2. TSA7887’s Power Management Operating Modes
PM1 PM0 Mode
0 0
PM Mode 1: In this operating mode, the TSA7887’s power-down mode is enabled if its CS input is a “one” ( a “1”) and is
operating in full-power mode when its CS input is a “zero” (a “0”). Thus, the TSA7887 is powered down on a low-to-high
CS transition and is powered up on a high-to-low CS transition.
0 1
PM Mode 2: In this operating mode and regardless of the status of any of the logic inputs, the TSA7887 is always fully
powered up.
1 0
PM Mode 3: In this operating mode, the TSA7887 is automatically powered down at the end of each conversion
regardless of the state of the CS input. ADC wake-up time from full shutdown is 5s and system design should ensure
that at least 5s have elapsed before attempting to perform a conversion in this mode; otherwise, an invalid conversion
result may occur.
1 1
PM Mode 4: In this operating mode, the TSA7887 is configured for standby operation after conversion. Sections of the
TSA7887 are powered down; however, the internal 2.5-V reference voltage remains powered up. While PM Mode 4 is
similar to PM Mode 3, PM Mode 4 operation allows the TSA7887 to power up much faster. For optimal performance, the
Control Register’s REF bit (DB5) should be a “zero” (“0”) to ensure the internal reference is enabled/remains enabled.
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TSA7887
TSA7887 Rev. 1.0 Page 9
DESCRIPTION OF OPERATION
The TSA7887 is a single-supply, low-power,
single/dual-channel, 12-bit successive-
approximation ADC with an easy-to-use serial
interface. The ADC can be operated from a 3V
supply (2.7V to 3.6V) or from a 5V supply (4.75V to
5.25V). When operated from either a 3V or 5V
supply, the TSA7887 can operate at throughput
rates up to 125ksps when an external 2 MHz clock is
applied.
In 8-pin SOIC and MSOP packages, the TSA7887
integrates a 2.5-V reference, a high-speed
track/hold, a successive-approximation ADC, and a
serial digital interface. An external serial clock is
used to transfer data to/from the ADC and controls
the TSA7887’s conversion process. The TSA7887
can be configured for single- or two-channel
operation. When configured as a single-channel
ADC, the analog input range is 0 to VREF (where an
externally applied VREF, if used, can range between
1.2 V and VDD). When the TSA7887 is configured
for two-channel applications, the analog input range
on each channel is set internally from 0V to VDD.
If the TSA7887 is configured for single-channel
operation, the TSA7887 can be operated in a read-
only mode by applying a logic LOW at all times to
the DIN pin (Pin 6) or by hard-wiring the DIN pin
permanently to GND. For maximum flexibility to
address multiple configurations based on the
application, the DIN input can be used to load ADC
configuration data from a host processor into the
TSA7887’s 8-bit Control Register.
TSA7887 Operation and Transfer Function
The TSA7887 is a successive-approximation ADC,
the core of which is a charge-redistribution DAC.
Figure 1 illustrates an equivalent circuit for the
TSA7887 in signal acquisition phase. Here, Switch
SW1 is in Position A and Switch SW2 is closed. With
the sampling capacitor’s terminals connected to the
analog input on one side and REF on the other, the
analog signal is acquired. During the acquisition
phase, the inputs to the comparator are balanced
since both inputs are connected to REF.
During the conversion phase as shown in the
equivalent circuit in Figure 2, Switch SW1 is moved
from Position A to GND at Position B and Switch
SW2 is opened. At this point in time, the inputs to
the comparator become unbalanced. The
TSA7887’s control logic and the charge-
redistribution DAC work together to add or subtract
fixed packets of charge from the sampling capacitor
to balance once again the comparator input
terminals. At the time when the comparator is
rebalanced, the conversion process is complete and
the ADC’s control logic generates the ADC serial
output conversion data.
Figure 3 illustrates the ideal transfer function for the
TSA7887 where the output data is coded straight
binary. Thus, the designed code transitions occur at
successive integer LSB values (that is, at 1 LSB, at
2 LSBs, etc) where the LSB size is VREF/4096.
Figure 1:TSA7887’s Acquisition Phase Equivalent
Circuit
Figure 2: TSA7887’s Conversion Phase Equivalent
Circuit
Figure 3: TSA7887’s Unipolar Transfer Function for
Straight Binary Digital Data.
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TSA7887
Page 10 TSA7887 Rev. 1.0
Typical Application Circuit
Figure 4 shows a typical application circuit for the
TSA7887 where the ADC’s GND pin is connected to
the analog ground plane of the system. In this
application circuit, the TSA7887 has been
configured for two-channel operation so the ADC’s
VREF is internally connected to VDD; as a result,
the analog input range on either analog input is 0V
to VDD. It is always considered good engineering
practice to bypass the ADC’s VDD with good quality
capacitors with short leads (surface-mount
components are preferred) and located a very short
distance from the ADC. The conversion result at the
DOUT pin is a 16-bit word with four leading zeros
followed by the MSB of the 12-bit conversion result.
In low-power applications, automatic-power-down-at-
the-end-of-conversion modes (PM Modes 3 or 4)
should be used to improve the ADC’s power
consumption-versus-throughput rate performance.
For additional information on the TSA7887’s four
power management operating modes, please
consult the Operating Modes section of the
datasheet.
Analog Input Details
An equivalent circuit of the analog input structure of
the TSA7887 is illustrated in Figure 5 where diodes
D1 and D2 serve as ESD-clamp protection for the
analog inputs. Since there are diodes from the
analog input to both VDD and GND, it is important
any forward conduction of current in D1 or D2 is
avoided. Thus, the analog input signal should never
exceed the either VDD or GND by more than
200mV. Even though the maximum current these
diodes can conduct without causing irreversible
damage to the ADC is 20mA, any small amount of
forward diode current into the substrate because of
an overvoltage condition on an unselected channel
can cause inaccurate conversion results on the
selected channel.
Attributed to parasitic package pin capacitance,
capacitor C1 in Figure 5 is typically about 1 pF.
Resistor R1 is the equivalent series resistance of the
TSA7887’s input multiplexer and input sampling
switch and is approximately 100. Capacitor C2 is
the ADC sampling capacitor and has a typical
capacitance of 10 pF.
In signal-acquisition (or ac) applications, the use of
an external R-C low-pass filter on either or both
analog inputs can be useful in removing out-of-band
high-frequency components from the analog input
signal. In applications where harmonic distortion and
signal-to-noise ratio performance are important, the
analog input(s) should be driven from a low-
impedance source. Large source impedances will
affect significantly the TSA7887’s ac performance.
To lower the driving-point impedance level may
impose the use of an input buffer amplifier. The
optimal choice for the external drive op amp will be
determined by application requirements as well as
the TSA7887’s dynamic performance.
When the analog input is not driven by an external
amplifier, the driving-point source impedance should
be low. The maximum source impedance will
depend upon the amount of total harmonic distortion
(THD) that can be tolerated in the application. THD
will increase as the source impedance increases
Figure 4:
TSA7887's Typical Application Circuit.
Figure 5:
TSA7887’s Analog Input Equivalent Circuit.
INPUT FREQUENCY - kHz
TOTAL HARMONIC DISTORTION - dBc
VDD = 5V
5V External Reference
-65
-75
-85
-90 0.2 10 30 50
20
-60
Figure 6: TSA7887 THD vs Analog Input Frequency
RIN = 50,CIN = 2.2nF
RIN = 10,CIN = 10nF
-70
-80
40
7 . SILICON LAB“ AINWREF I TO CDAC 5w: .2 5v 10m __ REF g
TSA7887
TSA7887 Rev. 1.0 Page 11
and performance will degrade. Figure 6 illustrates
how the TSA7887’s harmonic performance as a
function of frequency is affected by different source
impedances.
The TSA7887’s Internal 2.5-V Reference
Using the REF bit (the DB5 bit) in the TSA7887’s
Control Register, the TSA7887’s internal 2.5-V
reference can be enabled (DB5 cleared to “0”) or
disabled (DB5 set to “1”). If enabled (the default
condition), the internal voltage reference can be
used in applications for other purposes and, if this is
desired, the reference should be buffered by an
external, precision op amp. If an external, precision
voltage reference is to be used instead of the
TSA7887’s internal reference, the internal reference
is automatically overdriven. In this case, the
TSA7887’s internal reference should be disabled by
setting the REF bit in the control register. When the
internal reference is disabled, switch SW1 as shown
in Figure 7 opens and the input impedance seen at
the AIN1/VREF pin is the reference buffer’s input
impedance, approximately in the gigaohm range
(G). When the internal reference is enabled, the
input impedance at the AIN1/VREF pin is typically
10k. When the TSA7887 is configured for two-
channel operation, the TSA7887’s reference is set
internally to VDD.
TSA7887’s Power-Down Operating Modes
The TSA7887 provides flexible power management
to allow the user to achieve the best power
performance for a given throughput rate. The four
power management options are selected by
programming the TSA7887’s power management
bits (“PM” Bits PM1 and PM0) in the control register
as summarized in Table 6. When the PM bits are
programmed for either of the auto power-down
modes (PM Mode 3 or 4), the TSA7887 is powered-
down on the 16th low-to-high SCLK transition after a
high-to-low CS transition. The first high-to-low SCLK
transition after a high-to-low CS transition powers-
up the TSA7887 again. When the TSA7887 is
programmed in PM Mode 1 (i.e., [PM1,PM0] = [0,0],
the default condition), the TSA7887 is powered
down on a low-to-high CS transition and powers up
from shutdown on a high-to-low CS transition. If the
CSpin is toggled low-to-high during the conversion
in this operating mode, the ADC is immediately
powered down.
Cold-Start and Standby Power-Up Delay Times
When VDD is first applied to the TSA7887 (in other
words, from cold start-up), the ADC powers up in PM
Mode 1 ([PM1,PM0] = [0,0]). Upon a subsequent
high-to-low CStransition, the TSA7887’s power-up
delay time is approximately 5s When using an
external voltage reference in single-channel
operation or when the TSA7887 is powered up from
standby mode (PM Mode 4), its power-up delay time
is approximately 1s because the internal reference
has been either disabled (refer to Control Register
DB5) or the internal reference has remained
powered up (via PM Mode 4). Since the TSA7887’s
power-up delay time PM Mode 4 is very short,
powering up the ADC and executing a conversion
with valid results in the same read/write operation is
feasible.
TSA7887 Power Consumption vs.
Throughput Rate Considerations
In operating the TSA7887 in auto-shutdown mode
(PM Mode 3), in auto-standby mode (PM Mode 4),
or in PM Mode 1, the average power drawn by the
TSA7887 decreases at lower throughput rates. As
shown in Figure 8, the average power drawn from
Figure 7: TSA7887’s Integrated 2.5-V VREF Circuitry.
THROUGHPUT RATE - ksps
POWER CONSUMPTION - mW
1
0.1
0.01
0 10 30 50
20
10
Figure 8: TSA7887 Power Consumption
vs Throughput Rate
VDD = 3V
SCLK = 2MHz
VDD = 5V
SCLK = 2MHz
40
TsATsBT POWERS UP ON E TSATss1 POWERS DOWN ON (E FALLING EDGE FDR FMI AND PMO= o RISING EDGE FDR PMI AND PM) = 0 —\—\/— I 4 a 12 15 SCLK H (:5 HIGH-Z HIGH-Z BOUT FOUR LEADING ZEROS o CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA Is LOADED ON THE FIRST EIGHT CLOCKS PMI AND PM) = 0 To KEEP THE TsATIm IN MODE I QILICDN LABS
TSA7887
Page 12 TSA7887 Rev. 1.0
the supplies by the ADC is commensurately reduced
the longer the TSA7887 remains in a powered-down
state.
For example, consider the following TSA7887
application configuration: (a) the ADC is powered
from VDD = 5V and is configured for PM Mode 3
(that is, [PM1, PM0] = [1,0], where the ADC’s
internal reference is enabled and the ADC
automatically powers down after the conversion is
completed); and (b) the ADC operates at a
throughput rate of 10 ksps with a 2-MHz SCLK.
Given the above configuration, the TSA7887’s
power consumption during normal operation is
3.5mW at VDD = 5 V (0.7mA x 5V). Since its power-
up delay time is 5s and its conversion-plus-
acquisition time is ~7.75s (t
CONVERT
+ t
ACQ
= 14.5 x
t
SCLK
+ 1.5 x t
SCLK
= 15.5 x t
SCLK
), the TSA7887
consumes 3.5mW for 12.75s during each
conversion cycle. Since the conversion cycle time
(100s) is the reciprocal of the ADC’s throughput
rate (10ksps), the average power consumed by the
TSA7887 during each conversion cycle is
(12.75/100) × (3.5mW), or 446.25W. If the ADC’s
configuration were unchanged and, if the supply
voltage were then reduced to 3V, the power
consumed by the ADC would then be 2.1mW
(0.7mA x 3V). Since the total time required for
power-up, acquisition, and conversion remains at
12.75s, the average power consumed during each
cycle at a 10-ksps throughput rate is (12.75/100) ×
(2.1mW), or 267.75W. The TSA7887’s power
consumption vs. throughput rate when configured for
automatic shutdown post conversion and operating
on both 5V and 3V supplies is illustrated in Figure 8.
Power Management Operating Modes
Designed to provide flexible power consumption
profiles, the TSA7887 incorporates four different
operating modes to optimize the ADC’s power
consumption/throughput-rate ratio. As previously
described in Table 6, the four different modes of
operation in the TSA7887 are controlled by the PM1
and PM0 bits of the Control Register. Also
mentioned previously, the TSA7887 can be
configured as a read-only ADC by forcing an all
zeros (“0”s) condition in the control register. This can
be easily done by applying a logic LOW at all times
to the DIN pin or hard-wiring the DIN pin directly to
GND.
Power Management Mode 1 Operation:
[PM1,PM0] = [0,0]
Power Management Operating Mode 1 is used to
control the TSA7887’s power-down using the CSpin.
Whenever the CSpin is low, the TSA7887 is fully
powered up; whenever the CSpin is high, the
TSA7887 is completely powered down. When the
CS pin is toggled high-to-low, all internal circuitry
starts to power up where it can take as long as 5s
for the TSA7887’s internal circuitry to power up
completely. As a result, any conversion start
sequence should not be initiated during this initial
5s power-up delay.
Figure 9 shows a general operating diagram of the
TSA7887 in PM Mode 1. The analog input signal is
sampled on the second low-to-high SCLK transition
following the initial high-to-low CS transition. System
timing design should incorporate a 5-s delay
between the high-to-low CS transition and the
second low-to-high SCLK transition. In
microcontroller applications, this is achieved by
Figure 9: TSA7887’s Power Management Mode 1 Operation Diagram.
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TSA7887
TSA7887 Rev. 1.0 Page 13
driving the CS pin from one of the host processor’s
port lines and ensuring that the serial data read
(from the microcontroller’s serial port) is not initiated
for at least 5s.
In DSP applications, where the CS signal is derived
typically from the DSP’s serial frame synchronization
port, it is usually not possible to separate a high-to-
low CS transition and a second low-to-high SCLK
transition by up to 5s without affecting the DSP
system serial clock speed. Therefore, system timing
design should incorporate a WRITE to the
TSA7887’s control register to terminate PM Mode 1
operation and program the ADC into PM Mode 2;
that is, by writing [PM1,PM0] = [0,1] into the
TSA7887’s control register. To get a valid
conversion result, a second conversion must be
initiated when the ADC is powered up. A WRITE
operation that takes place with this second
conversion can program the ADC back into PM
Mode 1 where the power-down operation is enabled
when the CS pin is toggled high
Power Management Mode 2 Operation:
[PM1,PM0] = [0,1]
Regardless of the status of the CS signal, the
TSA7887 remains fully powered up in this mode of
operation. PM Mode 2 should be used for fastest
throughput rate performance because the system
timing design does not need to incorporate the
TSA7887’s 5-s power-up delay time. Figure 10
shows the general operating diagram for the
TSA7887 in PM Mode 2.
Serial data programmed into the TSA7887 at the
DIN input during the first eight clock cycles of data
transfer are loaded to the control register. For the
TSA7887 to remain in PM Mode 2, system timing
design must always write [PM1, PM0] = [0,1] into the
control register on every serial input data transfer.
A high-to-low CS transition initiates the conversion
sequence and the analog input signal is sampled on
the second low-to-high SCLK transition. Sixteen
serial clock cycles are required to complete the
conversion and to transfer the conversion result to
the host processor. Another conversion can be
initiated immediately by toggling the CS pin low
again once data transfer is complete (that is, once
the CS signal is toggled high).
Power Management Mode 3 Operation: [PM1,
PM0] = [1,0]
In this mode, the TSA7887 is automatically powered
down at the end of every conversion. It is similar to
PM Mode 1 except that the status of the CS signal in
PM Mode 3 does not have any effect on the power-
down status of the TSA7887.
Figure 11 shows the general operating diagram of
the TSA7887 in PM Mode 3. On the first high-to-low
SCLK transition after CS is toggled low, all
TSA7887’s internal circuitry starts to power up.
Similarly to PM Mode 1, it can take as long as 5s
for the TSA7887’s internal circuitry to power up
completely. As a result, any conversion start
sequence should not be initiated during this initial
5-s power-up delay. The analog input signal is
sampled on the second low-to-high SCLK transition
following the high-to-low CS transition. As shown in
Figure 18, system timing design should incorporate
a 5-s delay between the first high-to-low SCLK
transition and the second low-to-high SCLK
transition after the high-to-low CS transition.
Figure 10: TSA7887’s Power Management Mode 2 Operation Diagram.
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TSA7887
Page 14 TSA7887 Rev. 1.0
In microcontroller applications (or in systems with a
slow serial clock), the system timing design can be
devised to accommodate this timing alignment by
assigning the CS signal to one of the port lines and
then adjusting the timing such that the serial data
read (from the microcontroller’s serial port) is not
initiated for at least 5s.
However, in systems with higher speed serial clocks
(not unlike high-speed serial-clock DSP
applications), it may not be possible to insert a 5s
delay between ADC power up and the first low-to-
high SCLK transition. Therefore, system timing
design should incorporate a WRITE to the
TSA7887’s control register to terminate the ADC’s
PM Mode 3 operation and program the TSA7887
into PM Mode 2; that is, by writing [PM1,PM0] = [0,1]
into the TSA7887’s control register. To get a valid
conversion result, a second conversion must be
initiated when the ADC is powered up – see
Figure 19. A WRITE operation that takes place with
this second conversion can program the ADC back
into PM Mode 3 where the power-down operation is
enabled when the conversion sequence terminates.
Power Management Mode 4 Operation:
[PM1,PM0] = [1,1]
In PM Mode 4, the TSA7887 is automatically placed
in standby (or sleep) mode at the end of every
conversion. In this mode, all internal circuitry is
powered down except for the internal 2.5-V
reference. PM Mode 4 is similar to PM Mode 3; in
this case, the power-up delay time is much shorter
(1s vs 5s) because the internal reference remains
powered up at all times.
Figure 13 shows the general operating diagram of
the TSA7887 in PM Mode 4. On the first high-to-low
SCLK transition after the CS pin is toggled low, the
TSA7887 is powered up out of its standby mode.
Since the TSA7887’s power-up delay time PM Mode
4 is very short, powering up the ADC and executing
a conversion with valid results in the same read/write
operation is feasible. The analog input signal is
sampled on the second low-to-high SCLK transition
Figure 11: TSA7887’s Power Management Mode 3 Operation Diagram for Slow-SCLK Microcontrollers.
Figure 12: TSA7887’s Power Management Mode 3 Operation Diagram for Fast-SCLK Microcontrollers and DSPs.
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TSA7887
TSA7887 Rev. 1.0 Page 15
following the high-to-low CS transition. At the end of
conversion (after the last low-to-high SCLK
transition), the ADC is powered down automatically
back into its standby mode.
The TSA7887’s Serial Interface Description
Figure 14 shows the detailed timing diagram for
TSA7887’s serial interface. The serial clock provides
the conversion clock and also controls the transfer of
data to/from the TSA7887 during conversion.
The CS signal initiates the serial data transfer and
controls the TSA7887’s conversion process. In PM
Modes 1, 3, and 4, a high-to-low CS transition
powers up the ADC. In all cases, the CS signal
gates SCLK to the TSA7887 and sets the ADC’s
internal track-and-hold into track mode. The analog
input signal is then sampled on the second low-to-
high SCLK transition following the high-to-low CS
transition. Thus, the analog input signal is acquired
during the first 1.5 SCLK clock cycles (t
ACQ
) after the
high-to-low CS transition. In modes where the high-
to-low CS transition powers up the ADC, the
acquisition time must include a 5-s power-up delay.
The ADC’s internal track-and-hold moves from track
mode to hold mode on the second low-to-high SCLK
transition and a conversion is also initiated on this
transition. The conversion process takes an
additional 14.5 SCLK cycles to complete. After the
conversion is completed, a subsequent low-to-high
CS transition sets the serial data bus back into a
high-Z (or three-state) condition. A new conversion
can be initiated if the CS signal is left low.
In dual-channel operation, the current conversion
result is associated to the selected analog channel
programmed during the previous write cycle to the
control register. Therefore, in dual-channel
operation, the system code design must perform a
channel address write for the next conversion while
the current conversion is in progress.
Writing serial data to the Control Register always
takes place and occurs on the first eight low-to-high
SCLK transitions. However, the TSA7887 can be
configured as a read-only device by physically
Figure 14: TSA7887’s Detailed Serial Interface Timing Diagram.
Figure 13: TSA7887’s Power Management Mode 4 Operation Diagram.
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TSA7887
Page 16 TSA7887 Rev. 1.0
loading all “zeros” (“0”s) into the Control Register
every time, by applying a logic LOW to the DIN pin
at all times, or by hard-wiring the DIN pin to GND.
When the TSA7887 is configured in WRITE/READ
modes, system code design must be designed
always to load the correct data onto the DIN line
when reading data from the TSA7887.
Sixteen serial clock cycles are required to perform
the conversion process and to transfer data
to/access data from the TSA7887. In applications
where the first serial clock transition following a high-
to-low CS transition is a high-to-low SCLK transition,
DOUT transitions from a high-Z state to a first
leading zero; thus, the first low-to-high SCLK
transition generates the first leading zero on DOUT.
In applications where the first serial clock transition
following a high-to-low CS transition is a low-to-high
SCLK transition, the first leading zero may not be set
up in time for the host processor to read it correctly.
However, subsequent DOUT bits are transferred out
on high-to-low SCLK transitions so that they are
ready for the host processor on the following low-to-
high SCLK transition. Thus, the second leading zero
is transferred out on the high-to-low SCLK transition
subsequent to the first low-to-high SCLK transition.
Therefore, DOUT’s final bit in the data transfer is
valid on the 16th low-to-high SCLK transition, having
been transferred out of the ADC on the previous
high-to-low SCLK transition.
Interfacing the TSA7887 to Industry-
Standard Microprocessors and DSPs
The serial interface on the TSA7887 allows the ADC
to be directly connected to a number of many
microprocessors and DSPs. How to interface the
TSA7887 with some of the more common
microcontroller and DSP serial interface protocols is
covered in this section.
A TSA7887 to TMS320C5x DSP Interface
With peripheral serial devices like the TSA7887, the
TMS320C5x’s serial interface has a continuous
serial clock and frame synchronization signals to
time the data transfer operations. A single logic
inverter is the only glue logic required between the
TMS320C5x’s CLKX output and the TSA7887 SCLK
input and is illustrated in the connection diagram of
Figure 15. The TMS320C5x’s serial port is
configured to operate in burst mode using the
TMS320C5x’s internal CLKX (serial clock transmit)
and FSX (frame sync transmit) programmed as the
TSA7887’s CS input. The TMS320C5x’s serial port
control register (SPC) must be configured in the
following manner:
Table 3: TMS320C5x Serial Port Control Register
Setup
FO FSM MCM TXM
0 1 1 1
A TSA7887 to ADSP-21xx DSP Interface
The TSA7887 is easily interfaced to the ADSP-21xx
(or equivalent) family of DSPs using an inverter
between the ADSP-21xx’s serial clock and the
TSA7887 as shown in Figure 16. The ADSP-21xx’s
SPORT control register should be configured in
Alternate Framing mode as shown in Table 4 and
t
he ADSP-21xx’s serial clock frequency is set in its
SCLKDIV register.
Table 4: SPORT0 Control Register Setup
Bit(s) Setting Description
TFSW, RFSW 1 Alternative framing
INVRFS, INVTFS 1 Active-low frame signal
DTYPE 00 Right justified data
SLEN 1111 16-bit data word
ISCLK 1111 Internal serial clock
TFSR, RFSR 1 Frame every word
IRFS 0
ITFS 1
Figure 15: Interfacing the TSA7887 to TSM320C5x-type
DSPs.
Figure 16: Interfacing the TSA7887 to ADSP-21xx-type
DSPs.
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TSA7887
TSA7887 Rev. 1.0 Page 17
With the ADSP-21xx’s TFS and RFS pins of its
SPORT connected together, the TFS is configured
as an output and RFS configured as an input. The
frame synchronization signal generated on the TFS
output serves as the TSA7887’s CS input. In this
example, however, since a timer interrupt is used to
control the sampling rate of the ADC, it may not be
possible to perform equidistant sampling (a required
criterion in all signal processing applications) under
certain application conditions.
The ADSP-21xx’s timer registers are configured in
such a manner that an interrupt is generated
internally at the required sample interval. When the
timer interrupt is received, an ADC control word is
transmitted at the DT output with TFS. The TFS
signal is then used to control the RFS and hence the
data read from the TSA7887. When the instruction
to transmit with TFS is executed (that is, AX0 =
TX0), the state of the SCLK is checked. The DSP
waits until the SCLK has toggled high-to-low-to-high
before a transmission will commence. If the timer
and SCLK values are set such that the instruction to
transmit occurs on or near the low-to-high SCLK
transition, data may be transmitted or the DSP may
wait to transmit data until the next clock edge.
For example, consider an ADSP-2111 that has been
chosen as the host processor. Since it has a
16-MHz master clock frequency, a SCLKDIV value
of 3 is necessary to program its SPORT serial clock
output to operate at 2MHz for the TSA7887
(16MHz ÷ 2
3
= 2MHz); thus, eight master clock
periods will elapse for every one TSA7887 SCLK
period. If the ADSP-2111’s timer registers are
loaded with a value of 803, 100.5 SCLKs will occur
between interrupts and subsequently between
transmit instructions. Because the transmit
instruction occurs on an SCLK edge, non-equidistant
sampling is the result. The DSP will implement
equidistant sampling only if the number of SCLKs
between interrupts is a whole integer number.
A TSA7887 to DSP56xxx DSP Interface
Connecting the TSA7887 for use with Freescale’s
(nee Motorola’s) DSP56xxx family of DSPs is shown
in Figure 17 where an inverter is used between the
DSP56xxx’s SCK output and the TSA7887’s SCLK
input. The DSP56xxx’s SSI (synchronous serial
interface) is configured in synchronous mode (SYN
bit = 1 in CRB) with an internally generated 1-bit
clock period frame sync for both Tx and Rx (Bits
FSL1 = 1 and FSL0 = 0 in CRB). Word length is set
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.
A TSA7887 to 68HC11 Microcontroller Interface
Connecting the TSA7887 to Freescale’s 68HC11
(nee Motorola’s MC68HC11) is shown in Figure 18.
The microcontroller’s serial peripheral interface (SPI)
is configured for Master Mode (MSTR = 1) with its
Clock Polarity Bit (CPOL) set to 1 and Clock Phase
Bit (CPHA) set to 1. Serial data transfer from the
TSA7887 to the 68HC11 requires two 8-bit transfers
and the 68HC11’s SPI is configured by writing to the
SPI Control Register (SPCR) — consult the 68HC11
User Manual for more information.
A TSA7887 to 8051 Microcontroller Interface
Using the parallel port of legacy 8051-type (or
equivalent) microcontrollers, a serial interface to the
TSA7887 can be designed as shown in Figure 19.
As a result, full duplex serial transfer to be
implemented. The technique involves “bit-banging”
one of the the microcontroller’s I/O ports (for
example, P1.0) to generate a serial clock and using
Figure 18: Interfacing the TSA7887 to 68HC11-type
Microcontrollers.
Figure 17: Interfacing the TSA7887 to DSP56xxx-type
DSPs.
Figure 19: Interfacing the TSA7887 to Legacy 8051-type
Microcontrollers.
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TSA7887
Page 18 TSA7887 Rev. 1.0
two other I/O ports (for example, P1.1 for DOUT and
P1.2 for DIN) to transfer data from/to the TSA7887.
A TSA7887 to PIC16C6x/PIC16C7x
Microcontroller Interface
As shown in Figure 20, the connection between the
TSA7887 and the PIC16C6x/PIC16C7x is simple
and does not require any glue logic circuits. The
PIC16C6x synchronous serial port (SSP) is
configured as an SPI master with its clock polarity bit
set to 1 by writing to the synchronous serial port
control register (SSPCON). In this example, I/O port
RA1 is being used to generate the TSA7887’s CS
signal. Since this microcontroller family only
transfers eight bits of data during each serial transfer
operation, two consecutive read/write operations are
required. For additional information, please consult
the PIC16/PIC17 Microcontroller User Manual.
APPLICATIONS INFORMATION
Ground Plane Management and Layout
For best performance, printed circuit boards should
always be used and wire-wrap boards are not
recommended. Good PC board layout techniques
ensure that digital and analog signal lines are kept
separate from each other, analog and digital
(especially clock) lines are not routed parallel to one
another, and high-speed digital lines are not routed
underneath the ADC package.
A contiguous analog ground plane should be routed
under the TSA7887 to avoid digital noise coupling. A
single-point analog ground (star ground point)
should be created at the ADC’s GND and separate
from any digital logic ground. All analog grounds as
well as the ADC’s GND pin should be connected to
the star ground. No other digital system ground
should be made to this ground connection. For
lowest-noise operation, the ground return to the star
ground’s power supply should be low impedance
and as short as possible.
Even though the TSA7887’s exhibits excellent
supply rejection as shown in th Typical Operating
Characteristics, it is always considered good
engineering practice to prevent high-frequency noise
on the TSA7887’s VDD power supply from affecting
the ADC’s high-speed comparator. Therefore, the
VDD supply pin should be bypassed to the star
ground with 0.1F and 10F capacitors in parallel
and placed close to the ADC’s Pin 2 as was shown
in Figure 4. Component lead lengths should be very
short for optimal supply-noise rejection. If the power
supply is very noisy, an optional 10- resistor
inserted in series with the TSA7887’s VDD pin can
be used in conjunction with the bypass capacitors to
form a low-pass filter.
Evaluating the TSA7887’s Dynamic Performance
The recommended layout for the TSA7887 is
outlined in the demo board manual for the TSA7887.
The demo board kit includes a fully
assembled/tested demo board and documentation
describing how to evaluate the TSA7887’s dynamic
performance using Silicon Labs’ proprietary TSDA-
VB data acquisition/capture kit.
Figure 20: Interfacing the TSA7887 to
PIC16C6x/PIC16C7x-type Microcontrollers.
SILICON LAB“ 3.1a Max 0.35 Max 2.90 Mm 015 Mm 4 A 0.23 Max 0.127 0.13 Mm v «0.27 REF» 3.1uMax 503Max 2.9 Mm 4.57Mm 015 0.70 Max OSEMax 0.40Mm 0.2a Mm DETAIL ”A" 0.95 Max 1.1a Max ‘ 0.75 Mm . 4L sums mu: f 0 15 Max 0.05 Mm NOTE: 1. PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURNS. 2. PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTUSIONS. 3. CDNTRQLLING DIMENSION IN MILIMETERS. 4. THIS PART Is COMPLIANT WITH JEDEC M0187VARIATION5 AA 5. LEAD SPAN/STAND OFF HEIGHT/COPLANARITV ARE CONSIDERED AS SPECIAL CHARACIERISTIC
TSA7887
TSA7887 Rev. 1.0 Page 19
PACKAGE OUTLINE DRAWING
8-Pin MSOP Package Outline Drawing
(N.B., Drawings are not to scale)
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TSA7887
Page 20 Silicon Laboratories, Inc. TSA7887 Rev. 1.0
400 West Cesar Chavez, Austin, TX 78701
+1 (512) 416-8500 www.silabs.com
PACKAGE OUTLINE DRAWING
8-Pin SOIC Package Outline Drawing
(N.B., Drawings are not to scale)
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