RoHS (A @ Halogen-Free
eGaN® FET DATASHEET EPC2021
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
EPC2021 eGaN® FETs are supplied only in
passivated die form with solder bars.
Die Size: 6.05 mm x 2.3 mm
Applications
High Frequency DC-DC Conversion
Motor Drive
Industrial Automation
Synchronous Rectification
Inrush Protection
Class-D Audio
Benefits
Ultra High Efficiency
No Reverse Recovery
Ultra Low QG
Small Footprint
EFFICIENT POWER CONVERSION
G
D
S
HAL
EPC2021 – 80 V (D-S) Enhancement Mode
Power Transistor
VDS , 80 V
RDS(on) , 2.2 mΩ
ID , 90 A
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 80 V
ID
Continuous (TA = 25°C) 90 A
Pulsed (25°C, TPULSE = 300 µs) 390
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction-to-Case
0.4
°C/W RθJB
Thermal Resistance, Junction-to-Board
1.1
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 500 μA 80 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 20 200 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.02 4 mA
Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.1 9 mA
Gate-to-Source Reverse Leakage VGS = -4 V 20 200 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 13 mA 0.7 1.2 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 29 A 1.8 2.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
mmmmmmmmmmmmmmmmmmmm
eGaN® FET DATASHEET EPC2021
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320
240
160
80
00 0.5 1.0 1.5 2.0 2.5 3.0
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VDS = 3 V
320
240
160
80
0
6
4
2
02.5 3.02.0 3.5 4.0 4.5 5.0
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 15 A
ID = 30 A
ID = 45 A
ID = 60 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
ID = 29 A
6
4
2
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance#
VDS = 40 V, VGS = 0 V
1610 1940
pF
CRSS
Reverse Transfer Capacitance
15
COSS
Output Capacitance#
1100 1650
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 40 V, VGS = 0 V 1450
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
1790
RG
Gate Resistance
0.3 Ω
QG
Total Gate Charge#
VDS = 40 V, VGS = 5 V, ID = 29 A 15 19
nC
QGS
Gate-to-Source Charge
VDS = 40 V, ID = 29 A
4.1
QGD
Gate-to-Drain Charge
3
QG(TH)
Gate Charge at Threshold
2.7
QOSS
Output Charge#
VDS = 40 V, VGS = 0 V 72 108
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2021
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Capacitance (pF)
0 20 40 60 80
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
3000
2500
2000
1500
1000
500
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
10000
1000
100
10
00 20 40 60 80
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Output Charge and COSS Stored Energy
QOSS Output Charge (nC)
EOSS COSS Stored Energy (µJ)
120
100
80
60
40
20
00 20 40 60 80
VDS – Drain-to-Source Voltage (V)
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Figure 7: Gate Charge
VGS Gate-to-Source Voltage (V)
5
4
3
2
1
00 1510 5
QG – Gate Charge (nC)
ID = 29 A
VDS = 40 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
320
240
160
80
0
25˚C
125˚C
Figure 9: Normalized On-State Resistance vs. Temperature
Normalized On-State Resistance RDS(on)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 29 A
VGS = 5 V
W /
eGaN® FET DATASHEET EPC2021
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Figure 12: Transient Thermal Response Curves
Figure 10: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 13 mA
0.1
1
10
100
1000
0.1 1 10 100
ID – Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width
1 ms
250 µs
100 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.2
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
0.2
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
TJ = Max Rated, TC = +25°C, Single Pulse
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eGaN® FET DATASHEET EPC2021
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DIE MARKINGS
DIE OUTLINE
Solder Bump View
(685)
Seating plane
(785)
100 ± 20
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
A
f
d
X30
B
g
X4
e
c
X30
X28
Pad 1 is Gate;
Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
DIM
Micrometers
MIN Nominal MAX
A6020 6050 6080
B2270 2300 2330
c2047 2050 2053
d717 720 723
e210 225 240
f195 200 205
g400 400 400
Side View
YYYY
ZZZZ
TAPE AND REEL CONFIGURATION
8 mm pitch, 12 mm wide tape on 7” reel
7” inch reel Die
orientation
dot
Gate
solder bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
a
d
e
f g
h
c b
DIM Dimension (mm)
EPC2021 (Note 1) Target MIN MAX
a12.00 11.90 12.30
b1.75 1.65 1.85
c (Note 2) 5.50 5.45 5.55
d4.00 3.90 4.10
e8.00 7.90 8.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
h1.50 1.50 1.75
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
2021
2021
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2021 2021 YYYY ZZZZ
QJmmuium Ammmum mrrrrrmrrm] mgmumm
eGaN® FET DATASHEET EPC2021
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RECOMMENDED
LAND PATTERN
(units in µm)
RECOMMENDED
STENCIL DRAWING
(units in µm)
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
6050
400
X34
2300
1330
2050
720
200
X35
R60
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
6050
180
700
X30
2300
400
2030
X30
X28
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Information subject to
change without notice.
Revised July, 2020
Land pattern is solder mask defined
Solder mask opening is 180 µm
It is recommended to have on-Cu trace PCB vias
Pad 1 is Gate;
Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22,
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
Note: Datasheet is applicable for devices with date code of 1918 and later. For older date code devices please contact EPC for data sheet

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