STM32F427xx, STM32F429xx Datasheet by STMicroelectronics

This is information on a product in full production.
January 2018 DocID024030 Rev 10 1/239
STM32F427xx STM32F429xx
32b Arm
®
Cortex
®
-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT
Datasheet - production data
Features
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Memories
Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
Up to 256+4 KB of SRAM including 64-KB
of CCM (core coupled memory) data RAM
Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, Compact
Flash/NOR/NAND memories
LCD parallel interface, 8080/6800 modes
LCD-TFT controller with fully programmable
resolution (total width up to 4096 pixels, total
height up to 2048 lines and pixel clock up to
83 MHz)
Chrom-ART Accelerator™ for enhanced
graphic content creation (DMA2D)
Clock, reset and supply management
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low power
Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
2×12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
Debug mode
SWD & JTAG interfaces
Cortex-M4 Trace Macrocell™
Up to 168 I/O ports with interrupt capability
Up to 164 fast I/Os up to 90 MHz
Up to 166 5 V-tolerant I/Os
Up to 21 communication interfaces
Up to 3 × I2C interfaces (SMBus/PMBus)
Up to 4 USARTs/4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
Up to 6 SPIs (45 Mbits/s), 2 with muxed
full-duplex I2S for audio class accuracy via
internal audio PLL or external clock
1 x SAI (serial audio interface)
2 × CAN (2.0B Active) and SDIO interface
Advanced connectivity
USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit parallel camera interface up to
54 Mbytes/s
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm) UFBGA176 (10 x 10 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 x 28 mm)
WLCSP143
TFBGA216 (13 x 13 mm)
UFBGA169 (7 × 7 mm)
&"'!
www.st.com
STM32F427xx STM32F429xx
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Table 1. Device summary
Reference Part number
STM32F427xx STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI,
STM32F427II, STM32F427AI
STM32F429xx
STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG,
STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI,
STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE,
STM32F429NE
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STM32F427xx STM32F429xx Contents
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10 LCD-TFT controller (available only on STM32F429xx) . . . . . . . . . . . . . . 24
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32
3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 32
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 37
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41
3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41
3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.36 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.37 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.38 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.40 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.41 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.42 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 98
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 98
6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 99
6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 127
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 133
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 193
6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 194
6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 196
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6.3.30 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.5 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 227
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 228
B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 230
B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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STM32F427xx STM32F429xx List of tables
9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32F427xx and STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . 16
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 29
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10. STM32F427xx and STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 12. STM32F427xx and STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75
Table 13. STM32F427xx and STM32F429xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 87
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 97
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 98
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 98
Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM. . . . . . 102
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 26. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 104
Table 27. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 105
Table 28. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 106
Table 29. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 106
Table 30. Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 31. Typical current consumption in Run mode, code with data processing running
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 109
Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 110
Table 33. Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 111
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 39. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 41. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 43. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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Table 44. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 46. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 48. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 49. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 50. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 51. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 52. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 53. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 54. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 55. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 56. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 60. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 61. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 62. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 63. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 64. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 65. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 66. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 67. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 68. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 69. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 70. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 71. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 72. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 73. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 74. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 75. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
Table 79. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159
Table 80. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 81. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 82. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 83. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 84. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 85. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 171
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 90. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 173
Table 92. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175
Table 94. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 95. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 97. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 98. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 99. Switching characteristics for PC Card/CF read and write cycles
in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 106. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 108. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 109. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 199
Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 204
Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 218
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 221
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 121. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 122. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 123. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227
Table 124. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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List of figures
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. STM32F427xx and STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. STM32F42x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13. STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. STM32F42x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 20. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 21. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 22. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 24. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 107
Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 107
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 31. ACCHSI accuracy versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 35. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 39. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 40. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 41. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 42. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 43. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Figure 44. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 45. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 151
Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162
Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 163
Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 169
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 171
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 182
Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 182
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory
read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory
write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 184
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 185
Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 188
Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 188
Figure 73. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 74. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 198
Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 82. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 84. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 85. WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 205
Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 88. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 209
List of figures STM32F427xx STM32F429xx
12/239 DocID024030 Rev 10
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 211
Figure 91. LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 213
Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 94. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch
ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 97. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 100. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 102. TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 103. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 104. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 228
Figure 105. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 229
Figure 106. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 107. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 108. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 109. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
DocID024030 Rev 10 13/239
STM32F427xx STM32F429xx Introduction
44
1 Introduction
This datasheet provides the description of the STM32F427xx and STM32F429xx line of
microcontrollers. For more details on the whole STMicroelectronics STM32 family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214), available from www.st.com.
Description STM32F427xx STM32F429xx
14/239 DocID024030 Rev 10
2 Description
The STM32F427xx and STM32F429xx devices are based on the high-performance Arm®
Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4
core features a Floating point unit (FPU) single precision which supports all Arm® single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances application security.
The STM32F427xx and STM32F429xx devices incorporate high-speed embedded
memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of
backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces.
Up to three I2Cs
Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
Two CANs
One SAI serial audio interface
An SDIO/MMC interface
Ethernet and camera interface
LCD-TFT display controller
Chrom-ART Accelerator™.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors. Refer to Table 2: STM32F427xx and STM32F429xx
features and peripheral counts for the list of peripherals available on each part number.
The STM32F427xx and STM32F429xx devices operates in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F427xx and STM32F429xx devices offer devices in 8 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
arm
DocID024030 Rev 10 15/239
STM32F427xx STM32F429xx Description
44
These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a
wide range of applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Figure 4 shows the general block diagram of the device family.
Description STM32F427xx STM32F429xx
16/239 DocID024030 Rev 10
Table 2. STM32F427xx and STM32F429xx features and peripheral counts
Peripherals STM32F427
Vx STM32F429Vx STM32F427
Zx STM32F429Zx STM32F427
Ax
STM32F429
Ax
STM32F427
Ix STM32F429Ix STM32F429Bx STM32F429Nx
Flash memory in Kbytes 1024 2048 512 1024 2048 1024 2048 512 1024 2048 1024 2048 1024 2048 1024 2048 512 1024 2048 512 1024 2048 512 1024 2048
SRAM in
Kbytes
System 256(112+16+64+64)
Backup 4
FMC memory controller Yes(1)
Ethernet Yes
Timers
General-
purpose 10
Advanced
-control 2
Basic 2
Random number generator Yes
Communication
interfaces
SPI / I2S 4/2 (full duplex)(2) 6/2 (full duplex)(2)
I2C 3
USART/
UART 4/4
USB OTG
FS Yes
USB OTG
HS Yes
CAN 2
SAI 1
SDIO Yes
Camera interface Yes
LCD-TFT (STM32F429xx
only) No Yes No Yes No Yes No Yes
Chrom-ART Accelerator™ Yes
GPIOs 82 114 130 140 168
12-bit ADC
Number of channels
3
16 24
STM32F427xx STM32F429xx Description
DocID024030 Rev 10 17/239
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 180 MHz
Operating voltage 1.8 to 3.6 V(3)
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Packages LQFP100 WLCSP143
LQFP144 UFBGA169 UFBGA176
LQFP176 LQFP208 TFBGA216
1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. For UFBGA169 package, only SDRAM, NAND and multiplexed
static memories are supported.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset
OFF).
Table 2. STM32F427xx and STM32F429xx features and peripheral counts (continued)
Peripherals STM32F427
Vx STM32F429Vx STM32F427
Zx STM32F429Zx STM32F427
Ax
STM32F429
Ax
STM32F427
Ix STM32F429Ix STM32F429Bx STM32F429Nx
Description STM32F427xx STM32F429xx
18/239 DocID024030 Rev 10
2.1 Full compatibility throughout the family
The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are
fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the
user to try different memory densities, peripherals, and performances (FPU, higher
frequency) for a greater degree of freedom during the development cycle.
The STM32F427xx and STM32F429xx devices maintain a close compatibility with the
whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F427xx
and STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices:
the two families do not have the same power scheme, and so their power pins are different.
Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as
only a few pins are impacted.
Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx,
STM32F2xx, and STM32F10xx families.
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package
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STM32F427xx STM32F429xx Description
44
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package
Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages
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Description STM32F427xx STM32F429xx
20/239 DocID024030 Rev 10
Figure 4. STM32F427xx and STM32F429xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. The LCD-TFT is available only on STM32F429xx devices.
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STM32F427xx STM32F429xx Functional overview
44
3 Functional overview
3.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an Arm core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F42x family is compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F42x family.
Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F427xx STM32F429xx
22/239 DocID024030 Rev 10
3.4 Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
3.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6 Embedded SRAM
All devices embed:
Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
3.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several high-speed
peripherals work simultaneously.
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DocID024030 Rev 10 23/239
STM32F427xx STM32F429xx Functional overview
44
Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix
3.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview STM32F427xx STM32F429xx
24/239 DocID024030 Rev 10
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1.
3.9 Flexible memory controller (FMC)
All devices embed an FMC. It has four Chip Select outputs supporting the following modes:
PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND
Flash.
Functionality overview:
8-,16-, 32-bit data bus width
Read FIFO for SDRAM controller
Write FIFO
Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10 LCD-TFT controller (available only on STM32F429xx)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
DocID024030 Rev 10 25/239
STM32F427xx STM32F429xx Functional overview
44
3.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
3.14 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
Functional overview STM32F427xx STM32F429xx
26/239 DocID024030 Rev 10
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
3.16 Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator
configuration mode versus device operating mode to identify the packages supporting this
option.
3.17 Power supply supervisor
3.17.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
EJ—
DocID024030 Rev 10 27/239
STM32F427xx STM32F429xx Functional overview
44
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.17.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
this external power supply supervisor. Refer to Figure 6: Power supply supervisor
interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal.
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Figure 7. PDR_ON control with internal reset OFF
3.18 Voltage regulator
The regulator has four operating modes:
Regulator ON
Main regulator mode (MR)
Low power regulator (LPR)
– Power-down
Regulator OFF
3.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR mode used in Run/sleep modes or in Stop modes
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
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STM32F427xx STM32F429xx Functional overview
44
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions.
All packages have the regulator ON feature.
3.18.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 17: General operating
conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 22: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
Voltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down
mode ---Yes
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30/239 DocID024030 Rev 10
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 8. Regulator OFF
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
(see Table 17: General operating conditions).
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STM32F427xx STM32F429xx Functional overview
44
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
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3.18.3 Regulator ON/OFF and internal reset ON/OFF availability
3.19 Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 3.20: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.20: Low-power
modes).
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
LQFP100
Yes No
Yes No
LQFP144,
LQFP208
Yes
PDR_ON set to
VDD
Yes
PDR_ON
connected to an
external power
supply supervisor
WLCSP143,
LQFP176,
UFBGA169,
UFBGA176,
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
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STM32F427xx STM32F429xx Functional overview
44
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
3.20 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
Table 5. Voltage regulator modes in stop mode
Voltage regulator
configuration Main regulator (MR) Low-power regulator (LPR)
Normal mode MR ON LPR ON
Under-drive mode MR in under-drive mode LPR in under-drive mode
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3.21 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is
no more available and VBAT pin should be connected to VDD.
3.22 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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STM32F427xx STM32F429xx Functional overview
44
Table 6. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
Advanced
-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 90 180
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 45 90/180
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 45 90/180
TIM9 16-bit Up
Any
integer
between 1
and
65536
No 2 No 90 180
TIM10
,
TIM11
16-bit Up
Any
integer
between 1
and
65536
No 1 No 90 180
TIM12 16-bit Up
Any
integer
between 1
and
65536
No 2 No 45 90/180
TIM13
,
TIM14
16-bit Up
Any
integer
between 1
and
65536
No 1 No 45 90/180
Basic TIM6,
TIM7 16-bit Up
Any
integer
between 1
and
65536
Yes 0 No 45 90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
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3.22.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.22.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F42x devices
(see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F42x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.22.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
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3.22.4 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.22.5 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.22.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.23 Inter-integrated circuit interface ( I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
3.24 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
Table 7. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes 50 ns Programmable length from 1 to 15
I2C peripheral clocks
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communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
3.25 Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
Table 8. USART feature comparison(1)
USART
name
Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud
rate in Mbit/s
(oversampling
by 16)
Max. baud
rate in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
USART2 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
USART3 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
UART4 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART5 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
USART6 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
UART7 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART8 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
1. X = feature supported.
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STM32F427xx STM32F429xx Functional overview
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3.26 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
3.27 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
3.28 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
3.29 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
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3.30 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.32 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
DocID024030 Rev 10 41/239
STM32F427xx STM32F429xx Functional overview
44
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
3.33 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.34 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator.
The major features are:
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Functional overview STM32F427xx STM32F429xx
42/239 DocID024030 Rev 10
3.35 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
3.36 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.37 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
3.38 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
DocID024030 Rev 10 43/239
STM32F427xx STM32F429xx Functional overview
44
3.39 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT
, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.40 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.41 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
Functional overview STM32F427xx STM32F429xx
44/239 DocID024030 Rev 10
3.42 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F42x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID024030 Rev 10 45/239
STM32F427xx STM32F429xx Pinouts and pin description
85
4 Pinouts and pin description
Figure 11. STM32F42x LQFP100 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F427xx STM32F429xx
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Figure 12. STM32F42x WLCSP143 ballout
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DocID024030 Rev 10 47/239
STM32F427xx STM32F429xx Pinouts and pin description
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Figure 13. STM32F42x LQFP144 pinout
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Pinouts and pin description STM32F427xx STM32F429xx
48/239 DocID024030 Rev 10
Figure 14. STM32F42x LQFP176 pinout
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STM32F427xx STM32F429xx Pinouts and pin description
DocID024030 Rev 10 49/239
Figure 15. STM32F42x LQFP208 pinout
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Pinouts and pin description STM32F427xx STM32F429xx
50/239 DocID024030 Rev 10
Figure 16. STM32F42x UFBGA169 ballout
1. The above figure shows the package top view.
2. The 4 corners balls, A1,A13, N1 and N13, are not bonded internally and should be left not connected on the PCB.
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STM32F427xx STM32F429xx Pinouts and pin description
85
Figure 17. STM32F42x UFBGA176 ballout
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Pinouts and pin description STM32F427xx STM32F429xx
52/239 DocID024030 Rev 10
Figure 18. STM32F42x TFBGA216 ballout
1. The above figure shows the package top view.
-36
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DocID024030 Rev 10 53/239
STM32F427xx STM32F429xx Pinouts and pin description
85
Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to ADC
B Dedicated BOOT0 pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Table 10. STM32F427xx and STM32F429xx pin and ball definitions
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
1 1 B2 A2 1 D8 1 A3 PE2 I/O FT -
TRACECLK,
SPI4_SCK,
SAI1_MCLK_A,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
2 2 C1 A1 2 C10 2 A2 PE3 I/O FT -
TRACED0,
SAI1_SD_B, FMC_A19,
EVENTOUT
-
3 3 C2 B1 3 B11 3 A1 PE4 I/O FT -
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
Pinouts and pin description STM32F427xx STM32F429xx
54/239 DocID024030 Rev 10
4 4 D1 B2 4 D9 4 B1 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO,
SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
5 5 D2 B3 5 E8 5 B2 PE6 I/O FT -
TRACED3, TIM9_CH2,
SPI4_MOSI,
SAI1_SD_A, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
-
-- - - ---G6 V
SS S-- - -
-- - - ---F5 V
DD S-- - -
66E5C16C116C1 V
BAT S-- - -
--
NC
(2) D2 7 - 7 C2 PI8 I/O FT
(3)
(4) EVENTOUT TAMP_2
77E4D18D108D1 PC13 I/OFT
(3)
(4) EVENTOUT TAMP_1
8 8 E1 E1 9 D11 9 E1
PC14-
OSC32_IN
(PC14)
I/O FT
(3)
(4) EVENTOUT OSC32_IN
(5)
99F1F110E1110F1
PC15-
OSC32_OUT
(PC15)
I/O FT
(3)
(4) EVENTOUT OSC32_
OUT(5)
-- - - ---G5 V
DD S-- - -
- - E2 D3 11 - 11 E4 PI9 I/O FT -
CAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
- - E3 E3 12 - 12 D5 PI10 I/O FT -
ETH_MII_RX_ER,
FMC_D31,
LCD_HSYNC,
EVENTOUT
-
--
NC
(2) E4 13 - 13 F3 PI11 I/O FT - OTG_HS_ULPI_DIR,
EVENTOUT -
- - F6 F2 14 E7 14 F2 VSS S-- - -
--F4F315E1015F4 V
DD S-- - -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 55/239
STM32F427xx STM32F429xx Pinouts and pin description
85
-10F2E216F1116D2 PF0 I/OFT-
I2C2_SDA, FMC_A0,
EVENTOUT -
-11F3H317E917E2 PF1 I/OFT-I2C2_SCL, FMC_A1,
EVENTOUT -
- 12 G5 H2 18 F10 18 G2 PF2 I/O FT - I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - - - - 19 E3 PI12 I/O FT - LCD_HSYNC,
EVENTOUT -
- - - - - - 20 G3 PI13 I/O FT - LCD_VSYNC,
EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT LCD_CLK, EVENTOUT -
-13G4J219G1122H2 PF3 I/OFT
(5) FMC_A3, EVENTOUT ADC3_IN9
-14G3J320F923J2 PF4 I/OFT
(5) FMC_A4, EVENTOUT ADC3_
IN14
-15H3K321F824K3 PF5 I/OFT
(5) FMC_A5, EVENTOUT ADC3_
IN15
10 16 G7 G2 22 H7 25 H6 VSS S-- - -
11 17 G8 G3 23 - 26 H5 VDD S-- - -
-18
NC
(2) K2 24 G10 27 K2 PF6 I/O FT (5)
TIM10_CH1,
SPI5_NSS,
SAI1_SD_B,
UART7_Rx,
FMC_NIORD,
EVENTOUT
ADC3_IN4
-19
NC
(2) K1 25 F7 28 K1 PF7 I/O FT (5)
TIM11_CH1,
SPI5_SCK,
SAI1_MCLK_B,
UART7_Tx,
FMC_NREG,
EVENTOUT
ADC3_IN5
-20
NC
(2) L3 26 H11 29 L3 PF8 I/O FT (5)
SPI5_MISO,
SAI1_SCK_B,
TIM13_CH1,
FMC_NIOWR,
EVENTOUT
ADC3_IN6
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
56/239 DocID024030 Rev 10
-21
NC
(2) L2 27 G8 30 L2 PF9 I/O FT (5)
SPI5_MOSI,
SAI1_FS_B,
TIM14_CH1, FMC_CD,
EVENTOUT
ADC3_IN7
-22H1L128G931L1 PF10 I/OFT
(5)
FMC_INTR,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
12 23 G2 G1 29 J11 32 G1 PH0-OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN(5)
13 24 G1 H1 30 H10 33 H1
PH1-
OSC_OUT
(PH1)
I/O FT - EVENTOUT OSC_OUT
(5)
14 25 H2 J1 31 H9 34 J1 NRST I/O RS
T-- -
15 26 G6 M2 32 H8 35 M2 PC0 I/O FT (5)
OTG_HS_ULPI_STP,
FMC_SDNWE,
EVENTOUT
ADC123_
IN10
16 27 H5 M3 33 K11 36 M3 PC1 I/O FT (5) ETH_MDC,
EVENTOUT
ADC123_
IN11
17 28 H6 M4 34 J10 37 M4 PC2 I/O FT (5)
SPI2_MISO,
I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_
IN12
18 29 H7 M5 35 J9 38 L4 PC3 I/O FT (5)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC123_
IN13
19 30 - - 36 G7 39 J5 VDD S-- - -
-- - - ---J6 V
SS S-- - -
20 31 J1 M1 37 K10 40 M1 VSSA S-- - -
--J2N1---N1 V
REF S-- - -
21 32 J3 P1 38 L11 41 P1 VREF+ S-- - -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 57/239
STM32F427xx STM32F429xx Pinouts and pin description
85
22 33 J4 R1 39 L10 42 R1 VDDA S-- - -
23 34 J5 N3 40 K9 43 N3 PA0-WKUP
(PA0) I/O FT (6)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_
IN0/WKUP
(5)
24 35 K1 N2 41 K8 44 N2 PA1 I/O FT (5)
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
ETH_MII_RX_CLK/ETH
_RMII_REF_CLK,
EVENTOUT
ADC123_
IN1
25 36 K2 P2 42 L9 45 P2 PA2 I/O FT (5)
TIM2_CH3, TIM5_CH3,
TIM9_CH1,
USART2_TX,
ETH_MDIO,
EVENTOUT
ADC123_
IN2
- - L2 F4 43 - 46 K4 PH2 I/O FT -
ETH_MII_CRS,
FMC_SDCKE0,
LCD_R0, EVENTOUT
-
- - L1 G4 44 - 47 J4 PH3 I/O FT -
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
- - M2 H4 45 - 48 H4 PH4 I/O FT -
I2C2_SCL,
OTG_HS_ULPI_NXT,
EVENTOUT
-
- - L3 J4 46 - 49 J3 PH5 I/O FT -
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
-
26 37 K3 R2 47 M11 50 R2 PA3 I/O FT (5)
TIM2_CH4, TIM5_CH4,
TIM9_CH2,
USART2_RX,
OTG_HS_ULPI_D0,
ETH_MII_COL,
LCD_B5, EVENTOUT
ADC123_
IN3
27 38 - - - 51 K6 VSS S-- - -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
58/239 DocID024030 Rev 10
- - M1 L4 48 N11 - L5 BYPASS_
REG IFT- - -
28 39 J11 K4 49 J8 52 K5 VDD S-- - -
29 40 N2 N4 50 M10 53 N4 PA4 I/O TTa (5)
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_
IN4 /DAC_
OUT1
30 41 M3 P4 51 M9 54 P4 PA5 I/O TTa (5)
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK,
OTG_HS_ULPI_CK,
EVENTOUT
ADC12_
IN5/DAC_
OUT2
31 42 N3 P3 52 N10 55 P3 PA6 I/O FT (5)
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK,
LCD_G2, EVENTOUT
ADC12_
IN6
32 43 K4 R3 53 L8 56 R3 PA7 I/O FT (5)
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI,
TIM14_CH1,
ETH_MII_RX_DV/ETH_
RMII_CRS_DV,
EVENTOUT
ADC12_
IN7
33 44 L4 N5 54 M8 57 N5 PC4 I/O FT (5)
ETH_MII_RXD0/ETH_
RMII_RXD0,
EVENTOUT
ADC12_
IN14
34 45 M4 P5 55 N9 58 P5 PC5 I/O FT (5)
ETH_MII_RXD1/ETH_
RMII_RXD1,
EVENTOUT
ADC12_
IN15
-- - - -J759L7 V
DD S-- - -
- - - - - - 60 L6 VSS S - - - -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 59/239
STM32F427xx STM32F429xx Pinouts and pin description
85
35 46 N4 R5 56 N8 61 R5 PB0 I/O FT (5)
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
ADC12_
IN8
36 47 K5 R4 57 K7 62 R4 PB1 I/O FT (5)
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
EVENTOUT
ADC12_
IN9
37 48 L5 M6 58 L7 63 M5 PB2-BOOT1
(PB2) I/O FT - EVENTOUT -
- - - - - - 64 G4 PI15 I/O FT - LCD_R0, EVENTOUT -
- - - - - - 65 R6 PJ0 I/O FT - LCD_R1, EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -
- - - - - - 67 P7 PJ2 I/O FT - LCD_R3, EVENTOUT -
- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -
- 49 M5 R6 59 M7 70 P8 PF11 I/O FT -
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12,
EVENTOUT
-
- 50 N5 P6 60 N7 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -
- 51G9M861 - 72K7 V
SS S- - -
- 52 D10 N8 62 - 73 L8 VDD S- - -
- 53 M6 N6 63 K6 74 N6 PF13 I/O FT - FMC_A7, EVENTOUT -
- 54 K7 R7 64 L6 75 P6 PF14 I/O FT - FMC_A8, EVENTOUT -
- 55 L7 P7 65 M6 76 M8 PF15 I/O FT - FMC_A9, EVENTOUT -
- 56 N6 N7 66 N6 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT -
- 57 M7 M7 67 K5 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
60/239 DocID024030 Rev 10
38 58 N7 R8 68 L5 79 R8 PE7 I/O FT - TIM1_ETR, UART7_Rx,
FMC_D4, EVENTOUT -
39 59 J8 P8 69 M5 80 N9 PE8 I/O FT -
TIM1_CH1N,
UART7_Tx, FMC_D5,
EVENTOUT
-
40 60 K8 P9 70 N5 81 P9 PE9 I/O FT - TIM1_CH1, FMC_D6,
EVENTOUT -
-61J6M971H382K8 V
SS S- -
- 62 G10 N9 72 J5 83 L9 VDD S- -
41 63 L8 R9 73 J4 84 R9 PE10 I/O FT - TIM1_CH2N, FMC_D7,
EVENTOUT -
42 64 M8 P10 74 K4 85 P10 PE11 I/O FT -
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
-
43 65 N8 R10 75 L4 86 R10 PE12 I/O FT -
TIM1_CH3N,
SPI4_SCK, FMC_D9,
LCD_B4, EVENTOUT
-
44 66 H9 N11 76 N4 87 R12 PE13 I/O FT -
TIM1_CH3,
SPI4_MISO, FMC_D10,
LCD_DE, EVENTOUT
-
45 67 J9 P11 77 M4 88 P11 PE14 I/O FT -
TIM1_CH4,
SPI4_MOSI, FMC_D11,
LCD_CLK, EVENTOUT
-
46 68 K9 R11 78 L3 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT -
47 69 L9 R12 79 M3 90 P12 PB10 I/O FT -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
48 70 M9 R13 80 N3 91 R13 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, LCD_G5,
EVENTOUT
-
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 61/239
STM32F427xx STM32F429xx Pinouts and pin description
85
49 71 N9 M10 81 N2 92 L11 VCAP_1 S-- - -
-- - - -H293K9 V
SS S-- - -
50 72 F8 N10 82 J6 94 L10 VDD S-- - -
- - - - - - 95 M14 PJ5 I/O - - LCD_R6, EVENTOUT -
- - N10 M11 83 - 96 P13 PH6 I/O FT -
I2C2_SMBA,
SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1,
DCMI_D8, EVENTOUT
-
- - M10 N12 84 - 97 N13 PH7 I/O FT -
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
- - L10 M12 85 - 98 P14 PH8 I/O FT -
I2C3_SDA, FMC_D16,
DCMI_HSYNC,
LCD_R2, EVENTOUT
-
- - K10 M13 86 - 99 N14 PH9 I/O FT -
I2C3_SMBA,
TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
- - N11 L13 87 - 100 P15 PH10 I/O FT -
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
- - M11 L12 88 - 101 N15 PH11 I/O FT -
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
-
- - L11 K12 89 - 102 M15 PH12 I/O FT -
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
--E7H1290--K10 V
SS S-- - -
- - H8 J12 91 - 103 K11 VDD S-- - -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
62/239 DocID024030 Rev 10
51 73 N12 P12 92 M2 104 L13 PB12 I/O FT -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK,
CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0,
OTG_HS_ID,
EVENTOUT
-
52 74 M12 P13 93 N1 105 K14 PB13 I/O FT -
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, EVENTOUT
OTG_HS_
VBUS
53 75 M13 R14 94 K3 106 R14 PB14 I/O FT -
TIM1_CH2N,
TIM8_CH2N,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
-
54 76 L13 R15 95 J3 107 R15 PB15 I/O FT -
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2,
OTG_HS_DP,
EVENTOUT
-
55 77 L12 P15 96 L2 108 L15 PD8 I/O FT - USART3_TX,
FMC_D13, EVENTOUT -
56 78 K13 P14 97 M1 109 L14 PD9 I/O FT - USART3_RX,
FMC_D14, EVENTOUT -
57 79 K11 N15 98 H4 110 K15 PD10 I/O FT -
USART3_CK,
FMC_D15, LCD_B3,
EVENTOUT
-
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 63/239
STM32F427xx STM32F429xx Pinouts and pin description
85
58 80 H10 N14 99 K2 111 N10 PD11 I/O FT - USART3_CTS,
FMC_A16, EVENTOUT -
59 81 J13 N13 100 H6 112 M10 PD12 I/O FT -
TIM4_CH1,
USART3_RTS,
FMC_A17, EVENTOUT
-
60 82 K12 M15 101 H5 113 M11 PD13 I/O FT - TIM4_CH2, FMC_A18,
EVENTOUT -
-83 - -102-114J10 V
SS S- - -
- 84 F7 J13 103 L1 115 J11 VDD S- - -
61 85 H11 M14 104 J2 116 L12 PD14 I/O FT - TIM4_CH3, FMC_D0,
EVENTOUT -
62 86 J12 L14 105 K1 117 K13 PD15 I/O FT - TIM4_CH4, FMC_D1,
EVENTOUT -
- - - - - - 118 K12 PJ6 I/O FT - LCD_R7, EVENTOUT -
- - - - - - 119 J12 PJ7 I/O FT - LCD_G0, EVENTOUT -
- - - - - - 120 H12 PJ8 I/O FT - LCD_G1, EVENTOUT -
- - - - - - 121 J13 PJ9 I/O FT - LCD_G2, EVENTOUT -
- - - - - - 122 H13 PJ10 I/O FT - LCD_G3, EVENTOUT -
- - - - - - 123 G12 PJ11 I/O FT - LCD_G4, EVENTOUT -
-- - - --124H11 VDD I/OFT- - -
- - - - - - 125 H10 VSS I/O FT - - -
- - - - - - 126 G13 PK0 I/O FT - LCD_G5, EVENTOUT -
- - - - - - 127 F12 PK1 I/O FT - LCD_G6, EVENTOUT -
- - - - - - 128 F13 PK2 I/O FT - LCD_G7, EVENTOUT -
- 87 H13 L15 106 J1 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -
-88
NC
(2) K15 107 G3 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -
- 89 H12 K14 108 G5 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0,
EVENTOUT -
- 90 G13 K13 109 G6 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1,
EVENTOUT -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
64/239 DocID024030 Rev 10
- 91 G11 J15 110 G4 133 J15 PG6 I/O FT - FMC_INT2, DCMI_D12,
LCD_R7, EVENTOUT -
- 92 G12 J14 111 H1 134 J14 PG7 I/O FT -
USART6_CK,
FMC_INT3, DCMI_D13,
LCD_CLK, EVENTOUT
-
- 93 F13 H14 112 G2 135 H14 PG8 I/O FT -
SPI6_NSS,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK,
EVENTOUT
-
-94J7G12113D2136G10 V
SS S- - -
-95E6H13114G1137G11 V
DD S- - -
63 96 F9 H15 115 F2 138 H15 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
I2S2_MCK,
USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
-
64 97 F10 G15 116 F3 139 G15 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
I2S3_MCK,
USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
65 98 F11 G14 117 E4 140 G14 PC8 I/O FT -
TIM3_CH3, TIM8_CH3,
USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
-
66 99 F12 F14 118 E3 141 F14 PC9 I/O FT -
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, SDIO_D1,
DCMI_D3, EVENTOUT
-
67 100 E13 F15 119 F1 142 F15 PA8 I/O FT -
MCO1, TIM1_CH1,
I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
LCD_R6, EVENTOUT
-
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 65/239
STM32F427xx STM32F429xx Pinouts and pin description
85
68 101 E8 E15 120 E2 143 E15 PA9 I/O FT -
TIM1_CH2,
I2C3_SMBA,
USART1_TX,
DCMI_D0, EVENTOUT
OTG_FS_
VBUS
69 102 E9 D15 121 D5 144 D15 PA10 I/O FT -
TIM1_CH3,
USART1_RX,
OTG_FS_ID,
DCMI_D1, EVENTOUT
-
70 103 E10 C15 122 D4 145 C15 PA11 I/O FT -
TIM1_CH4,
USART1_CTS,
CAN1_RX, LCD_R4,
OTG_FS_DM,
EVENTOUT
-
71 104 E11 B15 123 E1 146 B15 PA12 I/O FT -
TIM1_ETR,
USART1_RTS,
CAN1_TX, LCD_R5,
OTG_FS_DP,
EVENTOUT
-
72 105 E12 A15 124 D3 147 A15
PA13
(JTMS-
SWDIO)
I/O FT - JTMS-SWDIO,
EVENTOUT -
73 106 D12 F13 125 D1 148 E11 VCAP_2 S- - -
74 107 J10 F12 126 D2 149 F10 VSS S- - -
75 108 H4 G13 127 C1 150 F11 VDD S- - -
- - D13 E12 128 - 151 E12 PH13 I/O FT -
TIM8_CH1N,
CAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
- - C13 E13 129 - 152 E13 PH14 I/O FT -
TIM8_CH2N,
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
-
- - C12 D13 130 - 153 D13 PH15 I/O FT -
TIM8_CH3N,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
-
- - B13 E14 131 - 154 E14 PI0 I/O FT -
TIM5_CH4,
SPI2_NSS/I2S2_WS(7),
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
66/239 DocID024030 Rev 10
- - C11 D14 132 - 155 D14 PI1 I/O FT -
SPI2_SCK/I2S2_CK(7),
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
- - B12 C14 133 - 156 C14 PI2 I/O FT -
TIM8_CH4,
SPI2_MISO,
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
-
- - A12 C13 134 - 157 C13 PI3 I/O FT -
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
--D11D9135F5-F9 V
SS S- - -
- - D3 C9 136 A1 158 E10 VDD S- - -
76 109 A11 A14 137 B1 159 A14
PA14
(JTCK-
SWCLK)
I/O FT - JTCK-SWCLK/
EVENTOUT -
77 110 B11 A13 138 C2 160 A13 PA15
(JTDI) I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
-
78 111 C10 B14 139 A2 161 B14 PC10 I/O FT -
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX, SDIO_D2,
DCMI_D8, LCD_R2,
EVENTOUT
-
79 112 B10 B13 140 B2 162 B13 PC11 I/O FT -
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
UART4_RX, SDIO_D3,
DCMI_D4, EVENTOUT
-
80 113 A10 A12 141 C3 163 A12 PC12 I/O FT -
SPI3_MOSI/I2S3_SD,
USART3_CK,
UART5_TX, SDIO_CK,
DCMI_D9, EVENTOUT
-
81 114 D9 B12 142 B3 164 B12 PD0 I/O FT - CAN1_RX, FMC_D2,
EVENTOUT -
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
DocID024030 Rev 10 67/239
STM32F427xx STM32F429xx Pinouts and pin description
85
82 115 C9 C12 143 C4 165 C12 PD1 I/O FT - CAN1_TX, FMC_D3,
EVENTOUT -
83 116 B9 D12 144 A3 166 D12 PD2 I/O FT -
TIM3_ETR,
UART5_RX,
SDIO_CMD,
DCMI_D11,
EVENTOUT
-
84 117 A9 D11 145 B4 167 C11 PD3 I/O FT -
SPI2_SCK/I2S2_CK,
USART2_CTS,
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
-
85 118 D8 D10 146 B5 168 D11 PD4 I/O FT -
USART2_RTS,
FMC_NOE,
EVENTOUT
-
86 119 C8 C11 147 A4 169 C10 PD5 I/O FT -
USART2_TX,
FMC_NWE,
EVENTOUT
-
- 120 - D8 148 - 170 F8 VSS S- - -
- 121 D6 C8 149 C5 171 E9 VDD S- - -
87 122 B8 B11 150 F4 172 B11 PD6 I/O FT -
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
USART2_RX,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
-
88 123 A8 A11 151 A5 173 A11 PD7 I/O FT -
USART2_CK,
FMC_NE1/FMC_NCE2,
EVENTOUT
-
- - - - - - 174 B10 PJ12 I/O FT - LCD_B0, EVENTOUT -
- - - - - - 175 B9 PJ13 I/O FT - LCD_B1, EVENTOUT -
- - - - - - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT -
-124
NC
(2) C10 152 E5 178 D9 PG9 I/O FT -
USART6_RX,
FMC_NE2/FMC_NCE3,
DCMI_VSYNC(8),
EVENTOUT
-
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
UFBGA176
LQFP176
WLCSP143
LQFP208
TFBGA216
Pinouts and pin description STM32F427xx STM32F429xx
68/239 DocID024030 Rev 10
- 125 C7 B10 153 C6 179 C8 PG10 I/O FT -
LCD_G3,
FMC_NCE4_1/FMC_N
E3, DCMI_D2,
LCD_B2, EVENTOUT
-
- 126 B7 B9 154 B6 180 B8 PG11 I/O FT -
ETH_MII_TX_EN/ETH_
RMII_TX_EN,
FMC_NCE4_2,
DCMI_D3, LCD_B3,
EVENTOUT
-
- 127 A7 B8 155 A6 181 C7 PG12 I/O FT -
SPI6_MISO,
USART6_RTS,
LCD_B4, FMC_NE4,
LCD_B1, EVENTOUT
-
-128
NC
(2) A8 156 D6 182 B3 PG13 I/O FT -
SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
EVENTOUT
-
-129
NC
(2)