EPC8004 Datasheet by EPC

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eGaN® FET DATASHEET EPC8004
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EPC8004 – Enhancement Mode Power Transistor
VDS , 40 V
RDS(on) , 110 mΩ
ID , 4 A
EFFICIENT POWER CONVERSION
EPC8004 eGaN FETs are supplied only in
passivated die form with solder bars
Die Size: 2.1 mm x 0.85 mm
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (Lidar)
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
HAL
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 40 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 125°C) 48
ID
Continuous (TA = 25°C, RθJA = 39°C/W) 4A
Pulsed (25°C, TPULSE = 300 µs) 7. 5
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage –4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Static Characteristics (TJ= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 40 V
IDSS Drain-Source Leakage VDS = 32 V, VGS = 0 V 50 100 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 100 500 µA
Gate-to-Source Reverse Leakage VGS = -4 V 50 100
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.25 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 80 110 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 2.2 V
Thermal Characteristics
PARAMETER TYP UNIT
R
θ
JC Thermal Resistance, Junction-to-Case 8.2
°C/WR
θ
JB Thermal Resistance, Junction-to-Board 16
R
θ
JA Thermal Resistance, Junction-to-Ambient (Note 1) 82
Specifications are with substrate connected to source where applicable.
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
G
D
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET
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EPC8004
7
6
5
4
8
3
2
1
00 0.5 1.5
1 2 2.5 3
Figure 1: Typical Output Characteristics at 25°C
VGS
GS
GS
GS
= 5
V = 4
V = 3
V = 2
VDS– Drain-to-Source Voltage (V)
ID– Drain Current (A)
7
6
5
4
8
3
2
1
0
VGS– Gate-to-Source Voltage (V)
ID– Drain Current (A)
0.5 1 1.5 2 32.5 3.5 4 4.5 5
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
350
300
250
200
400
150
100
50
0
VGS– Gate-to-Source Voltage (V)
2 2.5 3 3.5 4.54 5
Figure 3: R DS(ON) vs VGS for Various Drain Currents
Drain-to-Source Resistance (mΩ)
ID= 0.5 A
ID= 1 A
ID= 1.5 A
ID= 2 A
350
300
250
200
400
150
100
50
0
VGS– Gate-to-Source Voltage (V)
2 2.5 3 3.5 4.54 5
Figure 4: R DS(ON) vs VGS for Various Temperatures
RDS(ON) – Drain-to-Source Resistance (mΩ)
25˚C
125˚C
ID = 1 A
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VGS = 0 V, VDS = 20 V
45 52
pFCOSS Output Capacitance 23 34
CRSS Reverse Transfer Capacitance 0.8 1.3
RG Gate Resistance 0.34 Ω
QG Total Gate Charge
VDS = 20 V, VGS = 5 V, ID = 1 A
370 450
pC
QGS Gate-to-Source Charge 120
QGD Gate-to-Drain Charge 47 80
QG(TH) Gate Charge at Threshold 95
QOSS Output Charge VGS = 0 V, VDS = 20 V 630 940
QRR Source-Drain Recovery Charge 0
Specifications are with substrate connected to source where applicable.
a mu ion 40 0 ZS Sn 75 100 175 150
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EPC8004
40
50
30
10
20
00 10 30
20 40
Figure 5: Capacitance (Linear Scale)
VDS– Drain-to-Source Voltage (V)
C – Capacitance (pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
102
101
100
10-1
0 10 30
20 40
Figure 5A: Capacitance (Log Scale)
VDS– Drain-to-Source Voltage (V)
C – Capacitance (pF)
4
5
3
1
2
00 100 300
200 400
Figure 6: Gate Charge
QG– Gate Charge (pC)
VG– Gate Voltage (V)
ID= 1 A
VDS = 20 V
25˚C
125˚C
7
6
5
4
8
3
2
1
0
VSD– Source-to-Drain Voltage (V)
ISD– Source-to-Drain Current (A)
0.5 0 1 1.5 2 32.5 3.5 4 4.5 5
Figure 7: Reverse Drain-Source Characteristics
1.6
1.8
1.4
1
1.2
0.8 0 5025 75 100 125 150
Figure 8: Normalized On Resistance vs Temperature
TJ– Junction Temperature (°C)
Normalized On-State Resistance – RDS(ON)
ID= 1 A
VGS = 5 V
ID = 0.25 mA
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
TJ– Junction Temperature (°C)
Normalized Threshold Voltage (V)
0 25 50 75 125100 150
Figure 9: Normalized Threshold Voltage vs Temperature
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EPC8004
Figure 11: Smith Chart
S-Parameter Characteristics
VGSQ = 1.38 V, VDSQ = 20 V, IDQ = 0.50 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
Figure 12: Gain Chart Figure 13: Device Reflection
Figure 14: Taper and Reference Plane details – Device Connection
Frequency Gate (ZGS) Drain (ZDS)
[MHz] [Ω] [Ω]
200 2.00 – j8.07 15.27 – j6.36
500 1.74 – j2.18 10.78 – j7.01
1000 1.41 + j1.60 5.98 – j4.42
1200 1.30 + j3.20 4.52 – j3.07
1500 1.11 + j4.75 3.19 – j0.98
2000 0.84 + j8.32 2.14 + j3.07
2400 0.70 + j10.24 1.95 + j5.86
3000 0.65 + j14.17 2.17 + j10.24
S-Parameter Table - Download S-parameter files at www.epc-co.com
ZDS
ZGS
Gate Circuit
Reference Plane
Drain Circuit
Reference Plane
Device Outline
914
1621
1621
149
1000
271
271
All dimensions in µm
914 355
0
5
10
15
20
25
30
35
40
45
100 1000
Amplitude Gmax
[dB]
Frequency (MHz)
25˚C
125˚C
1.2
1.4
1
0.6
0.8
0.4
0.2
0
10 32 4 5 6
Figure 10: Gate Current
VGS– Gate-to-Source Voltage (V)
IG– Gate Current (mA)
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
1.0
0.9
0.8
0.7
1.2
1.4
1.6
1.8
2.0
0.6
0.5
0.4
0.3
0.2
0.1
3.0
6.0
8.0
10
5.0
4.0
20
RF Café
2002
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
1.0
0.9
0.8
0.7
1.2
1.4
1.6
1.8
2.0
3.0
6.0
8.0
10
5.0
4.0
0.6
0.5
0.4
0.3
0.2
0.1
20
3 GHz
200 MHz
S11 – Gate Reflection
S22 – Drain Reflection
EPC8004
3 GHz
200 MHz
All measurements were done with substrate shortened to source.
Duty Factors: Duty Facmrs:
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EPC8004
TJ = Max Rated, TC = +25°C, Single Pulse
Figure 16: Safe Operating Area
100 ms
10 ms
1 ms
100 µs
Pulse Width
Limited by RDS(on)
0.1
1
10
0.1 1 10 100
ID - Drain Current (A)
VDS – Drain Voltage (V)
10-4 10-3 10-2 10-1 1 10010
tp– Rectangular Pulse Duration (s)
0.5
0.2
0.1
0.05
10-6 10-5 10-4 10-3 10-2 10-1 1 10
Figure 15: Transient Thermal Response Curves
tp– Rectangular Pulse Duration (s)
Duty Factors:
Single Pulse
Single Pulse
Junction-to-Board
Junction-to-Case
0.5
0.2
0.1
0.05
Duty Factors:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
Notes:
tp
T
PDM
ZθJC Normalized Thermal Impedance
1
0.1
0.01
0.001
0.02
0.01 Notes:
tp
T
PDM
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
10-5
1
0.1
0.01
0.001
ZθJB Normalized Thermal Impedance
0.02
0.01
, WHEN numemlonmm) um“ mln max 3 3.00 7.90 3.30 h 1.75 1.65 1.35 c (seenale) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10 llseenole) 2.00 1.95 2.05 g 1.5 1.5 1.6 1/
eGaN® FET DATASHEET
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EPC8004
8004
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC8004 8004 YYYY ZZZZ
DIE MARKINGS
YYYY
8004
ZZZZ
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
pad bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
EPC8004 (note 1)
U U \ / U
eGaN® FET DATASHEET
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EPC8004
850
570
2050
1 2
4
3
6
5
400
190
600
600
400
440
190
190
RECOMMENDED LAND PATTERN (measurements in µm)
Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
DIE OUTLINE
Solder Bar View
Side View
Dim Micrometers
Min Nominal Max
A 2020 2050 2080
B 820 850 880
C 555 580 605
d 400 400 400
e 600 600 600
f 200 225 250
g 175 200 225
h 425 450 475
i 175 200 225
j 400 400 400
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate*
*Substrate pin should be connected to Source
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate*
*Substrate pin should be connected to Source
RECOMMENDED STENCIL DRAWING (measurements in µm)
R60
850
325 200 245 230 450 Blue = bump, Gray = stencil
275
272200
592
250200
1 2
4
3
6
5
B
A
i
1 2
3
4
5
6
j
g
x2
e
e
d f
h
C
i
X2
815 Max
100 +/- 20
Seating Plane
(685)
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
The land pattern is solder mask defined.
Solder mask opening is 5 µm smaller per side than bump.
Information subject to
change without notice.
Revised August, 2019