TSV711/2/4 Datasheet by STMicroelectronics

'l meaugmemed
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
March 2013 DocID023707 Rev 2 1/29
29
TSV711, TSV712, TSV714
High accuracy (200 μV) micropower 14 μA, 150 kHz
5 V CMOS operational amplifiers
Datasheet - preliminary data
Features
Low offset voltage: 200 µV max.
Low power consumption: 10 µA at 5 V
Low supply voltage: 1.5 V to 5.5 V
Gain bandwidth product: 150 kHz typ.
Low input bias current: 1 pA typ.
Rail-to-rail input and output
EMI hardened operational amplifiers
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 to +125 °C
Benefits
Higher accuracy without calibration
Energy saving
Guaranteed operation on low-voltage battery
Related products
See the TSV73 series (900 kHz for 60 μA) for
higher gain bandwidth products
Applications
Battery powered applications
Portable devices
Signal conditioning
Active filtering
Medical instrumentation
Description
The TSV71x series of single, dual, and quad
operational amplifiers offer low-voltage operation,
rail-to-rail input and output, and excellent
accuracy (Vio lower than 200 μV at 25 °C).
These devices benefit from STMicroelectronics®
5 V CMOS technology and offer an excellent
speed/power consumption ratio (150 kHz typical
gain bandwidth) while consuming less than 14 μA
at 5 V. The TSV71x series also feature an
ultra-low input bias current.
The single version (TSV711), the dual version
(TSV712), and the quad version (TSV714) are
housed in the smallest industrial packages.
These characteristics make the TSV71x family
ideal for sensor interfaces, battery-powered and
portable applications, and active filtering.
Single (TSV711)
SC70-5
DFN8 2x2 MiniSO-8
Dual (TSV712)
Quad (TSV714)
QFN16 3x3 TSSOP14
www.st.com
Contents TSV711, TSV712, TSV714
2/29 DocID023707 Rev 2
Contents
1 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Long-term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Initialization time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 SC70-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Egg KEEP CECE CECE U m U H U H U H 01:11 .1311
DocID023707 Rev 2 3/29
TSV711, TSV712, TSV714 Pin connections
1 Pin connections
Figure 1. Pin connections (top view)
1. The exposed pads of the QFN16 3x3 can be connected to VCC- or left floating.
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DFN8 2x2 (TSV712) MiniSO-8 (TSV712)
Dual
TSSOP14 (TSV714)QFN16 3x3 (TSV714)
SC70-5 (TSV711)
Quad
Single
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Absolute maximum ratings and operating conditions TSV711, TSV712, TSV714
4/29 DocID023707 Rev 2
2 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage(1)
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
6
VVid Differential input voltage(2)
2. The differential voltage is a non-inverting input terminal with respect to the inverting input terminal. The
TSV712 and TSV714 devices include an internal differential voltage limiter that clamps internal differential
voltage at 0.5 V.
±VCC
Vin Input voltage(3)
3. VCC - Vin must not exceed 6 V, Vin must not exceed 6 V.
VCC- - 0.2 to VCC++ 0.2
Iin Input current(4)
4. Input current must be limited by a resistor in series with the inputs.
10 mA
Tstg Storage temperature -65 to +150 °C
Rthja
Thermal resistance junction-to-ambient(5)(6)
SC70-5
DFN8 2x2
MiniSO8
QFN16 3x3
TSSOP14
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
205
120
190
45
100
°C/W
Rthjc
Thermal resistance junction-to-case
DFN8 2x2 33
TjMaximum junction temperature 150 °C
ESD
HBM: human body model(7)
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
4kV
MM: machine model for TSV711(8)
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
150
VMM: machine model for TSV712(8) 200
MM: machine model for TSV714(8) 300
CDM: charged device model except MiniSO8(9)
9. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to ground.
1.5 kV
CDM: charged device model for MiniSO8(9) 1.3
Latchup immunity 200 mA
E]
DocID023707 Rev 2 5/29
TSV711, TSV712, TSV714 Absolute maximum ratings and operating conditions
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 1.5 to 5.5 V
Vicm Common mode input voltage range VCC- - 0.1 to VCC+ + 0.1
Toper Operating free air temperature range -40 to +125 °C
Electrical characteristics TSV711, TSV712, TSV714
6/29 DocID023707 Rev 2
3 Electrical characteristics
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio
Input offset voltage
(Vicm = 0 V)
T = 25 °C 200
μV-40 °C < T< 85 °C 850
-40 °C < T< 125 °C 1200
ΔVio/ΔT Input offset voltage drift -40 °C < T< 125 °C(1) 10 μV/°C
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C 1 10(2)
pA
-40 °C < T< 125 °C 1 300(2)
Iib Input bias current (Vout = VCC/2)
T = 25 °C 1 10(2)
-40 °C < T< 125 °C 1 300(2)
CMR
Common mode rejection ratio
20 log (ΔVicm/ΔVio)
Vicm = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
T = 25 °C 69 88
dB
-40 °C < T< 125 °C 61
Avd
Large signal voltage gain
Vout = 0.5 V to (VCC - 0.5 V)
T = 25 °C 95
-40 °C < T< 125 °C 85
VOH
High level output voltage
(VOH = VCC - Vout)
T = 25 °C 75
mV
-40 °C < T< 125 °C 80
VOL Low level output voltage
T = 25 °C 40
-40 °C < T< 125 °C 60
Iout
Isink (Vout = VCC)
T = 25 °C 6 12
mA
-40 °C < T< 125 °C 4
Isource (Vout = 0 V)
T = 25 °C 5 7
-40 °C < T< 125 °C 3
ICC
Supply current (per channel,
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C 9 14
µA
-40 °C < T< 125 °C 16
CC nV 4H1 E]
DocID023707 Rev 2 7/29
TSV711, TSV712, TSV714 Electrical characteristics
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
100 120
kHz
FuUnity gain frequency 100
Φ
mPhase margin 45 Degrees
GmGain margin 19 dB
SR Slew rate(3) RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V 0.04 V/μs
enEquivalent input noise voltage
f = 1 kHz 100
f = 10 kHz 96
tinit Initialization time(4) T = 25 °C 5
ms
-40 °C < T< 125 °C 60
1. See Section 4.4: Input offset voltage drift over temperature.
2. Guaranteed by characterization.
3. Slew rate value is calculated as the average between positive and negative slew rates.
4. Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed
by design. See Section 4.6: Initialization time.
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
nV
Hz
------------
Electrical characteristics TSV711, TSV712, TSV714
8/29 DocID023707 Rev 2
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage
T = 25 °C 200
μV-40 °C < T< 85 °C 850
-40 °C < T< 125 °C 1200
ΔVio/ΔT Input offset voltage drift -40 °C < T< 125 °C(1) 10 μV/°C
ΔVio
Long-term input offset voltage
drift T = 25 °C(2) 0.3
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C 1 10(3)
pA
-40 °C < T< 125 °C 1 300(3)
Iib Input bias current (Vout = VCC/2)
T = 25 °C 1 10(3)
-40 °C < T< 125 °C 1 300(3)
CMR
Common mode rejection ratio
20 log (ΔVicm/ΔVio)
Vicm = 0 V to VCC, Vout = VCC/2,
RL > 1 MΩ
T = 25 °C 80 100
dB
-40 °C < T< 125 °C 69
Avd
Large signal voltage gain
Vout = 0.5 V to (VCC - 0.5 V)
T = 25 °C 95
-40 °C < T< 125 °C 85
VOH
High level output voltage
(VOH = VCC - Vout)
T = 25 °C 75
mV
-40 °C < T< 125 °C 80
VOL Low level output voltage
T = 25 °C 40
-40 °C < T< 125 °C 60
Iout
Isink (Vout = VCC)
T = 25 °C 20 34
mA
-40 °C < T< 125 °C 15
Isource (Vout = 0 V)
T = 25 °C 20 26
-40 °C < T< 125 °C 15
ICC
Supply current (per channel,
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C 9 14
µA
-40 °C < T< 125 °C 16
μV
month
---------------------------
CC nV 4H1 E]
DocID023707 Rev 2 9/29
TSV711, TSV712, TSV714 Electrical characteristics
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
100 120
kHz
FuUnity gain frequency 100
Φ
mPhase margin 45 Degrees
GmGain margin 19 dB
SR Slew rate(4) RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V 0.05 V/μs
enEquivalent input noise voltage
f = 1 kHz 100
f = 10 kHz 96
tinit Initialization time(5) T = 25 °C 5
ms
-40 °C < T< 125 °C 50
1. See Section 4.4: Input offset voltage drift over temperature.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Section 4.5:
Long-term input offset voltage drift.
3. Guaranteed by characterization.
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay after power-up which guarantees operation within specified performances.
Guaranteed by design. See Section 4.6: Initialization time.
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
nV
Hz
------------
CC (month
Electrical characteristics TSV711, TSV712, TSV714
10/29 DocID023707 Rev 2
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage
T = 25 °C 200
μV-40 °C < T< 85 °C 850
-40 °C < T< 125 °C 1200
ΔVio/ΔT Input offset voltage drift -40 °C < T< 125 °C(1) 10 μV/°C
ΔVio
Long-term input offset voltage
drift T = 25 °C(2) 0.7
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C 1 10(3)
pA
-40 °C < T< 125 °C 1 300(3)
Iib
Input bias current
(Vout = VCC/2)
T = 25 °C 1 10(3)
-40 °C < T< 125 °C 1 300(3)
CMR
Common mode rejection ratio
20 log (ΔVicm/ΔVio)
Vicm = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
T = 25 °C 74 94
dB
-40 °C < T< 125 °C 73
SVR
Supply voltage rejection ratio
20 log (ΔVCC/ΔVio)
VCC = 1.5 to 5.5 V, Vic = 0 V,
RL > 1 MΩ
T = 25 °C 71 90
-40 °C < T< 125 °C 71
Avd
Large signal voltage gain
Vout = 0.5 V to (VCC - 0.5 V)
T = 25 °C 95
-40 °C < T< 125 °C 85
EMIRR EMI rejection ratio
EMIRR = 20 log (VRFpeak/ΔVio)
VRF = 100 mVRFpeak, f = 400 MHz 38(4)
VRF = 100 mVRFpeak, f = 900 MHz 50(4)
VRF = 100 mVRFpeak, f = 1800 MHz 60(4)
VRF = 100 mVRFpeak, f = 2400 MHz 63(4)
VOH
High level output voltage
(VOH = VCC - Vout)
T = 25 °C 75
mV
-40 °C < T< 125 °C 80
VOL Low level output voltage
T = 25 °C 40
-40 °C < T< 125 °C 60
Iout
Isink (Vout = VCC)
T = 25 °C 35 56
mA
-40 °C < T< 125 °C 20
Isource (Vout = 0 V)
T = 25 °C 35 45
-40 °C < T< 125 °C 20
ICC
Supply current (per channel,
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C 10 14
µA
-40 °C < T< 125 °C 16
μV
month
---------------------------
nV v‘Hz
DocID023707 Rev 2 11/29
TSV711, TSV712, TSV714 Electrical characteristics
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
110 150
kHz
FuUnity gain frequency 120
Φ
mPhase margin 45 Degrees
GmGain margin 19 dB
SR Slew rate(5) RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V 0.06 V/μs
en
Low-frequency peak-to-peak
input noise Bandwidth: f = 0.1 to 10 Hz 10 µVpp
enEquivalent input noise voltage
f = 1 kHz 100
f = 10 kHz 96
THD+N Total harmonic distortion +
noise
fin = 1 kHz, ACL = 1,
RL = 100 kΩ, Vicm = (VCC - 1 V)/2,
BW = 22 kHz, Vout = 0.5 Vpp
0.008 %
tinit Initialization time(6) T = 25 °C 5
ms
-40 °C < T< 125 °C 50
1. See Section 4.4: Input offset voltage drift over temperature.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Section 4.5:
Long-term input offset voltage drift.
3. Guaranteed by characterization.
4. Tested on SC70-5 package.
5. Slew rate value is calculated as the average between positive and negative slew rates.
6. Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed
by design. See Section 4.6: Initialization time.
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
nV
Hz
------------
Vicm cc cc Vicm cc 1n 200 I75 150 20 I25 100 4 u- m Sn pm y current WA) Papu‘ahon 1%) w o 25 me = Vac/2 n ‘ 5 2 0 2 5 3 0 3 5 A 0 A 5 5 0 5 5 7250 7200 150 mm 50 u in mm ‘50 200 25» Suppry manage (V) mom oNsel vmlage (uv) cc vicm cc Papu‘ahon w.) rmrursarzuzAEam AV‘D/ AT (uV/C) 500 400 300 um Maxwmum \/“7 5m) AN Goo Goo 400 7500 Inpm ousel vanage WV) mpm oHse‘ vouagewv) Lbri: Goo Goo Vcc = 5V 4000 V00 :5 v -500 0.0 0.5 10 15 2.0 25 30 3.5 m 45 so An 720 o 20 40 so 50 Inc 120 Inpm common mode vouage 1V? Tempemuve (’c)
Electrical characteristics TSV711, TSV712, TSV714
12/29 DocID023707 Rev 2
Figure 2. Supply current vs. supply voltage
at Vicm = VCC/2
Figure 3. Input offset voltage distribution
at VCC = 5 V, Vicm = VCC/2
Figure 4. Input offset voltage distribution
at VCC = 3.3 V, Vicm = VCC/2
Figure 5. Input offset voltage temperature
coefficient distribution
-250 -200 -150 -100 -50 0 50 100 150 200 250
0
5
10
15
20
25
30
VCC = 3.3 V
Vicm = 1.65 V
T = 25 ˚C
Population (%)
Input offset voltage (µV)
Figure 6. Input offset voltage vs. input common
mode voltage
Figure 7. Input offset voltage vs. temperature
 
CC CC 10 0 mo 7.5 75 5 u so 3 3 g 2.5 E, 25 E o u E c 5 72.5 .5 .25 5 5 o ,5 a 5 754: '7-5 .75 Some vm : ‘ v -m a "00 000 0.25 050 0.75 too ‘25 ‘50 no 05 «a ‘5 20 25 so 25 m 45 so 0mm vunage M empm vanage (V) Vcc we a 75 Q 50 2 «a g 25 z a C 5 c 3 4:5 3 3 § '1‘ '3 -25 0 ‘1 3 450 ° 750 r : «25 'c .775 '75 Source 7 : mm 7.00 vm :1v T :40 'c m 1.5 20 2.5 an 35 4.0 45 50 5.5 ‘k ‘0“ ”1"“ W Supp‘y vouage (V) Frequenq (Hz) a Fuuowevconugmanon v00 v r» me 5v C‘:1OODF m = ‘0 m 7 . c‘ : zoo 9F .99 T 5 25 c 5 .3 a: - 435 n- V % E % o m a Vcc m Warn 5 v R. : m m 7225 CI:TDOpF 1:125'5 Gam 4m: 727» w wk wok w w wk 100k IM Fvequency (Hz) Fvewenw 1H1)
DocID023707 Rev 2 13/29
TSV711, TSV712, TSV714 Electrical characteristics
Figure 8. Output current vs. output voltage
at VCC = 1.5 V
Figure 9. Output current vs. output voltage
at VCC = 5 V
Figure 10. Output current vs. supply voltage Figure 11. Bode diagram at VCC = 1.5 V
Figure 12. Bode diagram at VCC = 5 V Figure 13. Closed-loop gain diagram
vs. capacitive load
Oulpm vohage M 25 so 75 T\ me (vs) v05 v me :Vcc/2 0‘ : 100 DF R‘ : m m 100 125 150 mm vonage (V) 0 25 50 75 mo Tw me (us) é Vcc : 5 v 2 Vwcm : Vcc/2 3’ T : 25‘s 7,? E é q : mu pF g 7.? R‘ : 10 m g E me = Vcc/2 2 5 Wow : Vac/2 g a g E ‘2“ 5 m 15 20 25 so 35 40 45 so 55 m 100 100 0000 Supp‘y vouage (V) Frequency (Hz) a ‘ 4 R‘ : m m g 3 2 II I J l 3 2 § % 0 E m 2 + E g i 72 . F m : mu m 4 a 0.01 0 A 6 3 m H10 1000 10000 Tlmef ) Frequenc y (Hz)
Electrical characteristics TSV711, TSV712, TSV714
14/29 DocID023707 Rev 2
Figure 14. Positive slew rate Figure 15. Negative slew rate
Figure 16. Slew rate vs. supply voltage Figure 17. Noise vs. frequency
Figure 18. 0.1 Hz to 10 Hz noise Figure 19. THD+N vs. frequency
THD + N (m use 0.01 01 aw 22 kHz Vwcm Vac/2 T = 25 'c 001 Rlfloku Rpmum u ‘ ‘ ompm vouage (Vpp) 10 Ompul Im pedanoe 1sz 10000 moo we 6 01 mo 1K WK wok Frequency (Hz) 1M wM
DocID023707 Rev 2 15/29
TSV711, TSV712, TSV714 Electrical characteristics
Figure 20. THD+N vs. output voltage Figure 21. Output impedance vs. frequency
in closed-loop configuration
Application information TSV711, TSV712, TSV714
16/29 DocID023707 Rev 2
4 Application information
4.1 Operating voltages
The TSV71x series of devices can operate from 1.5 V to 5.5 V. The parameters are fully
specified for 1.8 V, 3.3 V, and 5 V power supplies. However, they are very stable in the full
VCC range and several characterization curves show TSV71x device characteristics at 1.5 V.
In addition, the main specifications are guaranteed in the extended temperature range from
-40 °C to +125 °C.
4.2 Rail-to-rail input
The TSV711, TSV712, and TSV714 devices have a rail-to-rail input, and the input common
mode range is extended from VCC-- 0.1 V to VCC+ + 0.1 V.
4.3 Rail-to-rail output
The output levels of the TSV71x operational amplifiers can go close to the rails: to a
maximum of 40 mV below the upper rail and to a maximum of 75 mV above the lower rail
when a 10 kΩ resistive load is connected to VCC/2.
4.4 Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset
variation related to offset value measured at 25 °C. The operational amplifier is one of the
main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative
sample size ensuring a Cpk (process capability index) greater than 1.33.
ΔVio
ΔT
------------max Vio T() Vio 25°C()
T25°C
---------------------------------------------------
=
E]
DocID023707 Rev 2 17/29
TSV711, TSV712, TSV714 Application information
4.5 Long-term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF
, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
AFV eβVSVU
()
=
AFT e
Ea
k
------ 1
TU
------ 1
TS
------
⎝⎠
⎛⎞
=
AFAFT AFV
×=
derifl /(monlhs)
Application information TSV711, TSV712, TSV714
18/29 DocID023707 Rev 2
Equation 5
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating (as
recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the
calculated number of months (Equation 7).
Equation 7
where Vio drift is the measured drift value in the specified test conditions after 1000 h stress
duration.
Months AF1000 h×12 months 24 h 365.25 days×()×=
VCC maxVop with Vicm VCC 2==
ΔVio
Viodrift
months()
------------------------------=
‘cc (M) 0.0 mmahzamn nme Phase ‘ Phase 2 Typmal ‘Cc as w Tune (ms) ‘5 Vcc (V)
DocID023707 Rev 2 19/29
TSV711, TSV712, TSV714 Application information
4.6 Initialization time
The TSV71x series of devices use a proprietary trimming topology that is initiated at each
device power-up and allows excellent Vio performance to be achieved. The initialization time
is defined as the delay after power-up which guarantees operation within specified
performances. During this period, the current consumption (ICC) and the input offset voltage
(Vio) can be different to the typical ones.
Figure 22. Initialization phase
The initialization time is VCC and temperature dependent. Table 6 sums up the
measurement results for different supply voltages and for temperatures varying from -40 °C
to 125 °C.
4.7 PCB layouts
For correct operation, it is advised to add a 10 nF decoupling capacitors as close as
possible to the power supply pins.
Table 6. Initialization time measurement results
VCC (V)
Temperature: -40 °C Temperature: 25 °C Temperature: 125 °C
Tinit (ms) ICC phase 1 (mA) Tinit (ms) ICC phase 1 (mA) Tinit (ms) ICC phase 1 (mA)
1.8 37 0.33 3.2 0.40 0.35 0.46
3.3 2.9 1.4 0.95 1.3 0.34 1.2
5 2.4 3.2 0.85 2.4 0.31 2.9
Application information TSV711, TSV712, TSV714
20/29 DocID023707 Rev 2
4.8 Macromodel
Accurate macromodels of the TSV71x devices are available on the STMicroelectronics’
website at www.st.com. These model are a trade-off between accuracy and complexity (that
is, time simulation) of the TSV71x operational amplifiers. They emulate the nominal
performance of a typical device within the specified operating conditions mentioned in the
datasheet. They also help to validate a design approach and to select the right operational
amplifier, but they do not replace on-board measurements.
E]
DocID023707 Rev 2 21/29
TSV711, TSV712, TSV714 Package information
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package information TSV711, TSV712, TSV714
22/29 DocID023707 Rev 2
5.1 SC70-5 package information
Figure 23. SC70-5 package mechanical drawing
Table 7. SC70-5 package mechanical data
Symbol
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A0.80 1.10 0.032 0.043
A1 00.10 0.004
A2 0.80 0.90 1.00 0.032 0.035 0.039
b0.15 0.30 0.006 0.012
c0.10 0.22 0.004 0.009
D1.80 2.00 2.20 0.071 0.079 0.087
E1.80 2.10 2.40 0.071 0.083 0.094
E1 1.15 1.25 1.35 0.045 0.049 0.053
e0.65 0.025
e1 1.30 0.051
L0.26 0.36 0.46 0.010 0.014 0.018
< 8° 0°
SEATING PLANE
GAUGE PLANE
DIMENSIONS IN MM
SIDE VIEW
TOP VIEW
COPLANAR LEADS
i i A E x i m \ "7 El 4 Q W‘ mflh— % ECU y / A W W PN ‘ \NUEX E, W m
DocID023707 Rev 2 23/29
TSV711, TSV712, TSV714 Package information
5.2 DFN8 2x2 package information
Figure 24. DFN8 2x2 package mechanical drawing
Table 8. DFN8 2x2 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.15 0.20 0.25 0.006 0.008 0.010
D 2.00 0.079
E 2.00 0.079
e 0.50 0.020
L 0.045 0.55 0.65 0.018 0.022 0.026
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Package information TSV711, TSV712, TSV714
24/29 DocID023707 Rev 2
5.3 MiniSO-8 package information
Figure 25. MiniSO-8 package mechanical drawing
Table 9. MiniSO-8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.1 0.043
A1 0 0.15 0 0.006
A2 0.75 0.85 0.95 0.030 0.033 0.037
b 0.22 0.40 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.80 3.00 3.20 0.11 0.118 0.126
E 4.65 4.90 5.15 0.183 0.193 0.203
E1 2.80 3.00 3.10 0.11 0.118 0.122
e 0.65 0.026
L 0.40 0.60 0.80 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.010
k0 ° 8 °0 ° 8 °
ccc 0.10 0.004
R (our/own) M a: BOTTOM V/EW EXPOSED PAD ‘ ‘ i L76x b 15x {4 LEADS PEP S/DE) A7 A] goos- LEADS aPLANAR/TY ; J SEA 7W6 FLA NE mp V/EW i , , , j 5 [<2>
DocID023707 Rev 2 25/29
TSV711, TSV712, TSV714 Package information
5.4 QFN16 3x3 package information
Figure 26. QFN16 3x3 package mechanical drawing
4)1B[B9BB&
M3 3.50 4—1»? 0.50
Package information TSV711, TSV712, TSV714
26/29 DocID023707 Rev 2
Figure 27. QFN16 3x3 footprint recommendation
Table 10. QFN16 3x3 mm package mechanical data (pitch 0.5 mm)
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0 0.05 0 0.002
A3 0.20 0.008
b 0.18 0.30 0.007 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
D2 1.50 1.80 0.059 0.071
E 2.90 3.00 3.10 0.114 0.118 0.122
E2 1.50 1.80 0.059 0.071
e 0.50 0.020
L 0.30 0.50 0.012 0.020
4)1B[B9BIRRWSULQWBB&
E] D [1 x \ macaw (51> 4‘ 1 :fi gal? 3: 13 am- mm g ‘ PLANE EB § 1 F 27"”? 777 7 m FL ‘0 1 D x \ fl‘ L1
DocID023707 Rev 2 27/29
TSV711, TSV712, TSV714 Package information
5.5 TSSOP14 package information
Figure 28. TSSOP14 package mechanical drawing
Table 11. TSSOP14 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A1.200.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.90 5.00 5.10 0.193 0.197 0.201
E 6.20 6.40 6.60 0.244 0.252 0.260
E1 4.30 4.40 4.50 0.169 0.173 0.176
e 0.65 0.0256
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
k0 ° 8 °0 ° 8 °
aaa 0.10 0.004
Ordering information TSV711, TSV712, TSV714
28/29 DocID023707 Rev 2
6 Ordering information
7 Revision history
Table 12. Order codes
Order code Temperature
range Package Packaging Marking
TSV711ICT
-40° C to +125° C
SC70-5
Tape and reel
K1W
TSV712IQ2T DFN8 2x2 K1W
TSV712IST MiniSO8 V712
TSV714IQ4T QFN16 3x3 K1W
TSV714IPT TSSOP14 TSV714IP
Table 13. Document revision history
Date Revision Changes
26-Sep-2012 1 Initial internal release
26-Mar-2013 2
Initial public release.
Datasheet updated for two new products: TSV712 and
TSV714.
Four new packages added: DFN8 2x2, MiniSO-8,
QFN16 3x3, and TSSOP14.
Updated Table 3, Table 4, and Table 5.
Section 4: Application information: re-written
E]
DocID023707 Rev 2 29/29
TSV711, TSV712, TSV714
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