Cyclone III Device Handbook Vol1 Datasheet by Intel

101 Innovation Drive

San Jose, CA 95134

www.altera.com

CIII5V1-4.2

Volume 1

Cyclone III Device Handbook

Document last updated for Altera Complete Design Suite version:

Document publication date:

12.0

August 2012

Cyclone III Device Handbook Volume 1

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

August 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

ISO

9001:2008

Registered

August 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Contents

Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Section I. Device Core

Chapter 1. Cyclone III Device Family Overview

Cyclone III Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Lowest Power FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Design Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Increased System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Cyclone III Device Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Logic Elements and Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

Embedded Multipliers and Digital Signal Processing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

Clock Networks and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8

Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

Support for Industry-Standard Embedded Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

Hot Socketing and Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9

SEU Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

JTAG Boundary Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Design Security (Cyclone III LS Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13

Chapter 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family

Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

LE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

LE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Chapter 3. Memory Blocks in the Cyclone III Device Family

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Mixed-Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

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Cyclone III Device Handbook August 2012 Altera Corporation

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Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Single-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

FIFO Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

I/O Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Read or Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Single-Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Read-During-Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18

Chapter 4. Embedded Multipliers in the Cyclone III Device Family

Embedded Multiplier Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Multiplier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

18-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

9-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Chapter 5. Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

GCLK Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

GCLK Network Clock Source Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

GCLK Network Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

PLLs in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9

Cyclone III Device Family PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

External Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11

Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12

No Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14

Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15

Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15

Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16

Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16

PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

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August 2012 Altera Corporation Cyclone III Device Handbook

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pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18

Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18

Manual Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20

Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21

Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21

Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22

Phase Shift Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22

PLL Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24

PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26

PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26

Post-Scale Counters (C0 to C4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28

Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29

Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30

Bypassing PLL Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31

Dynamic Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31

Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33

PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34

Section II. I/O Interfaces

Chapter 6. I/O Features in the Cyclone III Device Family

Cyclone III Device Family I/O Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

I/O Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

PCI-Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

LVDS Transmitter Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

On-Chip Series Termination Without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Termination Scheme for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Voltage-Referenced I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Differential I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Pad Placement and DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

Pad Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

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Cyclone III Device Handbook August 2012 Altera Corporation

Volume 1

Chapter 7. High-Speed Differential Interfaces in the Cyclone III Device Family

High-Speed I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

High-Speed I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

LVDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

Designing with LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

BLVDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

Designing with BLVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9

RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family . . . . . . . . . 7–10

Designing with RSDS, Mini-LVDS, and PPDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

LVPECL I/O Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12

Differential SSTL I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . 7–13

Differential HSTL I/O Standard Support in the Cyclone III Device Family . . . . . . . . . . . . . . . . . . . 7–14

True Output Buffer Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15

High-Speed I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16

Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Differential Pad Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Board Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17

Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19

Chapter 8. External Memory Interfaces in the Cyclone III Device Family

Cyclone III Device Family Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

Data and Data Clock/Strobe Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

Optional Parity, DM, and Error Correction Coding Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

Address and Control/Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

Cyclone III Device Family Memory Interfaces Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11

DDR Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11

DDR Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

OCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14

Section III. System Integration

Chapter 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device

Family

Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2

Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3

Configuration Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5

POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5

Configuration File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Configuration and JTAG Pin I/O Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7

Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10

Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11

AS Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12

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Single-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13

Multi-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14

Configuring Multiple Cyclone III Device Family with the Same Design . . . . . . . . . . . . . . . . . . . 9–16

Guidelines for Connecting Serial Configuration Device to Cyclone III Device Family on AS

Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20

Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21

AP Configuration (Supported Flash Memories) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23

AP Configuration Supported Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24

Single-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25

Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–27

Byte-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28

Word-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29

Guidelines for Connecting Parallel Flash to Cyclone III Devices for the AP Interface . . . . . . . . 9–30

Configuring With Multiple Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30

Estimating the AP Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–32

Programming Parallel Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33

PS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–34

PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–35

PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–38

PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–40

FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–42

FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–43

FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–47

JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–48

Configuring Cyclone III Device Family with Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–55

Configuring Cyclone III Device Family with the JRunner Software Driver . . . . . . . . . . . . . . . . . 9–56

Combining JTAG and AS Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–56

Programming Serial Configuration Devices In-System Using the JTAG Interface . . . . . . . . . . . 9–58

JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–60

Changing the Start Boot Address of the AP Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64

Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–64

Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–70

Cyclone III LS Design Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–70

Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71

Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71

Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71

AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71

Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–71

Cyclone III LS Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–72

Available Security Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–73

Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–73

No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74

FACTORY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74

Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–74

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–75

Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–76

Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77

Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77

Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–77

Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–80

Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–81

Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–84

User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–85

Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–86

viii Contents

Cyclone III Device Handbook August 2012 Altera Corporation

Volume 1

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–86

Chapter 10. Hot-Socketing and Power-On Reset in the Cyclone III Device Family

Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

Devices Driven Before Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

I/O Pins Remain Tristated During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2

Hot-Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3

POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4

Chapter 11. SEU Mitigation in the Cyclone III Device Family

Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2

User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2

Automated SEU Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3

Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4

Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5

Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7

Accessing Error Detection Block Through User Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8

Recovering from CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10

Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family

IEEE Std. 1149.1 BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

IEEE Std. 1149.1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2

I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5

Guidelines for IEEE Std. 1149.1 BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6

Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7

Additional Information

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

August 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Chapter Revision Dates

The chapters in this document, Cyclone III Device Handbook, were revised on the

following dates. Where chapters or groups of chapters are available separately, part

numbers are listed.

Chapter 1. Cyclone III Device Family Overview

Revised: July 2012

Part Number: CIII51001-2.4

Chapter 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51002-2.3

Chapter 3. Memory Blocks in the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51004-2.3

Chapter 4. Embedded Multipliers in the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51005-2.3

Chapter 5. Clock Networks and PLLs in the Cyclone III Device Family

Revised: July 2012

Part Number: CIII51006-4.1

Chapter 6. I/O Features in the Cyclone III Device Family

Revised: July 2012

Part Number: CIII51007-3.4

Chapter 7. High-Speed Differential Interfaces in the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51008-4.0

Chapter 8. External Memory Interfaces in the Cyclone III Device Family

Revised: July 2012

Part Number: CIII51009-3.1

Chapter 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III De-

vice Family

Revised: August 2012

Part Number: CIII51016-2.2

Chapter 10. Hot-Socketing and Power-On Reset in the Cyclone III Device Family

Revised: July 2012

Part Number: CIII51011-3.4

Chapter 11. SEU Mitigation in the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51013-2.3

xChapter Revision Dates

Cyclone III Device Handbook August 2012 Altera Corporation

Volume 1

Chapter 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family

Revised: December 2011

Part Number: CIII51014-2.3

August 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Section I. Device Core

This section provides a complete overview of all features relating to the Cyclone®III

device family.

This section includes the following chapters:

■Chapter 1, Cyclone III Device Family Overview

■Chapter 2, Logic Elements and Logic Array Blocks in the Cyclone III Device

Family

■Chapter 3, Memory Blocks in the Cyclone III Device Family

■Chapter 4, Embedded Multipliers in the Cyclone III Device Family

■Chapter 5, Clock Networks and PLLs in the Cyclone III Device Family

fFor information about the revision history for chapters in this section, refer to

“Document Revision History” in each individual chapter.

I–2 Section I: Device Core

Cyclone III Device Handbook August 2012 Altera Corporation

Volume 1

CIII51001-2.4

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

Cyclone III Device Handbook

Volume 1

July 2012

ISO

9001:2008

Registered

1. Cyclone III Device Family Overview

Cyclone® III device family offers a unique combination of high functionality, low

power and low cost. Based on Taiwan Semiconductor Manufacturing Company

(TSMC) low-power (LP) process technology, silicon optimizations and software

features to minimize power consumption, Cyclone III device family provides the ideal

solution for your high-volume, low-power, and cost-sensitive applications. To address

the unique design needs, Cyclone III device family offers the following two variants:

■Cyclone III—lowest power, high functionality with the lowest cost

■Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and

0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power

consumption, Cyclone III device family makes it easier for you to meet your power

budget. Cyclone III LS devices are the first to implement a suite of security features at

the silicon, software, and intellectual property (IP) level on a low-power and

high-functionality FPGA platform. This suite of security features protects the IP from

tampering, reverse engineering and cloning. In addition, Cyclone III LS devices

support design separation which enables you to introduce redundancy in a single

chip to reduce size, weight, and power of your application.

This chapter contains the following sections:

■“Cyclone III Device Family Features” on page 1–1

■“Cyclone III Device Family Architecture” on page 1–6

■“Reference and Ordering Information” on page 1–12

Cyclone III Device Family Features

Cyclone III device family offers the following features:

Lowest Power FPGAs

■Lowest power consumption with TSMC low-power process technology and

Altera® power-aware design flow

■Low-power operation offers the following benefits:

■Extended battery life for portable and handheld applications

■Reduced or eliminated cooling system costs

■Operation in thermally-challenged environments

■Hot-socketing operation support

July 2012

CIII51001-2.4

1–2 Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Features

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Design Security Feature

Cyclone III LS devices offer the following design security features:

■Configuration security using advanced encryption standard (AES) with 256-bit

volatile key

■Routing architecture optimized for design separation flow with the Quartus®II

software

■Design separation flow achieves both physical and functional isolation

between design partitions

■Ability to disable external JTAG port

■Error Detection (ED) Cycle Indicator to core

■Provides a pass or fail indicator at every ED cycle

■Provides visibility over intentional or unintentional change of configuration

random access memory (CRAM) bits

■Ability to perform zeroization to clear contents of the FPGA logic, CRAM,

embedded memory, and AES key

■Internal oscillator enables system monitor and health check capabilities

Increased System Integration

■High memory-to-logic and multiplier-to-logic ratio

■High I/O count, low-and mid-range density devices for user I/O constrained

applications

■Adjustable I/O slew rates to improve signal integrity

■Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,

LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS

■Supports the multi-value on-chip termination (OCT) calibration feature to

eliminate variations over process, voltage, and temperature (PVT)

■Four phase-locked loops (PLLs) per device provide robust clock management and

synthesis for device clock management, external system clock management, and

I/O interfaces

■Five outputs per PLL

■Cascadable to save I/Os, ease PCB routing, and reduce jitter

■Dynamically reconfigurable to change phase shift, frequency multiplication or

division, or both, and input frequency in the system without reconfiguring the

device

■Remote system upgrade without the aid of an external controller

■Dedicated cyclical redundancy code checker circuitry to detect single-event upset

(SEU) issues

■Nios® II embedded processor for Cyclone III device family, offering low cost and

custom-fit embedded processing solutions

Chapter 1: Cyclone III Device Family Overview 1–3

Cyclone III Device Family Features

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

■Wide collection of pre-built and verified IP cores from Altera and Altera

Megafunction Partners Program (AMPP) partners

■Supports high-speed external memory interfaces such as DDR, DDR2,

SDR SDRAM, and QDRII SRAM

■Auto-calibrating PHY feature eases the timing closure process and eliminates

variations with PVT for DDR, DDR2, and QDRII SRAM interfaces

Cyclone III device family supports vertical migration that allows you to migrate your

device to other devices with the same dedicated pins, configuration pins, and power

pins for a given package-across device densities. This allows you to optimize device

density and cost as your design evolves.

Table 1–1 lists Cyclone III device family features.

Table 1–1. Cyclone III Device Family Features

Family Device Logic

Elements

Number of

M9K

Blocks

Total RAM

Bits

18 x 18

Multipliers PLLs

Global

Clock

Networks

Maximum

User I/Os

Cyclone III

EP3C5 5,136 46 423,936 23 2 10 182

EP3C10 10,320 46 423,936 23 2 10 182

EP3C16 15,408 56 516,096 56 4 20 346

EP3C25 24,624 66 608,256 66 4 20 215

EP3C40 39,600 126 1,161,216 126 4 20 535

EP3C55 55,856 260 2,396,160 156 4 20 377

EP3C80 81,264 305 2,810,880 244 4 20 429

EP3C120 119,088 432 3,981,312 288 4 20 531

Cyclone III

EP3CLS70 70,208 333 3,068,928 200 4 20 429

EP3CLS100 100,448 483 4,451,328 276 4 20 429

EP3CLS150 150,848 666 6,137,856 320 4 20 429

EP3CLS200 198,464 891 8,211,456 396 4 20 429

1–4 Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Features

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Table 1–2 lists Cyclone III device family package options, I/O pins, and differential

channel counts.

Table 1–2. Cyclone III Device Family Package Options, I/O pin and Differential Channel Counts (1), (2), (3), (4), (5)

Family Package E144 (7) M164 P240 F256 U256 F324 F484 U484 F780

Cyclone III

(8)

EP3C5 94, 22 106, 28 — 182, 68 182, 68 — — — —

EP3C10 94, 22 106, 28 — 182, 68 182, 68 — — — —

EP3C16 84, 19 92, 23 160, 47 168, 55 168, 55 — 346, 140 346, 140 —

EP3C25 82, 18 — 148, 43 156, 54 156, 54 215, 83 — — —

EP3C40 — — 128, 26 — — 195, 61 331, 127 331, 127 535, 227 (6)

EP3C55 — — — — — — 327, 135 327, 135 377, 163

EP3C80 — — — — — — 295, 113 295, 113 429, 181

EP3C120 — — — — — — 283, 106 — 531, 233

Cyclone III

EP3CLS70 — — — — — — 294, 113 294, 113 429, 181

EP3CLS100 — — — — — — 294, 113 294, 113 429, 181

EP3CLS150 — — — — — — 226, 87 — 429, 181

EP3CLS200 — — — — — — 226, 87 — 429, 181

Notes to Table 1–2:

(1) For each device package, the first number indicates the number of the I/O pin; the second number indicates the differential channel count.

(2) For more information about device packaging specifications, refer to the Cyclone III Package and Thermal Resistance webpage.

(3) The I/O pin numbers are the maximum I/O counts (including clock input pins) supported by the device package combination and can be affected

by the configuration scheme selected for the device.

(4) All packages are available in lead-free and leaded options.

(5) Vertical migration is not supported between Cyclone III and Cyclone III LS devices.

(6) The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/Os are restricted to 510 I/Os if you enable

migration to the EP3C120 and are using voltage referenced I/O standards. If you are not using voltage referenced I/O standards, you can increase

the maximum number of I/Os.

(7) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground

plane on your PCB. Use this exposed pad for electrical connectivity and not for thermal purposes.

(8) All Cyclone III device UBGA packages are supported by the Quartus II software version 7.1 SP1 and later, with the exception of the UBGA

packages of EP3C16, which are supported by the Quartus II software version 7.2.

Chapter 1: Cyclone III Device Family Overview 1–5

Cyclone III Device Family Features

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Table 1–3 lists Cyclone III device family package sizes.

Table 1–4 lists Cyclone III device family speed grades.

Table 1–3. Cyclone III Device Family Package Sizes

Family Package Pitch (mm) Nominal Area (mm2) Length x Width (mm  mm) Height (mm)

Cyclone III

E144 0.5 484 22  22 1.60

M164 0.5 64 8  8 1.40

P240 0.5 1197 34.6  34.6 4.10

F256 1.0 289 17  17 1.55

U256 0.8 196 14  14 2.20

F324 1.0 361 19  19 2.20

F484 1.0 529 23 23 2.60

U484 0.8 361 19  19 2.20

F780 1.0 841 29  29 2.60

Cyclone III LS

F484 1.0 529 23  23 2.60

U484 0.8 361 19  19 2.20

F780 1.0 841 29  29 2.60

Table 1–4. Cyclone III Device Family Speed Grades (Part 1 of 2)

Family Device E144 M164 P240 F256 U256 F324 F484 U484 F780

Cyclone III

EP3C5 C7, C8,

I7, A7

C7, C8,

I7 —C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7 ————

EP3C10 C7, C8,

I7, A7

C7, C8,

I7 —C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7 ————

EP3C16 C7, C8,

I7, A7

C7, C8,

I7 C8 C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7 —C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7 —

EP3C25 C7, C8,

I7, A7 —C8

C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7 ———

EP3C40 — — C8 — — C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7

C6, C7,

C8, I7, A7

C6, C7,

C8, I7

EP3C55 — — — — — — C6, C7,

C8, I7

C6, C7,

C8, I7

C6, C7,

C8, I7

EP3C80 — — — — — — C6, C7,

C8, I7

C6, C7,

C8, I7

C6, C7,

C8, I7

EP3C120 — — — — — — C7, C8, I7 — C7, C8,

1–6 Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Architecture

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Table 1–5 lists Cyclone III device family configuration schemes.

Cyclone III Device Family Architecture

Cyclone III device family includes a customer-defined feature set that is optimized for

portable applications and offers a wide range of density, memory, embedded

multiplier, and I/O options. Cyclone III device family supports numerous external

memory interfaces and I/O protocols that are common in high-volume applications.

The Quartus II software features and parameterizable IP cores make it easier for you

to use the Cyclone III device family interfaces and protocols.

The following sections provide an overview of the Cyclone III device family features.

Logic Elements and Logic Array Blocks

The logic array block (LAB) consists of 16 logic elements and a LAB-wide control

block. An LE is the smallest unit of logic in the Cyclone III device family architecture.

Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic.

The four-input LUT is a function generator that can implement any function with four

variables.

fFor more information about LEs and LABs, refer to the Logic Elements and Logic Array

Blocks in the Cyclone III Device Family chapter.

Cyclone III

EP3CLS70 — — — — — — C7, C8, I7 C7, C8, I7 C7, C8,

EP3CLS100 — — — — — — C7, C8, I7 C7, C8, I7 C7, C8,

EP3CLS150 — — — — — — C7, C8, I7 — C7, C8,

EP3CLS200 — — — — — — C7, C8, I7 — C7, C8,

Table 1–4. Cyclone III Device Family Speed Grades (Part 2 of 2)

Family Device E144 M164 P240 F256 U256 F324 F484 U484 F780

Table 1–5. Cyclone III Device Family Configuration Schemes

Configuration Scheme Cyclone III Cyclone III LS

Active serial (AS) v v

Active parallel (AP) v —

Passive serial (PS) v v

Fast passive parallel (FPP) v v

Joint Test Action Group (JTAG) v v

Chapter 1: Cyclone III Device Family Overview 1–7

Cyclone III Device Family Architecture

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Memory Blocks

Each M9K memory block of the Cyclone III device family provides nine Kbits of

on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up

to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of

M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO)

buffers, or ROM. The Cyclone III device family memory blocks are optimized for

applications such as high throughout packet processing, embedded processor

program, and embedded data storage.

The Quartus II software allows you to take advantage of the M9K memory blocks by

instantiating memory using a dedicated megafunction wizard or by inferring memory

directly from the VHDL or Verilog source code.

M9K memory blocks support single-port, simple dual-port, and true dual-port

operation modes. Single-port mode and simple dual-port mode are supported for all

port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True

dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16,

and ×18.

fFor more information about memory blocks, refer to the Memory Blocks in the Cyclone

III Device Family chapter.

Embedded Multipliers and Digital Signal Processing Support

Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS

devices support up to 396 embedded multiplier blocks. Each block supports one

individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.

The Quartus II software includes megafunctions that are used to control the operation

mode of the embedded multiplier blocks based on user parameter settings.

Multipliers can also be inferred directly from the VHDL or Verilog source code. In

addition to embedded multipliers, Cyclone III device family includes a combination

of on-chip resources and external interfaces, making them ideal for increasing

performance, reducing system cost, and lowering the power consumption of digital

signal processing (DSP) systems. You can use Cyclone III device family alone or as

DSP device co-processors to improve price-to-performance ratios of DSP systems.

The Cyclone III device family DSP system design support includes the following

features:

■DSP IP cores:

■Common DSP processing functions such as finite impulse response (FIR), fast

Fourier transform (FFT), and numerically controlled oscillator (NCO) functions

■Suites of common video and image processing functions

■Complete reference designs for end-market applications

■DSP Builder interface tool between the Quartus II software and the MathWorks

Simulink and MATLAB design environments

■DSP development kits

fFor more information about embedded multipliers and digital signal processing

support, refer to the Embedded Multipliers in Cyclone III Devices chapter.

1–8 Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Architecture

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Clock Networks and PLLs

Cyclone III device family includes 20 global clock networks. You can drive global

clock signals from dedicated clock pins, dual-purpose clock pins, user logic, and

PLLs. Cyclone III device family includes up to four PLLs with five outputs per PLL to

provide robust clock management and synthesis. You can use PLLs for device clock

management, external system clock management, and I/O interfaces.

You can dynamically reconfigure the Cyclone III device family PLLs to enable

auto-calibration of external memory interfaces while the device is in operation. This

feature enables the support of multiple input source frequencies and corresponding

multiplication, division, and phase shift requirements. PLLs in Cyclone III device

family may be cascaded to generate up to ten internal clocks and two external clocks

on output pins from a single external clock source.

fFor more PLL specifications and information, refer to the Cyclone III Device Data Sheet,

Cyclone III LS Device Data Sheet, and Clock Networks and PLLs in the Cyclone III Device

Family chapters.

I/O Features

Cyclone III device family has eight I/O banks. All I/O banks support single-ended

and differential I/O standards listed in Table 1–6.

The Cyclone III device family I/O also supports programmable bus hold,

programmable pull-up resistors, programmable delay, programmable drive strength,

programmable slew-rate control to optimize signal integrity, and hot socketing.

Cyclone III device family supports calibrated on-chip series termination (RS OCT) or

driver impedance matching (Rs) for single-ended I/O standards, with one OCT

calibration block per side.

fFor more information, refer to the I/O Features in the Cyclone III Device Family chapter.

High-Speed Differential Interfaces

Cyclone III device family supports high-speed differential interfaces such as BLVDS,

LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in Cyclone III

device family provide high data throughput using a relatively small number of I/O

pins and are ideal for low-cost applications. Dedicated differential output drivers on

the left and right I/O banks can send data rates at up to 875 Mbps for Cyclone III

devices and up to 740 Mbps for Cyclone III LS devices, without the need for external

resistors. This saves board space or simplifies PCB routing. Top and bottom I/O banks

support differential transmission (with the addition of an external resistor network)

data rates at up to 640 Mbps for both Cyclone III and Cyclone III LS devices.

Table 1–6. Cyclone III Device Family I/O Standards Support

Type I/O Standard

Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X

Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS

Chapter 1: Cyclone III Device Family Overview 1–9

Cyclone III Device Family Architecture

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

fFor more information, refer to the High-Speed Differential Interfaces in the Cyclone III

Device Family chapter.

Auto-Calibrating External Memory Interfaces

Cyclone III device family supports common memory types such as DDR, DDR2,

SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interfaces support data

rates up to 400 Mbps for Cyclone III devices and 333 Mbps for Cyclone III LS devices.

Memory interfaces are supported on all sides of Cyclone III device family. Cyclone III

device family has the OCT, DDR output registers, and 8-to-36-bit programmable DQ

group widths features to enable rapid and robust implementation of different

memory standards.

An auto-calibrating megafunction is available in the Quartus II software for DDR and

QDR memory interface PHYs. This megafunction is optimized to take advantage of

the Cyclone III device family I/O structure, simplify timing closure requirements, and

take advantage of the Cyclone III device family PLL dynamic reconfiguration feature

to calibrate PVT changes.

fFor more information, refer to the External Memory Interfaces in the Cyclone III Device

Family chapter.

Support for Industry-Standard Embedded Processors

To quickly and easily create system-level designs using Cyclone III device family, you

can select among the ×32-bit soft processor cores: Freescale®V1 Coldfire, ARM®

Cortex M1, or Altera Nios®II, along with a library of 50 other IP blocks when using

the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera

Quartus II design tool that facilitates system-integration of IP blocks in an FPGA

design. The SOPC Builder automatically generates interconnect logic and creates a

testbench to verify functionality, saving valuable design time.

Cyclone III device family expands the peripheral set, memory, I/O, or performance of

legacy embedded processors. Single or multiple Nios II embedded processors are

designed into Cyclone III device family to provide additional co-processing power, or

even replace legacy embedded processors in your system. Using the Cyclone III

device family and Nios II together provide low-cost, high-performance embedded

processing solutions, which in turn allow you to extend the life cycle of your product

and improve time-to-market over standard product solutions.

1Separate licensing of the Freescale and ARM embedded processors are required.

Hot Socketing and Power-On-Reset

Cyclone III device family features hot socketing (also known as hot plug-in or hot

swap) and power sequencing support without the use of external devices. You can

insert or remove a board populated with one or more Cyclone III device family

during a system operation without causing undesirable effects to the running system

bus or the board that was inserted into the system.

1–10 Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Architecture

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

The hot socketing feature allows you to use FPGAs on PCBs that also contain a

mixture of 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. The Cyclone III device family

hot socketing feature eliminates power-up sequence requirements for other devices

on the board for proper FPGA operation.

fFor more information about hot socketing and power-on-reset, refer to the

Hot-Socketing and Power-on Reset in the Cyclone III Device Family chapter.

SEU Mitigation

Cyclone III LS devices offer built-in error detection circuitry to detect data corruption

due to soft errors in the CRAM cells. This feature allows CRAM contents to be read

and verified to match a configuration-computed CRC value. The Quartus II software

activates the built-in 32-bit CRC checker, which is part of the Cyclone III LS device.

fFor more information about SEU mitigation, refer to the SEU Mitigation in the

Cyclone III Device Family chapter.

JTAG Boundary Scan Testing

Cyclone III device family supports the JTAG IEEE Std. 1149.1 specification. The

boundary-scan test (BST) architecture offers the capability to test pin connections

without using physical test probes and captures functional data while a device is

operating normally. Boundary-scan cells in the Cyclone III device family can force

signals onto pins or capture data from pins or from logic array signals. Forced test

data is serially shifted into the boundary-scan cells. Captured data is serially shifted

out and externally compared to expected results. In addition to BST, you can use the

IEEE Std. 1149.1 controller for the Cyclone III LS device in-circuit reconfiguration

(ICR).

fFor more information about JTAG boundary scan testing, refer to the IEEE 1149.1

(JTAG) Boundary-Scan Testing for the Cyclone III Device Family chapter.

Quartus II Software Support

The Quartus II software is the leading design software for performance and

productivity. It is the only complete design solution for CPLDs, FPGAs, and ASICs in

the industry. The Quartus II software includes an integrated development

environment to accelerate system-level design and seamless integration with leading

third-party software tools and flows.

The Cyclone III LS devices provide both physical and functional separation between

security critical design partitions. Cyclone III LS devices offer isolation between

design partitions. This ensures that device errors do not propagate from one partition

to another, whether unintentional or intentional. The Quartus II software design

separation flow facilitates the creation of separation regions in Cyclone III LS devices

by tightly controlling the routing in and between the LogicLock regions. For ease of

use, the separation flow integrates in the existing incremental compilation flow.

fFor more information about the Quartus II software features, refer to the Quartus II

Handbook.

Chapter 1: Cyclone III Device Family Overview 1–11

Cyclone III Device Family Architecture

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Configuration

Cyclone III device family uses SRAM cells to store configuration data. Configuration

data is downloaded to Cyclone III device family each time the device powers up.

Low-cost configuration options include the Altera EPCS family serial flash devices as

well as commodity parallel flash configuration options. These options provide the

flexibility for general-purpose applications and the ability to meet specific

configuration and wake-up time requirements of the applications. Cyclone III device

family supports the AS, PS, FPP, and JTAG configuration schemes. The AP

configuration scheme is only supported in Cyclone III devices.

fFor more information about configuration, refer to the Configuration, Design Security,

and Remote System Upgrades in the Cyclone III Device Family chapter.

Remote System Upgrades

Cyclone III device family offers remote system upgrade without an external

controller. The remote system upgrade capability in Cyclone III device family allows

system upgrades from a remote location. Soft logic (either the Nios II embedded

processor or user logic) implemented in Cyclone III device family can download a

new configuration image from a remote location, store it in configuration memory,

and direct the dedicated remote system upgrade circuitry to start a reconfiguration

cycle. The dedicated circuitry performs error detection during and after the

configuration process, and can recover from an error condition by reverting to a safe

configuration image. The dedicated circuitry also provides error status information.

Cyclone III devices support remote system upgrade in the AS and AP configuration

scheme. Cyclone III LS devices support remote system upgrade in the AS

configuration scheme only.

fFor more information, refer to the Configuration, Design Security, and Remote System

Upgrades in the Cyclone III Device Family chapter.

Design Security (Cyclone III LS Devices Only)

Cyclone III LS devices offer design security features which play a vital role in the large

and critical designs in the competitive military and commercial environments.

Equipped with the configuration bit stream encryption and anti-tamper features,

Cyclone III LS devices protect your designs from copying, reverse engineering and

tampering. The configuration security of Cyclone III LS devices uses AES with 256-bit

security key.

fFor more information, refer to the Configuration, Design Security, and Remote System

Upgrades in Cyclone III Device Family chapter.

1–12 Chapter 1: Cyclone III Device Family Overview

Reference and Ordering Information

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Reference and Ordering Information

Figure 1–1 and Figure 1–2 show the ordering codes for Cyclone III and Cyclone III LS

devices.

Figure 1–1. Cyclone III Device Packaging Ordering Information

Family Signature

Package Type

Package Code

Operating Temperature

Speed Grade

Optional Suffix

Indicates specific device

options or shipment method

EP3C : Cyclone III

5 : 5,136 logic elements

10 : 10,320 logic elements

16 : 15,408 logic elements

25 : 24,624 logic elements

25E : 24,624 logic elements

40 : 39,600 logic elements

55 : 55,856 logic elements

80 : 81,264 logic elements

120 : 119,088 logic elements

E : Plastic Enhanced Quad Flat Pack (EQFP)

Q : Plastic Quad Flat Pack (PQFP)

F : FineLine Ball-Grid Array (FBGA)

U : Ultra FineLine Ball-Grid Array (UBGA)

M : Micro FineLine Ball-Grid Array (MBGA)

144 : 144 pins

164 : 164 pins

240 : 240 pins

256 : 256 pins

324 : 324 pins

484 : 484 pins

780 : 780 pins

C : Commercial temperature (T

= 0° C to 85° C)

I : Industrial temperature (T

= -40° C to 100° C)

A : Automotive temperature (T

= -40° C to 125° C)

6 (fastest)

N : Lead-free packaging

ES : Engineering sample

EP3C 25 F 324 C 7 N

Member Code

Figure 1–2. Cyclone III LS Device Packaging Ordering Information

Family Signature

Package Type

Package Code

Operating Temperature

Speed Grade

Optional Suffix

Indicates specific device

options or shipment method

EP3CLS : Cyclone III LS

70 : 70,208 logic elements

100 : 100,448 logic elements

150 : 150,848 logic elements

200 : 198,464 logic elements

F : FineLine Ball-Grid Array (FBGA)

U : Ultra FineLine Ball-Grid Array (UBGA)

484 : 484 pins

780 : 780 pins

C : Commercial temperature (TJ = 0° C to 85° C)

I : Industrial temperature (TJ = -40° C to 100° C)

7 (fastest)

N : Lead-free packaging

ES : Engineering sample

EP3CLS 70 F 484 C 7 N

Member Code

Chapter 1: Cyclone III Device Family Overview 1–13

Document Revision History

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Document Revision History

Table 1–7 lists the revision history for this document.

Table 1–7. Document Revision History

Date Version Changes

July 2012 2.4 Updated 484 pin package code in Figure 1–1.

December 2011 2.3

■Updated Table 1–1 and Table 1–2.

■Updated Figure 1–1 and Figure 1–2.

■Updated hyperlinks.

■Minor text edits.

December 2009 2.2 Minor text edits.

July 2009 2.1 Minor edit to the hyperlinks.

June 2009 2.0

■Added Table 1–5.

■Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.

■Updated “Introduction”, “Cyclone III Device Family Architecture”, “Embedded Multipliers

and Digital Signal Processing Support ”, “Clock Networks and PLLs ”, “I/O Features ”,

“High-Speed Differential Interfaces ”, “Auto-Calibrating External Memory Interfaces ”,

“Quartus II Software Support”, “Configuration ”, and “Design Security (Cyclone III LS

Devices Only)”.

■Removed “Referenced Document” section.

October 2008 1.3

■Updated “Increased System Integration” section.

■Updated “Memory Blocks” section.

■Updated chapter to new template.

May 2008 1.2

■Added 164-pin Micro FineLine Ball-Grid Array (MBGA) details to Table 1–2, Table 1–3 and

Table 1–4.

■Updated Figure 1–2 with automotive temperature information.

■Updated “Increased System Integration” section, Table 1–6, and “High-Speed Differential

Interfaces” section with BLVDS information.

July 2007 1.1

■Removed the text “Spansion” in “Increased System.

■Integration” and “Configuration” sections.

■Removed trademark symbol from “MultiTrack” in “MultiTrack Interconnect”.

■Removed registered trademark symbol from “Simulink” and “MATLAB” from “Embedded

Multipliers and Digital.

■Signal Processing Support” section.

■Added chapter TOC and “Referenced Documents” section.

March 2007 1.0 Initial release.

1–14 Chapter 1: Cyclone III Device Family Overview

Document Revision History

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

CIII51002-2.3

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

Cyclone III Device Handbook

Volume 1

December 2011

ISO

9001:2008

Registered

2. Logic Elements and Logic Array Blocks

in the Cyclone III Device Family

This chapter contains feature definitions for logic elements (LEs) and logic array

blocks (LABs). Details are provided on how LEs work, how LABs contain groups of

LEs, and how LABs interface with the other blocks in the Cyclone®III device family

(Cyclone III and Cyclone III LS devices).

Logic Elements

Logic elements (LEs) are the smallest units of logic in the Cyclone III device family

architecture. LEs are compact and provide advanced features with efficient logic

usage. Each LE has the following features:

■A four-input look-up table (LUT), which can implement any function of four

variables

■A programmable register

■A carry chain connection

■A register chain connection

■The ability to drive the following interconnects:

■Local

■Row

■Column

■Register chain

■Direct link

■Register packing support

■Register feedback support

December 2011

CIII51002-2.3

2–2 Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

Logic Elements

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Figure 2–1 shows the LEs for the Cyclone III device family.

LE Features

You can configure the programmable register of each LE for D, T, JK, or SR flipflop

operation. Each register has data, clock, clock enable, and clear inputs. Signals that

use the global clock network, general-purpose I/O pins, or any internal logic can

drive the clock and clear control signals of the register. Either general-purpose I/O

pins or the internal logic can drive the clock enable. For combinational functions, the

LUT output bypasses the register and drives directly to the LE outputs.

Each LE has three outputs that drive the local, row, and column routing resources. The

LUT or register output independently drives these three outputs. Two LE outputs

drive the column or row and direct link routing connections, while one LE drives the

local interconnect resources. This allows the LUT to drive one output while the

utilization because the device can use the register and the LUT for unrelated

functions. The LAB-wide synchronous load control signal is not available when using

to “LAB Control Signals” on page 2–6.

The register feedback mode allows the register output to feed back into the LUT of the

same LE to ensure that the register is packed with its own fan-out LUT, providing

another mechanism for improved fitting. The LE can also drive out registered and

unregistered versions of the LUT output.

Figure 2–1. Cyclone III Device Family LEs

Row, Column,

And Direct Link

Routing

data 1

data 2

data 3

data 4

labclr1

labclr2

Chip-Wide

Reset

(DEV_CLRn)

labclk1

labclk2

labclkena1

labclkena2

LE Carry-In

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

Row, Column,

And Direct Link

Routing

Local

Routing

Output

Programmable

Routing from

previous LE

LE Carry-Out

Synchronous

Load and

Clear Logic

Carry

Chain

Look-Up Table

(LUT)

Asynchronous

Clear Logic

Clock &

Clock Enable

Select

ENA

CLRN

Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family 2–3

LE Operating Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

In addition to the three general routing outputs, LEs in a LAB have register chain

outputs, which allows registers in the same LAB to cascade together. The register

chain output allows the LUTs to be used for combinational functions and the registers

to be used for an unrelated shift register implementation. These resources speed up

connections between LABs while saving local interconnect resources.

LE Operating Modes

Cyclone III device family LEs operate in the following modes:

■Normal mode

■Arithmetic mode

LE operating modes use LE resources differently. In each mode, there are six available

inputs to the LE. These inputs include the four data inputs from the LAB local

interconnect, the LE carry-in from the previous LE carry-chain, and the register chain

connection. Each input is directed to different destinations to implement the desired

logic function. LAB-wide signals provide clock, asynchronous clear, synchronous

clear, synchronous load, and clock enable control for the register. These LAB-wide

signals are available in all LE modes.

The Quartus®II software automatically chooses the appropriate mode for common

functions, such as counters, adders, subtractors, and arithmetic functions, in

conjunction with parameterized functions such as the library of parameterized

modules (LPM) functions. You can also create special-purpose functions that specify

which LE operating mode to use for optimal performance, if required.

Normal Mode

Normal mode is suitable for general logic applications and combinational functions.

In normal mode, four data inputs from the LAB local interconnect are inputs to a

four-input LUT (Figure 2–2). The Quartus II Compiler automatically selects the

carry-in (

cin

) or the

data3

signal as one of the inputs to the LUT. LEs in normal mode

support packed registers and register feedback.

Figure 2–2 shows LEs in normal mode.

Figure 2–2. Cyclone III Device Family LEs in Normal Mode

data1

Four-Input

LUT

data2

data3

cin (from cout

of previous LE)

data4

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

ENA

sclear

(LAB Wide)

sload

(LAB Wide)

Connection

Chain Output

Row, Column, and

Direct Link Routing

Row, Column, and

Direct Link Routing

Local Routing

Packed Register Input

ii ﬁH \

2–4 Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

Logic Array Blocks

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Arithmetic Mode

Arithmetic mode is ideal for implementing adders, counters, accumulators, and

comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry

chain (Figure 2–3). LEs in arithmetic mode can drive out registered and unregistered

versions of the LUT output. Register feedback and register packing are supported

when LEs are used in arithmetic mode.

Figure 2–3 shows LEs in arithmetic mode.

The Quartus II Compiler automatically creates carry chain logic during design

processing. You can also manually create the carry chain logic during design entry.

Parameterized functions, such as LPM functions, automatically take advantage of

carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 16 LEs by automatically

linking LABs in the same column. For enhanced fitting, a long carry chain runs

vertically, which allows fast horizontal connections to M9K memory blocks or

embedded multipliers through direct link interconnects. For example, if a design has a

long carry chain in a LAB column next to a column of M9K memory blocks, any LE

output can feed an adjacent M9K memory block through the direct link interconnect.

If the carry chains run horizontally, any LAB which is not next to the column of M9K

memory blocks uses other row or column interconnects to drive a M9K memory

block. A carry chain continues as far as a full column.

Logic Array Blocks

Logic array blocks (LABs) contain groups of LEs.

Topology

Each LAB consists of the following features:

■16 LEs

Figure 2–3. Cyclone III Device Family LEs in Arithmetic Mode

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

CLRN

ENA

sclear

(LAB Wide)

sload

(LAB Wide)

Chain Output

Row, Column, and

Direct link routing

Row, Column, and

Direct link routing

Local Routing

Three-Input

LUT

Three-Input

LUT

cin (from cout

of previous LE)

data2

data1

cout

data4

data3

Connection

Packed Register Input

Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family 2–5

Logic Array Blocks

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

■LAB control signals

■LE carry chains

■Register chains

■Local interconnect

The local interconnect transfers signals between LEs in the same LAB. Register chain

connections transfer the output of one LE register to the adjacent LE register in a LAB.

The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing

the use of local and register chain connections for performance and area efficiency.

Figure 2–4 shows the LAB structure for the Cyclone III device family.

LAB Interconnects

The LAB local interconnect is driven by column and row interconnects and LE

outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM

blocks, and embedded multipliers from the left and right can also drive the local

interconnect of a LAB through the direct link connection. The direct link connection

feature minimizes the use of row and column interconnects, providing higher

performance and flexibility. Each LE can drive up to 48 LEs through fast local and

direct link interconnects.

Figure 2–4. Cyclone III Device Family LAB Structure

Direct link

interconnect

from adjacent

block

Direct link

interconnect

to adjacent

block

Row Interconnect

Column

Interconnect

Local Interconnect

LAB

Direct link

interconnect

from adjacent

block

Direct link

interconnect

to adjacent

block

2–6 Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

LAB Control Signals

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Figure 2–5 shows the direct link connection.

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. The control

signals include:

■Two clocks

■Two clock enables

■Two asynchronous clears

■One synchronous clear

■One synchronous load

You can use up to eight control signals at a time. Register packing and synchronous

load cannot be used simultaneously.

Each LAB can have up to four non-global control signals. You can use additional LAB

control signals as long as they are global signals.

Synchronous clear and load signals are useful for implementing counters and other

functions. The synchronous clear and synchronous load signals are LAB-wide signals

that affect all registers in the LAB.

Each LAB can use two clocks and two clock enable signals. The clock and clock enable

signals of each LAB are linked. For example, any LE in a particular LAB using the

labclk1

signal also uses the

labclkena1

. If the LAB uses both the rising and falling

edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock

enable signal turns off the LAB-wide clock.

The LAB row clocks

[5..0]

and LAB local interconnect generate the LAB-wide

control signals. The MultiTrack interconnect inherent low skew allows clock and

control signal distribution in addition to data distribution.

Figure 2–5. Cyclone III Device Family Direct Link Connection

LAB

Direct link

interconnect

to right

Direct link interconnect from

right LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Direct link interconnect from

left LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

DLc LI LI LI LI

Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family 2–7

Document Revision History

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 2–6 shows the LAB control signal generation circuit.

LAB-wide signals control the logic for the clear signal of the register. The LE directly

supports an asynchronous clear function. Each LAB supports up to two asynchronous

clear signals (

labclr1

and

labclr2

A LAB-wide asynchronous load signal to control the logic for the preset signal of the

technique. The Cyclone III device family only supports either a preset or

asynchronous clear signal.

In addition to the clear port, the Cyclone III device family provides a chip-wide reset

pin (

DEV_CLRn

) that resets all registers in the device. An option set before compilation

in the Quartus II software controls this pin. This chip-wide reset overrides all other

control signals.

Document Revision History

Table 2–1 lists the revision history for this document.

Figure 2–6. Cyclone III Device Family LAB-Wide Control Signals

labclkena1

labclk2labclk1

labclkena2 labclr1

Dedicated

LAB Row

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

syncload

synclr

labclr2

Table 2–1. Document Revision History (Part 1 of 2)

Date Version Changes

December 2011 2.3 Minor text edits.

December 2009 2.2 Minor changes to the text.

July 2009 2.1 Minor edit to the hyperlinks.

June 2009 2.0

Updated to include Cyclone III LS information

■Updated chapter part number.

■Updated “Introduction” on page 2–1.

■Updated Figure 2–1 on page 2–2 and Figure 2–4 on page 2–5.

■Updated “LAB Control Signals” on page 2–6.

October 2008 1.2 Updated chapter to new template.

2–8 Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

Document Revision History

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

July 2007 1.1 Removed trademark symbol from “MultiTrack” in “LAB Control Signals” section.

March 2007 1.0 Initial release.

Table 2–1. Document Revision History (Part 2 of 2)

Date Version Changes

CIII51004-2.3

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

Cyclone III Device Handbook

Volume 1

December 2011

ISO

9001:2008

Registered

3. Memory Blocks in the Cyclone III

Device Family

The Cyclone®III device family (Cyclone III and Cyclone III LS devices) features

embedded memory structures to address the on-chip memory needs of Altera®

Cyclone III device family designs. The embedded memory structure consists of

columns of M9K memory blocks that you can configure to provide various memory

functions, such as RAM, shift registers, ROM, and FIFO buffers.

This chapter contains the following sections:

■“Memory Modes” on page 3–7

■“Clocking Modes” on page 3–14

■“Design Considerations” on page 3–15

Overview

M9K blocks support the following features:

■8,192 memory bits per block (9,216 bits per block including parity)

■Independent read-enable (

rden

) and write-enable (

wren

) signals for each port

■Packed mode in which the M9K memory block is split into two 4.5 K single-port

RAMs

■Variable port configurations

■Single-port and simple dual-port modes support for all port widths

■True dual-port (one read and one write, two reads, or two writes) operation

■Byte enables for data input masking during writes

■Two clock-enable control signals for each port (port A and port B)

■Initialization file to pre-load memory content in RAM and ROM modes

December 2011

CIII51004-2.3

3–2 Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Table 3–1 lists the features supported by the M9K memory

fFor information about the number of M9K memory blocks for the Cyclone III device

family, refer to the Cyclone III Device Family Overview chapter.

Table 3–1. Summary of M9K Memory Features

Feature M9K Blocks

Configurations (depth × width)

8192 × 1

4096 × 2

2048 × 4

1024 × 8

1024 × 9

512 × 16

512 × 18

256 × 32

256 × 36

Parity bits v

Byte enable v

Packed mode v

Address clock enable v

Single-port mode v

Simple dual-port mode v

True dual-port mode v

Embedded shift register mode (1) v

ROM mode v

FIFO buffer (1) v

Simple dual-port mixed width support v

True dual-port mixed width support (2) v

Memory initialization file (.mif)v

Mixed-clock mode v

Power-up condition Outputs cleared

Latch asynchronous clears Output latches only

Write or read operation triggering Write and read: Rising clock edges

Same-port read-during-write Outputs set to Old Data or New Data

Mixed-port read-during-write Outputs set to Old Data or Don’t Care

Notes to Table 3–1:

(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control

logic.

(2) Width modes of ×32 and ×36 are not available.

K WWWW

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–3

Overview

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Control Signals

The clock-enable control signal controls the clock entering the input and output

registers and the entire M9K memory block. This signal disables the clock so that the

M9K memory block does not see any clock edges and does not perform any

operations.

The

rden

and

wren

control signals control the read and write operations for each port

of M9K memory blocks. You can disable the

rden

wren

signals independently to

save power whenever the operation is not required.

Figure 3–1 shows how the register clock, clear, and control signals are implemented in

the Cyclone III device family M9K memory block.

Parity Bit Support

Parity checking for error detection is possible with the parity bit along with internal

logic resources. The Cyclone III device family M9K memory blocks support a parity

bit for each storage byte. You can use this bit as either a parity bit or as an additional

data bit. No parity function is actually performed on this bit.

Figure 3–1. M9K Control Signal Selection

clock_b

clocken_aclock_a

clocken_baclr_b

aclr_a

Dedicated

Row LAB

Clocks

rden_b

rden_a

Local

Interconnect

byteena_b

byteena_a

addressstall_b

addressstall_a

wren_a

wren_b

3–4 Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Byte Enable Support

The Cyclone III device family M9K memory blocks support byte enables that mask

the input data so that only specific bytes of data are written. The unwritten bytes

retain the previous written value. The

wren

signals, along with the byte-enable

(

byteena

) signals, control the write operations of the RAM block. The default value of

the

byteena

signals is high (enabled), in which case writing is controlled only by the

wren

signals. There is no clear port to the

byteena

registers. M9K blocks support byte

enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.

Byte enables operate in one-hot manner, with the LSB of the

byteena

signal

corresponding to the least significant byte of the data bus. For example, if

byteena = 01

and you are using a RAM block in ×18 mode,

data[8..0]

is enabled

and

data[17..9]

is disabled. Similarly, if

byteena = 11

, both

data[8..0]

and

data[17..9]

are enabled. Byte enables are active high.

Table 3–2 lists the byte selection.

Figure 3–2 shows how the

wren

and

byteena

signals control the RAM operations.

Table 3–2. byteena for Cyclone III Device Family M9K Blocks (1)

byteena[3..0]

Affected Bytes

datain × 16 datain × 18 datain × 32 datain × 36

[0] = 1 [7..0] [8..0] [7..0] [8..0]

[1] = 1 [15..8] [17..9] [15..8] [17..9]

[2] = 1 — — [23..16] [26..18]

[3] = 1 — — [31..24] [35..27]

Note to Table 3–2:

(1) Any combination of byte enables is possible.

Figure 3–2. Cyclone III Device Family byteena Functional Waveform (1)

inclock

wren

address

data

q (asynch)

XXXX

a0 a1 a2 a0 a1 a2

doutn ABFF FFCD ABCD ABFF FFCD

ABCD

byteena XX 10 01 11

XXXX

ABCD

ABCDFFFF

FFFF

ABFF

FFCD

contents at a0

contents at a1

contents at a2

rden

A? W ,

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–5

Overview

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

When a

byteena

bit is deasserted during a write cycle, the old data in the memory

appears in the corresponding data-byte output. When a

byteena

bit is asserted during

a write cycle, the corresponding data-byte output depends on the setting chosen in

the Quartus®II software. The setting can either be the newly written data or the old

data at that location.

Packed Mode Support

Cyclone III device family M9K memory blocks support packed mode. You can

implement two single-port memory blocks in a single block under the following

conditions:

■Each of the two independent block sizes is less than or equal to half of the M9K

block size. The maximum data width for each independent block is 18 bits wide.

■Each of the single-port memory blocks is configured in single-clock mode. For

more information about packed mode support, refer to “Single-Port Mode” on

page 3–8 and “Single-Clock Mode” on page 3–15.

Address Clock Enable Support

Cyclone III device family M9K memory blocks support an active-low address clock

enable, which holds the previous address value for as long as the

addressstall

signal

is high (

addressstall

'1'

). When you configure M9K memory blocks in dual-port

mode, each port has its own independent address clock enable.

Figure 3–3 shows an address clock enable block diagram. The address register output

feeds back to its input using a multiplexer. The multiplexer output is selected by the

address clock enable (

addressstall

) signal.

Note to Figure 3–2:

(1) For this functional waveform, New Data mode is selected.

Figure 3–2. Cyclone III Device Family byteena Functional Waveform (1)

Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram

address[0]

address[N]

addressstall

clock

address[0]

address[N]

address[0]

3–6 Chapter 3: Memory Blocks in the Cyclone III Device Family

Overview

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

The address clock enable is typically used to improve the effectiveness of cache

memory applications during a cache-miss. The default value for the address clock

enable signals is low.

Figure 3–4 and Figure 3–5 show the address clock enable waveform during read and

write cycles, respectively.

Mixed-Width Support

M9K memory blocks support mixed data widths. When using simple dual-port, true

dual-port, or FIFO modes, mixed width support allows you to read and write

different data widths to an M9K memory block. For more information about the

different widths supported per memory mode, refer to “Memory Modes” on

page 3–7.

Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform

Figure 3–5. Cyclone III Device Family Address Clock Enable During Write Cycle Waveform

inclock

rden

rdaddress

q (synch)

a0 a1 a2 a3 a4 a5 a6

q (asynch)

an a0 a4 a5

latched address

(inside memory)

dout0 dout1 dout1 dout4

dout1 dout4 dout5

addressstall

doutn-1 dout1

doutn

doutn dout1

dout0 dout1

inclock

wren

wraddress a0 a1 a2 a3 a4 a5 a6

an a0 a4 a5

latched address

(inside memory)

addressstall

data 00 01 02 03 04 05 06

contents at a0

contents at a1

contents at a2

contents at a3

contents at a4

contents at a5

XX 02

XX 05

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–7

Memory Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Asynchronous Clear

The Cyclone III device family supports asynchronous clears for read address registers,

output registers, and output latches only. Input registers other than read address

registers are not supported. When applied to output registers, the asynchronous clear

signal clears the output registers and the effects are immediately seen. If your RAM

does not use output registers, you can still clear the RAM outputs using the output

latch asynchronous clear feature.

1Asserting asynchronous clear to the read address register during a read operation

might corrupt the memory content.

Figure 3–6 shows the functional waveform for the asynchronous clear feature.

1You can selectively enable asynchronous clears per logical memory using the

Quartus II RAM MegaWizard™ Plug-In Manager.

fFor more information, refer to the Internal Memory (RAM and ROM) User Guide.

There are three ways to reset registers in the M9K blocks:

■Power up the device

■Use the

aclr

signal for output register only

■Assert the device-wide reset signal using the DEV_CLRn option

Memory Modes

Cyclone III device family M9K memory blocks allow you to implement

fully-synchronous SRAM memory in multiple modes of operation. Cyclone III device

family M9K memory blocks do not support asynchronous (unregistered) memory

inputs.

M9K memory blocks support the following modes:

■Single-port

■Simple dual-port

■True dual-port

■Shift-register

■ROM

■FIFO

Figure 3–6. Output Latch Asynchronous Clear Waveform

aclr

aclr at latch

clk

qa1 a0 a1

3–8 Chapter 3: Memory Blocks in the Cyclone III Device Family

Memory Modes

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

1Violating the setup or hold time on the M9K memory block input registers may

corrupt memory contents. This applies to both read and write operations.

Single-Port Mode

Single-port mode supports non-simultaneous read and write operations from a single

address. Figure 3–7 shows the single-port memory configuration for Cyclone III

device family M9K memory blocks.

During a write operation, the behavior of the RAM outputs is configurable. If you

activate

rden

during a write operation, the RAM outputs show either the new data

being written or the old data at that address. If you perform a write operation with

rden

deactivated, the RAM outputs retain the values they held during the most recent

active

rden

signal.

To choose the desired behavior, set the Read-During-Write option to either New Data

or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For

more information about read-during-write mode, refer to “Read-During-Write

Operations” on page 3–15.

The port width configurations for M9K blocks in single-port mode are as follow:

■8192 × 1

■4096 × 2

■2048 × 4

■1024 × 8

■1024 × 9

■512 × 16

■512 × 18

■256 × 32

■256 × 36

Figure 3–7. Single-Port Memory (1), (2)

Notes to Figure 3–7:

(1) You can implement two single-port memory blocks in a single M9K block.

(2) For more information, refer to “Packed Mode Support” on page 3–5.

data[ ]

address[ ]

wren

byteena[]

addressstall

inclock

inclocken

rden

aclr

outclock

q[]

outclocken

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–9

Memory Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 3–8 shows timing waveforms for read and write operations in single-port

mode with unregistered outputs. Registering the outputs of the RAM simply delays

the

output by one clock cycle.

Simple Dual-Port Mode

Simple dual-port mode supports simultaneous read and write operations to different

locations. Figure 3–9 shows the simple dual-port memory configuration.

Cyclone III device family M9K memory blocks support mixed-width configurations,

allowing different read and write port widths.

Table 3–3 lists mixed-width configurations.

Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms

clk_a

wren_a

address_a

data_a

rden_a

q_a (old data)

a0 a1

AB C D EF

a0(old data) a1(old data)AB D E

q_a (new data)

ADBC E F

Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory (1)

Note to Figure 3–9:

(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.

data[ ]

wraddress[ ]

wren

byteena[]

wr_addressstall

wrclock

wrclocken

aclr

rdaddress[ ]

rden

q[ ]

rd_addressstall

rdclock

rdclocken

Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)

Read Port

Write Port

8192 ×1 4096 ×2 2048 ×4 1024 ×8 512 ×16 256 ×32 1024 ×9 512 ×18 256 ×36

8192 × 1 vvvvvv———

4096 × 2 vvvvvv———

2048 × 4 vvvvvv———

1024 × 8 vvvvvv———

3–10 Chapter 3: Memory Blocks in the Cyclone III Device Family

Memory Modes

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

In simple dual-port mode, M9K memory blocks support separate

wren

and

rden

signals. You can save power by keeping the

rden

signal low (inactive) when not

reading. Read-during-write operations to the same address can either output “Don’t

Care” data at that location or output “Old Data”. To choose the desired behavior, set

the Read-During-Write option to either Don’t Care or Old Data in the RAM

MegaWizard Plug-In Manager in the Quartus II software. For more information about

this behavior, refer to “Read-During-Write Operations” on page 3–15.

Figure 3–10 shows the timing waveforms for read and write operations in simple

dual-port mode with unregistered outputs. Registering the outputs of the RAM

simply delays the

output by one clock cycle.

512 × 16 vvvvvv———

256 × 32 vvvvvv———

1024 × 9 — — — — — — vvv

512×18——————vvv

256×36——————vvv

Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)

Read Port

Write Port

8192 ×1 4096 ×2 2048 ×4 1024 ×8 512 ×16 256 ×32 1024 ×9 512 ×18 256 ×36

Figure 3–10. Cyclone III Device Family Simple Dual-Port Timing Waveforms

wrclock

wren

wraddress

rdclock

an-1 an a0 a1 a2 a3 a4 a5 a6

q (asynch)

rden

rdaddress bnb0b1b2b3

doutn-1 doutn dout0

din-1 din din4 din5 din6

data

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–11

Memory Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

True Dual-Port Mode

True dual-port mode supports any combination of two-port operations: two reads,

two writes, or one read and one write, at two different clock frequencies. Figure 3–11

shows the Cyclone III device family true dual-port memory configuration.

1The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit

(18-bit with parity).

Table 3–4 lists the possible M9K block mixed-port width configurations.

In true dual-port mode, M9K memory blocks support separate

wren

and

rden

signals.

You can save power by keeping the

rden

signal low (inactive) when not reading.

Read-during-write operations to the same address can either output “New Data” at

that location or “Old Data”. To choose the desired behavior, set the Read-During-

Write option to either New Data or Old Data in the RAM MegaWizard Plug-In

Manager in the Quartus II software. For more information about this behavior, refer to

“Read-During-Write Operations” on page 3–15.

Figure 3–11. Cyclone III Device Family True Dual-Port Memory (1)

Note to Figure 3–11:

(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.

data_a[ ]

address_a[ ]

wren_a

byteena_a[]

addressstall_a

clock_a

clocken_a

rden_a

aclr_a

q_a[]

data_b[ ]

address_b[]

wren_b

byteena_b[]

addressstall_b

clock_b

clocken_b

rden_b

aclr_b

q_b[]

Table 3–4. Cyclone III Device Family M9K Block Mixed-Width Configurations (True Dual-Port

Mode)

Read Port

Write Port

8192 ×1 4096 ×2 2048 ×4 1024 ×8 512 ×16 1024 ×9 512 ×18

8192 ×1vvvvv——

4096 ×2vvvvv——

2048 ×4vvvvv——

1024 ×8vvvvv——

512 ×16 vvvvv——

1024 ×9— — — — — vv

512 ×18 — — — — — vv

3–12 Chapter 3: Memory Blocks in the Cyclone III Device Family

Memory Modes

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

In true dual-port mode, you can access any memory location at any time from either

port A or port B. However, when accessing the same memory location from both

ports, you must avoid possible write conflicts. When you attempt to write to the same

address location from both ports at the same time, a write conflict happens. This

results in unknown data being stored to that address location. There is no conflict

resolution circuitry built into the Cyclone III device family M9K memory blocks. You

must handle address conflicts external to the RAM block.

Figure 3–12 shows true dual-port timing waveforms for the write operation at port A

and read operation at port B. Registering the outputs of the RAM simply delays the

outputs by one clock cycle.

Shift Register Mode

Cyclone III device family M9K memory blocks can implement shift registers for

digital signal processing (DSP) applications, such as finite impulse response (FIR)

filters, pseudo-random number generators, multi-channel filtering, and

auto-correlation and cross-correlation functions. These and other DSP applications

require local data storage, traditionally implemented with standard flipflops that

quickly exhaust many logic cells for large shift registers. A more efficient alternative is

to use embedded memory as a shift register block, which saves logic cell and routing

resources.

The size of a (w× m×n) shift register is determined by the input data width (w), the

length of the taps (m), and the number of taps (n), and must be less than or equal to

the maximum number of memory bits, which is 9,216 bits. In addition, the size of

(w×n) must be less than or equal to the maximum width of the block, which is 36 bits.

If you need a larger shift register, you can cascade the M9K memory blocks.

Figure 3–12. Cyclone III Device Family True Dual-Port Timing Waveforms

clk_a

wren_a

address_a

clk_b

an-1 an a0 a1 a2 a3 a4 a5 a6

q_b (asynch)

wren_b

address_bbnb0b1b2b3

doutn-1 doutn dout0

q_a (asynch)

din-1 din din4 din5 din6

data_a

din-1 din dout0 dout1 dout2 dout3 din4 din5

dout2

dout1

rden_a

rden_b

n Number gr Taps

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–13

Memory Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 3–13 shows the Cyclone III device family M9K memory block in the shift

ROM Mode

Cyclone III device family M9K memory blocks support ROM mode. A .mif initializes

the ROM contents of these blocks. The address lines of the ROM are registered. The

outputs can be registered or unregistered. The ROM read operation is identical to the

read operation in the single-port RAM configuration.

FIFO Buffer Mode

Cyclone III device family M9K memory blocks support single-clock or dual-clock

FIFO buffers. Dual clock FIFO buffers are useful when transferring data from one

clock domain to another clock domain. Cyclone III device family M9K memory blocks

do not support simultaneous read and write from an empty FIFO buffer.

fFor more information about FIFO buffers, refer to the SCFIFO and DCFIFO

Megafunctions user guide.

Figure 3–13. Cyclone III Device Family Shift Register Mode Configuration

w × m × n Shift Register

m-Bit Shift Register

n Number of Taps

3–14 Chapter 3: Memory Blocks in the Cyclone III Device Family

Clocking Modes

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Clocking Modes

Cyclone III device family M9K memory blocks support the following clocking modes:

■Independent

■Input or output

■Read or write

■Single-clock

When using read or write clock mode, if you perform a simultaneous read or write to

the same address location, the output read data is unknown. If you require the output

data to be a known value, use either single-clock mode or I/O clock mode and choose

the appropriate read-during-write behavior in the MegaWizard Plug-In Manager.

1Violating the setup or hold time on the memory block input registers might corrupt

the memory contents. This applies to both read and write operations.

1Asynchronous clears are available on read address registers, output registers, and

output latches only.

Table 3–5 lists the clocking mode versus memory mode support matrix.

Independent Clock Mode

Cyclone III device family M9K memory blocks can implement independent clock

mode for true dual-port memories. In this mode, a separate clock is available for each

port (port A and port B).

clock A

controls all registers on the port A side, while

clock

controls all registers on the port B side. Each port also supports independent clock

enables for port A and B registers.

I/O Clock Mode

Cyclone III device family M9K memory blocks can implement input or output clock

mode for FIFO, single-port, true, and simple dual-port memories. In this mode, an

input clock controls all input registers to the memory block, including data, address,

byteena

wren

, and

rden

registers. An output clock controls the data-output registers.

Each memory block port also supports independent clock enables for input and

output registers.

Table 3–5. Cyclone III Device Family Memory Clock Modes

Clocking Mode True Dual-Port

Mode

Simple

Dual-Port

Mode

Single-Port

Mode ROM Mode FIFO Mode

Independent v——v—

Input or output vvvv—

Read or write — v——v

Single-clock vvvvv

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–15

Design Considerations

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Read or Write Clock Mode

Cyclone III device family M9K memory blocks can implement read or write clock

mode for FIFO and simple dual-port memories. In this mode, a write clock controls

the data inputs, write address, and

wren

registers. Similarly, a read clock controls the

data outputs, read address, and

rden

registers. M9K memory blocks support

independent clock enables for both the read and write clocks.

When using read or write mode, if you perform a simultaneous read or write to the

same address location, the output read data is unknown. If you require the output

data to be a known value, use either single-clock mode, input clock mode, or output

clock mode and choose the appropriate read-during-write behavior in the

MegaWizard Plug-In Manager.

Single-Clock Mode

Cyclone III device family M9K memory blocks can implement single-clock mode for

FIFO, ROM, true dual-port, simple dual-port, and single-port memories. In this mode,

you can control all registers of the M9K memory block with a single clock together

with clock enable.

Design Considerations

This section describes designing with M9K memory blocks.

Read-During-Write Operations

“Same-Port Read-During-Write Mode” on page 3–16 and “Mixed-Port Read-During-

Write Mode” on page 3–16 describe the functionality of the various RAM

configurations when reading from an address during a write operation at that same

address.

There are two read-during-write data flows: same-port and mixed-port. Figure 3–14

shows the difference between these flows.

Figure 3–14. Cyclone III Device Family Read-During-Write Data Flow

Port A

data in

Port B

data in

Port A

data out

Port B

data out

Mixed-port

data flow

Same-port

data flow

write_a

read_a

read_b

write_b

3–16 Chapter 3: Memory Blocks in the Cyclone III Device Family

Design Considerations

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Same-Port Read-During-Write Mode

This mode applies to a single-port RAM or the same port of a true dual-port RAM. In

the same port read-during-write mode, there are two output choices: New Data mode

(or flow-through) and Old Data mode. In New Data mode, new data is available on

the rising edge of the same clock cycle on which it was written. In Old Data mode, the

RAM outputs reflect the old data at that address before the write operation proceeds.

When using New Data mode together with

byteena

, you can control the output of the

RAM. When

byteena

is high, the data written into the memory passes to the output

(flow-through). When

byteena

is low, the masked-off data is not written into the

memory and the old data in the memory appears on the outputs. Therefore, the

output can be a combination of new and old data determined by

byteena

Figure 3–15 and Figure 3–16 show sample functional waveforms of same port

read-during-write behavior with both New Data and Old Data modes, respectively.

Mixed-Port Read-During-Write Mode

This mode applies to a RAM in simple or true dual-port mode, which has one port

reading and the other port writing to the same address location with the same clock.

Figure 3–15. Same Port Read-During Write: New Data Mode

Figure 3–16. Same Port Read-During-Write: Old Data Mode

clk_a

wren_a

address_a

data_a

rden_a

q_a (asynch)

a0 a1

ABC D EF

ABC D E F

clk_a

wren_a

address_a

data_a

rden_a

q_a (asynch)

a0 a1

AB C D EF

a0(old data) a1(old data)

AB D E

a} a»

Chapter 3: Memory Blocks in the Cyclone III Device Family 3–17

Design Considerations

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

In this mode, you also have two output choices: Old Data mode or Don't Care mode.

In Old Data mode, a read-during-write operation to different ports causes the RAM

outputs to reflect the old data at that address location. In Don't Care mode, the same

operation results in a “Don't Care” or unknown value on the RAM outputs.

fFor more information about how to implement the desired behavior, refer to the

Internal Memory (RAM and ROM) User Guide.

Figure 3–17 shows a sample functional waveform of mixed port read-during-write

behavior for the Old Data mode. In Don't Care mode, the old data is replaced with

“Don't Care”.

1For mixed-port read-during-write operation with dual clocks, the relationship

between the clocks determines the output behavior of the memory. If you use the

same clock for the two clocks, the output is the old data from the address location.

However, if you use different clocks, the output is unknown during the mixed-port

read-during-write operation. This unknown value may be the old or new data at the

address location, depending on whether the read happens before or after the write.

Conflict Resolution

When you are using M9K memory blocks in true dual-port mode, it is possible to

attempt two write operations to the same memory location (address). Because there is

no conflict resolution circuitry built into M9K memory blocks, this results in unknown

data being written to that location. Therefore, you must implement conflict-resolution

logic external to the M9K memory block.

Figure 3–17. Mixed Port Read-During-Write: Old Data Mode

a (old data) b (old data)

clk_a&b

wren_a

address_a

q_b (asynch)

rden_b

address_b

data_a AB C D EF

ABDE

3–18 Chapter 3: Memory Blocks in the Cyclone III Device Family

Document Revision History

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Power-Up Conditions and Memory Initialization

The M9K memory block outputs of the Cyclone III device family power up to zero

(cleared) regardless of whether the output registers are used or bypassed. All M9K

memory blocks support initialization using a .mif. You can create .mifs in the

Quartus II software and specify their use using the RAM MegaWizard Plug-In

Manager when instantiating memory in your design. Even if memory is

pre-initialized (for example, using a .mif), it still powers up with its outputs cleared.

Only the subsequent read after power up outputs the pre-initialized values.

fFor more information about .mifs, refer to the Internal Memory (RAM and ROM) User

Guide and the Quartus II Handbook.

Power Management

The M9K memory block clock enables of the Cyclone III device family allow you to

control clocking of each M9K memory block to reduce AC power consumption. Use

the

rden

signal to ensure that read operations only occur when necessary. If your

design does not require read-during-write, reduce power consumption by deasserting

the

rden

signal during write operations, or any period when there are no memory

operations. The Quartus II software automatically powers down any unused M9K

memory blocks to save static power.

Document Revision History

Table 3–6 lists the revision history for this document.

Table 3–6. Document Revision History

Date Version Changes

December 2011 2.3 Minor text edits.

December 2009 2.2 Minor changes to the text.

July 2009 2.1 Made minor correction to the part number.

June 2009 2.0

Updated to include Cyclone III LS information

■Updated chapter part number.

■Updated “Introduction” on page 3–1.

■Updated “Overview” on page 3–1.

■Updated Table 3–1 on page 3–2.

■Updated “Control Signals” on page 3–3.

■Updated “Memory Modes” on page 3–8.

■Updated “Simple Dual-Port Mode” on page 3–10.

■Updated “Read or Write Clock Mode” on page 3–16.

October 2008 1.3 Updated chapter to new template.

May 2008 1.2

■Revised the maximum performance of the M9K blocks to 315 MHz in “Introduction” and

“Overview” sections, and in Table 3-1.

■Updated “Address Clock Enable Support” section.

July 2007 1.1 Added chapter TOC and “Referenced Documents” section.

March 2007 1.0 Initial release.

CIII51005-2.3

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

Cyclone III Device Handbook

Volume 1

December 2011

ISO

9001:2008

Registered

4. Embedded Multipliers in the

Cyclone III Device Family

The Cyclone®III device family (Cyclone III and Cyclone III LS devices) includes a

combination of on-chip resources and external interfaces that help to increase

performance, reduce system cost, and lower the power consumption of digital signal

processing (DSP) systems. The Cyclone III device family, either alone or as DSP device

co-processors, are used to improve price-to-performance ratios of DSP systems.

Particular focus is placed on optimizing Cyclone III and Cyclone III LS devices for

applications that benefit from an abundance of parallel processing resources, which

include video and image processing, intermediate frequency (IF) modems used in

wireless communications systems, and multi-channel communications and video

systems.

This chapter contains the following sections:

■“Embedded Multiplier Block Overview” on page 4–2

■“Architecture” on page 4–3

■“Operational Modes” on page 4–5

December 2011

CIII51005-2.3

4–2 Chapter 4: Embedded Multipliers in the Cyclone III Device Family

Embedded Multiplier Block Overview

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Embedded Multiplier Block Overview

Figure 4–1 shows one of the embedded multiplier columns with the surrounding logic

array blocks (LABs). The embedded multiplier is configured as either one 18 × 18

multiplier or two 9 × 9 multipliers. For multiplications greater than 18 × 18, the

Quartus®II software cascades multiple embedded multiplier blocks together. There

are no restrictions on the data width of the multiplier, but the greater the data width,

the slower the multiplication process.

Table 4–1 lists the number of embedded multipliers and the multiplier modes that can

be implemented in the Cyclone III device family.

Figure 4–1. Embedded Multipliers Arranged in Columns with Adjacent LABs

Embedded

Multiplier

Embedded

Multiplier

Column

1 LAB

Row

Table 4–1. Number of Embedded Multipliers in the Cyclone III Device Family

Device Family Device Embedded Multipliers 9 × 9 Multipliers (1) 18 × 18 Multipliers (1)

Cyclone III

EP3C5 23 46 23

EP3C10 23 46 23

EP3C16 56 112 56

EP3C25 66 132 66

EP3C40 126 252 126

EP3C55 156 312 156

EP3C80 244 488 244

EP3C120 288 576 288

Cyclone III LS

EP3CLS70 200 400 200

EP3CLS100 276 552 276

EP3CLS150 320 640 320

EP3CLS200 396 792 396

Note to Table 4–1:

(1) These columns show the number of 9 × 9 or 18 × 18 multipliers for each device. The total number of multipliers for each device is not the sum

of all the multipliers.

Chapter 4: Embedded Multipliers in the Cyclone III Device Family 4–3

Architecture

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

In addition to the embedded multipliers in the Cyclone III device family, you can

implement soft multipliers by using the M9K memory blocks as look-up tables

(LUTs). The LUTs contain partial results from the multiplication of input data with

coefficients that implement variable depth and width high-performance soft

multipliers for low-cost, high-volume DSP applications. The availability of soft

multipliers increases the number of available multipliers in the device.

Table 4–2 lists the total number of multipliers available in the Cyclone III device

family using embedded multipliers and soft multipliers.

fFor more information about M9K memory blocks of the Cyclone III device family,

refer to the Memory Blocks in the Cyclone III Device Family chapter.

fFor more information about soft multipliers, refer to the Implementing Multipliers in

FPGA Devices application note.

Architecture

Each embedded multiplier consists of the following elements:

■Multiplier stage

■Input and output registers

■Input and output interfaces

Table 4–2. Number of Multipliers in the Cyclone III Device Family

Device Family Device Embedded Multipliers Soft Multipliers

(16 ×16) (1) Total Multipliers (2)

Cyclone III

EP3C5 23 — 23

EP3C10 23 46 69

EP3C16 56 56 112

EP3C25 66 66 132

EP3C40 126 126 252

EP3C55 156 260 416

EP3C80 244 305 549

EP3C120 288 432 720

Cyclone III LS

EP3CLS70 200 333 533

EP3CLS100 276 483 759

EP3CLS150 320 666 986

EP3CLS200 396 891 1287

Notes to Table 4–2:

(1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit

coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.

(2) The total number of multipliers may vary, depending on the multiplier mode you use.

AH“

4–4 Chapter 4: Embedded Multipliers in the Cyclone III Device Family

Architecture

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Figure 4–2 shows the multiplier block architecture.

Input Registers

You can send each multiplier input signal into an input register or directly into the

multiplier in 9- or 18-bit sections, depending on the operational mode of the

multiplier. Each multiplier input signal can be sent through a register independently

of other input signals. For example, you can send the multiplier

Data A

signal through

a register and send the

Data B

signal directly to the multiplier.

The following control signals are available to each input register in the embedded

multiplier:

■clock

■clock enable

■asynchronous clear

All input and output registers in a single embedded multiplier are fed by the same

clock, clock enable, and asynchronous clear signals.

Multiplier Stage

The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18

multipliers as well as other multipliers in between these configurations. Depending

on the data width or operational mode of the multiplier, a single embedded multiplier

can perform one or two multiplications in parallel. For multiplier information, refer to

“Operational Modes” on page 4–5.

Each multiplier operand is a unique signed or unsigned number. Two signals,

signa

and

signb

, control an input of a multiplier and determine if the value is signed or

unsigned. If the

signa

signal is high, the

Data A

operand is a signed number. If the

signa

signal is low, the

Data A

operand is an unsigned number.

Figure 4–2. Multiplier Block Architecture

CLRN

ENA

Data A

Data B

aclr

clock

ena

signa

signb

CLRN

ENA

CLRN

ENA Data Out

Embedded Multiplier Block

Output

Input

Chapter 4: Embedded Multipliers in the Cyclone III Device Family 4–5

Operational Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Table 4–3 lists the sign of the multiplication results for the various operand sign

representations. The results of the multiplication are signed if any one of the operands

is a signed value.

Each embedded multiplier block has only one

signa

and one

signb

signal to control

the sign representation of the input data to the block. If the embedded multiplier

block has two 9 × 9 multipliers, the

Data A

input of both multipliers share the same

signa

signal, and the

Data B

input of both multipliers share the same

signb

signal.

You can dynamically change the

signa

and

signb

signals to modify the sign

representation of the input operands at run time. You can send the

signa

and

signb

signals through a dedicated input register. The multiplier offers full precision,

regardless of the sign representation.

1When the

signa

and

signb

signals are unused, the Quartus II software sets the

multiplier to perform unsigned multiplication by default.

Output Registers

You can register the embedded multiplier output using output registers in either

18- or 36-bit sections, depending on the operational mode of the multiplier. The

following control signals are available for each output register in the embedded

multiplier:

■clock

■clock enable

■asynchronous clear

All input and output registers in a single embedded multiplier are fed by the same

clock, clock enable, and asynchronous clear signals.

Operational Modes

You can use an embedded multiplier block in one of two operational modes,

depending on the application needs:

■One 18-bit × 18-bit multiplier

■Up to two 9-bit × 9-bit independent multipliers

Table 4–3. Multiplier Sign Representation

Data A Data B

Result

signa Value Logic Level signb Value Logic Level

Unsigned Low Unsigned Low Unsigned

Unsigned Low Signed High Signed

Signed High Unsigned Low Signed

Signed High Signed High Signed

4–6 Chapter 4: Embedded Multipliers in the Cyclone III Device Family

Operational Modes

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

1You can also use embedded multipliers of the Cyclone III device family to implement

multiplier adder and multiplier accumulator functions, in which the multiplier

portion of the function is implemented using embedded multipliers, and the adder or

accumulator function is implemented in logic elements (LEs).

18-Bit Multipliers

You can configure each embedded multiplier to support a single 18 × 18 multiplier for

input widths of 10 to 18 bits.

Figure 4–3 shows the embedded multiplier configured to support an 18-bit multiplier.

All 18-bit multiplier inputs and results are independently sent through registers. The

multiplier inputs can accept signed integers, unsigned integers, or a combination of

both. Also, you can dynamically change the

signa

and

signb

signals and send these

signals through dedicated input registers.

9-Bit Multipliers

You can configure each embedded multiplier to support two 9 × 9 independent

multipliers for input widths of up to 9 bits.

Figure 4–3. 18-Bit Multiplier Mode

CLRN

ENA

Data A [17..0]

Data B [17..0]

aclr

clock

ena

signa

signb

CLRN

ENA

CLRN

ENA

Data Out [35..0]

18 × 18 Multiplier

Embedded Multiplier

Chapter 4: Embedded Multipliers in the Cyclone III Device Family 4–7

Operational Modes

December 2011 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 4–4 shows the embedded multiplier configured to support two 9-bit

multipliers.

All 9-bit multiplier inputs and results are independently sent through registers. The

multiplier inputs can accept signed integers, unsigned integers, or a combination of

both. Two 9 × 9 multipliers in the same embedded multiplier block share the same

signa

and

signb

signal. Therefore, all the

Data A

inputs feeding the same embedded

multiplier must have the same sign representation. Similarly, all the

Data B

inputs

feeding the same embedded multiplier must have the same sign representation.

Figure 4–4. 9-Bit Multiplier Mode

CLRN

ENA

Data A 0 [8..0]

Data B 0 [8..0]

aclr

clock

ena

signa

signb

CLRN

ENA

CLRN

ENA Data Out 0 [17..0]

9 × 9 Multiplier

Embedded Multiplier

CLRN

ENA

Data A 1 [8..0]

Data B 1 [8..0]

CLRN

ENA

CLRN

ENA Data Out 1 [17..0]

9 × 9 Multiplier

4–8 Chapter 4: Embedded Multipliers in the Cyclone III Device Family

Document Revision History

Cyclone III Device Handbook December 2011 Altera Corporation

Volume 1

Document Revision History

Table 4–4 lists the revision history for this document.

Table 4–4. Document Revision History

Date Version Changes

December 2011 2.3 Minor text edits.

December 2009 2.2 Minor changes to the text.

July 2009 2.1 Made minor correction to the part number.

June 2009 2.0

Updated to include Cyclone III LS information

■Updated chapter part number.

■Updated “Introduction” on page 4–1.

■Updated “Embedded Multiplier Block Overview” on page 4–1.

■Updated Table 4–1 on page 4–2 and Table 4–2 on page 4–2.

■Updated “Input Registers” on page 4–4.

October 2008 1.2 Updated chapter to new template.

July 2007 1.1

Added EP3C120 information.

■Updated “Introduction” section.

■Updated Table 4–1 and Table 4–2.

■Added chapter TOC and “Referenced Documents” section.

March 2007 1.0 Initial release.

CIII51006-4.1

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

Cyclone III Device Handbook

Volume 1

July 2012

ISO

9001:2008

Registered

5. Clock Networks and PLLs in the

Cyclone III Device Family

This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)

with advanced features in the Cyclone®III device family (Cyclone III and

Cyclone III LS devices).

This chapter includes the following sections:

■“Clock Networks” on page 5–1

■“PLLs in the Cyclone III Device Family” on page 5–9

■“Cyclone III Device Family PLL Hardware Overview” on page 5–10

■“Clock Feedback Modes” on page 5–11

■“Hardware Features” on page 5–15

■“Programmable Bandwidth” on page 5–22

■“Phase Shift Implementation” on page 5–22

■“PLL Cascading” on page 5–24

■“PLL Reconfiguration” on page 5–26

■“Spread-Spectrum Clocking” on page 5–33

■“PLL Specifications” on page 5–33

Clock Networks

The Cyclone III device family provides up to 16 dedicated clock pins (

CLK[15..0]

)

that can drive the global clocks (GCLKs). The Cyclone III device family supports four

dedicated clock pins on each side of the device except EP3C5 and EP3C10 devices.

EP3C5 and EP3C10 devices only support four dedicated clock pins on the left and

right sides of the device.

fFor more information about the number of GCLK networks in each device density,

refer to the Cyclone III Device Family Overview chapter.

GCLK Network

GCLKs drive throughout the entire device, feeding all device quadrants. All resources

in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,

and M9K memory blocks) can use GCLKs as clock sources. Use these clock network

resources for control signals, such as clock enables and clears fed by an external pin.

Internal logic can also drive GCLKs for internally generated GCLKs and

asynchronous clears, clock enables, or other control signals with high fan-out.

July 2012

CIII51006-4.1

5–2 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Table 5–1 lists the connectivity of the clock sources to the GCLK networks.

Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 1 of 2)

GCLK Network Clock

Sources

GCLK Networks (1)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK0

DIFFCLK_0p

v—v—v———————————————

CLK1

DIFFCLK_0n

—vv—————————————————

CLK2

DIFFCLK_1p

—v—vv———————————————

CLK3

DIFFCLK_1n

v——v————————————————

CLK4

DIFFCLK_2p

—————v—v—v——————————

CLK5

DIFFCLK_2n

——————vv————————————

CLK6

DIFFCLK_3p

——————v—vv——————————

CLK7

DIFFCLK_3n

—————v——v———————————

CLK8

DIFFCLK_5n

(2) ——————————v—v—v—————

CLK9

DIFFCLK_5p

(2) ———————————vv———————

CLK10

DIFFCLK_4n

(2) ———————————v—vv—————

CLK11

DIFFCLK_4p

(2) ——————————v——v——————

CLK12

DIFFCLK_7n

(2) ———————————————v—v—v

CLK13

DIFFCLK_7p

(2) ————————————————vv——

CLK14

DIFFCLK_6n

(2) ————————————————v—vv

CLK15

DIFFCLK_6p

(2) ———————————————v——v—

PLL1_C0

(3) v——v————————————————

PLL1_C1

(3) —v——v———————————————

PLL1_C2

(3) v—v—————————————————

PLL1_C3

(3) —v—v————————————————

PLL1_C4

(3) ——v—v———————————————

PLL2_C0

(3) —————v——v———————————

PLL2_C1

(3) ——————v——v——————————

PLL2_C2

(3) —————v—v————————————

PLL2_C3

(3) ——————v—v———————————

PLL2_C4

(3) ———————v—v——————————

PLL3_C0

——————————v——v——————

PLL3_C1

———————————v——v—————

PLL3_C2

——————————v—v———————

PLL3_C3

———————————v—v——————

PLL3_C4

————————————v—v—————

PLL4_C0

———————————————v——v—

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–3

Clock Networks

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

PLL4_C1

————————————————v——v

PLL4_C2

———————————————v—v——

PLL4_C3

————————————————v—v—

PLL4_C4

—————————————————v—v

DPCLK0

v———————————————————

DPCLK1

—v——————————————————

DPCLK7

(4)

CDPCLK0

, or

CDPCLK7

(2), (5)

——v—————————————————

DPCLK2

(4)

CDPCLK1

, or

CDPCLK2

(2), (5)

———vv———————————————

DPCLK5

(4)

DPCLK7

(2) —————v——————————————

DPCLK4

(4)

DPCLK6

(2) ——————v—————————————

DPCLK6

(4)

CDPCLK5

, or

CDPCLK6

(2), (5)

———————v————————————

DPCLK3

(4)

CDPCLK4

, or

CDPCLK3

(2), (5)

————————vv——————————

DPCLK8

——————————v—————————

DPCLK11

———————————v————————

DPCLK9

————————————v———————

DPCLK10

—————————————vv—————

DPCLK5

———————————————v————

DPCLK2

————————————————v———

DPCLK4

—————————————————v——

DPCLK3

——————————————————vv

Notes to Table 5–1:

(1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9.

(2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices.

(3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2.

(4) This pin applies only to EP3C5 and EP3C10 devices.

(5) Only one of the two

CDPCLK

pins can feed the clock control block. You can use the other pin as a regular I/O pin.

Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2)

GCLK Network Clock

Sources

GCLK Networks (1)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

5–4 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

If you do not use dedicated clock pins to feed the GCLKs, you can use them as

general-purpose input pins to feed the logic array. However, when using them as

general-purpose input pins, they do not have support for an I/O register and must

use LE-based registers in place of an I/O register.

fFor more information about how to connect the clock and PLL pins, refer to the

Cyclone III Device Family Pin Connection Guidelines on the Altera® website.

Clock Control Block

The clock control block drives GCLKs. Clock control blocks are located on each side of

the device, close to the dedicated clock input pins. GCLKs are optimized for

minimum clock skew and delay.

Table 5–2 lists the sources that can feed the clock control block, which in turn feeds the

GCLKs.

In the Cyclone III device family, dedicated clock input pins, PLL counter outputs,

dual-purpose clock I/O inputs, and internal logic can all feed the clock control block

for each GCLK.

1Normal I/O pins cannot drive the PLL input clock port.

The output from the clock control block in turn feeds the corresponding GCLK. The

GCLK can drive the PLL input if the clock control block inputs are outputs of another

PLL or dedicated clock input pins. The clock control blocks are at the device

periphery; there are a maximum of 20 clock control blocks available per Cyclone III

device family.

The control block has two functions:

■Dynamic GCLK clock source selection (not applicable for

DPCLK

CDPCLK

and

internal logic input)

■GCLK network power down (dynamic enable and disable)

Table 5–2. Clock Control Block Inputs

Input Description

Dedicated clock inputs

Dedicated clock input pins can drive clocks or global signals, such as

synchronous and asynchronous clears, presets, or clock enables onto

given GCLKs.

Dual-purpose clock

(

DPCLK

and

CDPCLK)

I/O input

DPCLK

and

CDPCLK

I/O pins are bidirectional dual function pins that

are used for high fan-out control signals, such as protocol signals,

TRDY

and

IRDY

signals for PCI, via the GCLK. Clock control blocks

that have inputs driven by dual-purpose clock I/O pins are not able to

drive PLL inputs.

PLL outputs PLL counter outputs can drive the GCLK.

Internal logic

You can drive the GCLK through logic array routing to enable internal

logic elements (LEs) to drive a high fan-out, low-skew signal path.

Clock control blocks that have inputs driven by internal logic are not

able to drive PLL inputs.

coo

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–5

Clock Networks

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 5–1 shows the clock control block.

Each PLL generates five clock outputs through the

c[4..0]

counters. Two of these

clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.

fFor more information about how to use the clock control block in the Quartus®II

software, refer to the Clock Control Block (ALTCLKCTRL) Megafunction User Guide.

Figure 5–1. Clock Control Block

Notes to Figure 5–1:

(1) The

clkswitch

signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The

output of the multiplexer is the input clock (fIN) for the PLL.

(2) The

clkselect[1..0]

signals are fed by internal logic and is used to dynamically select the clock source for the GCLK when the device is in user

mode.

(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.

(4) You can use internal logic to enable or disable the GCLK in user mode.

CLKSWITCH (1)

Static Clock Select (3)

Static Clock

Select (3)

Internal Logic

Clock Control Block

DPCLK or CDPCLK

CLKSELECT[1..0] (2) Internal Logic (4)

inclk1

inclk0

CLK[n + 3]

CLK[n + 2]

CLK[n + 1]

CLK[n]

fIN

PLL

Global

Clock

Enable/

Disable

U Uj U . ,, ,,,,,,,,,, (31/, ,,,,,,,, W‘ A G b 6 L 1 [ V 4 LL: ,,,,, ,‘ > D D K5 K4

5–6 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

GCLK Network Clock Source Generation

Figure 5–2 shows Cyclone III device family PLLs, clock inputs, and clock control

block location for different device densities.

Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family (1)

Notes to Figure 5–2:

(1) There are five clock control blocks on each side.

(2) Only one of the corner

CDPCLK

pins in each corner can feed the clock control block at a time. You can use the other

CDPCLK

pins as

general-purpose I/O pins.

(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.

PLL

(2)(2)

(2) (2)

CDPCLK7

CDPCLK0

CDPCLK1

DPCLK1

DPCLK[11.10] DPCLK[9..8]

CLK[11..8]CDPCLK6

DPCLK0

CLK[3..0]

Clock Control

Block (1)

GCLK[19..0]

CDPCLK5

DPCLK7

CLK[7..4]

DPCLK6

CDPCLK4

CDPCLK2

DPCLK[3..2]

CLK[15..12]

DPCLK[5..4]

CDPCLK3

Clock Control

Block (1)

(3)

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–7

Clock Networks

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

The inputs to the five clock control blocks on each side must be chosen from among

the following clock sources:

■Four clock input pins

■Five PLL counter outputs

■Two

DPCLK

pins and two

CDPCLK

pins from both the left and right sides, and four

DPCLK

pins and two

CDPCLK

pins from both the top and bottom

■Five signals from internal logic

From the clock sources listed above, only two clock input pins, two PLL clock outputs,

one

DPCLK

CDPCLK

pin, and one source from internal logic can drive into any given

clock control block, as shown in Figure 5–1 on page 5–5.

Out of these five inputs to any clock control block, the two clock input pins and two

PLL outputs are dynamically selected to feed a GCLK. The clock control block

supports static selection of the signal from internal logic.

Figure 5–3 shows a simplified version of the five clock control blocks on each side of

the Cyclone III device family periphery.

GCLK Network Power Down

You can disable the Cyclone III device family GCLK (power down) by using both

static and dynamic approaches. In the static approach, configuration bits are set in the

configuration file generated by the Quartus II software, which automatically disables

unused GCLKs. The dynamic clock enable or disable feature allows internal logic to

control clock enable or disable of the GCLKs in the Cyclone III device family.

When a clock network is disabled, all the logic fed by the clock network is in an

off-state, thereby reducing the overall power consumption of the device. This function

is independent of the PLL and is applied directly on the clock network, as shown in

Figure 5–1 on page 5–5.

You can set the input clock sources and the

clkena

signals for the GCLK multiplexers

through the Quartus II software using the ALTCLKCTRL megafunction.

fFor more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction

User Guide.

Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family (1)

Note to Figure 5–3:

(1) The left and right sides of the device have two

DPCLK

pins; the top and bottom of the device have four

DPCLK

pins.

5GCLK

Clock Input Pins 4

DPCLK

Internal Logic

Clock

Control

Block

PLL Outputs

2 or 4

CDPCLK 2

Five Clock Control

Blocks on Each Side

of the Device

5–8 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

clkena Signals

The Cyclone III device family supports

clkena

signals at the GCLK network level.

This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the

output clock, the PLL does not need a resynchronization or re-lock period because the

circuit gates off the clock at the clock network level. In addition, the PLL can remain

locked independent of the

clkena

signals because the loop-related counters are not

affected.

Figure 5–4 shows how to implement the

clkena

signal.

1The

clkena

circuitry controlling the output C0 of the PLL to an output pin is

implemented with two registers instead of a single register, as shown in Figure 5–4.

Figure 5–5 shows the waveform example for a clock output enable. The

clkena

signal

is sampled on the falling edge of the clock (

clkin

1This feature is useful for applications that require low power or sleep mode.

The

clkena

signal can also disable clock outputs if the system is not tolerant to

frequency overshoot during PLL resynchronization.

Figure 5–4. clkena Implementation

clkena clkena_out

clk_out

clkin

Figure 5–5. clkena Implementation: Output Enable

clkin

clkena

clk_out

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–9

PLLs in the Cyclone III Device Family

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Altera recommends using the

clkena

signals when switching the clock source to the

PLLs or the GCLK. The recommended sequence is:

1. Disable the primary output clock by deasserting the

clkena

signal.

2. Switch to the secondary clock using the dynamic select signals of the clock control

block.

3. Allow some clock cycles of the secondary clock to pass before reasserting the

clkena

signal. The exact number of clock cycles you must wait before enabling the

secondary clock is design-dependent. You can build custom logic to ensure glitch-

free transition when switching between different clock sources.

PLLs in the Cyclone III Device Family

The Cyclone III device family offers up to four PLLs that provide robust clock

management and synthesis for device clock management, external system clock

management, and high-speed I/O interfaces.

fFor more information about the number of PLLs in each device density, refer to the

Cyclone III Device Family Overview chapter.

The Cyclone III device family PLLs have the same core analog structure.

Table 5–3 lists the features available in the Cyclone III device family PLLs.

Table 5–3. Cyclone III Device Family PLL Hardware Features

Hardware Features Availability

C (output counters) 5

M, N, C counter sizes 1 to 512 (1)

Dedicated clock outputs 1 single-ended or 1 differential pair

Clock input pins 4 single-ended or 2 differential pairs

Spread-spectrum input clock tracking v (2)

PLL cascading Through GCLK

Compensation modes Source-Synchronous Mode, No Compensation

Mode, Normal Mode, and Zero Delay Buffer Mode

Phase shift resolution Down to 96-ps increments (3)

Programmable duty cycle v

Output counter cascading v

Input clock switchover v

User mode reconfiguration v

Loss of lock detection v

Notes to Table 5–3:

(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a

non-50% duty cycle, the post-scale counters range from 1 through 256.

(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.

(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For

degree increments, the Cyclone III device family can shift all output frequencies in increments of at least 45°.

Smaller degree increments are possible depending on the frequency and divide parameters.

5–10 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Cyclone III Device Family PLL Hardware Overview

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Cyclone III Device Family PLL Hardware Overview

This section gives a hardware overview of the Cyclone III device family PLL.

Figure 5–6 shows a simplified block diagram of the major components of the PLL of

the Cyclone III device family.

1The VCO post-scale counter K is used to divide the supported VCO range by two. The

VCO frequency reported by the Quartus II software in the PLL summary section of

the compilation report takes into consideration the VCO post-scale counter value.

Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is

lower than the fVCO specification specified in the Cyclone III Device Data Sheet and

Cyclone III LS Device Data Sheet chapters.

External Clock Outputs

Each PLL of the Cyclone III device family supports one single-ended clock output or

one differential clock output. Only the C0 output counter can feed the dedicated

external clock outputs, as shown in Figure 5–7, without going through the GCLK.

Other output counters can feed other I/O pins through the GCLK.

Figure 5–6. Cyclone III Device Family PLL Block Diagram (1)

Notes to Figure 5–6:

(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.

(2) This is the VCO post-scale counter K.

(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another

PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.

Clock

Switchover

Block

inclk0

inclk1

Clock inputs

from pins

GCLK

pfdena

clkswitch

clkbad0

clkbad1

activeclock

PFD

LOCK

circuit

lock

÷n CP LF VCO ÷2

(2)

÷C0

÷C1

÷C2

÷C3

÷C4

÷M

PLL

output

mux GCLKs

External cloc

output

GCLK

networks

no compensation;

ZDB mode

source-synchronous;

normal mode

VCO

Range

Detector

VCOOVRR

VCOUNDR

(3)

(1)

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–11

Clock Feedback Modes

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Figure 5–7 shows the external clock outputs for PLLs.

Each pin of a differential output pair is 180° out of phase. The Quartus II software

places the NOT gate in your design into the I/O element to implement 180° phase

with respect to the other pin in the pair. The clock output pin pairs support the same

I/O standards as standard output pins (in the top and bottom banks) as well as LVDS,

LVPECL, differential HSTL, and differential SSTL.

fTo determine which I/O standards are supported by the PLL clock input and output

pins, refer to the I/O Features in the Cyclone III Device Family chapter.

Cyclone III device family PLLs can drive out to any regular I/O pin through the

GCLK. You can also use the external clock output pins as general purpose I/O pins if

external PLL clocking is not required.

Clock Feedback Modes

Cyclone III device family PLLs support up to four different clock feedback modes.

Each mode allows clock multiplication and division, phase shifting, and

programmable duty cycle.

Figure 5–7. External Clock Outputs for PLLs

Notes to Figure 5–7:

(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.

(2)

PLL#_CLKOUTp

and

PLL#_CLKOUTn

pins are dual-purpose I/O pins that you can use as one single-ended or one

differential clock output.

PLL #

clkena 1

(1)

clkena 0

(1)

PLL #_CLKOUTp

(2)

PLL #_CLKOUTn

(2)

5–12 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Feedback Modes

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

1Input and output delays are fully compensated by the PLL only when you are using

the dedicated clock input pins associated with a given PLL as the clock sources. For

example, when using PLL1 in normal mode, the clock delays from the input pin to the

PLL and the PLL clock output-to-destination register are fully compensated, provided

that the clock input pin is one of the following four pins:

■

CLK0

■

CLK1

■

CLK2

■

CLK3

When driving the PLL using the GCLK network, the input and output delays may not

be fully compensated in the Quartus II software.

Source-Synchronous Mode

If the data and clock arrive at the same time at the input pins, the phase relationship

between the data and clock remains the same at the data and clock ports of any I/O

element input register.

Figure 5–8 shows an example waveform of the data and clock in this mode. Use this

mode for source-synchronous data transfers. Data and clock signals at the I/O

element experience similar buffer delays as long as the same I/O standard is used.

Source-synchronous mode compensates for delay of the clock network used,

including any difference in the delay between the following two paths:

■Data pin to I/O element register input

■Clock input pin to the PLL phase-frequency detector (PFD) input

1Set the input pin to the register delay chain in the I/O element to zero in the

Quartus II software for all data pins clocked by a source-synchronous mode PLL.

Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II

software.

Figure 5–8. Phase Relationship Between Data and Clock in Source-Synchronous Mode

Data pin

PLL reference

clock at input pin

Data at register

Clock at register

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–13

Clock Feedback Modes

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

No Compensation Mode

In no compensation mode, the PLL does not compensate for any clock networks. This

provides better jitter performance because clock feedback into the PFD does not pass

through as much circuitry. Both the PLL internal and external clock outputs are

phase-shifted with respect to the PLL clock input.

Figure 5–9 shows a waveform example of the phase relationship of the PLL clock in

this mode.

Normal Mode

An internal clock in normal mode is phase-aligned to the input clock pin. The external

clock output pin has a phase delay relative to the clock input pin if connected in this

mode. The Quartus II software timing analyzer reports any phase difference between

the two. In normal mode, the PLL fully compensates the delay introduced by the

GCLK network.

Figure 5–9. Phase Relationship Between PLL Clocks in No Compensation Mode

Notes to Figure 5–9:

(1) Internal clocks fed by the PLL are phase-aligned to each other.

(2) The PLL clock outputs can lead or lag the PLL input clocks.

PLL Reference

Clock at the Input Pin

PLL Clock at the

(1), (2)

External PLL Clock

Outputs

(2)

Phase Aligned

5–14 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Feedback Modes

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Figure 5–10 shows a waveform example of the phase relationship of the PLL clocks in

this mode.

Zero Delay Buffer Mode

In zero delay buffer (ZDB) mode, the external clock output pin is phase-aligned with

the clock input pin for zero delay through the device. When using this mode, use the

same I/O standard on the input clock and output clocks to guarantee clock alignment

at the input and output pins.

Figure 5–11 shows an example waveform of the phase relationship of the PLL clocks

in ZDB mode.

Figure 5–10. Phase Relationship Between PLL Clocks in Normal Mode

Note to Figure 5–10:

(1) The external clock output can lead or lag the PLL internal clock signals.

PLL Reference

Clock at the Input pin

PLL Clock at the

External PLL Clock

Outputs

(1)

Phase Aligned

Figure 5–11. Phase Relationship Between PLL Clocks in ZDB Mode

PLL Reference Clock

at the Input Pin

PLL Clock

at the Register Clock Port

External PLL Clock Output

at the Output Pin

Phase Aligned

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–15

Hardware Features

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

Hardware Features

Cyclone III device family PLLs support several features for general-purpose clock

management. This section discusses clock multiplication and division

implementation, phase shifting implementations, and programmable duty cycles.

Clock Multiplication and Division

Each Cyclone III device family PLL provides clock synthesis for PLL output ports

using M/(N*post-scale counter) scaling factors. The input clock is divided by a

pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop

drives the VCO to match fIN (M/N). Each output port has a unique post-scale counter

that divides down the high-frequency VCO. For multiple PLL outputs with different

frequencies, the VCO value is the least common multiple of the output frequencies

that meets its frequency specifications. For example, if output frequencies required

from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz

(the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale

counters scale down the VCO frequency for each output port.

There is one pre-scale counter, N, and one multiply counter, M, per PLL, with a range

of 1 to 512 for both M and N. The N counter does not use duty cycle control because

the purpose of this counter is only to calculate frequency division. There are five

generic post-scale counters per PLL that can feed GCLKs or external clock outputs.

These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The

post-scale counters range from 1 to 256 with any non-50% duty cycle setting. The sum

of the high/low count values chosen for a design selects the divide value for a given

counter.

The Quartus II software automatically chooses the appropriate scaling factors

according to the input frequency, multiplication, and division values entered into the

ALTPLL megafunction.

1Phase alignment between output counters are determined using the tPLL_PSERR

specification.

E: E

5–16 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Hardware Features

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

Post-Scale Counter Cascading

Cyclone III device family PLLs support post-scale counter cascading to create

counters larger than 512. This is implemented by feeding the output of one C counter

into the input of the next C counter, as shown in Figure 5–12.

When cascading counters to implement a larger division of the high-frequency VCO

clock, the cascaded counters behave as one counter with the product of the individual

counter settings.

For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.

1Post-scale counter cascading is automatically set by the Quartus II software in the

configuration file. Post-scale counter cascading cannot be performed using the PLL

reconfiguration.

Programmable Duty Cycle

The programmable duty cycle allows PLLs to generate clock outputs with a variable

duty cycle. This feature is supported on the PLL post-scale counters. You can achieve

the duty cycle setting by a low and high time count setting for the post-scale counters.

The Quartus II software uses the frequency input and the required multiply or divide

rate to determine the duty cycle choices. The post-scale counter value determines the

precision of the duty cycle. The precision is defined by 50% divided by the post-scale

counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty

cycle choices between 5 to 90%.

Combining the programmable duty cycle with programmable phase shift allows the

generation of precise non-overlapping clocks.

Figure 5–12. Counter Cascading

VCO Output

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–17

Hardware Features

July 2012 Altera Corporation Cyclone III Device Handbook

Volume 1

PLL Control Signals

You can use the following three signals to observe and control the PLL operation and

resynchronization.

pfdena

Use the

pfdena

signal to maintain the last locked frequency so that your system has

time to store its current settings before shutting down. The

pfdena

signal controls the

PFD output with a programmable gate. If you disable the PFD, the VCO operates at

its last set value of control voltage and frequency with some long-term drift to a lower

frequency.

areset

The

areset

signal is the reset or resynchronization input for each PLL. The device

input pins or internal logic can drive these input signals. When driven high, the PLL

counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is

then set back to its nominal setting. When driven low again, the PLL resynchronizes

to its input as it re-locks.

You must include the

areset

signal in your designs if one of the following conditions

is true:

■PLL reconfiguration or clock switchover enabled in your design

■Phase relationships between the PLL input clock and output clocks must be

maintained after a loss-of-lock condition

1If the input clock to the PLL is toggling or unstable upon power up, assert the

areset

signal after the input clock is stable and within specifications.

locked

The

locked

output indicates that the PLL has locked onto the reference clock and the

PLL clock outputs are operating at the desired phase and frequency set in the

Quartus II MegaWizard™ Plug-in Manager.

1Altera recommends that you use the

areset

and

locked

signals in your designs to

control and observe the status of your PLL.

This implementation is illustrated in Figure 5–13.

Figure 5–13. Locked Signal Implementation

OFF

PLL

locked

areset

VCC

5–18 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Hardware Features

Cyclone III Device Handbook July 2012 Altera Corporation

Volume 1

If you use the SignalTap®II tool to probe the

locked

signal before the D flip-flop, the

locked

signal goes low only when

areset

is deasserted. If the

areset

signal is not

enabled, the extra logic is not implemented in the ALTPLL megafunction.

fFor more information about the PLL control signals, refer to the Phase-Locked Loop

(ALTPLL) Megafunction User Guide.

Clock Switchover

The clock switchover feature allows the PLL to switch between two reference input

clocks. Use this feature for clock redundancy or for a dual-clock domain application,