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KL02 Sub-Family Reference Manual
Supports: MKL02Z32CAF4R and KKL02Z32CAF4R
Document Number: KL02P20M48SF0RM
Rev 2.1, July 2013
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................25
1.1.1 Purpose...........................................................................................................................................................25
1.1.2 Audience........................................................................................................................................................25
1.2 Conventions..................................................................................................................................................................25
1.2.1 Numbering systems........................................................................................................................................25
1.2.2 Typographic notation.....................................................................................................................................26
1.2.3 Special terms..................................................................................................................................................26
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................27
2.2 Kinetis L series.............................................................................................................................................................27
2.3 KL02 sub-family introduction......................................................................................................................................30
2.4 Module functional categories........................................................................................................................................31
2.4.1 ARM Cortex-M0+ core modules...................................................................................................................32
2.4.2 System modules.............................................................................................................................................32
2.4.3 Memories and memory interfaces..................................................................................................................33
2.4.4 Clocks.............................................................................................................................................................33
2.4.5 Security and integrity modules......................................................................................................................33
2.4.6 Analog modules.............................................................................................................................................34
2.4.7 Timer modules...............................................................................................................................................34
2.4.8 Communication interfaces.............................................................................................................................34
2.4.9 Human-machine interfaces............................................................................................................................35
2.5 Orderable part numbers.................................................................................................................................................35
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................37
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3.2 Module to module interconnects...................................................................................................................................37
3.2.1 Interconnection overview...............................................................................................................................37
3.2.2 Analog reference options...............................................................................................................................38
3.3 Core modules................................................................................................................................................................39
3.3.1 ARM Cortex-M0+ core configuration...........................................................................................................39
3.3.2 Nested vectored interrupt controller (NVIC) configuration...........................................................................42
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration..............................................................45
3.4 System modules............................................................................................................................................................46
3.4.1 SIM configuration..........................................................................................................................................46
3.4.2 System mode controller (SMC) configuration...............................................................................................47
3.4.3 PMC configuration.........................................................................................................................................48
3.4.4 MCM configuration.......................................................................................................................................48
3.4.5 Crossbar-light switch configuration...............................................................................................................49
3.4.6 Peripheral bridge configuration.....................................................................................................................51
3.4.7 Computer operating properly (COP) watchdog configuration......................................................................52
3.5 Clock modules..............................................................................................................................................................54
3.5.1 MCG configuration........................................................................................................................................54
3.5.2 OSC configuration.........................................................................................................................................55
3.6 Memories and memory interfaces.................................................................................................................................56
3.6.1 Flash memory configuration..........................................................................................................................56
3.6.2 Flash memory controller configuration..........................................................................................................58
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3.6.3 SRAM configuration......................................................................................................................................59
3.7 Analog...........................................................................................................................................................................61
3.7.1 12-bit SAR ADC configuration.....................................................................................................................61
3.7.2 CMP configuration.........................................................................................................................................63
3.8 Timers...........................................................................................................................................................................66
3.8.1 Timer/PWM module configuration................................................................................................................66
3.8.2 Low-power timer configuration.....................................................................................................................68
3.9 Communication interfaces............................................................................................................................................70
3.9.1 SPI configuration...........................................................................................................................................70
3.9.2 I2C configuration...........................................................................................................................................71
3.9.3 UART configuration......................................................................................................................................72
3.10 Human-machine interfaces (HMI)................................................................................................................................73
3.10.1 GPIO configuration........................................................................................................................................73
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................77
4.2 System memory map.....................................................................................................................................................77
4.3 Flash memory map........................................................................................................................................................78
4.3.1 Alternate non-volatile IRC user trim description...........................................................................................78
4.4 SRAM memory map.....................................................................................................................................................79
4.5 Bit Manipulation Engine...............................................................................................................................................79
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................79
4.6.1 Read-after-write sequence and required serialization of memory operations................................................80
4.6.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................80
4.6.3 Modules restricted access in user mode.........................................................................................................84
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................84
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................85
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5.2 Programming model......................................................................................................................................................85
5.3 High-level device clocking diagram.............................................................................................................................85
5.4 Clock definitions...........................................................................................................................................................86
5.4.1 Device clock summary...................................................................................................................................87
5.5 Internal clocking requirements.....................................................................................................................................88
5.5.1 Clock divider values after reset......................................................................................................................89
5.5.2 VLPR mode clocking.....................................................................................................................................89
5.6 Clock gating..................................................................................................................................................................90
5.7 Module clocks...............................................................................................................................................................90
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................91
5.7.2 COP clocking.................................................................................................................................................91
5.7.3 LPTMR clocking............................................................................................................................................92
5.7.4 TPM clocking.................................................................................................................................................92
5.7.5 UART clocking..............................................................................................................................................93
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................95
6.2 Reset..............................................................................................................................................................................95
6.2.1 Power-on reset (POR)....................................................................................................................................95
6.2.2 System reset sources......................................................................................................................................96
6.2.3 MCU resets....................................................................................................................................................99
6.2.4 RESET_b pin ................................................................................................................................................100
6.2.5 Debug resets...................................................................................................................................................100
6.3 Boot...............................................................................................................................................................................101
6.3.1 Boot sources...................................................................................................................................................101
6.3.2 FOPT boot options.........................................................................................................................................101
6.3.3 Boot sequence................................................................................................................................................103
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Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................105
7.2 Clocking modes............................................................................................................................................................105
7.2.1 Partial Stop.....................................................................................................................................................105
7.2.2 Compute Operation........................................................................................................................................106
7.2.3 Peripheral Doze..............................................................................................................................................107
7.2.4 Clock gating...................................................................................................................................................107
7.3 Power modes.................................................................................................................................................................108
7.4 Entering and exiting power modes...............................................................................................................................109
7.5 Module operation in low-power modes........................................................................................................................110
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................113
8.2 Flash security................................................................................................................................................................113
8.3 Security interactions with other modules......................................................................................................................113
8.3.1 Security interactions with Debug...................................................................................................................114
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................115
9.2 Debug port pin descriptions..........................................................................................................................................115
9.3 SWD status and control registers..................................................................................................................................116
9.3.1 MDM-AP Control Register............................................................................................................................117
9.3.2 MDM-AP Status Register..............................................................................................................................118
9.4 Debug resets..................................................................................................................................................................120
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................120
9.6 Debug in low-power modes..........................................................................................................................................121
9.7 Debug and security.......................................................................................................................................................122
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Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................123
10.2 Signal multiplexing integration....................................................................................................................................123
10.2.1 Port control and interrupt module features....................................................................................................124
10.2.2 Clock gating...................................................................................................................................................125
10.2.3 Signal multiplexing constraints......................................................................................................................125
10.3 Pinout............................................................................................................................................................................125
10.3.1 KL02 signal multiplexing and pin assignments.............................................................................................125
10.3.2 KL02 pinouts..................................................................................................................................................126
10.4 Module Signal Description Tables................................................................................................................................127
10.4.1 Core modules.................................................................................................................................................127
10.4.2 System modules.............................................................................................................................................127
10.4.3 Clock modules................................................................................................................................................128
10.4.4 Memories and memory interfaces..................................................................................................................128
10.4.5 Analog............................................................................................................................................................128
10.4.6 Timer Modules...............................................................................................................................................129
10.4.7 Communication interfaces.............................................................................................................................129
10.4.8 Human-machine interfaces (HMI).................................................................................................................130
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................131
11.2 Overview.......................................................................................................................................................................131
11.2.1 Features..........................................................................................................................................................131
11.2.2 Modes of operation........................................................................................................................................132
11.3 External signal description............................................................................................................................................132
11.4 Detailed signal description............................................................................................................................................133
11.5 Memory map and register definition.............................................................................................................................133
11.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................136
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11.5.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................138
11.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................139
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)..............................................................................................139
11.6 Functional description...................................................................................................................................................140
11.6.1 Pin control......................................................................................................................................................140
11.6.2 Global pin control..........................................................................................................................................141
11.6.3 External interrupts..........................................................................................................................................141
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................143
12.1.1 Features..........................................................................................................................................................143
12.2 Memory map and register definition.............................................................................................................................143
12.2.1 System Options Register 2 (SIM_SOPT2)....................................................................................................144
12.2.2 System Options Register 4 (SIM_SOPT4)....................................................................................................145
12.2.3 System Options Register 5 (SIM_SOPT5)....................................................................................................147
12.2.4 System Options Register 7 (SIM_SOPT7)....................................................................................................148
12.2.5 System Device Identification Register (SIM_SDID).....................................................................................149
12.2.6 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................151
12.2.7 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................153
12.2.8 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................154
12.2.9 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................155
12.2.10 Flash Configuration Register 1 (SIM_FCFG1).............................................................................................157
12.2.11 Flash Configuration Register 2 (SIM_FCFG2).............................................................................................158
12.2.12 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................159
12.2.13 Unique Identification Register Mid Low (SIM_UIDML).............................................................................159
12.2.14 Unique Identification Register Low (SIM_UIDL)........................................................................................160
12.2.15 COP Control Register (SIM_COPC).............................................................................................................160
12.2.16 Service COP Register (SIM_SRVCOP)........................................................................................................161
12.3 Functional description...................................................................................................................................................162
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Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................163
13.2 Modes of operation.......................................................................................................................................................163
13.3 Memory map and register descriptions.........................................................................................................................165
13.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................165
13.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................167
13.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................168
13.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................169
13.4 Functional description...................................................................................................................................................170
13.4.1 Power mode transitions..................................................................................................................................170
13.4.2 Power mode entry/exit sequencing................................................................................................................173
13.4.3 Run modes......................................................................................................................................................175
13.4.4 Wait modes....................................................................................................................................................176
13.4.5 Stop modes.....................................................................................................................................................177
13.4.6 Debug in low power modes...........................................................................................................................179
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................181
14.2 Features.........................................................................................................................................................................181
14.3 Low-voltage detect (LVD) system................................................................................................................................181
14.3.1 LVD reset operation.......................................................................................................................................182
14.3.2 LVD interrupt operation.................................................................................................................................182
14.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................182
14.4 I/O retention..................................................................................................................................................................183
14.5 Memory map and register descriptions.........................................................................................................................183
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................184
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................185
14.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................186
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Chapter 15
Reset Control Module (RCM)
15.1 Introduction...................................................................................................................................................................189
15.2 Reset memory map and register descriptions...............................................................................................................189
15.2.1 System Reset Status Register 0 (RCM_SRS0)..............................................................................................189
15.2.2 System Reset Status Register 1 (RCM_SRS1)..............................................................................................191
15.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................192
15.2.4 Reset Pin Filter Width register (RCM_RPFW).............................................................................................193
Chapter 16
Bit Manipulation Engine (BME)
16.1 Introduction...................................................................................................................................................................195
16.1.1 Overview........................................................................................................................................................196
16.1.2 Features..........................................................................................................................................................196
16.1.3 Modes of operation........................................................................................................................................197
16.2 External signal description............................................................................................................................................197
16.3 Memory map and register definition.............................................................................................................................198
16.4 Functional description...................................................................................................................................................198
16.4.1 BME decorated stores....................................................................................................................................198
16.4.2 BME decorated loads.....................................................................................................................................205
16.4.3 Additional details on decorated addresses and GPIO accesses......................................................................211
16.5 Application information................................................................................................................................................212
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................215
17.1.1 Features..........................................................................................................................................................215
17.2 Memory map/register descriptions...............................................................................................................................215
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................216
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)..............................................................217
17.2.3 Platform Control Register (MCM_PLACR)..................................................................................................217
17.2.4 Compute Operation Control Register (MCM_CPO).....................................................................................220
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Chapter 18
Micro Trace Buffer (MTB)
18.1 Introduction...................................................................................................................................................................223
18.1.1 Overview........................................................................................................................................................223
18.1.2 Features..........................................................................................................................................................226
18.1.3 Modes of operation........................................................................................................................................227
18.2 External signal description............................................................................................................................................227
18.3 Memory map and register definition.............................................................................................................................228
18.3.1 MTB_RAM Memory Map.............................................................................................................................228
18.3.2 MTB_DWT Memory Map.............................................................................................................................240
18.3.3 System ROM Memory Map...........................................................................................................................251
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................257
19.1.1 Features..........................................................................................................................................................257
19.2 Memory Map / Register Definition...............................................................................................................................257
19.3 Functional Description..................................................................................................................................................258
19.3.1 General operation...........................................................................................................................................258
19.3.2 Arbitration......................................................................................................................................................259
19.4 Initialization/application information...........................................................................................................................260
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................261
20.1.1 Features..........................................................................................................................................................261
20.1.2 General operation...........................................................................................................................................261
20.2 Functional description...................................................................................................................................................262
20.2.1 Access support...............................................................................................................................................262
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Chapter 21
Multipurpose Clock Generator (MCG)
21.1 Introduction...................................................................................................................................................................263
21.1.1 Features..........................................................................................................................................................263
21.1.2 Modes of Operation.......................................................................................................................................266
21.2 External Signal Description..........................................................................................................................................266
21.3 Memory Map/Register Definition.................................................................................................................................266
21.3.1 MCG Control 1 Register (MCG_C1).............................................................................................................266
21.3.2 MCG Control 2 Register (MCG_C2).............................................................................................................267
21.3.3 MCG Control 3 Register (MCG_C3).............................................................................................................269
21.3.4 MCG Control 4 Register (MCG_C4).............................................................................................................269
21.3.5 MCG Control 6 Register (MCG_C6).............................................................................................................271
21.3.6 MCG Status Register (MCG_S)....................................................................................................................271
21.3.7 MCG Status and Control Register (MCG_SC)..............................................................................................272
21.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)..............................................................274
21.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)................................................................274
21.4 Functional Description..................................................................................................................................................274
21.4.1 MCG mode state diagram..............................................................................................................................274
21.4.2 Low Power Bit Usage....................................................................................................................................278
21.4.3 MCG Internal Reference Clocks....................................................................................................................278
21.4.4 External Reference Clock..............................................................................................................................279
21.4.5 MCG Fixed frequency clock .........................................................................................................................279
21.4.6 MCG Auto TRIM (ATM)..............................................................................................................................279
21.5 Initialization / Application information........................................................................................................................281
21.5.1 MCG module initialization sequence.............................................................................................................281
21.5.2 Using a 32.768 kHz reference........................................................................................................................283
21.5.3 MCG mode switching....................................................................................................................................284
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Chapter 22
Oscillator (OSC)
22.1 Introduction...................................................................................................................................................................287
22.2 Features and Modes......................................................................................................................................................287
22.3 Block Diagram..............................................................................................................................................................288
22.4 OSC Signal Descriptions..............................................................................................................................................288
22.5 External Crystal / Resonator Connections....................................................................................................................289
22.6 External Clock Connections.........................................................................................................................................290
22.7 Memory Map/Register Definitions...............................................................................................................................291
22.7.1 OSC Memory Map/Register Definition.........................................................................................................291
22.8 Functional Description..................................................................................................................................................292
22.8.1 OSC Module States........................................................................................................................................292
22.8.2 OSC Module Modes.......................................................................................................................................294
22.8.3 Counter...........................................................................................................................................................295
22.8.4 Reference Clock Pin Requirements...............................................................................................................295
22.9 Reset..............................................................................................................................................................................296
22.10 Low Power Modes Operation.......................................................................................................................................296
22.11 Interrupts.......................................................................................................................................................................296
Chapter 23
Flash Memory Controller (FMC)
23.1 Introduction...................................................................................................................................................................297
23.1.1 Overview........................................................................................................................................................297
23.1.2 Features..........................................................................................................................................................297
23.2 Modes of operation.......................................................................................................................................................298
23.3 External signal description............................................................................................................................................298
23.4 Memory map and register descriptions.........................................................................................................................298
23.5 Functional description...................................................................................................................................................298
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Chapter 24
Flash Memory Module (FTFA)
24.1 Introduction...................................................................................................................................................................301
24.1.1 Features..........................................................................................................................................................302
24.1.2 Block Diagram...............................................................................................................................................302
24.1.3 Glossary.........................................................................................................................................................303
24.2 External Signal Description..........................................................................................................................................304
24.3 Memory Map and Registers..........................................................................................................................................304
24.3.1 Flash Configuration Field Description...........................................................................................................304
24.3.2 Program Flash IFR Map.................................................................................................................................305
24.3.3 Register Descriptions.....................................................................................................................................306
24.4 Functional Description..................................................................................................................................................315
24.4.1 Flash Protection..............................................................................................................................................315
24.4.2 Interrupts........................................................................................................................................................315
24.4.3 Flash Operation in Low-Power Modes..........................................................................................................316
24.4.4 Functional Modes of Operation.....................................................................................................................317
24.4.5 Flash Reads and Ignored Writes....................................................................................................................317
24.4.6 Read While Write (RWW).............................................................................................................................317
24.4.7 Flash Program and Erase................................................................................................................................317
24.4.8 Flash Command Operations...........................................................................................................................317
24.4.9 Margin Read Commands...............................................................................................................................322
24.4.10 Flash Command Description..........................................................................................................................323
24.4.11 Security..........................................................................................................................................................336
24.4.12 Reset Sequence..............................................................................................................................................338
Chapter 25
Analog-to-Digital Converter (ADC)
25.1 Introduction...................................................................................................................................................................339
25.1.1 Features..........................................................................................................................................................339
25.1.2 Block diagram................................................................................................................................................340
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25.2 ADC signal descriptions...............................................................................................................................................341
25.2.1 Analog Power (VDDA).................................................................................................................................342
25.2.2 Analog Ground (VSSA).................................................................................................................................342
25.2.3 Analog Channel Inputs (ADx).......................................................................................................................342
25.3 Memory map and register definitions...........................................................................................................................342
25.3.1 ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................343
25.3.2 ADC Configuration Register 1 (ADCx_CFG1).............................................................................................347
25.3.3 ADC Configuration Register 2 (ADCx_CFG2).............................................................................................348
25.3.4 ADC Data Result Register (ADCx_Rn).........................................................................................................349
25.3.5 Compare Value Registers (ADCx_CVn).......................................................................................................350
25.3.6 Status and Control Register 2 (ADCx_SC2)..................................................................................................351
25.3.7 Status and Control Register 3 (ADCx_SC3)..................................................................................................353
25.3.8 ADC Offset Correction Register (ADCx_OFS).............................................................................................355
25.3.9 ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................355
25.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)...........................................................356
25.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................356
25.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................357
25.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................357
25.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................358
25.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................358
25.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................359
25.4 Functional description...................................................................................................................................................359
25.4.1 Clock select and divide control......................................................................................................................360
25.4.2 Voltage reference selection............................................................................................................................360
25.4.3 Hardware trigger and channel selects............................................................................................................361
25.4.4 Conversion control.........................................................................................................................................362
25.4.5 Automatic compare function..........................................................................................................................368
25.4.6 Calibration function.......................................................................................................................................370
25.4.7 User-defined offset function..........................................................................................................................371
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25.4.8 Temperature sensor........................................................................................................................................372
25.4.9 MCU wait mode operation.............................................................................................................................373
25.4.10 MCU Normal Stop mode operation...............................................................................................................373
25.4.11 MCU Low-Power Stop mode operation........................................................................................................374
25.5 Initialization information..............................................................................................................................................375
25.5.1 ADC module initialization example..............................................................................................................375
25.6 Application information................................................................................................................................................377
25.6.1 External pins and routing...............................................................................................................................377
25.6.2 Sources of error..............................................................................................................................................379
Chapter 26
Comparator (CMP)
26.1 Introduction...................................................................................................................................................................383
26.2 CMP features................................................................................................................................................................383
26.3 6-bit DAC key features.................................................................................................................................................384
26.4 ANMUX key features...................................................................................................................................................384
26.5 CMP, DAC and ANMUX diagram...............................................................................................................................385
26.6 CMP block diagram......................................................................................................................................................386
26.7 Memory map/register definitions..................................................................................................................................387
26.7.1 CMP Control Register 0 (CMPx_CR0).........................................................................................................387
26.7.2 CMP Control Register 1 (CMPx_CR1).........................................................................................................388
26.7.3 CMP Filter Period Register (CMPx_FPR).....................................................................................................390
26.7.4 CMP Status and Control Register (CMPx_SCR)...........................................................................................390
26.7.5 DAC Control Register (CMPx_DACCR)......................................................................................................391
26.7.6 MUX Control Register (CMPx_MUXCR)....................................................................................................392
26.8 Functional description...................................................................................................................................................393
26.8.1 CMP functional modes...................................................................................................................................393
26.8.2 Power modes..................................................................................................................................................402
26.8.3 Startup and operation.....................................................................................................................................403
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26.8.4 Low-pass filter...............................................................................................................................................403
26.9 CMP interrupts..............................................................................................................................................................406
26.10 Digital-to-analog converter...........................................................................................................................................406
26.11 DAC functional description..........................................................................................................................................407
26.11.1 Voltage reference source select......................................................................................................................407
26.12 DAC resets....................................................................................................................................................................407
26.13 DAC clocks...................................................................................................................................................................407
26.14 DAC interrupts..............................................................................................................................................................408
26.15 CMP Trigger Mode.......................................................................................................................................................408
Chapter 27
Timer/PWM Module (TPM)
27.1 Introduction...................................................................................................................................................................409
27.1.1 TPM Philosophy............................................................................................................................................409
27.1.2 Features..........................................................................................................................................................409
27.1.3 Modes of Operation.......................................................................................................................................410
27.1.4 Block Diagram...............................................................................................................................................410
27.2 TPM Signal Descriptions..............................................................................................................................................411
27.2.1 TPM_EXTCLK — TPM External Clock......................................................................................................411
27.2.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................412
27.3 Memory Map and Register Definition..........................................................................................................................412
27.3.1 Status and Control (TPMx_SC).....................................................................................................................413
27.3.2 Counter (TPMx_CNT)...................................................................................................................................414
27.3.3 Modulo (TPMx_MOD)..................................................................................................................................415
27.3.4 Channel (n) Status and Control (TPMx_CnSC).............................................................................................416
27.3.5 Channel (n) Value (TPMx_CnV)...................................................................................................................417
27.3.6 Capture and Compare Status (TPMx_STATUS)...........................................................................................418
27.3.7 Configuration (TPMx_CONF).......................................................................................................................420
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27.4 Functional Description..................................................................................................................................................421
27.4.1 Clock Domains...............................................................................................................................................422
27.4.2 Prescaler.........................................................................................................................................................422
27.4.3 Counter...........................................................................................................................................................423
27.4.4 Input Capture Mode.......................................................................................................................................425
27.4.5 Output Compare Mode...................................................................................................................................426
27.4.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................427
27.4.7 Center-Aligned PWM (CPWM) Mode..........................................................................................................429
27.4.8 Registers Updated from Write Buffers..........................................................................................................431
27.4.9 Reset Overview..............................................................................................................................................431
27.4.10 TPM Interrupts...............................................................................................................................................432
Chapter 28
Low-Power Timer (LPTMR)
28.1 Introduction...................................................................................................................................................................433
28.1.1 Features..........................................................................................................................................................433
28.1.2 Modes of operation........................................................................................................................................433
28.2 LPTMR signal descriptions..........................................................................................................................................434
28.2.1 Detailed signal descriptions...........................................................................................................................434
28.3 Memory map and register definition.............................................................................................................................434
28.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)........................................................................435
28.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)..................................................................................436
28.3.3 Low Power Timer Compare Register (LPTMRx_CMR)...............................................................................438
28.3.4 Low Power Timer Counter Register (LPTMRx_CNR).................................................................................438
28.4 Functional description...................................................................................................................................................439
28.4.1 LPTMR power and reset................................................................................................................................439
28.4.2 LPTMR clocking............................................................................................................................................439
28.4.3 LPTMR prescaler/glitch filter........................................................................................................................439
28.4.4 LPTMR compare............................................................................................................................................441
28.4.5 LPTMR counter.............................................................................................................................................441
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Section number Title Page
28.4.6 LPTMR hardware trigger...............................................................................................................................442
28.4.7 LPTMR interrupt............................................................................................................................................442
Chapter 29
Serial Peripheral Interface (SPI)
29.1 Introduction...................................................................................................................................................................443
29.1.1 Features..........................................................................................................................................................443
29.1.2 Modes of operation........................................................................................................................................444
29.1.3 Block diagrams..............................................................................................................................................444
29.2 External signal description............................................................................................................................................447
29.2.1 SPSCK — SPI Serial Clock...........................................................................................................................447
29.2.2 MOSI — Master Data Out, Slave Data In.....................................................................................................447
29.2.3 MISO — Master Data In, Slave Data Out.....................................................................................................447
29.2.4 SS — Slave Select..........................................................................................................................................447
29.3 Memory Map and Register Descriptions......................................................................................................................448
29.3.1 SPI Control Register 1 (SPIx_C1).................................................................................................................448
29.3.2 SPI Control Register 2 (SPIx_C2).................................................................................................................450
29.3.3 SPI Baud Rate Register (SPIx_BR)...............................................................................................................451
29.3.4 SPI Status Register (SPIx_S).........................................................................................................................452
29.3.5 SPI Data Register (SPIx_D)...........................................................................................................................453
29.3.6 SPI Match Register (SPIx_M)........................................................................................................................454
29.4 Functional description...................................................................................................................................................455
29.4.1 General...........................................................................................................................................................455
29.4.2 Master mode...................................................................................................................................................455
29.4.3 Slave mode.....................................................................................................................................................457
29.4.4 SPI clock formats...........................................................................................................................................458
29.4.5 SPI baud rate generation................................................................................................................................461
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29.4.6 Special features..............................................................................................................................................461
29.4.7 Error conditions..............................................................................................................................................463
29.4.8 Low-power mode options..............................................................................................................................464
29.4.9 Reset...............................................................................................................................................................465
29.4.10 Interrupts........................................................................................................................................................466
29.5 Initialization/application information...........................................................................................................................467
29.5.1 Initialization sequence....................................................................................................................................467
29.5.2 Pseudo-Code Example...................................................................................................................................468
Chapter 30
Inter-Integrated Circuit (I2C)
30.1 Introduction...................................................................................................................................................................471
30.1.1 Features..........................................................................................................................................................471
30.1.2 Modes of operation........................................................................................................................................472
30.1.3 Block diagram................................................................................................................................................472
30.2 I2C signal descriptions..................................................................................................................................................473
30.3 Memory map and register descriptions.........................................................................................................................473
30.3.1 I2C Address Register 1 (I2Cx_A1)................................................................................................................474
30.3.2 I2C Frequency Divider register (I2Cx_F)......................................................................................................475
30.3.3 I2C Control Register 1 (I2Cx_C1).................................................................................................................476
30.3.4 I2C Status register (I2Cx_S)..........................................................................................................................477
30.3.5 I2C Data I/O register (I2Cx_D).....................................................................................................................479
30.3.6 I2C Control Register 2 (I2Cx_C2).................................................................................................................479
30.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).........................................................................480
30.3.8 I2C Range Address register (I2Cx_RA)........................................................................................................482
30.4 Functional description...................................................................................................................................................482
30.4.1 I2C protocol...................................................................................................................................................482
30.4.2 10-bit address.................................................................................................................................................487
30.4.3 Address matching...........................................................................................................................................489
30.4.4 Resets.............................................................................................................................................................489
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Section number Title Page
30.4.5 Interrupts........................................................................................................................................................490
30.4.6 Programmable input glitch filter....................................................................................................................491
30.4.7 Address matching wakeup.............................................................................................................................492
30.5 Initialization/application information...........................................................................................................................492
Chapter 31
Universal Asynchronous Receiver/Transmitter (UART0)
31.1 Introduction...................................................................................................................................................................495
31.1.1 Features..........................................................................................................................................................495
31.1.2 Modes of operation........................................................................................................................................496
31.1.3 Block diagram................................................................................................................................................496
31.2 Register definition.........................................................................................................................................................498
31.2.1 UART Baud Rate Register High (UARTx_BDH).........................................................................................499
31.2.2 UART Baud Rate Register Low (UARTx_BDL)..........................................................................................500
31.2.3 UART Control Register 1 (UARTx_C1).......................................................................................................500
31.2.4 UART Control Register 2 (UARTx_C2).......................................................................................................502
31.2.5 UART Status Register 1 (UARTx_S1)..........................................................................................................503
31.2.6 UART Status Register 2 (UARTx_S2)..........................................................................................................505
31.2.7 UART Control Register 3 (UARTx_C3).......................................................................................................507
31.2.8 UART Data Register (UARTx_D).................................................................................................................508
31.2.9 UART Match Address Registers 1 (UARTx_MA1)......................................................................................509
31.2.10 UART Match Address Registers 2 (UARTx_MA2)......................................................................................510
31.2.11 UART Control Register 4 (UARTx_C4).......................................................................................................510
31.2.12 UART Control Register 5 (UARTx_C5).......................................................................................................511
31.3 Functional description...................................................................................................................................................512
31.3.1 Baud rate generation......................................................................................................................................512
31.3.2 Transmitter functional description.................................................................................................................512
31.3.3 Receiver functional description.....................................................................................................................514
31.3.4 Additional UART functions...........................................................................................................................517
31.3.5 Interrupts and status flags..............................................................................................................................519
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Section number Title Page
Chapter 32
General-Purpose Input/Output (GPIO)
32.1 Introduction...................................................................................................................................................................521
32.1.1 Features..........................................................................................................................................................521
32.1.2 Modes of operation........................................................................................................................................521
32.1.3 GPIO signal descriptions...............................................................................................................................522
32.2 Memory map and register definition.............................................................................................................................523
32.2.1 Port Data Output Register (GPIOx_PDOR)...................................................................................................524
32.2.2 Port Set Output Register (GPIOx_PSOR)......................................................................................................524
32.2.3 Port Clear Output Register (GPIOx_PCOR)..................................................................................................525
32.2.4 Port Toggle Output Register (GPIOx_PTOR)...............................................................................................525
32.2.5 Port Data Input Register (GPIOx_PDIR).......................................................................................................526
32.2.6 Port Data Direction Register (GPIOx_PDDR)...............................................................................................526
32.3 FGPIO memory map and register definition................................................................................................................527
32.3.1 Port Data Output Register (FGPIOx_PDOR)................................................................................................528
32.3.2 Port Set Output Register (FGPIOx_PSOR)...................................................................................................528
32.3.3 Port Clear Output Register (FGPIOx_PCOR)...............................................................................................529
32.3.4 Port Toggle Output Register (FGPIOx_PTOR).............................................................................................529
32.3.5 Port Data Input Register (FGPIOx_PDIR).....................................................................................................530
32.3.6 Port Data Direction Register (FGPIOx_PDDR)............................................................................................530
32.4 Functional description...................................................................................................................................................530
32.4.1 General-purpose input....................................................................................................................................530
32.4.2 General-purpose output..................................................................................................................................531
32.4.3 IOPORT.........................................................................................................................................................531
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Chapter 1
About This Document
1.1 Overview
1.1.1 Purpose
This document describes the features, architecture, and programming model of the
Freescale KL02 microcontroller.
1.1.2 Audience
A reference manual is primarily for system architects and software application developers
who are using or considering using a Freescale product in a system.
1.2 Conventions
1.2.1 Numbering systems
The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are
shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general,
decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases,
hexadecimal numbers are shown with the prefix 0x.
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uuln/
1.2.2 Typographic notation
The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.2.3 Special terms
The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
An active-high signal is asserted when high (1).
An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
An active-high signal is deasserted when low (0).
An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the
module or chip behavior is unpredictable.
Conventions
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Chapter 2
Introduction
2.1 Overview
This chapter provides an overview of the Kinetis L series of ARM® Cortex®-M0+ MCUs
and KL02 product family. It also presents high-level descriptions of the modules
available on the devices covered by this document.
2.2 Kinetis L series
The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal
ARM® Cortex®-M0+ MCUs in the industry. The portfolio includes five MCU families
that offer a broad range of memory, peripheral and package options. Kinetis L Series
families share common peripherals and pin-counts allowing developers to migrate easily
within an MCU family or between MCU families to take advantage of more memory or
feature integration. This scalability allows developers to standardize on the Kinetis L
Series for their end product platforms, maximising hardware and software reuse and
reducing time-to-market.
Features common to all Kinetis L series families include:
48 MHz ARM Cortex-M0+ core
High-speed 12/16-bit analog-to-digital converters
12-bit digital-to-analog converters for all series except for KLx4/KLx2 family
High-speed analog comparators
Low-power touch sensing with wake-up on touch from reduced power states for all
series except for KLx4/KLx2 family
Powerful timers for a broad range of applications including motor control
Low-power focused serial communication interfaces such as low-power UART, SPI,
I2C, and others.
Single power supply: 1.71–3.6 V with multiple low-power modes support single
operation temperature:
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muck Program ---— KL4xFamily128-256KB 64-121pin lawmwv 0%» B KL3x Family 64-256KB 64-121pin i W 8 KL2x Family 32-256KB 32-121pin l W 0%» KL1x Family 32-256KB 32-80pin i W KLOx Family 8-32KB 16-48pin i W i Low power WV Mixed signal QUSB 8 Segment LCD
–40 ~ 105 °C (exclude WLCSP package)
–40 ~ 85 °C (WLCSP package)
Kinetis L series MCU families combine the latest low-power innovations with precision
mixed-signal capability and a broad range of communication, connectivity, and human-
machine interface peripherals. Each MCU family is supported by a market-leading
enablement bundle from Freescale and numerous ARM third party ecosystem partners.
The KL0x family is the entry-point to the Kinetis L series and is pin-compatible with the
8-bit S08PT family. The KL1x/2x/3x/4x families are compatible with each other and
their equivalent ARM Cortex-M4 Kinetis K series families—K10/20/30/40.
The following figure depicts key features, memory and package options for Kinetis L
series family of MCUs.
KL2x Family
KL1x Family
KL0x Family
KL3x Family
Family Program
Flash Packages Key Features
Low power Mixed signal USB Segment LCD
KL4x Family
8-32KB
32-256KB
32-256KB
64-256KB
128-256KB
16-48pin
32-80pin
32-121pin
64-121pin
64-121pin
Figure 2-1. Kinetis L series families of MCU portfolio
All Kinetis L series families include a powerful array of analog, communication and
timing and control peripherals with the level of feature integration increasing with flash
memory size and the pin count. Features within the Kinetis L series families include:
Core and architecture:
ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution
from memories
Single-cycle access to I/O: Up to 50 percent faster than standard I/O,
improves reaction time to external events allowing bit banging and software
protocol emulation
Kinetis L series
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Two-stage pipeline: Reduced number of cycles per instruction (CPI),
enabling faster branch instruction and ISR entry, and reducing power
consumption
Excellent code density as compared to 8-bit and 16-bit MCUs: Reduces flash
size, system, cost and power consumption
Optimized access to program memory: Accesses on alternate cycles reduces
power consumption.
100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-
M3/M4: Reuse existing compilers and debug tools.
Simplified architecture: 56 instructions and 17 registers enable easy
programming and efficient packaging of 8/16/32-bit data in memory.
Linear 4 GB address space removes the need for paging/banking, reducing
software complexity.
ARM third-party ecosystem support: Software and tools to help minimize
development time/cost
Micro Trace Buffer: Lightweight trace solution allows fast bug identification and
correction.
Bit Manipulation Engine (BME): BME reduces code size and cycles for bit-
oriented operations to peripheral registers eliminating traditional methods where
the core would need to perform read-modify-write operations.
Up to 4-channel DMA for peripheral and memory servicing with minimal CPU
intervention (feature not available on KL02 family)
Ultra low-power:
Extreme dynamic efficiency: 32-bit ARM Cortex-M0+ core combined with
Freescale 90 nm thin-film storage flash technology delivers 50% energy savings
per Coremark in comparison to the closest 8/16-bit competitive solution.
Multiple flexible low-power modes, including new operation clocking option
which reduces dynamic power by shutting off bus and system clocks for lowest
power core processing. Peripherals with an alternate asynchronous clock source
can continue operation.
UART, SPI, I2C, ADC, DAC, TPM, LPTMR, and DMA support low-power
mode operation without waking up the core (DMA is not available on KL02).
• Memory:
Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32
KB SRAM
Embedded 64 B cache memory for optimizing bus bandwidth and flash
execution performance (32 B cache on KL02 family)
Mixed-signal analog:
Chapter 2 Introduction
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“Luz
Fast, high-precision 16-, or 12-bit ADC with optional differential pairs, 12-bit
DAC, high-speed comparators.
Powerful signal conditioning, conversion, and analysis capability with reduced
system cost (12-bit DAC not available on KL02 family)
Human Machine Interface (HMI):
Optional capacitive Touch Sensing Interface with full low-power support and
minimal current adder when enabled
Segment LCD controller
Connectivity and communications:
Up to three UARTs:
All UARTs support DMA transfers, and can trigger when data on bus is
detected;
UART0 supports 4x to 32x over sampling ratio;
Asynchronous transmit and receive operation for operating in STOP/VLPS
modes.
Up to two SPIs
Up to two I2Cs
Full-speed USB OTG controller with on-chip transceiver
3.3–5 V USB on-chip regulator
Up to one I2S
Reliability, safety, and security:
Internal watchdog with independent clock source
Timing and control:
Powerful timer modules which support general-purpose, PWM, and motor
control functions
Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for
ADC conversion and timer modules
• System:
GPIO with pin interrupt functionality
Wide operating voltage range from 1.71 V to 3.6 V with flash programmable
down to 1.71 V with fully functional flash and analog peripherals
Ambient operating temperature ranges from –40 °C to 85 °C for WLCSP
package and 105 °C for all the other packages
2.3 KL02 sub-family introduction
The device is highly-integrated, market leading ultra low-power 32-bit microcontroller
based on the enhanced Cortex-M0+ (CM0+) core platform. The features of the KL0x
family derivatives are as follows.
Core platform clock up to 48 MHz, bus clock up to 24 MHz
KL02 sub-family introduction
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Wide operating voltage ranges from 1.71–3.6 V with fully functional flash program/
erase/read operations
20-pin WLCSP package
Ambient operating temperature ranges from –40 °C to 85 °C for WLCSP package
and –40 °C to 105 °C for all the others.
The family acts as an ultra low-power, cost-effective microcontroller to provide
developers an appropriate entry-level 32-bit solution. The family is the next-generation
MCU solution for low-cost, low-power, high-performance devices applications. It’s
valuable for cost-sensitive, portable applications requiring long battery life-time.
2.4 Module functional categories
The modules on this device are grouped into functional categories. The following
sections describe the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category Description
ARM Cortex-M0+ core 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark®/MHz from
single-cycle access memories, 48 MHz CPU frequency
System System integration module
Power management and mode controllers
Multiple power modes available based on run, wait, stop, and power-
down modes
Miscellaneous control module
Peripheral bridge
COP watchdog
Memories Internal memories include:
Up to 32 KB flash memory
Up to 4 KB SRAM
Clocks Multiple clock generation options available from internally- and externally-
generated clocks
MCG module with FLL for systems and CPU clock sources
Low power 1 kHz RC oscillator for COP watchdog
System oscillator to provide clock source for the MCU
Security COP watchdog timer (COP)
Analog 12-bit analog-to-digital converters
Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
Timers Two 2-channel TPMs
Low-power timer
System tick timer
Communications One8-bit serial peripheral interface
Two inter-integrated circuit (I2C) modules
One low power UART module
Human-Machine Interfaces (HMI) General purpose input/output controller
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mum:
2.4.1 ARM Cortex-M0+ core modules
The following core modules are available on this device.
Table 2-2. Core modules
Module Description
ARM Cortex-M0+ The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors
targeting microcontroller applications focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M0+ processor is based on the ARMv6
Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its
predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4
cores.
NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the ARM CoreSight architecture. One
debug interface is supported:
Serial Wire Debug (SWD)
2.4.2 System modules
The following system modules are available on this device.
Table 2-3. System modules
Module Description
System integration module (SIM) The SIM includes integration logic and several module configuration settings.
System mode controller (SMC) The SMC provides control and protection on entry and exit to each power mode,
control for the power management controller (PMC), and reset entry and exit for
the complete MCU.
Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Table continues on the next page...
Module functional categories
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Table 2-3. System modules (continued)
Module Description
Miscellaneous control module (MCM) The MCM includes integration logic and details.
Crossbar switch lite (AXBS-Lite) The AXBS connects bus masters and bus slaves, allowing all bus masters to
access different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.
Peripheral bridge (AIPS-Lite) The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
Computer operating properly watchdog
(WDOG)
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 kHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
2.4.3 Memories and memory interfaces
The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module Description
Flash memory Program flash memory — up to 32 KB of the non-volatile flash memory that can
execute program code
Flash memory controller Manages the interface between the device and the on-chip flash memory.
SRAM Up to 4 KB internal system RAM.
2.4.4 Clocks
The following clock modules are available on this device.
Table 2-5. Clock modules
Module Description
Multipurpose Clock Generator (MCG) MCG module containing a frequency-locked-loop (FLL) controlled by internal or
external reference oscillator.
System oscillator (OSC) The system oscillator, in conjunction with an external crystal or resonator,
generates a reference clock for the MCU.
2.4.5 Security and integrity modules
The following security and integrity modules are available on this device:
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Table 2-6. Security and integrity modules
Module Description
Watchdog timer (WDOG) Watchdog timer keeps a watch on the system functioning and resets it in case of
its failure.
2.4.6 Analog modules
The following analog modules are available on this device:
Table 2-7. Analog modules
Module Description
Analog-to-digital converters (ADC) 12-bit successive-approximation ADC module.
Analog comparators One comparator that compares two analog input voltages across the full range of
the supply voltage and can trigger an ADC acquisition, TPM update, or CPU
interrupt.
6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for
comparator.
2.4.7 Timer modules
The following timer modules are available on this device:
Table 2-8. Timer modules
Module Description
Timer/PWM module (TPM) Selectable TPM clock mode
Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
16-bit free-running counter or modulo counter with counting be up or up-
down
Two configurable channels for input capture, output compare, or edge-
aligned PWM mode
Support the generation of an interrupt per channel
Support the generation of an interrupt when the counter overflows
Support selectable trigger input to optionally reset or cause the counter to
start incrementing.
Support the generation of hardware triggers when the counter overflows and
per channel
Low power timer (LPTMR) 16-bit time counter or pulse counter with compare
Configurable clock source for prescaler/glitch filter
Configurable input source for pulse counter
Module functional categories
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2.4.8 Communication interfaces
The following communication interfaces are available on this device:
Table 2-9. Communication modules
Module Description
Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device
Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2.
Universal asynchronous receiver/
transmitters (UART)
One low power UART module that retains functional in stop modes.
2.4.9 Human-machine interfaces
The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module Description
General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt request
generation.
2.5 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this
document.
Table 2-11. Orderable part numbers summary
Freescale part
number
CPU
frequency
Pin count Package Total
flash
memory
RAM Reel Temperature range
MKL02Z32CAF4R 48 MHz 20 WLCSP 32 KB 4 KB 100 pieces -40 to 85 °C
KKL02Z32CAF4R 48 MHz 20 WLCSP 32 KB 4 KB 3000
pieces
-40 to 85 °C
Chapter 2 Introduction
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Orderable part numbers
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Chapter 3
Chip Configuration
3.1 Introduction
This chapter provides details on the individual modules of the microcontroller. It
includes:
Module block diagrams showing immediate connections within the device
Specific module-to-module interactions not necessarily discussed in the individual
module chapters
Links for more information
3.2 Module to module interconnects
3.2.1 Interconnection overview
The following table captures the module to module interconnections for this device.
Table 3-1. Module-to-module interconnects
Peripheral Signal to Peripheral Use Case Control Comment
TPM1 CH0F, CH1F to ADC (Trigger) ADC
Triggering (A
AND B)
SOPT7_ADCALTTRG
EN = 0
Ch0 is A, and Ch1 is
B, selecting this ADC
trigger is for
supporting A and B
triggering. In Stop and
VLPS modes, the
second trigger must
be set to >10 µs after
the first trigger
LPTMR Hardware
trigger
to ADC (Trigger) ADC
Triggering (A
or B)
SOPT7_ADC0TRGSE
L (4-bit field),
ADC0PRETRGSEL to
select A or B
Table continues on the next page...
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mum:
Table 3-1. Module-to-module interconnects (continued)
Peripheral Signal to Peripheral Use Case Control Comment
TPMx TOF to ADC (Trigger) ADC
Triggering (A
or B)
SOPT7_ADC0TRGSE
L (4-bit field),
SOPT7_ADC0PRETR
GSEL to select A or B
EXTRG_IN EXTRG_IN to ADC (Trigger) ADC
Triggering (A
or B)
SOPT7_ADC0TRGSE
L (4-bit field)
ADC0PRETRGSEL to
select A or B
CMP0 CMP0_OUT to ADC (Trigger) ADC
Triggering
(Aor B)
SOPT7_ADC0TRGSE
L (4-bit field)
ADC0PRETRGSEL to
select A or B
CMP0 CMP0_OUT to LPTMR_ALT0 Count CMP
events
LPTMR_CSR[TPS] —
CMP0 CMP0_OUT to TPM1 CH0 Input capture SOPT4_TPM1CH0SR
C
CMP0 CMP0_OUT to UART0_RX IR interface SOPT5_UART0RXSR
C
LPTMR Hardware
trigger
to CMPx Low power
triggering of
the
comparator
CMP_CR1[TRIGM] —
LPTMR Hardware
trigger
to TPMx TPM Trigger
input
TPMx_CONF[TRGSE
L] (4 bit field)
TPMx TOF to TPMx TPM Trigger
input
TPMx_CONF[TRGSE
L] (4-bit field)
TPM1 Timebase to TPMx TPM Global
timebase
input
TPMx_CONF[GTBEE
N]
EXTRG_IN EXTRG_IN to TPMx TPM Trigger
input
TPMx_CONF[TRGSE
L] (4-bit field)
CMP0 CMP0_OUT to TPMx TPM Trigger
input
TPMx_CONF[TRGSE
L] (4-bit field)
UART0 UART0_TX to Modulated by
TPM1 CH0
UART
modulation
SOPT5_UART0TXSR
C
Module to module interconnects
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3.2.2 Analog reference options
Several analog blocks have selectable reference voltages as shown in Table 3-2. These
options allow analog peripherals to share or have separate analog references. Care should
be taken when selecting analog references to avoid cross talk noise.
Table 3-2. Analog reference options
Module Reference option Comment/ Reference selection
12-bit SAR ADC 1 - VREFH
2 - VDDA
3 - Reserved
Selected by ADCx_SC2[REFSEL]
CMP with 6-bit DAC Vin1 - VREFH
Vin2 - VDD1
Selected by CMPx_DACCR[VRSEL]
1. Use this option for the best ADC operation.
3.3 Core modules
3.3.1 ARM Cortex-M0+ core configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
ARM Cortex-M0+
Core
Debug Interrupts
Crossbar
switch
Figure 3-1. Core configuration
Table 3-3. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M0+ core,
r0p0
ARM Cortex-M0+ Technical Reference Manual, r0p0
System memory map System memory map
Clocking Clock distribution
Table continues on the next page...
Chapter 3 Chip Configuration
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Table 3-3. Reference links to related information (continued)
Topic Related module Reference
Power management Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug Serial wire debug
(SWD)
Debug
Interrupts Nested vectored
interrupt controller
(NVIC)
NVIC
Miscellaneous control
module (MCM)
MCM
3.3.1.1 ARM Cortex M0+ core
The ARM Cortex M0+ parameter settings are as follows:
Table 3-4. ARM Cortex-M0+ parameter settings
Parameter Verilog name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock gating
DAP Slave Port Support AHBSLV 1 Supports any AHB debug access port (like the
CM4 DAP)
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM table
Endianess BE 0 Little endian control for data transfers
Breakpoints BKPT 2 Implements 2 breakpoints
Debug Support DBG 1 = Present
Halt Event Support HALTEV 1 = Present
I/O Port IOP 1 = Present Implements single-cycle ld/st accesses to
special address space
IRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs are used (set if
IRQ is disabled)
Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAG
Core Memory Protection MPU 0 = Absent No MPU
Number of IRQs NUMIRQ 32 Assume full NVIC request vector
Reset all registers RAR 0 = Standard Do not force all registers to be async reset
Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier
Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multi-
drop
System Tick Timer SYST 1 = Present Implements system tick timer (for CM4
compatibility)
DAP Target ID TARGETID 0
User/Privileged USER 1 = Present Implements processor operating modes
Table continues on the next page...
Core modules
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Table 3-4. ARM Cortex-M0+ parameter settings (continued)
Parameter Verilog name Value Description
Vector Table Offset Register VTOR 1 = Present Implements relocation of exception vector
table
WIC Support WIC 1 = Present Implements WIC interface
WIC Requests WICLINES 34 Exact number of wake-up IRQs is 34
Watchpoints WPT 2 Implements two watchpoints
For details on the ARM Cortex-M0+ processor core, see the ARM website:arm.com.
3.3.1.2 Buses, interconnects, and interfaces
The ARM Cortex-M0+ core has two bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
3.3.1.3 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.
3.3.1.4 Debug facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
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3.3.2 Nested vectored interrupt controller (NVIC) configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+
core
Interrupts Module
Module
Module
PPB
Figure 3-2. NVIC configuration
Table 3-5. Reference links to related information
Topic Related module Reference
Full description Nested vectored
interrupt controller
(NVIC)
ARM Cortex-M0+ Technical Reference Manual
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Private peripheral bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
3.3.2.1 Interrupt priority levels
This device supports four priority levels for interrupts. Therefore, in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIRQ3 000000IRQ2 000000IRQ1 0 0 0 0 0 0 IRQ0 0 0 0 0 0 0
W
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.
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3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
Vector number — the value stored on the stack when an interrupt is serviced.
IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
NOTE
The NVIC wake-up sources in the following table support only
down to VLPS.
Table 3-7. Interrupt vector assignments
Address Vector IRQ1NVIC
IPR
register
number2
Source module Source description
ARM core system handler vectors
0x0000_0000 0 ARM core Initial stack pointer
0x0000_0004 1 ARM core Initial program counter
0x0000_0008 2 ARM core Non-maskable interrupt (NMI)
0x0000_000C 3 ARM core Hard fault
0x0000_0010 4 — — —
0x0000_0014 5 — — —
0x0000_0018 6 — — —
0x0000_001C 7 — — —
0x0000_0020 8 — — —
0x0000_0024 9 — — —
0x0000_0028 10 — — —
0x0000_002C 11 ARM core Supervisor call (SVCall)
0x0000_0030 12 — — —
0x0000_0034 13 — — —
0x0000_0038 14 ARM core Pendable request for system service
(PendableSrvReq)
0x0000_003C 15 ARM core System tick timer (SysTick)
Non-Core Vectors
0x0000_0040 16 0 0 —
0x0000_0044 17 1 0 —
0x0000_0048 18 2 0 —
0x0000_004C 19 3 0 —
0x0000_0050 20 4 1 —
Table continues on the next page...
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Table 3-7. Interrupt vector assignments (continued)
Address Vector IRQ1NVIC
IPR
register
number2
Source module Source description
0x0000_0054 21 5 1 FTFA Command complete and read collision
0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning
0x0000_005C 23 7 1 —
0x0000_0060 24 8 2 I2C0 —
0x0000_0064 25 9 2 I2C1 —
0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources
0x0000_006C 27 11 2
0x0000_0070 28 12 3 UART0 Status and error
0x0000_0074 29 13 3
0x0000_0078 30 14 3
0x0000_007C 31 15 3 ADC0
0x0000_0080 32 16 4 CMP0
0x0000_0084 33 17 4 TPM0
0x0000_0088 34 18 4 TPM1
0x0000_008C 35 19 4
0x0000_0090 36 20 5
0x0000_0094 37 21 5
0x0000_0098 38 22 5
0x0000_009C 39 23 5
0x0000_00A0 40 24 6
0x0000_00A4 41 25 6
0x0000_00A8 42 26 6
0x0000_00AC 43 27 6 MCG
0x0000_00B0 44 28 7 LPTMR0
0x0000_00B4 45 29 7
0x0000_00B8 46 30 7 Port control module Pin detect (Port A)
0x0000_00BC 47 31 7 Port control module Pin detect (Port B)
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
3.3.2.3.1 Determining the bitfield and register location for configuring a
particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
SPI0 row from Interrupt priority levels.
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Table 3-8. Interrupt vector assignments
Address Vector IRQ1NVIC IPR
register
number2
Source module Source description
0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
To determine the particular IRQ's field location within these particular registers:
NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22
Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field
range is 22–23.
Therefore, the following field locations are used to configure the SPI0 interrupts:
• NVICIPR2[23:22]
3.3.3 Asynchronous wake-up interrupt controller (AWIC)
configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at arm.com.
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Figure 3-3. Asynchronous wake-up interrupt controller configuration
Table 3-9. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Table continues on the next page...
Chapter 3 Chip Configuration
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Table 3-9. Reference links to related information (continued)
Topic Related module Reference
Nested vectored
interrupt controller
(NVIC)
NVIC
Wake-up requests AWIC wake-up sources
3.3.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-10. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET_b pin when LPO is its clock source
Low-voltage detect Power management controller—functional in Stop mode
Low-voltage warning Power management controller—functional in Stop mode
Pin interrupts Port control module—any enabled pin interrupt is capable of waking the system.
ADC The ADC is functional when using internal clock source.
CMP0 Interrupt in normal or trigger mode
I2Cx Address match wakeup
UART0 Any interrupt provided clock remains enabled.
NMI NMI_b pin
TPMx Any interrupt provided clock remains enabled.
LPTMR Any interrupt provided clock remains enabled.
SPI Slave mode interrupt
3.4 System modules
3.4.1 SIM configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
System modules
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621V 3:928 Ememmmcms axon
Register
access
Peripheral
bridge
System integration
module (SIM)
Figure 3-4. SIM configuration
Table 3-11. Reference links to related information
Topic Related module Reference
Full description SIM SIM
System memory map System memory map
Clocking — Clock distribution
Power management Power management
3.4.2 System mode controller (SMC) configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Power Management
Controller (PMC)
Register
access
Peripheral
bridge
System Mode
Controller (SMC)
Resets
Figure 3-5. System mode controller configuration
Table 3-12. Reference links to related information
Topic Related module Reference
Full description System mode controller
(SMC)
SMC
System memory map System memory map
Power management Power management
Table continues on the next page...
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Table 3-12. Reference links to related information (continued)
Topic Related module Reference
Power management
controller (PMC)
PMC
Reset control module
(RCM)
Reset
3.4.2.1 VLLS2 not supported
VLLS2 power mode is not supported on this device.
3.4.3 PMC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register access
Power Management
Controller (PMC)
Peripheral
bridge
Module
signals
System Mode
Controller (SMC)
Figure 3-6. PMC configuration
Table 3-13. Reference links to related information
Topic Related module Reference
Full description PMC PMC
System memory map System memory map
Power management Power management
Full description System mode controller
(SMC)
System Mode Controller
Reset control module
(RCM)
Reset
System modules
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3.4.4 MCM configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Miscellaneous
Control Module
(MCM)
Transfers
ARM Cortex-M0+
core
Flash Memory
Controller
Transfers
Figure 3-7. MCM configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description Miscellaneous control
module (MCM)
MCM
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Private peripheral bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
Transfer Flash memory
controller
Flash memory controller
3.4.5 Crossbar-light switch configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
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flue
Figure 3-8. Crossbar-light switch integration
Table 3-15. Reference links to related information
Topic Related module Reference
Full description Crossbar switch Crossbar switch
System memory map System memory map
Clocking — Clock distribution
Crossbar switch master ARM Cortex-M0+ core ARM Cortex-M0+ core
Crossbar switch slave Flash memory
controller
Flash memory controller
Crossbar switch slave SRAM controller SRAM configuration
Crossbar switch slave Peripheral bridge Peripheral bridge
2-ported peripheral GPIO controller GPIO controller
3.4.5.1 Crossbar-light switch master assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core unified bus 0
System modules
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3.4.5.2 Crossbar switch slave assignments
This device contains 3 slaves connected to the crossbar switch.
The slave assignment is as follows:
Slave module Slave port number
Flash memory controller 0
SRAM controller 1
Peripheral bridge 0 2
3.4.6 Peripheral bridge configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Figure 3-9. Peripheral bridge configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
Peripheral bridge (AIPS-Lite)
System memory map System memory map
Clocking — Clock distribution
Crossbar switch Crossbar switch Crossbar switch
3.4.6.1 Number of peripheral bridges
This device contains one peripheral bridge.
3.4.6.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See AIPS0 Memory Map for the memory slot assignment for each module.
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3.4.7 Computer operating properly (COP) watchdog
configuration
This section summarizes how the module has been configured in the chip.
WDOG
Mode Controller
Peripheral
bridge 0
Register
access
Figure 3-10. COP watchdog configuration
Table 3-17. Reference links to related information
Topic Related module Reference
Clocking — Clock distribution
Power management Power management
Programming model System integration
module (SIM)
SIM
3.4.7.1 COP clocks
The multiple clock inputs for the COP are the 1 kHz clock and the bus clock.
3.4.7.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails
to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), the application software must reset the COP counter periodically. If the
application program gets lost and fails to reset the COP counter before it times out, a
system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an
application, it can be disabled by clearing SIM_COPCTRL[COPT].
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The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the
SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not
affect the data in the SRVCOP register. As soon as the write sequence is complete, the
COP timeout period is restarted. If the program fails to perform this restart during the
timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is
written to the SRVCOP register, the microcontroller immediately resets.
SIM_COPCTRL[COPCLKS] selects the clock source used for the COP timer. The clock
source options are either the bus clock or an internal 1 kHz clock source. With each clock
source, there are three associated timeouts controlled by SIM_COPCTRL[COPT]. The
following table summarizes the control functions of SIM_COPCTRL[COPCLKS] and
SIM_COPCTRL[COPT] fields. The COP watchdog defaults to operation from the 1 kHz
clock source and the longest timeout for that clock source (210 cycles).
Table 3-18. COP configuration options
Control bits Clock
source
COP window opens
(SIM_COPCTRL[COPW]=1)
COP overflow count
SIM_COPCTRL[COPCLKS] SIM_COPCTRL[COPT
]
N/A 00 N/A N/A COP is disabled.
0 01 1 kHz N/A 25 cycles (32 ms)
0 10 1 kHz N/A 28 cycles (256 ms)
0 11 1 kHz N/A 210 cycles (1024 ms)
1 01 Bus 6,144 cycles 213 cycles
1 10 Bus 49,152 cycles 216 cycles
1 11 Bus 196,608 cycles 218 cycles
After the bus clock source is selected, windowed COP operation is available by setting
SIM_COPCTRL[COPW]. In this mode, writes to the SIM_SRVCOP register to clear the
COP timer must occur in the last 25% of the selected timeout period. A premature write
immediately resets the chip. When the 1 kHz clock source is selected, windowed COP
operation is not available.
The COP counter is initialized by the first writes to the SIM_COPCTRL register and after
any system reset. Subsequent writes to the SIM_COPCTRL register have no effect on
COP operation. Even if an application uses the reset default settings of
SIM_COPCTRL[COPT], SIM_COPCTRL[COPCLKS], and SIM_COPCTRL[COPW]
fields, the user should write to the write-once SIM_COPCTRL register during reset
initialization to lock in the settings. This approach prevents accidental changes if the
application program becomes lost.
The write to the SIM_SRVCOP register that services (clears) the COP counter should not
be placed in an interrupt service routine (ISR) because the ISR could continue to be
executed periodically even if the main application program fails.
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If the bus clock source is selected, the COP counter does not increment while the
microcontroller is in Debug mode or while the system is in Stop (including VLPS) mode.
The COP counter resumes when the microcontroller exits Debug or Stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry
to either debug mode or stop (including VLPS) mode. The counter begins from zero upon
exit from debug mode or stop mode.
Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx
mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is reinitialized
and enabled as for any reset.
3.4.7.3 Clock gating
This family of devices includes clock gating control for each peripheral, that is, the clock
to each peripheral can explicitly be gated on or off, using clock-gate control bits in the
SIM module.
3.5 Clock modules
3.5.1 MCG configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Peripheral
bridge
Multipurpose Clock
Generator (MCG)
System
oscillator
System integration
module (SIM)
Figure 3-11. MCG configuration
Table 3-19. Reference links to related information
Topic Related module Reference
Full description MCG MCG
Table continues on the next page...
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Table 3-19. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.5.1.1 MCG FLL modes
The MCGFLLCLK frequency is limited to 48 MHz at maximum in this device. The
digitally-controller oscillator (DCO) is limited to the two lowest range settings, that is,
MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01.
3.5.2 OSC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Register
access
Peripheral
bridge
System oscillator
MCG
Module signals
Figure 3-12. OSC configuration
Table 3-20. Reference links to related information
Topic Related module Reference
Full description OSC OSC
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
Full description MCG MCG
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3.5.2.1 OSC modes of operation with MCG
The most common method of controlling the OSC block is through MCG_C1[CLKS] and
the fields of MCG_C2 register to configure for crystal or external clock operation. Since
the OSC is limited to support 32 kHz VLP oscillation mode only, the range, gain mode
selections from MCG are ignored by the OSC. OSC_CR also provides control for
enabling the OSC module and configuring internal load capacitors for the EXTAL and
XTAL pins. See the OSC and MCG chapters for more details.
3.6 Memories and memory interfaces
3.6.1 Flash memory configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Flash memory
Transfers
Flash memory
controller
Peripheral bus
controller 0
Figure 3-13. Flash memory configuration
Table 3-21. Reference links to related information
Topic Related module Reference
Full description Flash memory Flash memory
System memory map System memory map
Clocking — Clock distribution
Transfers Flash memory
controller
Flash memory controller
Register access Peripheral bridge Peripheral bridge
Memories and memory interfaces
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
56 Freescale Semiconductor, Inc.
3.6.1.1 Flash memory sizes
The devices covered in this document contain 1 program flash block consisting of 1 KB
sectors.
The amounts of flash memory for the devices covered in this document are:
Table 3-22. KL02 flash memory size
Freescale part number Program flash (KB) Block 0 (P-flash) address range
MKL02Z32CAF4R 32 0x0000_0000 – 0x0000_7FFF
KKL02Z32CAF4R 32 0x0000_0000 – 0x0000_7FFF
3.6.1.2 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown
in the following figure. The base address for each is specified in System memory map.
Flash
Flash configuration field
Flash base address
Flash memory base address
Registers
Figure 3-14. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to
form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash and EEPROM memory sizes for details of supported ranges.
Access to the flash memory ranges outside the amount of flash on the device causes the
bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master.
3.6.1.3 Flash security
For information on how flash security is implemented on this device, see Chip Security.
Chapter 3 Chip Configuration
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m: .o 22.9.. 5% 12:3 .3390
3.6.1.4 Flash modes
The flash memory chapter defines two modes of operation: NVM normal and NVM
special modes. On this device, the flash memory only operates in NVM normal mode. All
references to NVM special mode must be ignored.
3.6.1.5 Erase all flash contents
In addition to software, the entire flash memory may be erased external to the flash
memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP
STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP
STATUS[0] is cleared when the mass erase completes.
3.6.1.6 FTFA_FOPT register
The flash memory's FTFA_FOPT register allows the user to customize the operation of
the MCU at boot time. See FOPT boot options for details of its definition.
3.6.2 Flash memory controller configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
See MCM_PLACR register description for details on the reset configuration of the FMC.
Flash memory
controller
Transfers Transfers
Flash memory
Crossbar switch
MCM
Figure 3-15. Flash memory controller configuration
Table 3-23. Reference links to related information
Topic Related module Reference
Full description Flash memory
controller
Flash memory controller
Table continues on the next page...
Memories and memory interfaces
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
58 Freescale Semiconductor, Inc.
Table 3-23. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking — Clock distribution
Transfers Flash memory Flash memory
Transfers Crossbar switch Crossbar switch
Register access MCM MCM
3.6.3 SRAM configuration
This section summarizes how the module has been configured in the chip.
SRAM upper
Transfers
Cortex-M0+
core switch
SRAM lower
crossbar
SRAM
controller
Figure 3-16. SRAM configuration
Table 3-24. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking — Clock distribution
ARM Cortex-M0+ core ARM Cortex-M0+ core
3.6.3.1 SRAM sizes
This device contains SRAM which could be accessed by bus masters through the cross-
bar switch. The amount of SRAM for the devices covered in this document is shown in
the following table.
Table 3-25. KL02 SRAM memory size
Freescale part number RAM
MKL02Z32CAF4R 4 KB
KKL02Z32CAF4R 4 KB
Chapter 3 Chip Configuration
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
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memo A| E5. mum 3mm |V $5 . mum 52mm
3.6.3.2 SRAM ranges
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated
to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
This is illustrated in the following figure.
SRAM_U
0x2000_0000
SRAM size *(1/4)
SRAM_L
0x1FFF_FFFF
SRAM size * (3/4)
0x2000_0000 – SRAM_size/4
0x2000_0000 + SRAM_size(3/4) - 1
Figure 3-17. SRAM blocks memory map
For example, for a device containing 16 KB of SRAM, the ranges are:
Memories and memory interfaces
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60 Freescale Semiconductor, Inc.
2:29.32 :23
SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF
SRAM_U: 0x2000_0000 – 0x2000_2FFF
3.6.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0, no SRAM is
retained.
3.7 Analog
3.7.1 12-bit SAR ADC configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
12-bit SAR ADC
Peripheral bus
controller 0
Other peripherals
Figure 3-18. 12-bit SAR ADC configuration
Table 3-26. Reference links to related information
Topic Related module Reference
Full description 12-bit SAR ADC 12-bit SAR ADC
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.1.1 ADC instantiation information
This device contains one 12-bit successive approximation ADC with up to 10 channels.
Chapter 3 Chip Configuration
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc. 61
The ADC supports both software and hardware triggers. The hardware trigger sources are
listed in the Module-to-Module section.
The number of ADC channels present on the device is determined by the pinout of the
specific device package and is shown in the following table.
Table 3-27. Number of KL02 ADC channels
Device Number of ADC channels
MKL02Z32CAF4R 10
KKL02Z32CAF4R 10
3.7.1.2 ADC0 connections/channel assignment
3.7.1.2.1 ADC0 channel assignment
ADC Channel
(SC1n[ADCH]) Channel Input signal
(SC1n[DIFF]= 1) Input signal
(SC1n[DIFF]= 0)
00000 AD0 Reserved ADC0_SE0
00001 AD1 Reserved ADC0_SE1
00010 AD2 Reserved ADC0_SE2
00011 AD3 Reserved ADC0_SE3
00100 AD4 Reserved ADC0_SE4
00101 AD5 Reserved Reserved
00110 AD6 Reserved Reserved
00111 AD7 Reserved Reserved
01000 AD8 Reserved ADC0_SE5
01001 AD9 Reserved ADC0_SE6
01010 AD10 Reserved ADC0_SE7
01011 AD11 Reserved ADC0_SE8
01100 AD12 Reserved ADC0_SE9
01101 AD13 Reserved ADC0_SE10
01110 AD14 Reserved ADC0_SE11
01111 AD15 Reserved ADC0_SE12
10000 AD16 Reserved ADC0_SE13
10001 AD17 Reserved Reserved
10010 AD18 Reserved Reserved
10011 AD19 Reserved Reserved
10100 AD20 Reserved Reserved
10101 AD21 Reserved Reserved
10110 AD22 Reserved Reserved
Table continues on the next page...
Analog
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62 Freescale Semiconductor, Inc.
ADC Channel
(SC1n[ADCH]) Channel Input signal
(SC1n[DIFF]= 1) Input signal
(SC1n[DIFF]= 0)
10111 AD23 Reserved Reserved
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)1Bandgap (S.E)1
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
3.7.1.3 ADC analog supply and reference connections
VREFH and VREFL are internally connected to VDD and VSS respectively.
This device internally connects VDDA to VDD and VSSA to VSS.
This device contains separate VREFH and VREFL pins on 32-pin and higher devices.
These pins are internally connected to VDD and VSS respectively, on packages less than
32-pin.
3.7.1.4 Alternate clock
For this device, the alternate clock is connected to the external reference clock
(OSCERCLK).
NOTE
This clock option is only usable when OSCERCLK is in the
MHz range. A system with OSCERCLK in the kHz range has
the optional clock source below minimum ADC clock operating
frequency.
3.7.2 CMP configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
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n no 22% 2: 35a
Signal multiplexing
Module signals
Register
access
CMP
Peripheral
bridge 0
Other peripherals
Figure 3-19. CMP configuration
Table 3-28. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP instantiation information
The device includes one high-speed comparator and two 8-input multiplexers for both the
inverting and non-inverting inputs of the comparator. Each CMP input channel connects
to both muxes. Two of the channels are connected to internal sources, leaving resources
to support up to 6 input pins. See the channel assignment table for a summary of CMP
input connections for this device.
The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which
provides a selectable voltage reference for applications where voltage reference is needed
for internal connection to the CMP.
The CMP can be optionally on in all modes except VLLS0.
The CMP has several module-to-module interconnects in order to facilitate ADC
triggering, TPM triggering, and UART IR interfaces. For complete details on the CMP
module interconnects, see the Module-to-Module section.
The CMP does not support window compare function and a 0 must always be written to
CMP_CR1[WE]. The sample function has limited functionality since the SAMPLE input
to the block is not connected to a valid input. Usage of sample operation is limited to a
divided version of the bus clock (CMP_CR1[SE] = 0).
Analog
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64 Freescale Semiconductor, Inc.
Due to the pin number limitation, the CMP pass through mode is not supported by this
device, so the CMPx_MUXCR[PSTM] must be left as 0.
3.7.2.2 CMP input connections
The following table shows the fixed internal connections to the CMP.
Table 3-29. CMP input connections
CMP inputs CMP0
IN0 CMP0_IN0
IN1 CMP0_IN1
IN2 CMP0_IN2
IN3 CMP0_IN3
IN4 —
IN5 —
IN6 Bandgap1
IN7 6-bit DAC0 reference
1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by
setting PMC_REGSC[BGBE]. See the device data sheet for the bandgap voltage (VBG) specification.
3.7.2.3 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the
references are connected as follows:
• VREFH–Vin1 input. When using VREFH, any ADC conversion using this same
reference at the same time is negatively impacted.
• VDD–Vin2 input
3.7.2.4 CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when
CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a
compare sequence that must first enable the CMP and DAC prior to performing a CMP
operation and capturing the output. In this device, control for this two-staged sequencing
is provided from the LPTMR. The LPTMR triggering output is always enabled when the
LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is
asserted at the same time as the TCF flag is set. The delay to the second signal that
triggers the CMP to capture the result of the compare operation is dependent on the
LPTMR configuration.
Chapter 3 Chip Configuration
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2:29.32 :23
In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output
period.
In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock
period.
The delay between the first signal from LPTMR and the second signal from LPTMR
must be greater than the analog comparator initialization delay as defined in the device
datasheet.
3.8 Timers
3.8.1 Timer/PWM module configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
TPM
Peripheral bus
controller 0
Other peripherals
Figure 3-20. TPM configuration
Table 3-30. Reference links to related information
Topic Related module Reference
Full description Timer/PWM module Timer/PWM module
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
Timers
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
66 Freescale Semiconductor, Inc.
3.8.1.1 TPM instantiation information
This device contains two low power TPM modules (TPM). All TPM modules in the
device are configured only as basic TPM function, do not support quadrature decoder
function, and all can be functional in Stop/VLPS mode. The clock source is either
external or internal in Stop/VLPS mode.
The following table shows how these modules are configured.
Table 3-31. TPM configuration
TPM instance Number of channels Features/usage
TPM0 2 Basic TPM,functional in Stop/VLPS mode
TPM1 2 Basic TPM,functional in Stop/VLPS mode
There are several connections to and from the TPMs in order to facilitate customer use
cases. For complete details on the TPM module interconnects please refer to the Module-
to-Module section.
3.8.1.2 Clock options
The TPM blocks are clocked from a single TPM clock that can be selected from
OSCERCLK, MCGIRCLK, or MCGFLLCLK. The selected source is controlled by
SIM_SOPT2[TPMSRC] .
Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the
counter increments after a synchronized (to the selected TPM clock source) rising edge
detect of an external clock input. The available external clock (either TPM_CLKIN0 or
TPM_CLKIN1) is selected by SIM_SOPT4[TPMxCLKSEL] control register. To
guarantee valid operation the selected external clock must be less than half the frequency
of the selected TPM clock source.
3.8.1.3 Trigger options
Each TPM has a selectable trigger input source controlled by the
TPMx_CONF[TRGSEL] field to use for starting the counter and/or reloading the
counter. The options available are shown in the following table.
Table 3-32. TPM trigger options
TPMx_CONF[TRGSEL] Selected source
0000 External trigger pin input (EXTRG_IN)
Table continues on the next page...
Chapter 3 Chip Configuration
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Freescale Semiconductor, Inc. 67
Table 3-32. TPM trigger options (continued)
TPMx_CONF[TRGSEL] Selected source
0001 CMP0 output
0010 Reserved
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 TPM0 overflow
1001 TPM1 overflow
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 LPTMR trigger
1111 Reserved
3.8.1.4 Global timebase
Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit.
TPM1 is configured as the global time when this option is enabled.
3.8.1.5 TPM interrupts
The TPM has multiple sources of interrupt. However, these sources are OR'd together to
generate a single interrupt request to the interrupt controller. When an TPM interrupt
occurs, read the TPM status registers to determine the exact interrupt source.
3.8.2 Low-power timer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Timers
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68 Freescale Semiconductor, Inc.
222%? Ram
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
Low-power timer
Figure 3-21. LPT configuration
Table 3-33. Reference links to related information
Topic Related module Reference
Full description Low-power timer Low-power timer
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal Multiplexing Port control Signal multiplexing
3.8.2.1 LPTMR instantiation information
The low-power timer (LPTMR) allows operation during all power modes. The LPTMR
can operate as a real-time interrupt or pulse accumulator. It includes a 2N prescaler (real-
time interrupt mode) or glitch filter (pulse accumulator mode).
The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO,
OSCERCLK, or an external 32.768 kHz crystal.
An interrupt is generated (and the counter may reset) when the counter equals the value
in the 16-bit compare register.
3.8.2.2 LPTMR pulse counter input options
LPTMR_CSR[TPS] configures the input source used in pulse counter mode. The
following table shows the chip-specific input assignments for this field.
LPTMR_CSR[TPS] Pulse counter input number Chip input
00 0 CMP0 output
01 1 LPTMR_ALT1 pin
10 2 LPTMR_ALT2 pin
Table continues on the next page...
Chapter 3 Chip Configuration
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nu .m
LPTMR_CSR[TPS] Pulse counter input number Chip input
11 3 LPTMR_ALT3 pin
3.8.2.3 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four
sources determined by LPTMR0_PSR[PCS]. The following table shows the chip-specific
clock assignments for this field.
NOTE
The chosen clock must remain enabled if the LPTMR is to
continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock
number Chip clock
00 0 MCGIRCLK—internal reference clock
(not available in VLLS modes)
01 1 LPO—1 kHz clock (not available in
VLLS0 mode)
10 2 ERCLK32K (not available in VLLS0
mode when using 32 kHz oscillator)
11 3 OSCERCLK—external reference clock
(not available in VLLS0 mode)
See Clock Distribution for more details on these clocks.
3.9 Communication interfaces
3.9.1 SPI configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Communication interfaces
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
70 Freescale Semiconductor, Inc.
Signal
multiplexing
Register
access
SPI
Peripheral
bridge
Module signals
Figure 3-22. SPI configuration
Table 3-34. Reference links to related information
Topic Related module Reference
Full description SPI SPI
System memory map System memory map
Clocking — Clock distribution
Signal multiplexing Port control Signal multiplexing
3.9.1.1 SPI instantiation information
This device contains one SPI module that supports 8-bit data length.
SPI0 is clocked on the bus clock.
The SPI can operate in VLPS mode. When the SPI is operating in VLPS mode, it will
operate as a slave.
SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode.
3.9.2 I2C configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
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uu .m 22% E Ema
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
2
I C
Figure 3-23. I2C configuration
Table 3-35. Reference links to related information
Topic Related module Reference
Full description I2CI2C
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.9.2.1 IIC instantiation information
This device has two IIC modules. IIC0 is clocked by the bus clock and IIC1 is clocked by
the system clock. Clocking IIC1 at the faster system clock is needed to support standard
IIC communication rates of 100 kbit/s in VLPR mode.
When the package pins associated with IIC have their mux select configured for IIC
operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration.
The digital glitch filter implemented in the IIC0 module, controlled by the
I2C0_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in
bus clock cycle counts.
The digital glitch filter implemented in the IIC1 module, controlled by the
I2C1_FLT[FLT] registers, is clocked from the system clock and thus has filter
granularity in system clock cycle counts.
3.9.3 UART configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Communication interfaces
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72 Freescale Semiconductor, Inc.
2:29.32 Ema
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
UART
Figure 3-24. UART configuration
Table 3-36. Reference links to related information
Topic Related module Reference
Full description UART0 UART
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.9.3.1 UART0 overview
The UART0 module supports basic UART, x4 to x32 oversampling of baud-rate.
This module supports LIN slave operation.
The module can remain functional in VLPS mode provided the clock it is using remains
enabled.
ISO7816 protocol is intended to be handled in software for this product. To support smart
card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like
ISO7816 communication via SIM_SOPT5[UART0ODE].
3.10 Human-machine interfaces (HMI)
Chapter 3 Chip Configuration
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953522: Eggm Soc 32‘ $.50 25
3.10.1 GPIO configuration
Signal multiplexing
Register
access
Peripheral
bridge
Module signals
GPIO controller
ARM Cortex -M0+
Core
Register access
Figure 3-25. GPIO configuration
Table 3-37. Reference links to related information
Topic Related module Reference
Full description GPIO GPIO
System memory map System memory map
Clocking — Clock distribution
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Signal multiplexing Port control Signal multiplexing
3.10.1.1 GPIO instantiation information
The device includes four pins, PTB0, PTB1, PTA12, and PTA13, with high current drive
capability. These pins can be used to drive LED or power MOSFET directly. The high
drive capability applies to all functions which are multiplexed on these pins (UART,
TPM, SPI...etc)
The device includes two pins, PTB3 and PTB4, with true open drain setting. These pins
have the capability to support 5 V voltage input in 3.3 V systems.
3.10.1.1.1 Pull devices and directions
The pull devices are enabled out of POR only on RESET_b, NMI_b and respective SWD
signals. Other pins can be enabled by writing to PORTx_PCRn[PE].
All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected
in the PORTx_PCRn[PS] field.
Human-machine interfaces (HMI)
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74 Freescale Semiconductor, Inc.
3.10.1.2 Port control and interrupt summary
The following table provides more information regarding the Port Control and Interrupt
configurations .
Table 3-38. Ports summary
Feature Port A Port B
Pull select control No No
Pull select at reset PTA0=Pull down, Others=Pull up Pull up
Pull enable control Yes Yes
Pull enable at reset PTA0/PTA2/RESET_b=Enabled;
Others=Disabled
PTB5=Enabled; Others=Disabled
Slew rate enable control No No
Slew rate enable at reset PTA2/PTA6/PTA7=Disabled;
Others=Enabled
PTB0= Disabled; Others=Enabled
Passive filter enable control RESET_b only PTB5 only
Passive filter enable at reset RESET_b=Enabled; Others=Disabled Disabled
Open drain enable control1No No
Open drain enable at reset Disabled Disabled
Drive strength enable control PTA12/PTA13 only PTB0/PTB1 only
Drive strength enable at reset Disabled Disabled
Pin mux control Yes Yes
Pin mux at reset PTA0/PTA2=ALT3; Others=ALT0 PTB5=ALT3; Others=ALT0
Lock bit No No
Interrupt request PTA0/PTA1/PTA7/PTA10/PTA11/PTA12
only
PTB0/PTB1/PTB2/PTB3/PTB4/PTB5/
PTB6/PTB7 only
Digital glitch filter No No
1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open
drain when selected.
3.10.1.3 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000. It can also be accessed by the core through the cross bar/
AIPS interface at 0x400F_F000 and at an aliased slot (15) at address 0x4000_F000. All
BME operations to the GPIO space can be accomplished referencing the aliased slot (15)
at address 0x4000_F000. Only some of the BME operations can be accomplished
referencing GPIO at address 0x400F_F000.
Chapter 3 Chip Configuration
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Human-machine interfaces (HMI)
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76 Freescale Semiconductor, Inc.
Chapter 4
Memory Map
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. This chapter describes the memory and peripheral
locations within that memory space.
4.2 System memory map
The following table shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit address range Destination slave Access
0x0000_0000–0x07FF_FFFF1Program flash and read-only data
(Includes exception vectors in first 196 bytes)
Cortex-M0+ core
0x0800_0000–0x1FFF_FBFF Reserved
0x1FFF_FC00–0x1FFF_FFFF2SRAM_L: Lower SRAM Cortex-M0+ core
0x2000_0000–0x2000_0BFF2SRAM_U: Upper SRAM Cortex-M0+ core
0x2000_0C00–0x3FFF_FFFF Reserved
0x4000_0000–0x4007_FFFF AIPS Peripherals Cortex-M0+ core
0x4008_0000–0x400F_EFFF Reserved
0x400F_F000–0x400F_FFFF General-purpose input/output (GPIO) Cortex-M0+ core
0x4010_0000–0x43FF_FFFF Reserved
0x4400_0000–0x5FFF_FFFF Bit Manipulation Engine (BME) access to AIPS Peripherals for
slots 0-1273Cortex-M0+ core
0x6000_0000–0xDFFF_FFFF Reserved
0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M0+ core
0xE010_0000–0xEFFF_FFFF Reserved
0xF000_0000–0xF000_0FFF Micro Trace Buffer (MTB) registers Cortex-M0+ core
0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core
Table continues on the next page...
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Table 4-1. System memory map (continued)
System 32-bit address range Destination slave Access
0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core
0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core
0xF000_4000–0xF7FF_FFFF Reserved
0xF800_0000–0xFFFF_FFFF IOPORT: GPIO (single cycle) Cortex-M0+ core
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See Flash memory sizes for details.
2. This range varies depending on SRAM sizes. See SRAM ranges for details.
3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
4.3 Flash memory map
The flash memory and the flash registers are located at different base addresses as shown
in the following figure. The base address for each is specified in System memory map.
Flash
Flash configuration field
Flash base address
Flash memory base address
Registers
Figure 4-1. Flash memory map
The on-chip flash memory is implemented in a portion of the allocated Flash range to
form a contiguous block in the memory map beginning at address 0x0000_0000. See
Flash and EEPROM memory sizes for details of supported ranges.
Access to the flash memory ranges outside the amount of flash on the device causes the
bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master.
4.3.1 Alternate non-volatile IRC user trim description
The following non-volatile locations (4 bytes) are reserved for custom IRC user trim
supported by some development tools. An alternate IRC trim to the factory loaded trim
can be stored at this location. To override the factory trim, the user software must load
new values into the MCG trim registers.
Flash memory map
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Non-volatile byte address Alternate IRC Trim Value
0x0000_03FC Reserved
0x0000_03FD Reserved
0x0000_03FE (bit 0) SCFTRIM
0x0000_03FE (bit 4:1) FCTRIM
0x0000_03FE (bit 6) FCFTRIM
0x0000_03FF SCTRIM
4.4 SRAM memory map
The on-chip RAM is split between SRAM_L and SRAM_U. The RAM is also
implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in
the memory map. See SRAM ranges for details.
Access to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on
the device causes the bus cycle to be terminated with an error followed by the appropriate
response in the requesting bus master.
4.5 Bit Manipulation Engine
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify-
write memory operations to the peripheral address space. By combining the basic load
and store instruction support in the Cortex-M instruction set architecture with the concept
of decorated storage provided by the BME, the resulting implementation provides a
robust and efficient read-modify-write capability to this class of ultra low-end
microcontrollers. See the Bit Manipulation Engine Block Guide (BME) for a detailed
description of BME functionality.
4.6 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via one slave port on the crossbar in the
0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that
defines a 1024 KB address space.
The three regions associated with this space are:
A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on-
platform peripheral devices. The AIPS controller generates unique module enables
for all 32 spaces.
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A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. The AIPS controller generates unique module enables for all 96
spaces.
The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO
module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly
interfaced to the core and provides direct access without incurring wait states
associated with accesses via the AIPS controller.
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.6.1 Read-after-write sequence and required serialization of
memory operations
In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:
Exiting an interrupt service routine (ISR)
Changing a mode
Configuring a function
In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
4.6.2 Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments
System 32-bit base address Slot
number
Module
0x4000_0000 0 —
0x4000_1000 1 —
0x4000_2000 2 —
0x4000_3000 3 —
Table continues on the next page...
Peripheral bridge (AIPS-Lite) memory map
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Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
Module
0x4000_4000 4 —
0x4000_5000 5 —
0x4000_6000 6 —
0x4000_7000 7 —
0x4000_8000 8 —
0x4000_9000 9 —
0x4000_A000 10 —
0x4000_B000 11 —
0x4000_C000 12 —
0x4000_D000 13 —
0x4000_E000 14 —
0x4000_F000 15 GPIO controller (aliased to 0x400F_F000)
0x4001_0000 16 —
0x4001_1000 17 —
0x4001_2000 18 —
0x4001_3000 19 —
0x4001_4000 20 —
0x4001_5000 21 —
0x4001_6000 22 —
0x4001_7000 23 —
0x4001_8000 24 —
0x4001_9000 25 —
0x4001_A000 26 —
0x4001_B000 27 —
0x4001_C000 28 —
0x4001_D000 29 —
0x4001_E000 30 —
0x4001_F000 31 —
0x4002_0000 32 Flash memory
0x4002_1000 33 —
0x4002_2000 34 —
0x4002_3000 35 —
0x4002_4000 36 —
0x4002_5000 37 —
0x4002_6000 38 —
0x4002_7000 39 —
0x4002_8000 40 —
0x4002_9000 41 —
0x4002_A000 42 —
Table continues on the next page...
Chapter 4 Memory Map
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rump
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
Module
0x4002_B000 43 —
0x4002_C000 44 —
0x4002_D000 45 —
0x4002_E000 46 —
0x4002_F000 47 —
0x4003_0000 48 —
0x4003_1000 49 —
0x4003_2000 50 —
0x4003_3000 51 —
0x4003_4000 52 —
0x4003_5000 53 —
0x4003_6000 54 —
0x4003_7000 55 —
0x4003_8000 56 Timer'/PWM (TPM) 0
0x4003_9000 57 Timer'/PWM (TPM) 1
0x4003_A000 58 —
0x4003_B000 59 Analog-to-digital converter (ADC) 0
0x4003_C000 60 —
0x4003_D000 61 —
0x4003_E000 62 —
0x4003_F000 63 —
0x4004_0000 64 Low-power timer (LPTMR)
0x4004_1000 65 —
0x4004_2000 66 —
0x4004_3000 67 —
0x4004_4000 68 —
0x4004_5000 69 —
0x4004_6000 70 —
0x4004_7000 71 SIM low-power logic
0x4004_8000 72 System integration module (SIM)
0x4004_9000 73 Port A multiplexing control
0x4004_A000 74 Port B multiplexing control
0x4004_B000 75 —
0x4004_C000 76 —
0x4004_D000 77 —
0x4004_E000 78 —
0x4004_F000 79 —
0x4005_0000 80 —
0x4005_1000 81 —
Table continues on the next page...
Peripheral bridge (AIPS-Lite) memory map
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Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
Module
0x4005_2000 82 —
0x4005_3000 83 —
0x4005_4000 84 —
0x4005_5000 85 —
0x4005_6000 86 —
0x4005_7000 87 —
0x4005_8000 88 —
0x4005_9000 89 —
0x4005_A000 90 —
0x4005_B000 91 —
0x4005_C000 92 —
0x4005_D000 93 —
0x4005_E000 94 —
0x4005_F000 95 —
0x4006_0000 96 —
0x4006_1000 97 —
0x4006_2000 98 —
0x4006_3000 99 —
0x4006_4000 100 Multi-purpose clock generator (MCG)
0x4006_5000 101 System oscillator (OSC)
0x4006_6000 102 I2C 0
0x4006_7000 103 I2C 1
0x4006_8000 104 —
0x4006_9000 105 —
0x4006_A000 106 UART 0
0x4006_B000 107 —
0x4006_C000 108 —
0x4006_D000 109 —
0x4006_E000 110 —
0x4006_F000 111 —
0x4007_0000 112 —
0x4007_1000 113 —
0x4007_2000 114 —
0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC)
0x4007_4000 116 —
0x4007_5000 117 —
0x4007_6000 118 SPI 0
0x4007_7000 119 —
0x4007_8000 120 —
Table continues on the next page...
Chapter 4 Memory Map
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rllvd
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
Module
0x4007_9000 121 —
0x4007_A000 122 —
0x4007_B000 123 —
0x4007_C000 124 —
0x4007_D000 125 Power management controller (PMC)
0x4007_E000 126 System mode controller (SMC)
0x4007_F000 127 Reset control module (RCM)
0x400F_F000 128 GPIO controller
4.6.3 Modules restricted access in user mode
In user mode, for MCG, RCM, SIM (slot 71 and 72), SMC, and PMC, reads are allowed,
but writes are blocked and generate bus error.
4.7 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 4-3. PPB memory map
System 32-bit Address Range Resource Additional Range Detail Resource
0xE000_0000–0xE000_DFFF Reserved
0xE000_E000–0xE000_EFFF System Control Space
(SCS)
0xE000_E000–0xE000_E00F Reserved
0xE000_E010–0xE000_E0FF SysTick
0xE000_E100–0xE000_ECFF NVIC
0xE000_ED00–0xE000_ED8F System Control Block
0xE000_ED90–0xE000_EDEF Reserved
0xE000_EDF0–0xE000_EEFF Debug
0xE000_EF00–0xE000_EFFF Reserved
0xE000_F000–0xE00F_EFFF Reserved
0xE00F_F000–0xE00F_FFFF Core ROM Space (CRS)
Private Peripheral Bus (PPB) memory map
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Chapter 5
Clock Distribution
5.1 Introduction
This chapter presents the clock architecture for the device, the overview of the clocks and
includes a terminology section.
The Cortex M0+ resides within a synchronous core platform, where the processor and
bus masters, flash memory, and peripheral clocks can be configured independently. The
clock distribution figure shows how clocks from the MCG and XOSC modules are
distributed to the microcontroller’s other function units. Some modules in the
microcontroller have selectable clock input.
5.2 Programming model
The selection and multiplexing of system clock sources is controlled and programmed via
the MCG module. The setting of clock dividers and module clock gating for the system
are programmed via the SIM module. Refer to the MCG and SIM" sections for detailed
register and bit descriptions.
5.3 High-level device clocking diagram
The following system oscillator, MCG, and SIM module registers control the
multiplexers, dividers, and clock gates shown in the following figure:
OSC MCG SIM
Multiplexers MCG_CxMCG_CxSIM_SOPT1, SIM_SOPT2
Dividers — MCG_CxSIM_CLKDIVx
Clock gates OSC_CR MCG_C1 SIM_SCGCx
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32 kHz IRC
FLL
MCGOUTCLK
MCG
OUTDIV1
4 MHz IRC
OUTDIV4 Flash clock
Bus clock/
EXTAL0
XTAL0
System oscillator
SIM
FRDIV
MCGIRCLK
ERCLK32K
XTAL_CLK OSCERCLK
OSC
logic
Clock options for some
peripherals (see note)
Clock options for
some peripherals
(see note)
MCGFLLCLK
Note: See subsequent sections for details on where these clocks are used.
PMC logic
PMC
LPO
OSCCLK
CG
CG
CG
CG — Clock gate
CG
FCRDIV
Core clock,
platform clock,
and system clock
Figure 5-1. Clocking diagram
5.4 Clock definitions
The following table describes the clocks in the previous block diagram.
Clock name Description
Core clock MCGOUTCLK divided by OUTDIV1
Clocks the ARM Cortex-M0+ core.
Platform clock MCGOUTCLK divided by OUTDIV1
Clocks the crossbar switch and NVIC.
System clock MCGOUTCLK divided by OUTDIV1
Clocks the bus masters directly .
Bus clock System clock divided by OUTDIV4.
Table continues on the next page...
Clock definitions
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Clocks Ihe bus slaves and perwpherals.
Clock name Description
Clocks the bus slaves and peripherals.
Flash clock Flash memory clock
On this device, it is the same as Bus clock.
MCGIRCLK MCG output of the slow or fast internal reference clock
MCGOUTCLK MCG output of either IRC, MCGFLLCLK or MCG's external
reference clock that sources the core, system, bus, and flash
clock.
MCGFLLCLK MCG output of the FLL
MCGFLLCLK may clock some modules. In addition,
this clock is used for UART0 and TPM modules.
OSCCLK System oscillator output of the internal oscillator or sourced
directly from EXTAL. Used as MCG external reference clock.
OSCERCLK System oscillator output sourced from OSCCLK that may
clock some on-chip modules
ERCLK32K Clock source for some modules that is chosen as
OSC32KCLK
LPO PMC 1 kHz output
5.4.1 Device clock summary
The following table provides more information regarding the on-chip clocks.
Table 5-1. Clock summary
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
MCGOUTCLK Up to 48 MHz Up to 4 MHz MCG In all stop modes
except for partial stop
modes.
MCGFLLCLK Up to 48 MHz N/A MCG MCG clock controls are
not enabled and in all
stop modes
Core clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all wait and stop
modes
Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all stop modes
System clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock
divider
In all stop modes and
Compute Operation
Bus clock Up to 24 MHz Up to 1 MHz 1MCGOUTCLK clock
divider
In all stop modes
except for partial
STOP2 mode, and
Compute Operation
SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes
Table continues on the next page...
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Table 5-1. Clock summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
Flash clock Up to 24 MHz Up to 1 MHz in BLPE
Up to 800 kHz in BLPI
MCGOUTCLK clock
divider
In all stop modes
except for partial
STOP2 mode
Internal reference
(MCGIRCLK)
30–40 kHz Slow IRC
or 4 MHz Fast IRC
4 MHz Fast IRC only MCG MCG_C1[IRCLKEN]
cleared,
Stop/VLPS mode and
MCG_C1[IREFSTEN]
cleared, or
VLLS mode
External reference
(OSCERCLK)
Up to 48 MHz (bypass),
30–40 kHz
Up to 16 MHz (bypass),
30–40 kHz
System OSC System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
or VLLS0 and oscillator
not in external clock
mode.
External reference
32kHz
(ERCLK32K)
30–40 kHz 30–40 kHz System OSC System OSC's
OSC_CR[ERCLKEN]
cleared
or VLLS0 and oscillator
not in external clock
mode.
LPO 1 kHz 1 kHz PMC in VLLS0
TPM clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[TPMSRC
]=00 or selected clock
source disabled.
UART0 clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[UART0SR
C]=00 or selected clock
source disabled.
1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 800 kHz if executing from flash.
5.5 Internal clocking requirements
The clock dividers are programmed via the CLKDIV registers of the SIM module. The
following requirements must be met when configuring the clocks for this device:
Internal clocking requirements
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The core, platform, and system clock are programmable from a divide-by-1 through
divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
The frequency of bus clock and flash clock is divided by the system clock and is
programmable from a divide-by-1 through divide-by-8 setting. The bus clock and
flash clock must be programmed to 24 MHz or slower.
The following is a common clock configuration for this device:
Clock Frequency
Core clock 48 MHz
Platform clock 48 MHz
System clock 48 MHz
Bus clock 24 MHz
Flash clock 24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two
bits in the flash memory's FTFA_FOPT register control the reset value of the core clock,
system clock, bus clock, and flash clock dividers as shown in the table given below:
FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Description
00 0x7 (divide by 8) 0x1 (divide by 2) Low power boot
01 0x3 (divide by 4) 0x1 (divide by 2) Low power boot
10 0x1 (divide by 2) 0x1 (divide by 2) Low power boot
11 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot
This gives the user flexibility in selecting between a lower frequency, low-power boot
option and higher frequency, higher power during and after reset.
The flash erased state defaults to fast clocking mode, since these bits reside in flash,
which is logic 1 in the flash erased state. To enable a lower power boot option, program
the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control
bits is cleared, the system is in a slower clock configuration. Upon any system reset, the
clock dividers return to this configurable reset state.
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5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. These dividers must be
programmed prior to entering VLPR mode to guarantee operation. Maximum frequency
limitations for VLPR mode is as follows :
the core/system clocks are less than or equal to 4 MHz, and
the bus and flash clocks are less than or equal to 1 MHz
NOTE
When the MCG is in BLPI and clocking is derived from the
Fast IRC, the clock divider controls (MCG_SC[FCRDIV],
SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4])
must be programmed such that the resulting flash clock nominal
frequency is 800 kHz or less. In this case, one example of
correct configuration is MCG_SC[FCRDIV] = 000b,
SIM_CLKDIV1[OUTDIV1] = 0000b, and
SIM_CLKDIV1[OUTDIV4] = 100b, resulting in a divide-by-5
setting.
5.6 Clock gating
The clock to each module can be individually gated on and off using bits of the SCGCx
registers of the SIM module. These bits are cleared after any reset, which disables the
clock to the corresponding module to conserve power. Prior to initializing a module, set
the corresponding bit in the SCGCx register to enable the clock. Before turning off the
clock, make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The following table summarizes the clocks associated with each module.
Table 5-2. Module clocks
Module Bus interface clock Internal clocks I/O interface clocks
Core modules
ARM Cortex-M0+ core Platform clock Core clock
NVIC Platform clock
DAP Platform clock SWD_CLK
Table continues on the next page...
Clock gating
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Table 5-2. Module clocks (continued)
Module Bus interface clock Internal clocks I/O interface clocks
System modules
Port control Bus clock
Crossbar Switch Platform clock
Peripheral bridges System clock Bus clock
PMC, SIM, RCM Bus clock LPO
Mode controller Bus clock
MCM Platform clock
Watchdog timer Bus clock LPO
Clocks
MCG Bus clock MCGOUTCLK, MCGFLLCLK,
MCGIRCLK, OSCERCLK
OSC Bus clock OSCERCLK
Memory and memory interfaces
Flash Controller Platform clock Flash clock
Flash memory Flash clock
Analog
ADC Bus clock OSCERCLK
CMP Bus clock
Timers
TPM Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1
LPTMR Bus clock LPO, OSCERCLK,
MCGIRCLK, ERCLK32K
Communication interfaces
SPI0 Bus clock SPI0_SCK
I2C0 Bus clock I2C0_SCL
I2C1 System clock I2C1_SCL
UART0 Bus clock UART0 clock
Human-machine interfaces
GPIO Platform clock
5.7.1 PMC 1-kHz LPO clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all
modes of operation, including all low-power modes except VLLS0. This 1-kHz source is
commonly referred to as LPO clock or 1-kHz LPO clock.
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mum: SIM,COPCTRL[COPCLKS]
5.7.2 COP clocking
The COP may be clocked from two clock sources as shown in the following figure.
SIM_COPCTRL[COPCLKS]
COP clock
Bus clock
LPO
Figure 5-2. COP clock generation
5.7.3 LPTMR clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown
in the following figure.
NOTE
The chosen clock must remain enabled if the LPTMRx is to
continue operating in all required low-power modes.
LPTMRx_PSR[PCS]
LPTMRx prescaler/glitch
filter clock
MCGIRCLK
OSCERCLK
ERCLK32K
LPO
Figure 5-3. LPTMRx prescaler/glitch filter clock generation
5.7.4 TPM clocking
The counter for the TPM modules has a selectable clock as shown in the following figure.
Module clocks
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NOTE
The chosen clock must remain enabled if the TPMx is to
continue operating in all required low-power modes.
SIM_SOPT2[TPMSRC]
TPM clock
MCGIRCLK
OSCERCLK
MCGFLLCLK
Figure 5-4. TPM clock generation
5.7.5 UART clocking
The UART0 module has a selectable clock as shown in the following figure.
NOTE
The chosen clock must remain enabled if the UART0 is to
continue operating in all required low-power modes.
UART0 clock
SIM_SOPT2[UART0SRC]
MCGFLLCLK
MCGIRCLK
OSCERCLK
Figure 5-5. UART0 clock generation
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mum:
Module clocks
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Chapter 6
Reset and Boot
6.1 Introduction
The following reset sources are supported in this MCU:
Table 6-1. Reset sources
Reset sources Description
POR reset Power-on reset (POR)
System resets External pin reset (PIN)
Low-voltage detect (LVD)
Computer operating properly (COP) watchdog reset
Multipurpose clock generator loss of clock (LOC) reset
Stop mode acknowledge error (SACKERR)
Software reset (SW)
Lockup reset (LOCKUP)
MDM DAP system reset
Debug reset Debug reset
Each of the system reset sources has an associated bit in the System Reset Status (SRS)
registers. See the Reset Control Module for register details.
The MCU can exit and reset in functional mode where the CPU is executing code
(default) or the CPU is in a debug halted state. There are several boot options that can be
configured. See Boot information for more details.
6.2 Reset
This section discusses basic reset mechanisms and sources. Some modules that cause
resets can be configured to cause interrupts instead. Consult the individual peripheral
chapters for more information.
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6.2.1 Power-on reset (POR)
When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset
condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has
risen above the LVD low threshold (VLVDL). The POR and LVD fields in the Reset
Status Register are set following a POR.
6.2.2 System reset sources
Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:
Reads the start SP (SP_main) from vector-table offset 0
Reads the start PC from vector-table offset 4
LR is set to 0xFFFF_FFFF.
The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them default to their
analog function after reset.
During and following a reset, the SWD pins have their associated input pins configured
as:
SWD_CLK in pulldown (PD)
SWD_DIO in pullup (PU)
6.2.2.1 External pin reset (RESET_b)
This pin is open drain and has an internal pullup device. Asserting RESET_b wakes the
device from any mode.
The RESET_b pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option is selected, there could be a short period of contention during a POR
ramp where the device drives the pin-out low prior to establishing the setting of this
option and releasing the reset function on the pin.
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6.2.2.1.1 RESET_b pin filter
The RESET_b pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. The RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and
RCM_RPFW[RSTFLTSEL] fields set control this functionality; see the RCM chapter.
The filters are asynchronously reset by Chip POR. The reset value for each filter assumes
the RESET_b pin is negated.
For all stop modes where LPO clock is still active (Stop, VLPS, VLLS3, and VLLS1),
the only filtering option is the LPO-based digital filter. The filtering logic either switches
to bypass operation or has continued filtering operation depending on the filtering mode
selected. When entering VLLS0, the RESET_b pin filter is disabled and bypassed.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.
6.2.2.2 Low-voltage detect (LVD)
The chip includes a system for managing low-voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip
voltage. The LVD system is always enabled in Normal Run, Wait, or Stop mode. The
LVD system is disabled when entering VLPx or VLLSx modes.
The LVD can be configured to generate a reset upon detection of a low-voltage condition
by setting PMC_LVDSC1[LVDRE] to 1. The low-voltage detection threshold is
determined by PMC_LVDSC1[LVDV]. After an LVD reset has occurred, the LVD
system holds the MCU in reset until the supply voltage has risen above the low voltage
detection threshold. RCM_SRS0[LVD] is set following either an LVD reset or POR.
6.2.2.3 Computer operating properly (COP) watchdog timer
The computer operating properly (COP) watchdog timer (WDOG) monitors the operation
of the system by expecting periodic communication from the software. This
communication is generally known as servicing (or refreshing) the COP watchdog. If this
periodic refreshing does not occur, the watchdog issues a system reset. The COP reset
causes RCM_SRS0[WDOG] to set.
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6.2.2.4 Multipurpose clock generator loss-of-clock (LOC)
The MCG module supports an external reference clock.
If MCG_C6[CME] is set, the clock monitor is enabled. If the external reference falls
below floc_low or floc_high, as controlled by MCG_C2[RANGE], the MCU resets.
RCM_SRS0[LOC] is set to indicate this reset source.
NOTE
To prevent unexpected loss of clock reset events, all clock
monitors must be disabled before entering any low-power
modes, including VLPR and VLPW.
6.2.2.5 Stop mode acknowledge error (SACKERR)
This reset is generated if the core attempts to enter Stop mode or Compute Operation, but
not all modules acknowledge Stop mode within 1025 cycles of the 1 kHz LPO clock.
A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.
6.2.2.6 Software reset (SW)
The SYSRESETREQ field in the NVIC Application Interrupt and Reset Control register
can be set to force a software reset on the device. (See ARM's NVIC documentation for
the full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes
RCM_SRS1[SW] to set.
6.2.2.7 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes RCM_SRS1[LOCKUP] to
set.
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6.2.2.8 MDM-AP system reset request
Set the System Reset Request field in the MDM-AP control register to initiate a system
reset. This is the primary method for resets via the SWD interface. The system reset is
held until this field is cleared.
Set the Core Hold Reset field in the MDM-AP control register to hold the core in reset as
the rest of the chip comes out of system reset.
6.2.3 MCU resets
A variety of resets are generated by the MCU to reset different modules.
6.2.3.1 POR Only
The POR Only reset asserts on the POR reset source only. It resets the PMC.
The POR Only reset also causes all other reset types to occur.
6.2.3.2 Chip POR not VLLS
The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of
the SMC and SIM. It also resets the LPTMR.
The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset
not VLLS, and Chip Reset (including Early Chip Reset).
6.2.3.3 Chip POR
The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the
Reset Pin Filter registers and parts of the SIM and MCG.
The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur.
6.2.3.4 Chip Reset not VLLS
The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that
does not occur via the RESET_b pin. It resets parts of the SMC and other modules that
remain powered during VLLS mode.
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The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset)
to occur.
6.2.3.5 Early Chip Reset
The Early Chip Reset asserts on all reset sources. It resets only the flash memory module.
It negates before flash memory initialization begins ("earlier" than when the Chip Reset
negates).
6.2.3.6 Chip Reset
Chip Reset asserts on all reset sources and only negates after flash initialization has
completed and the RESET_b pin has also negated. It resets the remaining modules (the
modules not reset by other reset types).
6.2.4 RESET_b pin
For all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin,
the RESET_b pin is driven low by the MCU for at least 128 bus clock cycles and until
flash initialization has completed.
After flash initialization has completed, the RESET_b pin is released, and the internal
Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin
asserted externally delays the negation of the internal Chip Reset.
The RESET_b pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG]
option bit to 0 (See Table 6-2). When this option is selected, there could be a short period
of contention during a POR ramp where the device drives the pinout low prior to
establishing the setting of this option and releasing the RESET function on the pin.
6.2.5 Debug resets
The following sections detail the debug resets available on the device.
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6.2.5.1 Resetting the Debug subsystem
Use the CDBGRSTREQ field within the DP CTRL/STAT register to reset the debug
modules. However, as explained below, using the CDBGRSTREQ field does not reset all
debug-related registers.
CDBGRSTREQ resets the debug-related registers within the following modules:
• SW-DP
• AHB-AP
MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• BPU
• DWT
• NVIC
Crossbar bus switch1
• AHB-AP1
Private peripheral bus1
6.3 Boot
This section describes the boot sequence, including sources and options.
Some configuration information such as clock trim values stored in factory programmed
flash locations is autoloaded.
6.3.1 Boot sources
The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR)
to relocate the exception vector table. This device supports booting from internal flash
and RAM.
This device supports booting from internal flash with the reset vectors located at
addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception
vector table to RAM.
1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available
during System Reset.
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6.3.2 FOPT boot options
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains read-
only bits that are loaded from the NVM's option byte in the flash configuration field. The
default setting for all values in the FTFA_FOPT register is logic 1 since it is copied from
the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To
configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings will take effect on subsequent POR, VLLSx recoveries, and any system
reset. For more details on programming the option byte, see the flash memory chapter.
The MCU uses the FTFA_FOPT register bits to configure the device at reset as shown in
the following table.
Table 6-2. Flash Option Register (FTFA_FOPT) bit definitions
Bit
Num
Field Value Definition
7-6 Reserved Reserved for future expansion.
5 FAST_INIT Selects initialization speed on POR, VLLSx, and any system reset .
0 Slower initialization: The flash initialization will be slower with the benefit of
reduced average current during this time. The duration of the recovery will be
controlled by the clock divider selection determined by the LPBOOT setting.
1 Fast Initialization: The flash has faster recoveries at the expense of higher current
during these times.
3 RESET_PIN_CFG Enables/disables control for the RESET pin.
0 RESET_b pin is disabled following a POR and cannot be enabled as reset
function. When this option is selected, there could be a short period of contention
during a POR ramp where the device drives the pinout low prior to establishing the
setting of this option and releasing the reset function on the pin.
This bit is preserved through system resets and low-power modes. When
RESET_b pin function is disabled, it cannot be used as a source for low-power
mode wake-up.
NOTE: When the reset pin has been disabled and security has been enabled by
means of the FSEC register, a mass erase can be performed only by
setting both the Mass Erase and System Reset Request fields in the
MDM-AP register.
1 RESET_b pin is dedicated. The port is configured with pullup enabled, open drain,
passive filter enabled.
2 NMI_DIS Enables/disables control for the NMI function.
0 NMI interrupts are always blocked. The associated pin continues to default to
NMI_b pin controls with internal pullup enabled. When NMI_b pin function is
disabled, it cannot be used as a source for low-power mode wake-up.
1 NMI_b pin/interrupts reset default to enabled.
1 Reserved Reserved for future expansion.
Table continues on the next page...
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Table 6-2. Flash Option Register (FTFA_FOPT) bit definitions
(continued)
Bit
Num
Field Value Definition
4,0 LPBOOT Controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register. Larger divide value
selections produce lower average power consumption during POR, VLLSx recoveries and
reset sequencing and after reset exit. The recovery times are also extended if the
FAST_INIT option is not selected.
00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).
01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).
10 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2).
11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1).
6.3.3 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply
exceeds the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Reset Controller logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET_b pin is driven out low, and the
MCG is enabled in its default clocking mode.
2. Required clocks are enabled (system clock, flash clock, and any bus clocks that do
not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Reset Control logic
continues to drive the RESET_b pin out low.
4. Early in reset sequencing, the NVM option byte is read and stored to the FOPT
register of the Flash Memory module (FTFA_FOPT). If the bits associated with
FTFA_FOPT[LPBOOT] are programmed for an alternate clock divider reset value,
the system/core clock is switched to a slower clock speed. If
FTFA_FOPT[FAST_INIT] is programmed clear, the flash initialization switches to
slower clock resulting longer recovery times.
5. When flash Initialization completes, the RESET_b pin is released. If RESET_b
continues to be asserted (an indication of a slow rise time on the RESET_b pin or
external drive in low), the system continues to be held in reset. Once the RESET_b
pin is detected high, the core clock is enabled and the system is released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
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0xFFFF_FFFF. The next sequence of events depends on the NMI_b input and
FTFA_FOPT[NMI_DIS] (See Table 6-2) :
If the NMI_b input is high or the NMI function is disabled in the FOPT register,
the CPU begins execution at the PC location.
If the NMI_b input is low and the NMI function is enabled in the FOPT register,
this results in an NMI interrupt. The processor executes an Exception Entry and
reads the NMI interrupt handler address from vector-table offset 8. The CPU
begins execution at the NMI interrupt handler.
Subsequent system resets follow this same reset flow.
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Chapter 7
Power Management
7.1 Introduction
This chapter describes the various chip power modes and functionality of the individual
modules in these modes.
7.2 Clocking modes
This section describes the various clocking modes supported on this device.
7.2.1 Partial Stop
Partial Stop is a clocking option that can be taken instead of entering Stop mode and is
configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is
only partially entered, which leaves some additional functionality alive at the expense of
higher power consumption. Partial Stop can be entered from either Run mode or VLP
Run mode.
When configured for PSTOP2, only the core and system clocks are gated and the bus
clock remains active. The bus masters and bus slaves clocked by the system clock enter
Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode.
The clock generators in the MCG and the on-chip regulator in the PMC also remain in
Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous
interrupt from a bus master or bus slave clocked by the system clock, or a synchronous
interrupt from a bus slave clocked by the bus clock.
PSTOP2 is functionally similar to WAIT mode, but offers additional power savings
through the gating of the System clock. All the bus masters are disabled.
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vluuk
When configured for PSTOP1, both the system clock and bus clock are gated. All bus
masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on-
chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be
initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of
higher power consumption. Another benefit is that it keeps all of the MCG clocks
enabled, which can be useful for some of the asynchronous peripherals that can remain
functional in Stop modes.
7.2.2 Compute Operation
Compute Operation is an execution or compute-only mode of operation that keeps the
CPU enabled with full access to the SRAM and Flash read port, but places all other bus
masters and bus slaves into their stop mode. Compute Operation can be enabled in either
Run mode or VLP Run mode.
NOTE
Do not enter any Stop mode without first exiting Compute
Operation.
Because Compute Operation reuses the Stop mode logic (including the staged entry with
bus masters disabled before bus slaves), any bus master or bus slave that can remain
functional in Stop mode also remains functional in Compute Operation, including
generation of asynchronous interrupts requests. When enabling Compute Operation in
Run mode, module functionality for bus masters and slaves is the equivalent of STOP
mode. When enabling Compute Operation in VLP Run mode, module functionality for
bus masters and slaves is the equivalent of VLPS mode. The MCG, PMC, SRAM, and
Flash read port are not affected by Compute Operation, although the Flash register
interface is disabled.
During Compute Operation, the AIPS peripheral space is disabled and attempted accesses
generate bus errors. The private peripheral space remains accessible during Compute
Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the
GPIO registers via the IOPORT is supported, the GPIO port data input registers do not
return valid data since clocks are disabled to the Port Control and Interrupt modules. By
writing to the GPIO port data output registers, it is possible to control those GPIO ports
that are configured as output pins.
Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which
is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry
or exit into Compute Operation. Compute Operation can also be configured to exit
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automatically on detection of an interrupt, which is required in order to service most
interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and
any edge-sensitive interrupts can be serviced without exiting Compute Operation.
When entering Compute Operation, the CPOACK status field in the CPO register of
MCM module (MCM_CPO[CPOACK]) indicates when entry has completed.
When exiting Compute Operation in Run mode, MCM_CPO[CPOACK] negates
immediately.
When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the
PMC to handle the change in power consumption. This delay means that
MCM_CPO[CPOACK] is polled to determine when the AIPS peripheral space can
be accessed without generating a bus error.
7.2.3 Peripheral Doze
Several peripherals support a Peripheral Doze mode, where a register bit can be used to
disable the peripheral for the duration of a low-power mode. The flash memory can also
be placed in a low-power state during Peripheral Doze via a register bit in the SIM.
Peripheral Doze is defined to include all of the modes of operation listed below.
The CPU is in Wait mode.
The CPU is in Stop mode, including the entry sequence.
The CPU is in Compute Operation, including the entry sequence.
Peripheral Doze can therefore be used to disable selected bus masters or slaves for the
duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves
immediately on entry into any stop mode (or Compute Operation), instead of waiting for
the bus masters to acknowledge the entry as part of the stop entry sequence.
If the flash memory is not being accessed during WAIT and PSTOP modes, then the
Flash Doze mode can be used to reduce power consumption, at the expense of a slightly
longer wake-up when executing code and vectors from flash. It can also be used to reduce