K60_LQ/MD10 Ref Manual Datasheet by Rochester Electronics, LLC

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K60 Sub-Family Reference Manual
Supports: MK60DN256VLQ10, MK60DX256VLQ10,
MK60DN512VLQ10, MK60DN256VMD10, MK60DX256VMD10,
MK60DN512VMD10
Document Number: K60P144M100SF2V2RM
Rev. 2 Jun 2012
Preliminary
General Business Information
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................59
1.1.1 Purpose.........................................................................................................................................................59
1.1.2 Audience......................................................................................................................................................59
1.2 Conventions..................................................................................................................................................................59
1.2.1 Numbering systems......................................................................................................................................59
1.2.2 Typographic notation...................................................................................................................................60
1.2.3 Special terms................................................................................................................................................60
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................61
2.2 Module Functional Categories......................................................................................................................................61
2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................62
2.2.2 System Modules...........................................................................................................................................63
2.2.3 Memories and Memory Interfaces...............................................................................................................64
2.2.4 Clocks...........................................................................................................................................................65
2.2.5 Security and Integrity modules....................................................................................................................65
2.2.6 Analog modules...........................................................................................................................................66
2.2.7 Timer modules.............................................................................................................................................66
2.2.8 Communication interfaces...........................................................................................................................67
2.2.9 Human-machine interfaces..........................................................................................................................68
2.3 Orderable part numbers.................................................................................................................................................68
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................71
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3.2 Core modules................................................................................................................................................................71
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................71
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................73
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................79
3.2.4 JTAG Controller Configuration...................................................................................................................81
3.3 System modules............................................................................................................................................................81
3.3.1 SIM Configuration.......................................................................................................................................81
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................82
3.3.3 PMC Configuration......................................................................................................................................83
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................84
3.3.5 MCM Configuration....................................................................................................................................86
3.3.6 Crossbar Switch Configuration....................................................................................................................87
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................89
3.3.8 Peripheral Bridge Configuration..................................................................................................................92
3.3.9 DMA request multiplexer configuration......................................................................................................93
3.3.10 DMA Controller Configuration...................................................................................................................96
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................97
3.3.12 Watchdog Configuration..............................................................................................................................99
3.4 Clock modules..............................................................................................................................................................100
3.4.1 MCG Configuration.....................................................................................................................................100
3.4.2 OSC Configuration......................................................................................................................................101
3.4.3 RTC OSC configuration...............................................................................................................................102
3.5 Memories and memory interfaces.................................................................................................................................102
3.5.1 Flash Memory Configuration.......................................................................................................................102
3.5.2 Flash Memory Controller Configuration.....................................................................................................106
3.5.3 SRAM Configuration...................................................................................................................................107
3.5.4 SRAM Controller Configuration.................................................................................................................111
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3.5.5 System Register File Configuration.............................................................................................................111
3.5.6 VBAT Register File Configuration..............................................................................................................112
3.5.7 EzPort Configuration...................................................................................................................................113
3.5.8 FlexBus Configuration.................................................................................................................................114
3.6 Security.........................................................................................................................................................................117
3.6.1 CRC Configuration......................................................................................................................................117
3.6.2 MMCAU Configuration...............................................................................................................................118
3.6.3 RNG Configuration......................................................................................................................................119
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3.7 Analog...........................................................................................................................................................................119
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................119
3.7.2 CMP Configuration......................................................................................................................................127
3.7.3 12-bit DAC Configuration...........................................................................................................................129
3.7.4 VREF Configuration....................................................................................................................................130
3.8 Timers...........................................................................................................................................................................131
3.8.1 PDB Configuration......................................................................................................................................131
3.8.2 FlexTimer Configuration.............................................................................................................................134
3.8.3 PIT Configuration........................................................................................................................................138
3.8.4 Low-power timer configuration...................................................................................................................139
3.8.5 CMT Configuration......................................................................................................................................141
3.8.6 RTC configuration.......................................................................................................................................142
3.9 Communication interfaces............................................................................................................................................143
3.9.1 Ethernet Configuration.................................................................................................................................143
3.9.2 Universal Serial Bus (USB) FS Subsystem.................................................................................................146
3.9.3 CAN Configuration......................................................................................................................................151
3.9.4 SPI configuration.........................................................................................................................................153
3.9.5 I2C Configuration........................................................................................................................................156
3.9.6 UART Configuration...................................................................................................................................157
3.9.7 SDHC Configuration....................................................................................................................................160
3.9.8 I2S configuration..........................................................................................................................................162
3.10 Human-machine interfaces...........................................................................................................................................164
3.10.1 GPIO configuration......................................................................................................................................164
3.10.2 TSI Configuration........................................................................................................................................165
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................169
4.2 System memory map.....................................................................................................................................................169
4.2.1 Aliased bit-band regions..............................................................................................................................170
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4.3 Flash Memory Map.......................................................................................................................................................171
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................172
4.4 SRAM memory map.....................................................................................................................................................173
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................173
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................173
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................177
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................181
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................183
5.2 Programming model......................................................................................................................................................183
5.3 High-Level device clocking diagram............................................................................................................................183
5.4 Clock definitions...........................................................................................................................................................184
5.4.1 Device clock summary.................................................................................................................................185
5.5 Internal clocking requirements.....................................................................................................................................187
5.5.1 Clock divider values after reset....................................................................................................................188
5.5.2 VLPR mode clocking...................................................................................................................................188
5.6 Clock Gating.................................................................................................................................................................189
5.7 Module clocks...............................................................................................................................................................189
5.7.1 PMC 1-kHz LPO clock................................................................................................................................191
5.7.2 WDOG clocking..........................................................................................................................................191
5.7.3 Debug trace clock.........................................................................................................................................191
5.7.4 PORT digital filter clocking.........................................................................................................................192
5.7.5 LPTMR clocking..........................................................................................................................................192
5.7.6 Ethernet Clocking........................................................................................................................................193
5.7.7 USB FS OTG Controller clocking...............................................................................................................194
5.7.8 FlexCAN clocking.......................................................................................................................................195
5.7.9 UART clocking............................................................................................................................................195
5.7.10 SDHC clocking............................................................................................................................................195
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5.7.11 I2S/SAI clocking..........................................................................................................................................196
5.7.12 TSI clocking.................................................................................................................................................196
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................199
6.2 Reset..............................................................................................................................................................................200
6.2.1 Power-on reset (POR)..................................................................................................................................200
6.2.2 System reset sources....................................................................................................................................200
6.2.3 MCU Resets.................................................................................................................................................204
6.2.4 Reset Pin .....................................................................................................................................................206
6.2.5 Debug resets.................................................................................................................................................206
6.3 Boot...............................................................................................................................................................................207
6.3.1 Boot sources.................................................................................................................................................207
6.3.2 Boot options.................................................................................................................................................208
6.3.3 FOPT boot options.......................................................................................................................................208
6.3.4 Boot sequence..............................................................................................................................................209
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................211
7.2 Power modes.................................................................................................................................................................211
7.3 Entering and exiting power modes...............................................................................................................................213
7.4 Power mode transitions.................................................................................................................................................214
7.5 Power modes shutdown sequencing.............................................................................................................................215
7.6 Module Operation in Low Power Modes......................................................................................................................215
7.7 Clock Gating.................................................................................................................................................................218
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................219
8.2 Flash Security...............................................................................................................................................................219
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8.3 Security Interactions with other Modules.....................................................................................................................220
8.3.1 Security interactions with FlexBus..............................................................................................................220
8.3.2 Security Interactions with EzPort................................................................................................................220
8.3.3 Security Interactions with Debug.................................................................................................................220
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................223
9.1.1 References....................................................................................................................................................225
9.2 The Debug Port.............................................................................................................................................................225
9.2.1 JTAG-to-SWD change sequence.................................................................................................................226
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................226
9.3 Debug Port Pin Descriptions.........................................................................................................................................227
9.4 System TAP connection................................................................................................................................................227
9.4.1 IR Codes.......................................................................................................................................................227
9.5 JTAG status and control registers.................................................................................................................................228
9.5.1 MDM-AP Control Register..........................................................................................................................229
9.5.2 MDM-AP Status Register............................................................................................................................231
9.6 Debug Resets................................................................................................................................................................232
9.7 AHB-AP........................................................................................................................................................................233
9.8 ITM...............................................................................................................................................................................234
9.9 Core Trace Connectivity...............................................................................................................................................234
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................235
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................236
9.11.1 Performance Profiling with the ETB...........................................................................................................236
9.11.2 ETB Counter Control...................................................................................................................................237
9.12 TPIU..............................................................................................................................................................................237
9.13 DWT.............................................................................................................................................................................237
9.14 Debug in Low Power Modes........................................................................................................................................238
9.14.1 Debug Module State in Low Power Modes.................................................................................................239
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9.15 Debug & Security.........................................................................................................................................................239
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................241
10.2 Signal Multiplexing Integration....................................................................................................................................241
10.2.1 Port control and interrupt module features..................................................................................................242
10.2.2 PCRn reset values for port A.......................................................................................................................242
10.2.3 Clock gating.................................................................................................................................................242
10.2.4 Signal multiplexing constraints....................................................................................................................242
10.3 Pinout............................................................................................................................................................................243
10.3.1 K60 Signal Multiplexing and Pin Assignments...........................................................................................243
10.3.2 K60 Pinouts..................................................................................................................................................249
10.4 Module Signal Description Tables................................................................................................................................251
10.4.1 Core Modules...............................................................................................................................................251
10.4.2 System Modules...........................................................................................................................................252
10.4.3 Clock Modules.............................................................................................................................................253
10.4.4 Memories and Memory Interfaces...............................................................................................................253
10.4.5 Analog..........................................................................................................................................................256
10.4.6 Timer Modules.............................................................................................................................................258
10.4.7 Communication Interfaces...........................................................................................................................261
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................267
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................269
11.2 Overview.......................................................................................................................................................................269
11.2.1 Features........................................................................................................................................................269
11.2.2 Modes of operation......................................................................................................................................270
11.3 External signal description............................................................................................................................................271
11.4 Detailed signal description............................................................................................................................................271
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11.5 Memory map and register definition.............................................................................................................................271
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................277
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................280
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................280
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................281
11.6 Functional description...................................................................................................................................................281
11.6.1 Pin control....................................................................................................................................................281
11.6.2 Global pin control........................................................................................................................................282
11.6.3 External interrupts........................................................................................................................................282
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................285
12.1.1 Features........................................................................................................................................................285
12.2 Memory map and register definition.............................................................................................................................286
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................287
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................289
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................290
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................293
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................295
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................297
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................299
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................300
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................301
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................302
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................304
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................306
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................308
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................310
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................311
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12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................314
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................314
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................317
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................318
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................319
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................319
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................320
12.3 Functional description...................................................................................................................................................320
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................321
13.2 Reset memory map and register descriptions...............................................................................................................321
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................321
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................323
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................324
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................325
13.2.5 Mode Register (RCM_MR).........................................................................................................................327
Chapter 14
System Mode Controller
14.1 Introduction...................................................................................................................................................................329
14.2 Modes of operation.......................................................................................................................................................329
14.3 Memory map and register descriptions.........................................................................................................................331
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................332
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................333
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................334
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................335
14.4 Functional description...................................................................................................................................................336
14.4.1 Power mode transitions................................................................................................................................336
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14.4.2 Power mode entry/exit sequencing..............................................................................................................339
14.4.3 Run modes....................................................................................................................................................341
14.4.4 Wait modes..................................................................................................................................................343
14.4.5 Stop modes...................................................................................................................................................344
14.4.6 Debug in low power modes.........................................................................................................................347
Chapter 15
Power Management Controller
15.1 Introduction...................................................................................................................................................................349
15.2 Features.........................................................................................................................................................................349
15.3 Low-voltage detect (LVD) system................................................................................................................................349
15.3.1 LVD reset operation.....................................................................................................................................350
15.3.2 LVD interrupt operation...............................................................................................................................350
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................350
15.4 I/O retention..................................................................................................................................................................351
15.5 Memory map and register descriptions.........................................................................................................................351
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................352
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................353
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................354
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................357
16.1.1 Features........................................................................................................................................................357
16.1.2 Modes of operation......................................................................................................................................358
16.1.3 Block diagram..............................................................................................................................................359
16.2 LLWU signal descriptions............................................................................................................................................360
16.3 Memory map/register definition...................................................................................................................................361
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................362
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................363
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................364
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16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................365
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................366
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................368
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................369
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................371
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................373
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................374
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................375
16.4 Functional description...................................................................................................................................................376
16.4.1 LLS mode.....................................................................................................................................................376
16.4.2 VLLS modes................................................................................................................................................376
16.4.3 Initialization.................................................................................................................................................377
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................379
17.1.1 Features........................................................................................................................................................379
17.2 Memory map/register descriptions...............................................................................................................................379
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................380
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................381
17.2.3 Control Register (MCM_CR)......................................................................................................................381
17.2.4 Interrupt Status Register (MCM_ISR).........................................................................................................383
17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................384
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................385
17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................385
17.2.8 Process ID register (MCM_PID).................................................................................................................386
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17.3 Functional description...................................................................................................................................................386
17.3.1 Interrupts......................................................................................................................................................386
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................389
18.1.1 Features........................................................................................................................................................389
18.2 Memory Map / Register Definition...............................................................................................................................390
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................391
18.2.2 Control Register (AXBS_CRSn).................................................................................................................394
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................396
18.3 Functional Description..................................................................................................................................................396
18.3.1 General operation.........................................................................................................................................396
18.3.2 Register coherency.......................................................................................................................................398
18.3.3 Arbitration....................................................................................................................................................398
18.4 Initialization/application information...........................................................................................................................401
Chapter 19
Memory Protection Unit (MPU)
19.1 Introduction...................................................................................................................................................................403
19.2 Overview.......................................................................................................................................................................403
19.2.1 Block diagram..............................................................................................................................................403
19.2.2 Features........................................................................................................................................................404
19.3 Memory map/register definition...................................................................................................................................405
19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................409
19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................410
19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................411
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................412
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................412
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................413
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................416
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19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................417
19.4 Functional description...................................................................................................................................................419
19.4.1 Access evaluation macro..............................................................................................................................419
19.4.2 Putting it all together and error terminations...............................................................................................420
19.4.3 Power management......................................................................................................................................421
19.5 Initialization information..............................................................................................................................................421
19.6 Application information................................................................................................................................................421
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................425
20.1.1 Features........................................................................................................................................................425
20.1.2 General operation.........................................................................................................................................426
20.2 Memory map/register definition...................................................................................................................................426
20.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................428
20.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................431
20.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................436
20.3 Functional description...................................................................................................................................................441
20.3.1 Access support.............................................................................................................................................441
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................443
21.1.1 Overview......................................................................................................................................................443
21.1.2 Features........................................................................................................................................................444
21.1.3 Modes of operation......................................................................................................................................444
21.2 External signal description............................................................................................................................................445
21.3 Memory map/register definition...................................................................................................................................445
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................446
21.4 Functional description...................................................................................................................................................447
21.4.1 DMA channels with periodic triggering capability......................................................................................447
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21.4.2 DMA channels with no triggering capability...............................................................................................449
21.4.3 "Always enabled" DMA sources.................................................................................................................449
21.5 Initialization/application information...........................................................................................................................450
21.5.1 Reset.............................................................................................................................................................451
21.5.2 Enabling and configuring sources................................................................................................................451
Chapter 22
Direct Memory Access Controller (eDMA)
22.1 Introduction...................................................................................................................................................................455
22.1.1 Block diagram..............................................................................................................................................455
22.1.2 Block parts...................................................................................................................................................456
22.1.3 Features........................................................................................................................................................457
22.2 Modes of operation.......................................................................................................................................................459
22.3 Memory map/register definition...................................................................................................................................459
22.3.1 Control Register (DMA_CR).......................................................................................................................470
22.3.2 Error Status Register (DMA_ES)................................................................................................................472
22.3.3 Enable Request Register (DMA_ ERQ ).....................................................................................................474
22.3.4 Enable Error Interrupt Register (DMA_ EEI ).............................................................................................476
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................479
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................480
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................481
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................482
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................483
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................484
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................485
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................486
22.3.13 Interrupt Request Register (DMA_ INT )....................................................................................................487
22.3.14 Error Register (DMA_ ERR )......................................................................................................................489
22.3.15 Hardware Request Status Register (DMA_ HRS )......................................................................................492
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................494
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22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................495
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................495
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................496
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................497
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................497
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................498
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................500
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................500
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................501
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................501
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................502
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........503
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................504
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................506
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................507
22.4 Functional description...................................................................................................................................................508
22.4.1 eDMA basic data flow.................................................................................................................................508
22.4.2 Error reporting and handling........................................................................................................................511
22.4.3 Channel preemption.....................................................................................................................................513
22.4.4 Performance.................................................................................................................................................513
22.5 Initialization/application information...........................................................................................................................518
22.5.1 eDMA initialization.....................................................................................................................................518
22.5.2 Programming errors.....................................................................................................................................520
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22.5.3 Arbitration mode considerations..................................................................................................................520
22.5.4 Performing DMA transfers (examples)........................................................................................................521
22.5.5 Monitoring transfer descriptor status...........................................................................................................525
22.5.6 Channel Linking...........................................................................................................................................526
22.5.7 Dynamic programming................................................................................................................................528
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................533
23.1.1 Features........................................................................................................................................................533
23.1.2 Modes of Operation.....................................................................................................................................534
23.1.3 Block Diagram.............................................................................................................................................535
23.2 EWM Signal Descriptions............................................................................................................................................536
23.3 Memory Map/Register Definition.................................................................................................................................536
23.3.1 Control Register (EWM_CTRL).................................................................................................................536
23.3.2 Service Register (EWM_SERV)..................................................................................................................537
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................537
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................538
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................539
23.4 Functional Description..................................................................................................................................................539
23.4.1 The EWM_out Signal..................................................................................................................................539
23.4.2 The EWM_in Signal....................................................................................................................................540
23.4.3 EWM Counter..............................................................................................................................................541
23.4.4 EWM Compare Registers............................................................................................................................541
23.4.5 EWM Refresh Mechanism...........................................................................................................................541
23.4.6 EWM Interrupt.............................................................................................................................................542
23.4.7 Counter clock prescaler................................................................................................................................542
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................543
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24.2 Features.........................................................................................................................................................................543
24.3 Functional overview......................................................................................................................................................545
24.3.1 Unlocking and updating the watchdog.........................................................................................................546
24.3.2 Watchdog configuration time (WCT)..........................................................................................................547
24.3.3 Refreshing the watchdog..............................................................................................................................548
24.3.4 Windowed mode of operation......................................................................................................................548
24.3.5 Watchdog disabled mode of operation.........................................................................................................548
24.3.6 Low-power modes of operation...................................................................................................................549
24.3.7 Debug modes of operation...........................................................................................................................549
24.4 Testing the watchdog....................................................................................................................................................550
24.4.1 Quick test.....................................................................................................................................................550
24.4.2 Byte test........................................................................................................................................................551
24.5 Backup reset generator..................................................................................................................................................552
24.6 Generated resets and interrupts.....................................................................................................................................552
24.7 Memory map and register definition.............................................................................................................................553
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................554
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................555
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................556
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................556
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................557
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................557
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................558
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................558
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................558
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................559
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................559
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................560
24.8 Watchdog operation with 8-bit access..........................................................................................................................560
24.8.1 General guideline.........................................................................................................................................560
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24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................560
24.9 Restrictions on watchdog operation..............................................................................................................................561
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................565
25.1.1 Features........................................................................................................................................................565
25.1.2 Modes of Operation.....................................................................................................................................568
25.2 External Signal Description..........................................................................................................................................569
25.3 Memory Map/Register Definition.................................................................................................................................569
25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................570
25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................571
25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................572
25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................573
25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................574
25.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................575
25.3.7 MCG Status Register (MCG_S)..................................................................................................................577
25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................578
25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................580
25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................580
25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................580
25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................581
25.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................582
25.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................582
25.4 Functional Description..................................................................................................................................................583
25.4.1 MCG mode state diagram............................................................................................................................583
25.4.2 Low Power Bit Usage..................................................................................................................................587
25.4.3 MCG Internal Reference Clocks..................................................................................................................587
25.4.4 External Reference Clock............................................................................................................................588
25.4.5 MCG Fixed frequency clock .......................................................................................................................588
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25.4.6 MCG PLL clock ..........................................................................................................................................589
25.4.7 MCG Auto TRIM (ATM)............................................................................................................................589
25.5 Initialization / Application information........................................................................................................................590
25.5.1 MCG module initialization sequence...........................................................................................................590
25.5.2 Using a 32.768 kHz reference......................................................................................................................593
25.5.3 MCG mode switching..................................................................................................................................593
Chapter 26
Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................603
26.2 Features and Modes......................................................................................................................................................603
26.3 Block Diagram..............................................................................................................................................................604
26.4 OSC Signal Descriptions..............................................................................................................................................604
26.5 External Crystal / Resonator Connections....................................................................................................................605
26.6 External Clock Connections.........................................................................................................................................606
26.7 Memory Map/Register Definitions...............................................................................................................................607
26.7.1 OSC Memory Map/Register Definition.......................................................................................................607
26.8 Functional Description..................................................................................................................................................608
26.8.1 OSC Module States......................................................................................................................................608
26.8.2 OSC Module Modes.....................................................................................................................................610
26.8.3 Counter.........................................................................................................................................................612
26.8.4 Reference Clock Pin Requirements.............................................................................................................612
26.9 Reset..............................................................................................................................................................................612
26.10 Low Power Modes Operation.......................................................................................................................................613
26.11 Interrupts.......................................................................................................................................................................613
Chapter 27
RTC Oscillator
27.1 Introduction...................................................................................................................................................................615
27.1.1 Features and Modes.....................................................................................................................................615
27.1.2 Block Diagram.............................................................................................................................................615
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27.2 RTC Signal Descriptions..............................................................................................................................................616
27.2.1 EXTAL32 — Oscillator Input.....................................................................................................................616
27.2.2 XTAL32 — Oscillator Output.....................................................................................................................616
27.3 External Crystal Connections.......................................................................................................................................617
27.4 Memory Map/Register Descriptions.............................................................................................................................617
27.5 Functional Description..................................................................................................................................................617
27.6 Reset Overview.............................................................................................................................................................618
27.7 Interrupts.......................................................................................................................................................................618
Chapter 28
Flash Memory Controller (FMC)
28.1 Introduction...................................................................................................................................................................619
28.1.1 Overview......................................................................................................................................................619
28.1.2 Features........................................................................................................................................................620
28.2 Modes of operation.......................................................................................................................................................620
28.3 External signal description............................................................................................................................................621
28.4 Memory map and register descriptions.........................................................................................................................621
28.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................627
28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................630
28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................633
28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn).................................................................................................635
28.4.5 Cache Tag Storage (FMC_TAGVDW1Sn).................................................................................................636
28.4.6 Cache Tag Storage (FMC_TAGVDW2Sn).................................................................................................637
28.4.7 Cache Tag Storage (FMC_TAGVDW3Sn).................................................................................................638
28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................638
28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)..........................................................................639
28.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................639
28.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)..........................................................................640
28.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................640
28.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)..........................................................................641
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28.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................641
28.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)..........................................................................642
28.5 Functional description...................................................................................................................................................642
28.5.1 Default configuration...................................................................................................................................642
28.5.2 Configuration options..................................................................................................................................643
28.5.3 Wait states....................................................................................................................................................643
28.5.4 Speculative reads..........................................................................................................................................644
28.6 Initialization and application information.....................................................................................................................645
Chapter 29
Flash Memory Module (FTFL)
29.1 Introduction...................................................................................................................................................................647
29.1.1 Features........................................................................................................................................................648
29.1.2 Block Diagram.............................................................................................................................................650
29.1.3 Glossary.......................................................................................................................................................651
29.2 External Signal Description..........................................................................................................................................653
29.3 Memory Map and Registers..........................................................................................................................................653
29.3.1 Flash Configuration Field Description.........................................................................................................654
29.3.2 Program Flash IFR Map...............................................................................................................................654
29.3.3 Data Flash IFR Map.....................................................................................................................................655
29.3.4 Register Descriptions...................................................................................................................................657
29.4 Functional Description..................................................................................................................................................670
29.4.1 Program Flash Memory Swap......................................................................................................................670
29.4.2 Flash Protection............................................................................................................................................670
29.4.3 FlexNVM Description..................................................................................................................................672
29.4.4 Interrupts......................................................................................................................................................677
29.4.5 Flash Operation in Low-Power Modes........................................................................................................678
29.4.6 Functional Modes of Operation...................................................................................................................678
29.4.7 Flash Reads and Ignored Writes..................................................................................................................678
29.4.8 Read While Write (RWW)...........................................................................................................................679
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29.4.9 Flash Program and Erase..............................................................................................................................679
29.4.10 Flash Command Operations.........................................................................................................................679
29.4.11 Margin Read Commands.............................................................................................................................688
29.4.12 Flash Command Description........................................................................................................................689
29.4.13 Security........................................................................................................................................................717
29.4.14 Reset Sequence............................................................................................................................................719
Chapter 30
External Bus Interface (FlexBus)
30.1 Introduction...................................................................................................................................................................721
30.1.1 Definition.....................................................................................................................................................721
30.1.2 Features........................................................................................................................................................722
30.2 Signal descriptions........................................................................................................................................................722
30.3 Memory Map/Register Definition.................................................................................................................................725
30.3.1 Chip Select Address Register (FB_CSARn)................................................................................................727
30.3.2 Chip Select Mask Register (FB_CSMRn)...................................................................................................727
30.3.3 Chip Select Control Register (FB_CSCRn).................................................................................................728
30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................................731
30.4 Functional description...................................................................................................................................................732
30.4.1 Modes of operation......................................................................................................................................733
30.4.2 Address comparison.....................................................................................................................................733
30.4.3 Address driven on address bus.....................................................................................................................733
30.4.4 Connecting address/data lines......................................................................................................................733
30.4.5 Bit ordering..................................................................................................................................................734
30.4.6 Data transfer signals.....................................................................................................................................734
30.4.7 Signal transitions..........................................................................................................................................734
30.4.8 Data-byte alignment and physical connections............................................................................................734
30.4.9 Address/data bus multiplexing.....................................................................................................................735
30.4.10 Data transfer states.......................................................................................................................................736
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30.4.11 FlexBus Timing Examples...........................................................................................................................737
30.4.12 Burst cycles..................................................................................................................................................756
30.4.13 Extended Transfer Start/Address Latch Enable...........................................................................................764
30.4.14 Bus errors.....................................................................................................................................................765
30.5 Initialization/Application Information..........................................................................................................................766
30.5.1 Initializing a chip-select...............................................................................................................................766
30.5.2 Reconfiguring a chip-select.........................................................................................................................766
Chapter 31
EzPort
31.1 Overview.......................................................................................................................................................................767
31.1.1 Introduction..................................................................................................................................................767
31.1.2 Features........................................................................................................................................................768
31.1.3 Modes of operation......................................................................................................................................768
31.2 External signal description............................................................................................................................................769
31.2.1 EzPort Clock (EZP_CK)..............................................................................................................................769
31.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................769
31.2.3 EzPort Serial Data In (EZP_D)....................................................................................................................770
31.2.4 EzPort Serial Data Out (EZP_Q).................................................................................................................770
31.3 Command definition.....................................................................................................................................................770
31.3.1 Command descriptions.................................................................................................................................771
31.4 Flash memory map for EzPort access...........................................................................................................................777
Chapter 32
Cyclic Redundancy Check (CRC)
32.1 Introduction...................................................................................................................................................................779
32.1.1 Features........................................................................................................................................................779
32.1.2 Block diagram..............................................................................................................................................780
32.1.3 Modes of operation......................................................................................................................................780
32.2 Memory map and register descriptions.........................................................................................................................780
32.2.1 CRC Data register (CRC_CRC)..................................................................................................................781
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32.2.2 CRC Polynomial register (CRC_GPOLY)..................................................................................................782
32.2.3 CRC Control register (CRC_CTRL)............................................................................................................783
32.3 Functional description...................................................................................................................................................784
32.3.1 CRC initialization/reinitialization................................................................................................................784
32.3.2 CRC calculations..........................................................................................................................................784
32.3.3 Transpose feature.........................................................................................................................................785
32.3.4 CRC result complement...............................................................................................................................787
Chapter 33
Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
33.1 Introduction...................................................................................................................................................................789
33.2 MMCAU Block Diagram.............................................................................................................................................789
33.3 Overview.......................................................................................................................................................................791
33.4 Features.........................................................................................................................................................................792
33.5 Memory map/register definition...................................................................................................................................792
33.5.1 Status Register (CAU_CASR).....................................................................................................................794
33.5.2 Accumulator (CAU_CAA)..........................................................................................................................795
33.5.3 General Purpose Register (CAU_CAn).......................................................................................................795
33.6 Functional description...................................................................................................................................................796
33.6.1 MMCAU programming model....................................................................................................................796
33.6.2 MMCAU integrity checks............................................................................................................................798
33.6.3 CAU commands...........................................................................................................................................800
33.7 Application/initialization information..........................................................................................................................807
33.7.1 Code example...............................................................................................................................................807
33.7.2 Assembler equate values..............................................................................................................................807
Chapter 34
Random Number Generator Accelerator (RNGA)
34.1 Introduction...................................................................................................................................................................809
34.1.1 Overview......................................................................................................................................................809
34.2 Modes of operation.......................................................................................................................................................810
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34.3 Memory map and register definition.............................................................................................................................810
34.3.1 RNGA Control Register (RNG_CR)...........................................................................................................811
34.3.2 RNGA Status Register (RNG_SR)..............................................................................................................813
34.3.3 RNGA Entropy Register (RNG_ER)...........................................................................................................815
34.3.4 RNGA Output Register (RNG_OR)............................................................................................................816
34.4 Functional description...................................................................................................................................................816
34.4.1 RNGA Output Register................................................................................................................................817
34.4.2 RNGA Core/Control Logic Block...............................................................................................................817
34.5 Initialization/application information...........................................................................................................................818
Chapter 35
Analog-to-Digital Converter (ADC)
35.1 Introduction...................................................................................................................................................................819
35.1.1 Features........................................................................................................................................................819
35.1.2 Block diagram..............................................................................................................................................820
35.2 ADC Signal Descriptions..............................................................................................................................................821
35.2.1 Analog Power (VDDA)...............................................................................................................................822
35.2.2 Analog Ground (VSSA)...............................................................................................................................822
35.2.3 Voltage Reference Select.............................................................................................................................822
35.2.4 Analog Channel Inputs (ADx).....................................................................................................................823
35.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................823
35.3 Register definition.........................................................................................................................................................823
35.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................826
35.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................829
35.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................831
35.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................832
35.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................833
35.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................834
35.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................836
35.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................838
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35.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................838
35.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................839
35.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................839
35.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................840
35.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................840
35.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................841
35.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................841
35.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................842
35.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................842
35.3.18 ADC PGA Register (ADCx_PGA)..............................................................................................................843
35.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................844
35.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................845
35.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................845
35.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................846
35.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................846
35.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................847
35.3.25 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................847
35.4 Functional description...................................................................................................................................................847
35.4.1 PGA functional description..........................................................................................................................848
35.4.2 Clock select and divide control....................................................................................................................849
35.4.3 Voltage reference selection..........................................................................................................................849
35.4.4 Hardware trigger and channel selects..........................................................................................................850
35.4.5 Conversion control.......................................................................................................................................851
35.4.6 Automatic compare function........................................................................................................................858
35.4.7 Calibration function.....................................................................................................................................859
35.4.8 User-defined offset function........................................................................................................................861
35.4.9 Temperature sensor......................................................................................................................................862
35.4.10 MCU wait mode operation...........................................................................................................................863
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35.4.11 MCU Normal Stop mode operation.............................................................................................................863
35.4.12 MCU Low-Power Stop mode operation......................................................................................................864
35.5 Initialization information..............................................................................................................................................865
35.5.1 ADC module initialization example............................................................................................................865
35.6 Application information................................................................................................................................................867
35.6.1 External pins and routing.............................................................................................................................867
35.6.2 Sources of error............................................................................................................................................869
Chapter 36
Comparator (CMP)
36.1 Introduction...................................................................................................................................................................875
36.2 CMP features................................................................................................................................................................875
36.3 6-bit DAC key features.................................................................................................................................................876
36.4 ANMUX key features...................................................................................................................................................877
36.5 CMP, DAC and ANMUX diagram...............................................................................................................................877
36.6 CMP block diagram......................................................................................................................................................878
36.7 Memory map/register definitions..................................................................................................................................880
36.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................880
36.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................881
36.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................883
36.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................883
36.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................884
36.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................885
36.8 CMP functional description..........................................................................................................................................886
36.8.1 CMP functional modes.................................................................................................................................886
36.8.2 Power modes................................................................................................................................................895
36.8.3 Startup and operation...................................................................................................................................896
36.8.4 Low-pass filter.............................................................................................................................................897
36.9 CMP interrupts..............................................................................................................................................................899
36.10 CMP DMA support.......................................................................................................................................................899
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36.11 Digital-to-analog converter block diagram...................................................................................................................900
36.12 DAC functional description..........................................................................................................................................900
36.12.1 Voltage reference source select....................................................................................................................900
36.13 DAC resets....................................................................................................................................................................901
36.14 DAC clocks...................................................................................................................................................................901
36.15 DAC interrupts..............................................................................................................................................................901
Chapter 37
12-bit Digital-to-Analog Converter (DAC)
37.1 Introduction...................................................................................................................................................................903
37.2 Features.........................................................................................................................................................................903
37.3 Block diagram...............................................................................................................................................................904
37.4 Memory map/register definition...................................................................................................................................905
37.4.1 DAC Data Low Register (DACx_DATnL).................................................................................................906
37.4.2 DAC Data High Register (DACx_DATnH)................................................................................................906
37.4.3 DAC Status Register (DACx_SR)...............................................................................................................907
37.4.4 DAC Control Register (DACx_C0).............................................................................................................908
37.4.5 DAC Control Register 1 (DACx_C1)..........................................................................................................909
37.4.6 DAC Control Register 2 (DACx_C2)..........................................................................................................910
37.5 Functional description...................................................................................................................................................910
37.5.1 DAC data buffer operation...........................................................................................................................910
37.5.2 DMA operation............................................................................................................................................911
37.5.3 Resets...........................................................................................................................................................911
37.5.4 Low-Power mode operation.........................................................................................................................912
Chapter 38
Voltage Reference (VREFV1)
38.1 Introduction...................................................................................................................................................................913
38.1.1 Overview......................................................................................................................................................914
38.1.2 Features........................................................................................................................................................914
38.1.3 Modes of Operation.....................................................................................................................................915
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38.1.4 VREF Signal Descriptions...........................................................................................................................915
38.2 Memory Map and Register Definition..........................................................................................................................916
38.2.1 VREF Trim Register (VREF_TRM)............................................................................................................916
38.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................917
38.3 Functional Description..................................................................................................................................................918
38.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................918
38.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................919
38.4 Initialization/Application Information..........................................................................................................................920
Chapter 39
Programmable Delay Block (PDB)
39.1 Introduction...................................................................................................................................................................921
39.1.1 Features........................................................................................................................................................921
39.1.2 Implementation............................................................................................................................................922
39.1.3 Back-to-back acknowledgment connections................................................................................................923
39.1.4 DAC External Trigger Input Connections...................................................................................................923
39.1.5 Block diagram..............................................................................................................................................923
39.1.6 Modes of operation......................................................................................................................................925
39.2 PDB signal descriptions................................................................................................................................................925
39.3 Memory map and register definition.............................................................................................................................925
39.3.1 Status and Control Register (PDBx_SC).....................................................................................................927
39.3.2 Modulus Register (PDBx_MOD).................................................................................................................929
39.3.3 Counter Register (PDBx_CNT)...................................................................................................................930
39.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................930
39.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................931
39.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................932
39.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................932
39.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................933
39.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................933
39.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................934
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39.3.11 Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................934
39.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................935
39.4 Functional description...................................................................................................................................................935
39.4.1 PDB pre-trigger and trigger outputs.............................................................................................................935
39.4.2 PDB trigger input source selection..............................................................................................................937
39.4.3 DAC interval trigger outputs........................................................................................................................937
39.4.4 Pulse-Out's...................................................................................................................................................938
39.4.5 Updating the delay registers.........................................................................................................................938
39.4.6 Interrupts......................................................................................................................................................940
39.4.7 DMA............................................................................................................................................................940
39.5 Application information................................................................................................................................................940
39.5.1 Impact of using the prescaler and multiplication factor on timing resolution.............................................940
Chapter 40
FlexTimer Module (FTM)
40.1 Introduction...................................................................................................................................................................943
40.1.1 FlexTimer philosophy..................................................................................................................................943
40.1.2 Features........................................................................................................................................................944
40.1.3 Modes of operation......................................................................................................................................945
40.1.4 Block diagram..............................................................................................................................................946
40.2 FTM signal descriptions...............................................................................................................................................948
40.3 Memory map and register definition.............................................................................................................................948
40.3.1 Memory map................................................................................................................................................948
40.3.2 Register descriptions....................................................................................................................................949
40.3.3 Status And Control (FTMx_SC)..................................................................................................................955
40.3.4 Counter (FTMx_CNT).................................................................................................................................956
40.3.5 Modulo (FTMx_MOD)................................................................................................................................957
40.3.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................958
40.3.7 Channel (n) Value (FTMx_CnV).................................................................................................................960
40.3.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................961
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40.3.9 Capture And Compare Status (FTMx_STATUS)........................................................................................961
40.3.10 Features Mode Selection (FTMx_MODE)..................................................................................................963
40.3.11 Synchronization (FTMx_SYNC).................................................................................................................965
40.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................968
40.3.13 Output Mask (FTMx_OUTMASK).............................................................................................................969
40.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................971
40.3.15 Deadtime Insertion Control (FTMx_DEADTIME).....................................................................................976
40.3.16 FTM External Trigger (FTMx_EXTTRIG).................................................................................................977
40.3.17 Channels Polarity (FTMx_POL)..................................................................................................................978
40.3.18 Fault Mode Status (FTMx_FMS).................................................................................................................981
40.3.19 Input Capture Filter Control (FTMx_FILTER)...........................................................................................983
40.3.20 Fault Control (FTMx_FLTCTRL)...............................................................................................................984
40.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................986
40.3.22 Configuration (FTMx_CONF).....................................................................................................................988
40.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................989
40.3.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................991
40.3.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................993
40.3.26 FTM Software Output Control (FTMx_SWOCTRL)..................................................................................994
40.3.27 FTM PWM Load (FTMx_PWMLOAD).....................................................................................................996
40.4 Functional description...................................................................................................................................................997
40.4.1 Clock source.................................................................................................................................................998
40.4.2 Prescaler.......................................................................................................................................................999
40.4.3 Counter.........................................................................................................................................................999
40.4.4 Input Capture mode......................................................................................................................................1004
40.4.5 Output Compare mode.................................................................................................................................1007
40.4.6 Edge-Aligned PWM (EPWM) mode...........................................................................................................1008
40.4.7 Center-Aligned PWM (CPWM) mode........................................................................................................1010
40.4.8 Combine mode.............................................................................................................................................1012
40.4.9 Complementary mode..................................................................................................................................1020
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40.4.10 Registers updated from write buffers...........................................................................................................1021
40.4.11 PWM synchronization..................................................................................................................................1023
40.4.12 Inverting.......................................................................................................................................................1039
40.4.13 Software output control................................................................................................................................1040
40.4.14 Deadtime insertion.......................................................................................................................................1042
40.4.15 Output mask.................................................................................................................................................1045
40.4.16 Fault control.................................................................................................................................................1046
40.4.17 Polarity control.............................................................................................................................................1049
40.4.18 Initialization.................................................................................................................................................1050
40.4.19 Features priority...........................................................................................................................................1050
40.4.20 Channel trigger output.................................................................................................................................1051
40.4.21 Initialization trigger......................................................................................................................................1052
40.4.22 Capture Test mode.......................................................................................................................................1054
40.4.23 DMA............................................................................................................................................................1055
40.4.24 Dual Edge Capture mode.............................................................................................................................1056
40.4.25 Quadrature Decoder mode...........................................................................................................................1063
40.4.26 BDM mode...................................................................................................................................................1068
40.4.27 Intermediate load..........................................................................................................................................1069
40.4.28 Global time base (GTB)...............................................................................................................................1071
40.5 Reset overview..............................................................................................................................................................1072
40.6 FTM Interrupts..............................................................................................................................................................1074
40.6.1 Timer Overflow Interrupt.............................................................................................................................1074
40.6.2 Channel (n) Interrupt....................................................................................................................................1074
40.6.3 Fault Interrupt..............................................................................................................................................1074
Chapter 41
Periodic Interrupt Timer (PIT)
41.1 Introduction...................................................................................................................................................................1075
41.1.1 Block diagram..............................................................................................................................................1075
41.1.2 Features........................................................................................................................................................1076
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41.2 Signal description..........................................................................................................................................................1076
41.3 Memory map/register description.................................................................................................................................1077
41.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................1078
41.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................1078
41.3.3 Current Timer Value Register (PIT_CVALn).............................................................................................1079
41.3.4 Timer Control Register (PIT_TCTRLn)......................................................................................................1079
41.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................1080
41.4 Functional description...................................................................................................................................................1081
41.4.1 General operation.........................................................................................................................................1081
41.4.2 Interrupts......................................................................................................................................................1082
41.4.3 Chained timers.............................................................................................................................................1083
41.5 Initialization and application information.....................................................................................................................1083
41.6 Example configuration for chained timers....................................................................................................................1084
Chapter 42
Low-Power Timer (LPTMR)
42.1 Introduction...................................................................................................................................................................1087
42.1.1 Features........................................................................................................................................................1087
42.1.2 Modes of operation......................................................................................................................................1087
42.2 LPTMR signal descriptions..........................................................................................................................................1088
42.2.1 Detailed signal descriptions.........................................................................................................................1088
42.3 Memory map and register definition.............................................................................................................................1089
42.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................1089
42.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................1091
42.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................1092
42.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................1093
42.4 Functional description...................................................................................................................................................1093
42.4.1 LPTMR power and reset..............................................................................................................................1093
42.4.2 LPTMR clocking..........................................................................................................................................1093
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42.4.3 LPTMR prescaler/glitch filter......................................................................................................................1094
42.4.4 LPTMR compare..........................................................................................................................................1095
42.4.5 LPTMR counter...........................................................................................................................................1095
42.4.6 LPTMR hardware trigger.............................................................................................................................1096
42.4.7 LPTMR interrupt..........................................................................................................................................1096
Chapter 43
Carrier Modulator Transmitter (CMT)
43.1 Introduction...................................................................................................................................................................1099
43.2 Features.........................................................................................................................................................................1099
43.3 Block diagram...............................................................................................................................................................1100
43.4 Modes of operation.......................................................................................................................................................1101
43.4.1 Wait mode operation....................................................................................................................................1102
43.4.2 Stop mode operation....................................................................................................................................1103
43.5 CMT external signal descriptions.................................................................................................................................1103
43.5.1 CMT_IRO — Infrared Output.....................................................................................................................1103
43.6 Memory map/register definition...................................................................................................................................1104
43.6.1 CMT Carrier Generator High Data Register 1 (CMT_CGH1)....................................................................1105
43.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1).....................................................................1106
43.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)....................................................................1106
43.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2).....................................................................1107
43.6.5 CMT Output Control Register (CMT_OC).................................................................................................1107
43.6.6 CMT Modulator Status and Control Register (CMT_MSC).......................................................................1108
43.6.7 CMT Modulator Data Register Mark High (CMT_CMD1)........................................................................1110
43.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2).........................................................................1111
43.6.9 CMT Modulator Data Register Space High (CMT_CMD3).......................................................................1111
43.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)........................................................................1112
43.6.11 CMT Primary Prescaler Register (CMT_PPS)............................................................................................1112
43.6.12 CMT Direct Memory Access Register (CMT_DMA).................................................................................1113
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43.7 Functional description...................................................................................................................................................1114
43.7.1 Clock divider................................................................................................................................................1114
43.7.2 Carrier generator..........................................................................................................................................1114
43.7.3 Modulator.....................................................................................................................................................1117
43.7.4 Extended space operation.............................................................................................................................1121
43.8 CMT interrupts and DMA............................................................................................................................................1123
Chapter 44
Real Time Clock (RTC)
44.1 Introduction...................................................................................................................................................................1125
44.1.1 Features........................................................................................................................................................1125
44.1.2 Modes of operation......................................................................................................................................1125
44.1.3 RTC Signal Descriptions.............................................................................................................................1126
44.2 Register definition.........................................................................................................................................................1127
44.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................1128
44.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................1128
44.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................1129
44.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................1129
44.2.5 RTC Control Register (RTC_CR)................................................................................................................1130
44.2.6 RTC Status Register (RTC_SR)..................................................................................................................1132
44.2.7 RTC Lock Register (RTC_LR)....................................................................................................................1133
44.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................1134
44.2.9 RTC Write Access Register (RTC_WAR)..................................................................................................1135
44.2.10 RTC Read Access Register (RTC_RAR)....................................................................................................1137
44.3 Functional description...................................................................................................................................................1138
44.3.1 Power, clocking, and reset...........................................................................................................................1138
44.3.2 Time counter................................................................................................................................................1139
44.3.3 Compensation...............................................................................................................................................1140
44.3.4 Time alarm...................................................................................................................................................1140
44.3.5 Update mode................................................................................................................................................1141
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44.3.6 Register lock................................................................................................................................................1141
44.3.7 Access control..............................................................................................................................................1141
44.3.8 Interrupt........................................................................................................................................................1141
Chapter 45
10/100-Mbps Ethernet MAC (ENET)
45.1 Introduction...................................................................................................................................................................1143
45.1.1 Overview......................................................................................................................................................1143
45.1.2 Features........................................................................................................................................................1144
45.1.3 Block diagram..............................................................................................................................................1146
45.2 External signal description............................................................................................................................................1147
45.3 Memory map/register definition...................................................................................................................................1149
45.3.1 Interrupt Event Register (ENET_EIR).........................................................................................................1152
45.3.2 Interrupt Mask Register (ENET_EIMR)......................................................................................................1154
45.3.3 Receive Descriptor Active Register (ENET_RDAR)..................................................................................1157
45.3.4 Transmit Descriptor Active Register (ENET_TDAR).................................................................................1158
45.3.5 Ethernet Control Register (ENET_ECR).....................................................................................................1159
45.3.6 MII Management Frame Register (ENET_MMFR)....................................................................................1161
45.3.7 MII Speed Control Register (ENET_MSCR)..............................................................................................1162
45.3.8 MIB Control Register (ENET_MIBC)........................................................................................................1164
45.3.9 Receive Control Register (ENET_RCR).....................................................................................................1165
45.3.10 Transmit Control Register (ENET_TCR)....................................................................................................1168
45.3.11 Physical Address Lower Register (ENET_PALR)......................................................................................1170
45.3.12 Physical Address Upper Register (ENET_PAUR)......................................................................................1170
45.3.13 Opcode/Pause Duration Register (ENET_OPD).........................................................................................1171
45.3.14 Descriptor Individual Upper Address Register (ENET_IAUR)..................................................................1171
45.3.15 Descriptor Individual Lower Address Register (ENET_IALR)..................................................................1172
45.3.16 Descriptor Group Upper Address Register (ENET_GAUR).......................................................................1172
45.3.17 Descriptor Group Lower Address Register (ENET_GALR).......................................................................1173
45.3.18 Transmit FIFO Watermark Register (ENET_TFWR).................................................................................1173
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45.3.19 Receive Descriptor Ring Start Register (ENET_RDSR).............................................................................1174
45.3.20 Transmit Buffer Descriptor Ring Start Register (ENET_TDSR)................................................................1175
45.3.21 Maximum Receive Buffer Size Register (ENET_MRBR)..........................................................................1175
45.3.22 Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................1176
45.3.23 Receive FIFO Section Empty Threshold (ENET_RSEM)..........................................................................1176
45.3.24 Receive FIFO Almost Empty Threshold (ENET_RAEM)..........................................................................1177
45.3.25 Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1177
45.3.26 Transmit FIFO Section Empty Threshold (ENET_TSEM).........................................................................1178
45.3.27 Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1178
45.3.28 Transmit FIFO Almost Full Threshold (ENET_TAFL)..............................................................................1178
45.3.29 Transmit Inter-Packet Gap (ENET_TIPG)..................................................................................................1179
45.3.30 Frame Truncation Length (ENET_FTRL)...................................................................................................1179
45.3.31 Transmit Accelerator Function Configuration (ENET_TACC)..................................................................1180
45.3.32 Receive Accelerator Function Configuration (ENET_RACC)....................................................................1181
45.3.33 Timer Control Register (ENET_ATCR)......................................................................................................1182
45.3.34 Timer Value Register (ENET_ATVR)........................................................................................................1184
45.3.35 Timer Offset Register (ENET_ATOFF)......................................................................................................1184
45.3.36 Timer Period Register (ENET_ATPER)......................................................................................................1185
45.3.37 Timer Correction Register (ENET_ATCOR)..............................................................................................1185
45.3.38 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................1186
45.3.39 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................1186
45.3.40 Timer Global Status Register (ENET_TGSR).............................................................................................1187
45.3.41 Timer Control Status Register (ENET_TCSRn)..........................................................................................1188
45.3.42 Timer Compare Capture Register (ENET_TCCRn)....................................................................................1189
45.3.43 Statistic event counters.................................................................................................................................1189
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45.4 Functional description...................................................................................................................................................1192
45.4.1 Ethernet MAC frame formats......................................................................................................................1192
45.4.2 IP and higher layers frame format................................................................................................................1195
45.4.3 IEEE 1588 message formats........................................................................................................................1199
45.4.4 MAC receive................................................................................................................................................1203
45.4.5 MAC transmit..............................................................................................................................................1208
45.4.6 Full-duplex flow control operation..............................................................................................................1212
45.4.7 Magic packet detection................................................................................................................................1214
45.4.8 IP accelerator functions................................................................................................................................1215
45.4.9 Resets and stop controls...............................................................................................................................1220
45.4.10 IEEE 1588 functions....................................................................................................................................1223
45.4.11 FIFO thresholds............................................................................................................................................1226
45.4.12 Loopback options.........................................................................................................................................1229
45.4.13 Legacy buffer descriptors.............................................................................................................................1230
45.4.14 Enhanced buffer descriptors.........................................................................................................................1231
45.4.15 Client FIFO application interface................................................................................................................1237
45.4.16 FIFO protection............................................................................................................................................1240
45.4.17 PHY management interface.........................................................................................................................1243
45.4.18 Ethernet interfaces........................................................................................................................................1244
Chapter 46
Universal Serial Bus OTG Controller (USBOTG)
46.1 Introduction...................................................................................................................................................................1249
46.1.1 USB..............................................................................................................................................................1249
46.1.2 USB On-The-Go..........................................................................................................................................1250
46.1.3 USB-FS Features..........................................................................................................................................1251
46.2 Functional description...................................................................................................................................................1252
46.2.1 Data Structures.............................................................................................................................................1252
46.3 Programmers interface..................................................................................................................................................1252
46.3.1 Buffer Descriptor Table...............................................................................................................................1252
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46.3.2 RX vs. TX as a USB target device or USB host..........................................................................................1253
46.3.3 Addressing BDT entries...............................................................................................................................1254
46.3.4 Buffer Descriptors (BDs).............................................................................................................................1254
46.3.5 USB transaction...........................................................................................................................................1257
46.4 Memory map/Register definitions................................................................................................................................1259
46.4.1 Peripheral ID register (USBx_PERID)........................................................................................................1261
46.4.2 Peripheral ID Complement register (USBx_IDCOMP)...............................................................................1262
46.4.3 Peripheral Revision register (USBx_REV)..................................................................................................1262
46.4.4 Peripheral Additional Info register (USBx_ADDINFO).............................................................................1263
46.4.5 OTG Interrupt Status register (USBx_OTGISTAT)....................................................................................1263
46.4.6 OTG Interrupt Control Register (USBx_OTGICR).....................................................................................1264
46.4.7 OTG Status register (USBx_OTGSTAT)....................................................................................................1265
46.4.8 OTG Control register (USBx_OTGCTL)....................................................................................................1266
46.4.9 Interrupt Status register (USBx_ISTAT).....................................................................................................1267
46.4.10 Interrupt Enable register (USBx_INTEN)...................................................................................................1268
46.4.11 Error Interrupt Status register (USBx_ERRSTAT).....................................................................................1269
46.4.12 Error Interrupt Enable register (USBx_ERREN).........................................................................................1270
46.4.13 Status register (USBx_STAT)......................................................................................................................1271
46.4.14 Control register (USBx_CTL)......................................................................................................................1272
46.4.15 Address register (USBx_ADDR).................................................................................................................1273
46.4.16 BDT Page Register 1 (USBx_BDTPAGE1)................................................................................................1274
46.4.17 Frame Number Register Low (USBx_FRMNUML)...................................................................................1274
46.4.18 Frame Number Register High (USBx_FRMNUMH)..................................................................................1275
46.4.19 Token register (USBx_TOKEN)..................................................................................................................1275
46.4.20 SOF Threshold Register (USBx_SOFTHLD)..............................................................................................1276
46.4.21 BDT Page Register 2 (USBx_BDTPAGE2)................................................................................................1277
46.4.22 BDT Page Register 3 (USBx_BDTPAGE3)................................................................................................1277
46.4.23 Endpoint Control register (USBx_ENDPTn)...............................................................................................1277
46.4.24 USB Control register (USBx_USBCTRL)..................................................................................................1278
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46.4.25 USB OTG Observe register (USBx_OBSERVE)........................................................................................1279
46.4.26 USB OTG Control register (USBx_CONTROL)........................................................................................1280
46.4.27 USB Transceiver Control Register 0 (USBx_USBTRC0)...........................................................................1280
46.4.28 Frame Adjust Register (USBx_USBFRMADJUST)...................................................................................1281
46.5 OTG and Host mode operation.....................................................................................................................................1282
46.6 Host Mode Operation Examples...................................................................................................................................1282
46.7 On-The-Go operation....................................................................................................................................................1285
46.7.1 OTG dual role A device operation...............................................................................................................1286
46.7.2 OTG dual role B device operation...............................................................................................................1287
Chapter 47
USB Device Charger Detection Module (USBDCD)
47.1 Preface...........................................................................................................................................................................1289
47.1.1 References....................................................................................................................................................1289
47.1.2 Acronyms and abbreviations........................................................................................................................1289
47.1.3 Glossary.......................................................................................................................................................1290
47.2 Introduction...................................................................................................................................................................1290
47.2.1 Block diagram..............................................................................................................................................1290
47.2.2 Features........................................................................................................................................................1291
47.2.3 Modes of operation......................................................................................................................................1291
47.3 Module signal descriptions...........................................................................................................................................1292
47.4 Memory map/Register definition..................................................................................................................................1293
47.4.1 Control register (USBDCD_CONTROL)....................................................................................................1294
47.4.2 Clock register (USBDCD_CLOCK)............................................................................................................1295
47.4.3 Status register (USBDCD_STATUS)..........................................................................................................1297
47.4.4 TIMER0 register (USBDCD_TIMER0)......................................................................................................1298
47.4.5 TIMER1 register (USBDCD_TIMER1)......................................................................................................1299
47.4.6 TIMER2 register (USBDCD_TIMER2)