K10_LQ/MD10 Datasheet by NXP USA Inc.

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K10P144M100SF2V2
K10 Sub-Family
Supports the following:
MK10DX128VLQ10,
MK10DX128VMD10,
MK10DX256VLQ10,
MK10DX256VMD10,
MK10DN512VLQ10,
MK10DN512VMD10
Features
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): -40 to 105°C
Performance
Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
Up to 512 KB program flash memory on non-
FlexMemory devices
Up to 256 KB program flash memory on
FlexMemory devices
Up to 256 KB FlexNVM on FlexMemory devices
4 KB FlexRAM on FlexMemory devices
Up to 128 KB RAM
Serial programming interface (EzPort)
FlexBus external bus interface
Clocks
3 to 32 MHz crystal oscillator
32 kHz crystal oscillator
Multi-purpose clock generator
System peripherals
Multiple low-power modes to provide power
optimization based on application requirements
Memory protection unit with multi-master
protection
16-channel DMA controller, supporting up to 63
request sources
External watchdog monitor
Software watchdog
Low-leakage wakeup unit
Security and integrity modules
Hardware CRC module to support fast cyclic
redundancy checks
128-bit unique identification (ID) number per chip
Human-machine interface
Low-power hardware touch sensor interface (TSI)
General-purpose input/output
Analog modules
Two 16-bit SAR ADCs
Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
Two 12-bit DACs
Two transimpedance amplifiers
Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
Voltage reference
Timers
Programmable delay block
Eight-channel motor control/general purpose/PWM
timer
Two 2-channel quadrature decoder/general purpose
timers
Periodic interrupt timers
16-bit low-power timer
Carrier modulator transmitter
Real-time clock
Communication interfaces
Two Controller Area Network (CAN) modules
Three SPI modules
Two I2C modules
Six UART modules
Secure Digital host controller (SDHC)
I2S module
Freescale Semiconductor Document Number: K10P144M100SF2V2
Data Sheet: Technical Data Rev. 3, 6/2013
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
2 Freescale Semiconductor, Inc.
This page intentionally blank.
Table of Contents
1 Ordering parts...........................................................................4
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................10
5 General.....................................................................................11
5.1 AC electrical characteristics..............................................11
5.2 Nonswitching electrical specifications...............................11
5.2.1 Voltage and current operating requirements.........11
5.2.2 LVD and POR operating requirements.................12
5.2.3 Voltage and current operating behaviors..............13
5.2.4 Power mode transition operating behaviors..........15
5.2.5 Power consumption operating behaviors..............16
5.2.6 EMC radiated emissions operating behaviors.......19
5.2.7 Designing with radiated emissions in mind...........20
5.2.8 Capacitance attributes..........................................20
5.3 Switching specifications.....................................................20
5.3.1 Device clock specifications...................................20
5.3.2 General switching specifications...........................21
5.4 Thermal specifications.......................................................22
5.4.1 Thermal operating requirements...........................22
5.4.2 Thermal attributes.................................................22
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
6.1.1 Debug trace timing specifications.........................23
6.1.2 JTAG electricals....................................................24
6.2 System modules................................................................27
6.3 Clock modules...................................................................27
6.3.1 MCG specifications...............................................27
6.3.2 Oscillator electrical specifications.........................29
6.3.3 32 kHz oscillator electrical characteristics.............31
6.4 Memories and memory interfaces.....................................32
6.4.1 Flash electrical specifications................................32
6.4.2 EzPort switching specifications.............................37
6.4.3 Flexbus switching specifications...........................38
6.5 Security and integrity modules..........................................41
6.6 Analog...............................................................................41
6.6.1 ADC electrical specifications.................................41
6.6.2 CMP and 6-bit DAC electrical specifications.........49
6.6.3 12-bit DAC electrical characteristics.....................52
6.6.4 Voltage reference electrical specifications............55
6.7 Timers................................................................................56
6.8 Communication interfaces.................................................56
6.8.1 CAN switching specifications................................56
6.8.2 DSPI switching specifications (limited voltage
range)....................................................................57
6.8.3 DSPI switching specifications (full voltage range).58
6.8.4 Inter-Integrated Circuit Interface (I2C) timing........60
6.8.5 UART switching specifications..............................61
6.8.6 SDHC specifications.............................................61
6.8.7 I2S/SAI switching specifications............................62
6.9 Human-machine interfaces (HMI)......................................68
6.9.1 TSI electrical specifications...................................68
7 Dimensions...............................................................................69
7.1 Obtaining package dimensions.........................................69
8 Pinout........................................................................................69
8.1 K10 signal multiplexing and pin assignments....................69
8.2 K10 pinouts.......................................................................75
9 Revision history.........................................................................77
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 3
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK10 and MK10 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status M = Fully qualified, general market flow
P = Prequalification
K## Kinetis family K10
A Key attribute D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU
M Flash memory type N = Program flash only
X = Program flash and FlexMemory
Table continues on the next page...
Ordering parts
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
4 Freescale Semiconductor, Inc.
Field Description Values
FFF Program flash memory size 32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
R Silicon revision Z = Initial
(Blank) = Main
A = Revision after main
T Temperature range (°C) V = –40 to 105
C = –40 to 85
PP Package identifier FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) 5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
N Packaging type R = Tape and reel
(Blank) = Trays
2.4 Example
This is an example part number:
MK10DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 5
3.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
6 Freescale Semiconductor, Inc.
Fafluves m ume (ppm) / / / |_ Measured chamdensflc
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
3.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 7
3.6 Relationship between ratings and operating requirements
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
8 Freescale Semiconductor, Inc.
OAlx 5000 7:: Van
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
Terminology and guidelines
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 9
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Ratings
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
10 Freescale Semiconductor, Inc.
LOW Input Signa| Mldpomn FaH Time —> Rise Time The midpoint IS VIL + NIH - VILVZ
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
have CL=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 11
ucl .e
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICDIO Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V -5 — mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current —
single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
-5
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection
-25
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
12 Freescale Semiconductor, Inc.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 13
ucl .e
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ.1Max. Unit Notes
VOH Output high voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
V
V
IOHT Output high current total for all ports 100 mA
VOL Output low voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 5mA
0.5
0.5
V
V
2
Output low voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1mA
0.5
0.5
V
V
IOLT Output low current total for all ports 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
All pins except EXTAL32, XTAL32,
EXTAL, XTAL
EXTAL (PTA18) and XTAL (PTA19)
EXTAL32, XTAL32
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
3, 4
IIND Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
All digital pins
• VIN = VDD
All digital pins except PTD7
• PTD7
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
4, 5
IIND Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
18
12
8
3
26
49
13
6
μA
μA
μA
μA
4, 5, 6
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
14 Freescale Semiconductor, Inc.
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ.1Max. Unit Notes
IIND Input leakage current, digital pins
• VDD < VIN < 5.5 V
1
50
μA
4, 5
ZIND Input impedance examples, digital pins
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
48
55
57
85
4, 7
RPU Internal pullup resistors 20 35 50 8
RPD Internal pulldown resistors 20 35 50 9
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
+
Digital input
Source
ZIND
IIND
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 15
an .e
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
300
1.7 V / (VDD
slew rate)
μs
1
VLLS1 RUN 130 μs
VLLS2 RUN 92 μs
VLLS3 RUN 92 μs
LLS RUN 5.9 μs
VLPS RUN 5.0 μs
STOP RUN 5.0 μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
37
38
63
64
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 125°C
46
47
58
77
63
79
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 20 — mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 9 — mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 1.12 — mA 6
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
16 Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 1.71 — mA 7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
— 0.77 — mA 8
IDD_STOP Stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.74
2.45
6.61
1.41
11.5
30
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
83
425
1280
435
2000
4000
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
4.58
30.6
137
19.9
105
500
μA
μA
μA
9
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
3.0
18.6
84.9
23
43
230
μA
μA
μA
9
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.2
9.3
41.4
5.4
35
128
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.1
7.6
33.5
9
28
95.5
μA
μA
μA
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 17
ucl .e
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
@ 1.8V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0V
@ –40 to 25°C
@ 70°C
@ 105°C
0.57
0.90
2.4
0.67
1.0
2.7
0.67
1.2
3.5
0.94
1.4
3.9
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. For
devices with 32 KB of RAM, power consumption is reduced by 3 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFL
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
18 Freescale Semiconductor, Inc.
Run Mode Currem Consumption vs Core Frequency Temp IC)=25,VUI1=3 6MCACHE=ENABLECOG€ Residence=Flash so now) as com) a new! 35 noun 3 a n z 30 00503 g All mimml (1k Gales E as com E -O-‘|.|.CIFF g +ALLON .. 11: new! E k 3 u 15 coma in nos-as S cows ono DOEvDO a W 1- 1-1 m a mm m 4 ”+2 m “2‘24 mfg); 1 2 A 625 n 5 :5 5n 1; mo (av-Fv-qle!
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 144LQFP and
144MAPBGA
Symbol Description Frequency
band (MHz)
144LQFP 144MAPBGA Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 23 12 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 27 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 28 27 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 14 11 dBμV
VRE_IEC IEC level 0.15–1000 K K 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 19
ucl .e
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins 7 pF
CIN_D Input capacitance: digital pins 7 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock 100 MHz
fBUS Bus clock 50 MHz
FB_CLK FlexBus clock 50 MHz
fFLASH Flash clock 25 MHz
fLPTMR LPTMR clock 25 MHz
VLPR mode1
fSYS System and core clock 4 MHz
fBUS Bus clock 4 MHz
FB_CLK FlexBus clock 4 MHz
fFLASH Flash clock 1 MHz
fERCLK External reference clock 16 MHz
fLPTMR_pin LPTMR clock 25 MHz
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
20 Freescale Semiconductor, Inc.
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fFlexCAN_ERCLK FlexCAN external reference clock 8 MHz
fI2S_MCLK I2S master clock 12.5 MHz
fI2S_BCLK I2S bit clock 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 Bus clock
cycles
Port rise and fall time (high drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
36
24
ns
ns
ns
ns
5
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 21
ucl .e
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
5.4.2 Thermal attributes
Board type Symbol Description 144 LQFP 144
MAPBGA Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient (natural
convection)
45 48 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient (natural
convection)
36 29 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
36 38 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
30 25 °C/W 1
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
22 Freescale Semiconductor, Inc.
Board type Symbol Description 144 LQFP 144
MAPBGA Unit Notes
— RθJB Thermal
resistance,
junction to
board
24 16 °C/W 2
— RθJC Thermal
resistance,
junction to case
9 9 °C/W 3
ΨJT Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2 2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 ns
Twh High pulse width 2 ns
TrClock and data rise time 3 ns
TfClock and data fall time 3 ns
TsData setup 3 ns
ThData hold 2 ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 23
rcllll TRACECLK ”’ "
Figure 3. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
0
0
10
25
50
MHz
J2 TCLK cycle period 1/J1 ns
J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
20
10
ns
ns
ns
J4 TCLK rise and fall times 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 ns
J6 Boundary scan input data hold time after TCLK rise 0 ns
J7 TCLK low to boundary scan output data valid 25 ns
J8 TCLK low to boundary scan output high-Z 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 ns
J10 TMS, TDI input data hold time after TCLK rise 1 ns
J11 TCLK low to TDO data valid 17 ns
J12 TCLK low to TDO high-Z 17 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
24 Freescale Semiconductor, Inc.
Table 13. JTAG limited voltage range electricals (continued)
Symbol Description Min. Max. Unit
J13 TRST assert time 100 ns
J14 TRST setup time (negation) to TCLK high 8 ns
Table 14. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
0
0
10
20
40
MHz
J2 TCLK cycle period 1/J1 ns
J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
25
12.5
ns
ns
ns
J4 TCLK rise and fall times 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 ns
J6 Boundary scan input data hold time after TCLK rise 0 ns
J7 TCLK low to boundary scan output data valid 25 ns
J8 TCLK low to boundary scan output high-Z 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 ns
J10 TMS, TDI input data hold time after TCLK rise 1.4 ns
J11 TCLK low to TDO data valid 22.1 ns
J12 TCLK low to TDO high-Z 22.1 ns
J13 TRST assert time 100 ns
J14 TRST setup time (negation) to TCLK high 8 ns
Figure 5. Test clock input timing
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 25
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 6. Boundary scan (JTAG) timing
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 7. Test Access Port timing
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
26 Freescale Semiconductor, Inc.
TRST
J14
J13
TCLK
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) — user
trimmed
31.25 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
± 0.3 ± 0.6 %fdco 1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
± 0.2 ± 0.5 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
+0.5/-0.7 ± 3 %fdco 1,
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
± 0.3 ± 3 %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— kHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 27
rung
Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
FLL
ffll_ref FLL reference frequency range 31.25 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
— 23.99 — MHz 4, 5
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × ffll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
180
150
ps
tfll_acquire FLL target frequency acquisition time 1 ms 6
PLL
fvco VCO operating frequency 48.0 100 MHz
Ipll PLL operating current
PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
— 1060 — µA 7
Ipll PLL operating current
PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
— 600 — µA 7
fpll_ref PLL reference frequency range 2.0 4.0 MHz
Jcyc_pll PLL period jitter (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
120
50
ps
ps
8
Jacc_pll PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
1350
600
ps
ps
8
Dlock Lock entry frequency tolerance ± 1.49 ± 2.98 %
Dunl Lock exit frequency tolerance ± 4.47 ± 5.97 %
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
28 Freescale Semiconductor, Inc.
Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
tpll_lock Lock detector detection time 150 × 10-6
+ 1075(1/
fpll_ref)
s9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz
500
200
300
950
1.2
1.5
nA
μA
μA
μA
mA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 29
rung
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDDOSC Supply current — high gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz
25
400
500
2.5
3
4
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance 2, 3
CyXTAL load capacitance 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 —
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — —
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 —
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — —
Series resistor — low-frequency, high-gain mode
(HGO=1)
— 200 —
Series resistor — high-frequency, low-power
mode (HGO=0)
— — —
Series resistor — high-frequency, high-gain
mode (HGO=1)
0
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
30 Freescale Semiconductor, Inc.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 32 MHz
fec_extal Input clock frequency (external clock mode) 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
This section describes the module electrical characteristics.
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit
VBAT Supply voltage 1.71 3.6 V
RFInternal feedback resistor 100
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 31
rcllp
Table 18. 32kHz oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
Cpara Parasitical capacitance of EXTAL32 and XTAL32 5 7 pF
Vpp1Peak-to-peak amplitude of oscillation 0.6 V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal 32.768 kHz
tstart Crystal start-up time 1000 ms 1
fec_extal32 Externally provided input clock frequency 32.768 kHz 2
vec_extal32 Externally provided input clock amplitude 700 VBAT mV 2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time 7.5 18 μs
thversscr Sector Erase high-voltage time 13 113 ms 1
thversblk256k Erase Block high-voltage time for 256 KB 104 904 ms 1
1. Maximum time based on expectations at cycling end-of-life.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
32 Freescale Semiconductor, Inc.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk256k
Read 1s Block execution time
256 KB program/data flash
1.7
ms
trd1sec2k Read 1s Section execution time (flash sector) 60 μs 1
tpgmchk Program Check execution time 45 μs 1
trdrsrc Read Resource execution time 30 μs 1
tpgm4 Program Longword execution time 65 145 μs
tersblk256k
Erase Flash Block execution time
256 KB program/data flash
122
985
ms
2
tersscr Erase Flash Sector execution time 14 114 ms 2
tpgmsec512
tpgmsec1k
tpgmsec2k
Program Section execution time
512 bytes flash
1 KB flash
2 KB flash
2.4
4.7
9.3
ms
ms
ms
trd1all Read 1s All Blocks execution time 1.8 ms
trdonce Read Once execution time 25 μs 1
tpgmonce Program Once execution time 65 μs
tersall Erase All Blocks execution time 250 2000 ms 2
tvfykey Verify Backdoor Access Key execution time 30 μs 1
tswapx01
tswapx02
tswapx04
tswapx08
Swap Control execution time
control code 0x01
control code 0x02
control code 0x04
control code 0x08
200
70
70
150
150
30
μs
μs
μs
μs
tpgmpart64k
tpgmpart256k
Program Partition for EEPROM execution time
64 KB FlexNVM
256 KB FlexNVM
138
145
ms
ms
tsetramff
tsetram32k
tsetram64k
tsetram256k
Set FlexRAM Function execution time:
Control Code 0xFF
32 KB EEPROM backup
64 KB EEPROM backup
256 KB EEPROM backup
70
0.8
1.3
4.5
1.2
1.9
5.5
μs
ms
ms
ms
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
175 260 μs 3
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 33
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Table 21. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
Byte-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
385
475
650
1000
1800
2000
2400
3200
μs
μs
μs
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
175 260 μs
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
Word-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
385
475
650
1000
1800
2000
2400
3200
μs
μs
μs
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
360 540 μs
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
Longword-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
256 KB EEPROM backup
630
810
1200
1900
2050
2250
2675
3500
μs
μs
μs
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
1.5 4.0 mA
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
34 Freescale Semiconductor, Inc.
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 years
tnvmretp1k Data retention after up to 1 K cycles 20 100 years
nnvmcycp Cycling endurance 10 K 50 K cycles 2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles 5 50 years
tnvmretd1k Data retention after up to 1 K cycles 20 100 years
nnvmcycd Cycling endurance 10 K 50 K cycles 2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance 5 50 years
tnvmretee10 Data retention up to 10% of write endurance 20 100 years
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree32k
Write endurance
EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 4096
EEPROM backup to FlexRAM ratio =
32,768
35 K
315 K
1.27 M
10 M
80 M
175 K
1.6 M
6.4 M
50 M
400 M
writes
writes
writes
writes
writes
3
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash
memory module to obtain an effective endurance increase for the EEPROM data. The
built-in EEPROM record management system raises the number of program/erase cycles
that can be attained prior to device wear-out by cycling the EEPROM data through a
larger EEPROM NVM storage space.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 35
rump EEPROM — 2 x EEESPLIT x EEESIZE EEESPLIT x EEESIZE
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem = × Write_efficiency × n
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE nvmcycd
where
Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
Write_efficiency —
0.25 for 8-bit writes to FlexRAM
0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000
cycles)
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
36 Freescale Semiconductor, Inc.
LTDOD‘K‘LWO 100,000,000 10,000,000 —x-hn 1.000000 — 1602 bk Minimum Writes lo FIeIRAM 04 256 1,024 4,096 16,384 Ratio of EEPROM Backup to FlexflAM
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
EP1 EZP_CK frequency of operation (all commands except
READ)
— fSYS/2 MHz
EP1a EZP_CK frequency of operation (READ command) fSYS/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 ns
EP7 EZP_CK low to EZP_Q output valid 16 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 ns
EP9 EZP_CS negation to EZP_Q tri-state 12 ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 37
rcllll
EP2
EP3
EP4
EP5 EP6
EP7 EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation FB_CLK MHz
FB1 Clock period 20 ns
FB2 Address, data, and control output valid 11.5 ns 1
FB3 Address, data, and control output hold 0.5 ns 1
FB4 Data and FB_TA input setup 8.5 ns 2
FB5 Data and FB_TA input hold 0.5 ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
38 Freescale Semiconductor, Inc.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V
Frequency of operation FB_CLK MHz
FB1 Clock period 1/FB_CLK ns
FB2 Address, data, and control output valid 13.5 ns 1
FB3 Address, data, and control output hold 0 ns 1
FB4 Data and FB_TA input setup 13.7 ns 2
FB5 Data and FB_TA input hold 0.5 ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 39
FB TS FB CSn FB OEn FB BEn FB TA
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB5
FB4
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
Figure 11. FlexBus read timing diagram
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
40 Freescale Semiconductor, Inc.
FB TS FB_CSn FB OEn FB BEn FB TA
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
Figure 12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 41
rcllp
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 29 and
Table 30.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage 16-bit differential mode
All other modes
VREFL
VREFL
31/32 *
VREFH
VREFH
V
CADIN Input capacitance 16-bit mode
8-bit / 10-bit / 12-bit
modes
8
4
10
5
pF
RADIN Input resistance 2 5
RAS Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
5
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 18.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
818.330
Ksps
5
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
42 Freescale Semiconductor, Inc.
S‘MPLIFIED
Table 27. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
461.467
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS
CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PININPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 13. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 1.7 mA 3
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 43
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Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
fADACK
ADC
asynchronous
clock source
ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
12-bit modes
<12-bit modes
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
12-bit modes
<12-bit modes
±0.7
±0.2
-1.1 to +1.9
-0.3 to 0.5
LSB45
INL Integral non-
linearity
12-bit modes
<12-bit modes
±1.0
±0.5
-2.7 to +1.9
-0.7 to +0.5
LSB45
EFS Full-scale error 12-bit modes
<12-bit modes
-4
-1.4
-5.4
-1.8
LSB4VADIN =
VDDA
5
EQQuantization
error
16-bit modes
≤13-bit modes
-1 to 0
±0.5
LSB4
ENOB Effective number
of bits
16-bit differential mode
Avg = 32
Avg = 4
16-bit single-ended mode
Avg = 32
Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
bits
bits
bits
bits
6
SINAD Signal-to-noise
plus distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
–94
-85
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
82
78
95
90
dB
dB
7
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
44 Freescale Semiconductor, Inc.
ENOB 15mm Mm 144m 14m 138m 135m 132m 129m 125m 123m 12mm Typical ADC 16-bit Differential ENOB vs ADC Clock “NHL 90% F5 Sine lnpu‘ Havdwave Avevagmg Dwsab‘ed Avevagmg um samp‘es Avevagmg um samp‘es Avevagmg uvaz samp‘es A 5 E 7 ADC Clock Frequency (MHz) 8 m M 12
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 45
ENOB 14mm 1375 135a 1325 13mm 1275 125a 1225 12mm 1175 115a 1125 11mm Typical ADC 16-bit Single-Ended ENOB vs ADC Clock “NHL 90% F5 Sine lnpu‘ Avevagmg um Sammes Avevagmg D132 Sammes 3 A 5 E 7 ADC Clock Frequency (MHz) 8 1U 11 12
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 3.6 V
VREFPGA PGA ref voltage VREF_OU
T
VREF_OU
T
VREF_OU
T
V2, 3
VADIN Input voltage VSSA — VDDA V
VCM Input Common
Mode range
VSSA — VDDA V
RPGAD Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
128
64
32
IN+ to IN-4
RAS Analog source
resistance
— 100 — Ω 5
TSADC sampling
time
1.25 — µs 6
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
46 Freescale Semiconductor, Inc.
2 ((vau/xxn- Rwy/u) (Cam+l)
Table 29. 16-bit ADC with PGA operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
18.484 — 450 Ksps 7
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
37.037 — 250 Ksps 8
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics with Chop enabled
(ADC_PGA[PGACHPb] =0)
Table 30. 16-bit ADC with PGA characteristics
Symbol Description Conditions Min. Typ.1Max. Unit Notes
IDDA_PGA Supply current Low power
(ADC_PGA[PGALPb]=0)
420 644 μA 2
IDC_PGA Input DC current A 3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
— 1.54 — μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
— 0.57 — μA
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 47
rung (1min[vx,vnmwxyo.2><4) cam="">
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
G Gain4• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
PGAG=6
0.95
1.9
3.8
7.6
15.2
30.0
58.8
1
2
4
8
16
31.6
63.3
1.05
2.1
4.2
8.4
16.6
33.2
67.8
RAS < 100Ω
BW Input signal
bandwidth
16-bit modes
< 16-bit modes
4
40
kHz
kHz
PSRR Power supply
rejection ratio
Gain=1 -84 dB VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
-84
-85
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
VOFS Input offset
voltage
0.2 mV Output offset =
VOFS*(Gain+1)
TGSW Gain switching
settling time
10 µs 5
dG/dT Gain drift over full
temperature range
• Gain=1
• Gain=64
6
31
10
42
ppm/°C
ppm/°C
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
0.07
0.14
0.21
0.31
%/V
%/V
VDDA from 1.71
to 3.6V
EIL Input leakage
error
All modes IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
signal swing where VX = VREFPGA × 0.583
V6
SNR Signal-to-noise
ratio
• Gain=1
• Gain=64
80
52
90
66
dB
dB
16-bit
differential
mode,
Average=32
THD Total harmonic
distortion
• Gain=1
• Gain=64
85
49
100
95
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
48 Freescale Semiconductor, Inc.
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
SFDR Spurious free
dynamic range
• Gain=1
• Gain=64
85
53
105
88
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
ENOB Effective number
of bits
Gain=1, Average=4
Gain=1, Average=8
Gain=64, Average=4
Gain=64, Average=8
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32
11.6
8.0
7.2
6.3
12.8
11.0
7.9
7.3
6.8
6.8
7.5
13.4
13.6
9.6
9.6
14.5
14.3
13.8
13.1
12.5
11.5
10.6
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100Hz
SINAD Signal-to-noise
plus distortion
ratio
See ENOB 6.02 × ENOB + 1.76 dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) 20 μA
VAIN Analog input voltage VSS – 0.3 VDD V
VAIO Analog input offset voltage 20 mV
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 49
rcllp
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
VHAnalog comparator hysteresis1
CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11
5
10
20
30
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 V
VCMPOl Output low 0.5 V
tDHS Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Analog comparator initialization delay2 — 40 μs
IDAC6b 6-bit DAC current adder (enabled) 7 μA
INL 6-bit DAC integral non-linearity –0.5 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
50 Freescale Semiconductor, Inc.
0.04
0.05
0.06
0.07
0.08
P Hystereris (V)
00
01
10
HYSTCTR
Setting
0
0.01
0.02
0.03
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CM
10
11
Vin level (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 51
rump 0.18 1.6 Vinlwelm
0 08
0.1
0.12
0.14
0.16
0.18
P Hystereris (V)
00
01
10
HYSTCTR
Setting
0
0.02
0.04
0.06
0.08
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CMP
10
11
Vin level (V)
Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 pF 2
ILOutput load current 1 mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
52 Freescale Semiconductor, Inc.
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode 330 μA
IDDA_DACH
P
Supply current — high-speed mode 1200 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
— 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— ±1 LSB 4
VOFFSET Offset error ±0.4 ±0.8 %FSR 5
EGGain error ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA > = 2.4 V 60 90 dB
TCO Temperature coefficient offset voltage 3.7 μV/C 6
TGE Temperature coefficient gain error 0.000421 %FSR/C
Rop Output resistance load = 3 kΩ 250 Ω
SR Slew rate -80h F7Fh 80h
High power (SPHP)
Low power (SPLP)
1.2
0.05
1.7
0.12
V/μs
CT Channel to channel cross talk -80 dB
BW 3dB bandwidth
High power (SPHP)
Low power (SPLP)
550
40
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 53
a 33:: «GE .1 am new" on.
Figure 18. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
54 Freescale Semiconductor, Inc.
1493 ms: L491 L .19: 1.4575 omega; 080 .0301. RE 503 H515: mos m as 55 Ten puaure °c
Figure 19. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 34. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 55
rung
Table 35. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915 1.195 1.1977 V
Vout Voltage reference output — factory trim 1.1584 1.2376 V
Vout Voltage reference output — user trim 1.193 1.197 V
Vstep Voltage reference trim step 0.5 mV
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
80 mV
Ibg Bandgap only current 80 µA 1
Ilp Low-power buffer current 360 uA 1
Ihp High-power buffer current 1 mA 1
ΔVLOAD Load regulation
current = ± 1.0 mA
200
µV 1, 2
Tstup Buffer startup time 100 µs
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C
Table 37. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
56 Freescale Semiconductor, Inc.
6.8.1 CAN switching specifications
See General switching specifications.
6.8.2 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation 25 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid 8 ns
DS6 DSPI_SCK to DSPI_SOUT invalid 0 ns
DS7 DSPI_SIN to DSPI_SCK input setup 14 ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 20. DSPI classic SPI timing — master mode
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 57
Table 39. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation 12.5 MHz
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 ns
DS15 DSPI_SS active to DSPI_SOUT driven 14 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven 14 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 21. DSPI classic SPI timing — slave mode
6.8.3 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation 12.5 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
58 Freescale Semiconductor, Inc.
Table 40. Master mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit Notes
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -1.2 ns
DS7 DSPI_SIN to DSPI_SCK input setup 19.1 ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 22. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation 6.25 MHz
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid 24 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 ns
DS13 DSPI_SIN to DSPI_SCK input setup 3.2 ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 ns
DS15 DSPI_SS active to DSPI_SOUT driven 19 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven 19 ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 59
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
6.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 42. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 0.6 µs
LOW period of the SCL clock tLOW 4.7 — 1.3 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 0.6 µs
Data hold time for I2C bus devices tHD; DAT 013.452030.91µs
Data set-up time tSU; DAT 2504— 1002, 5— ns
Rise time of SDA and SCL signals tr 1000 20 +0.1Cb6300 ns
Fall time of SDA and SCL signals tf 300 20 +0.1Cb5300 ns
Set-up time for STOP condition tSU; STO 4 0.6 µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
60 Freescale Semiconductor, Inc.
6. Cb = total capacitance of the one bus line in pF.
SDA
SCL
tHD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
Figure 24. Timing definition for fast and standard mode devices on the I2C bus
6.8.5 UART switching specifications
See General switching specifications.
6.8.6 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 43. SDHC switching specifications
Num Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
fOD Clock frequency (identification mode) 0 400 kHz
SD2 tWL Clock low time 7 ns
SD3 tWH Clock high time 7 ns
SD4 tTLH Clock rise time 3 ns
SD5 tTHL Clock fall time 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 tOD SDHC output delay (output valid) -5 8.3 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 tISU SDHC input setup time 5 ns
SD8 tIH SDHC input hold time 0 ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 61
SD2SD3 SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 25. SDHC timing
6.8.7 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.7.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S1 I2S_MCLK cycle time 40 ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
15 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
62 Freescale Semiconductor, Inc.
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num. Characteristic Min. Max. Unit
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 26. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
Multiple SAI Synchronous mode
All other modes
21
15
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 63
H H H
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num. Characteristic Min. Max. Unit
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 ns
S17 I2S_RXD setup before I2S_RX_BCLK 4.5 ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 27. I2S/SAI timing — slave modes
6.8.7.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 46. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0 — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
64 Freescale Semiconductor, Inc.
Table 46. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num. Characteristic Min. Max. Unit
S7 I2S_TX_BCLK to I2S_TXD valid 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 28. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
Multiple SAI Synchronous mode
All other modes
24
20.6
ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 65
H H H
Table 47. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num. Characteristic Min. Max. Unit
S17 I2S_RXD setup before I2S_RX_BCLK 5.8 ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 29. I2S/SAI timing — slave modes
6.8.7.3 VLPR, VLPW, and VLPS mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 48. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 62.5 ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid 45 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
66 Freescale Semiconductor, Inc.
Table 48. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num. Characteristic Min. Max. Unit
S8 I2S_TX_BCLK to I2S_TXD invalid 0 ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 30. I2S/SAI timing — master modes
Table 49. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
3 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid 63 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 67
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 31. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 50. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDDTSI Operating voltage 1.71 3.6 V
CELE Target electrode capacitance range 1 20 500 pF 1
fREFmax Reference oscillator frequency 8 15 MHz 2, 3
fELEmax Electrode oscillator frequency 1 1.8 MHz 2, 4
CREF Internal reference capacitor 1 pF
VDELTA Oscillator delta voltage 500 mV 2, 5
IREF Reference oscillator current source base current
2 μA setting (REFCHRG = 0)
32 μA setting (REFCHRG = 15)
2
36
3
50
μA 2, 6
IELE Electrode oscillator current source base current
2 μA setting (EXTCHRG = 0)
32 μA setting (EXTCHRG = 15)
2
36
3
50
μA 2, 7
Pres5 Electrode capacitance measurement precision 8.3333 38400 fF/count 8
Pres20 Electrode capacitance measurement precision 8.3333 38400 fF/count 9
Pres100 Electrode capacitance measurement precision 8.3333 38400 fF/count 10
MaxSens Maximum sensitivity 0.008 1.46 fF/count 11
Res Resolution 16 bits
TCon20 Response time @ 20 pF 8 15 25 μs 12
ITSI_RUN Current added in run mode 55 μA
ITSI_LP Low power mode current adder 1.3 2.5 μA 13
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
68 Freescale Semiconductor, Inc.
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
144-pin LQFP 98ASS23177W
144-pin MAPBGA 98ASA00222D
8 Pinout
Dimensions
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 69
mu
8.1 K10 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
L5 RTC_
WAKEUP_B
RTC_
WAKEUP_B
RTC_
WAKEUP_B
M5 NC NC NC
A10 NC NC NC
B10 NC NC NC
C10 NC NC NC
1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT
2 D2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN
3 D1 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_
b
SDHC0_DCLK
4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_
b
SDHC0_CMD SPI1_SOUT
5 E5 VDD VDD VDD
6 F6 VSS VSS VSS
7 E3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_
b
I2S0_MCLK
10 F4 PTE7 DISABLED PTE7 UART3_RTS_
b
I2S0_RXD0
11 F3 PTE8 DISABLED PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS
12 F2 PTE9 DISABLED PTE9 I2S0_TXD1 UART5_RX I2S0_RX_
BCLK
13 F1 PTE10 DISABLED PTE10 UART5_CTS_
b
I2S0_TXD0
14 G4 PTE11 DISABLED PTE11 UART5_RTS_
b
I2S0_TX_FS
15 G3 PTE12 DISABLED PTE12 I2S0_TX_
BCLK
16 E6 VDD VDD VDD
17 F7 VSS VSS VSS
18 H1 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3
19 H2 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_
ALT3
20 G1 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_
b
I2C0_SDA
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
70 Freescale Semiconductor, Inc.
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
21 G2 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_
b
I2C0_SCL
22 H3 VSS VSS VSS
23 J1 ADC0_DP1 ADC0_DP1 ADC0_DP1
24 J2 ADC0_DM1 ADC0_DM1 ADC0_DM1
25 K1 ADC1_DP1 ADC1_DP1 ADC1_DP1
26 K2 ADC1_DM1 ADC1_DM1 ADC1_DM1
27 L1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
28 L2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
29 M1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
30 M2 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
31 H5 VDDA VDDA VDDA
32 G5 VREFH VREFH VREFH
33 G6 VREFL VREFL VREFL
34 H6 VSSA VSSA VSSA
35 K3 ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
36 J3 ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
37 M3 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
38 L3 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
39 L4 DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
40 M7 XTAL32 XTAL32 XTAL32
41 M6 EXTAL32 EXTAL32 EXTAL32
42 L6 VBAT VBAT VBAT
43 — VDD VDD VDD
44 — VSS VSS VSS
45 M4 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 71
mu
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
46 K5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN
47 K4 PTE26 DISABLED PTE26 UART4_CTS_
b
RTC_CLKOUT
48 J4 PTE27 DISABLED PTE27 UART4_RTS_
b
49 H4 PTE28 DISABLED PTE28
50 J5 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
51 J6 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
52 K6 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
53 K7 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
54 L7 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
55 M8 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_TX_
BCLK
JTAG_TRST_
b
56 E7 VDD VDD VDD
57 G7 VSS VSS VSS
58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_
CLKOUT
59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 FTM0_CH4 TRACE_D3
60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 FTM1_CH0 FTM1_QD_
PHA
TRACE_D2
61 L8 PTA9 DISABLED PTA9 FTM1_CH1 FTM1_QD_
PHB
TRACE_D1
62 M9 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_
PHA
TRACE_D0
63 L9 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_
PHB
64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
65 J9 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_
BCLK
I2S0_TXD1
67 L11 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b/
UART0_COL_
b
I2S0_RX_FS I2S0_RXD1
69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b
I2S0_MCLK
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
72 Freescale Semiconductor, Inc.
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
70 E8 VDD VDD VDD
71 G8 VSS VSS VSS
72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_
ALT1
74 L12 RESET_b RESET_b RESET_b
75 K12 PTA24 DISABLED PTA24 FB_A29
76 J12 PTA25 DISABLED PTA25 FB_A28
77 J11 PTA26 DISABLED PTA26 FB_A27
78 J10 PTA27 DISABLED PTA27 FB_A26
79 H12 PTA28 DISABLED PTA28 FB_A25
80 H11 PTA29 DISABLED PTA29 FB_A24
81 H10 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
82 H9 PTB1 ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
83 G12 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_
b
FTM0_FLT3
84 G11 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_
b/
UART0_COL_
b
FTM0_FLT0
85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 FTM1_FLT0
86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 FTM2_FLT0
87 F12 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23
88 F11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22
89 F10 PTB8 DISABLED PTB8 UART3_RTS_
b
FB_AD21
90 F9 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_
b
FB_AD20
91 E12 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1
92 E11 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2
93 H7 VSS VSS VSS
94 F5 VDD VDD VDD
95 E10 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN
96 E9 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b
97 D12 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_
BCLK
FB_AD15 FTM2_QD_
PHA
98 D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_
PHB
99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT
100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 73
mu
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT
102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28
103 B12 PTC0 ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14 I2S0_TXD1
104 B11 PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_
b
FTM0_CH0 FB_AD13 I2S0_TXD0
105 A12 PTC2 ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CTS_
b
FTM0_CH1 FB_AD12 I2S0_TX_FS
106 A11 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_
BCLK
107 H8 VSS VSS VSS
108 — VDD VDD VDD
109 A9 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT
110 D8 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 FB_AD10 CMP0_OUT
111 C8 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG I2S0_RX_
BCLK
FB_AD9 I2S0_MCLK
112 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN I2S0_RX_FS FB_AD8
113 A8 PTC8 ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8 I2S0_MCLK FB_AD7
114 D7 PTC9 ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9 I2S0_RX_
BCLK
FB_AD6 FTM2_FLT0
115 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL I2S0_RX_FS FB_AD5
116 B7 PTC11/
LLWU_P11
ADC1_SE7b ADC1_SE7b PTC11/
LLWU_P11
I2C1_SDA I2S0_RXD1 FB_RW_b
117 A7 PTC12 DISABLED PTC12 UART4_RTS_
b
FB_AD27
118 D6 PTC13 DISABLED PTC13 UART4_CTS_
b
FB_AD26
119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25
120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24
121 — VSS VSS VSS
122 — VDD VDD VDD
123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
b
124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_
b
125 C5 PTC18 DISABLED PTC18 UART3_RTS_
b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
74 Freescale Semiconductor, Inc.
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
126 B5 PTC19 DISABLED PTC19 UART3_CTS_
b
FB_CS3_b/
FB_BE7_0_b
FB_TA_b
127 A5 PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_
b
FB_ALE/
FB_CS1_b/
FB_TS_b
128 D4 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_
b
FB_CS0_b
129 C4 PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART2_RX FB_AD4
130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3
131 A4 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_
b
FTM0_CH4 FB_AD2 EWM_IN
132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 FB_AD1 EWM_OUT_b
133 A2 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
134 M10 VSS VSS VSS
135 F8 VDD VDD VDD
136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16
138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17
139 B3 PTD10 DISABLED PTD10 UART5_RTS_
b
FB_A18
140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_
b
SDHC0_
CLKIN
FB_A19
141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20
142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21
143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22
144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23
8.2 K10 pinouts
The figure below shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 75
rmw HnflHnflnnflnnHnflnnflnnflnflflnflflnnflnflnnflnfl I'll—”1|"I'll—Ifll—Ifll—Il—Il—H—H—Il—‘fll—IflI'll—Ifll—Il—Ifll—Il—‘fll—Ifll—Il—Ifll—Il—Ifll—I uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
75
74
73
60
59
58
57
56
55
54
53
52
51
72
71
70
69
68
67
66
65
64
63
62
61
25
24
23
22
21
40
39
38
37
50
49
48
47
46
45
44
43
42
41
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
98
97
96
95
94
93
92
91
90
89
88
80
81
82
83
84
85
86
87
100
108 VDD
107
106
105
104
103
102
101
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB23
PTB22
116 PTC11/LLWU_P11
115
114
113
112
111
110
109
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
124 PTC17
123
122
121
120
119
118
117
PTC16
VDD
VSS
PTC15
PTC14
PTC13
PTC12
132 PTD5
131
130
129
128
127
126
125
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC19
PTC18
140 PTD11
139
138
137
136
135
134
133
PTD10
PTD9
PTD8
PTD7
VDD
VSS
PTD6/LLWU_P15
144
143
142
141
PTD15
PTD14
PTD13
PTD12
PTB20
PTA28
PTA27
PTA26
PTA25
PTB19
PTB18
PTB17
PTB16
VDD
VSS
PTB11
PTB10
PTB9
PTB8
PTB7
PTA29
PTB0/LLWU_P5
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB21
PTA24
RESET_b
PTA19
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13/LLWU_P4
PTA12
PTA11
PTA10
PTA9
PTA8
PTA7
PTA6
VSS
VDD
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE28
PTE27
PTE26
PTE25
PTE24
VSS
VDD
VBAT
EXTAL32
XTAL32
DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
PTE18
PTE17
PTE16
VSS
VDD
PTE12
PTE11
PTE10
PTE9
PTE8
PTE7
PTE6
PTE5
PTE4/LLWU_P2
VSS
VDD
PTE3
PTE2/LLWU_P1
PTE1/LLWU_P0
PTE0
ADC1_DP1
ADC0_DM1
ADC0_DP1
VSS
PTE19
ADC0_SE16/CMP1_IN2/ADC0_SE21
ADC1_SE16/CMP2_IN2/ADC0_SE22
VSSA
VREFL
VREFH
VDDA
PGA1_DM/ADC1_DM0/ADC0_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA0_DP/ADC0_DP0/ADC1_DP3
ADC1_DM1
Figure 32. K10 144 LQFP Pinout Diagram
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
76 Freescale Semiconductor, Inc.
m H 12
1 2 3456789
12 3 456789
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
10
K
K
10
11
11
LL
12
12
MM PTA18
PTC8 PTC4/ NC PTC3/ PTC2
PTA1 PTA6PTA0PTE27
ADC0_SE16/
ADC1_SE16/ PTE26 PTE25 PTA2 PTA3 PTA8
PTA7
VSSVSSVSSAVDDAPTE28VSSPTE17
ADC0_DM1
ADC1_DM1
PGA0_DM/ DAC0_OUT/ DAC1_OUT/ RTC VBAT PTA4/ PTA9 PTA11
PTA12
PTA13/
PTB1
PTA27
PTB0/
PTB4PTB5VSSVSSVREFLVREFHPTE11PTE12PTE19PTE18
PTE16
ADC0_DP1
ADC1_DP1
PGA0_DP/
PGA1_DP/ PGA1_DM/ VREF_OUT/
PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS
PTA16
PTA14
PTB3
PTA29
PTA26
PTA17
PTA15
PTA19
RESET_b
PTA24
PTA25
PTA28
PTB2
PTB6PTB7PTB8PTB9VDD
VDD PTB17 PTB16 PTB10PTB11
PTB19 PTB18
PTB22PTB23NC
PTB20PTB21
PTC5/
PTD8
PTC6/
PTC7 PTD9 NC PTC1/ PTC0
VSS VSS
VDDVDD
PTC13 PTC9
PTC11/
PTC10
PTC19 PTC15
PTC14PTC18
PTD2/
PTD3PTD10
PTD13
PTE0 PTD1 PTC17
VDD
VDDPTE7
PTE3
PTE4/
PTE8PTE9PTE10
PTE6 PTE5
PTE1/PTE2/
PTD15 PTD14
PTD11PTD12
PTC12PTC16
PTD0/PTD4/
PTD5
PTD6/
PTD7 LLWU_P15 LLWU_P14 LLWU_P12 LLWU_P8 LLWU_P7
LLWU_P11 LLWU_P6
LLWU_P13 LLWU_P10
LLWU_P1 LLWU_P0 LLWU_P9
LLWU_P2
LLWU_P5
CMP1_IN2/
ADC0_SE21 LLWU_P4
CMP2_IN2/
ADC0_SE22
ADC0_DP0/
ADC1_DP3 ADC0_DM0/
ADC1_DM3 CMP1_IN3/
ADC0_SE23
CMP0_IN4/
CMP2_IN3/
ADC1_SE23 LLWU_P3
ADC1_DP0/
ADC0_DP3 ADC1_DM0/
ADC0_DM3
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
_WAKEUP_B
Figure 33. K10 144 MAPBGA Pinout Diagram
9 Revision history
The following table provides a revision history for this document.
Table 51. Revision history
Rev. No. Date Substantial Changes
1 6/2012 Initial public revision
Table continues on the next page...
Revision history
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
Freescale Semiconductor, Inc. 77
Table 51. Revision history (continued)
Rev. No. Date Substantial Changes
2 12/2012 Replaced TBDs throughout.
3 6/2013 In ESD handling ratings, added a note for ILAT.
Updated "Voltage and current operating requirements" Table 1.
Updated IOL data for VOL row in "Voltage and current operating behaviors" Table 4.
Updated wakeup times and tPOR value in "Power mode transition operating behaviors"
Table 5.
In "EMC radiated emissions operating behaviors . . ." Table 7, added a column for
144MAPBGA.
In "16-bit ADC operating conditions" Table 27, updated the max spec of VADIN.
In "16-bit ADC electrical characteristics" Table 28, updated the temp sensor slope and
voltage specs.
Updated Inter-Integrated Circuit Interface (I2C) timing.
In SDHC specifications, added operating voltage row.
Revision history
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
78 Freescale Semiconductor, Inc.
freescale"
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer’s technical experts. Freescale does not convey any
license under its patent rights nor the rights of others. Freescale sells products pursuant
to standard terms and conditions of sale, which can be found at the following address:
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How to Reach Us:
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Freescale, the Freescale logo and Kinetis are trademarks of Freescale Semiconductor,
Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property
of their respective owners. ARM is the registered trademark of ARM Limited. Cortex-M4
is the trademark of ARM Limited.
© 2012–2013Freescale Semiconductor, Inc.
Document Number: K10P144M100SF2V2
Rev. 3
06/2013

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