Z8 Encore! XP F082A Series Datasheet by Zilog

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PS022829-0814
Product Specification
High-Performance 8-Bit Microcontrollers
Z8 Encore! XP® F082A
Series
Copyright ©2014 Zilog®, Inc. All rights reserved.
www.zilog.com
mxu
PS022829-0814 P R E L I M I N A R Y Disclaimer
Z8 Encore! XP® F082A Series
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product
or service names are the property of their respective owners.
Warning:
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PS022829-0814 P R E L I M I N A R Y Revision History
Z8 Encore! XP® F082A Series
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Date Revision
Level Chapter/Section Description Page
No.
Aug
2014 29 Direct LED Drive Features
Alternative Function Register
Port Alternate Function Map-
ping
Clarified the Enabling through the LED
senence. Corrected Port C enabling sen-
tence. Added LED Drive to the Alternate
function description in table 14.
38, 40,
53
Apr
2013 28 Timer Pin Signal Operation Clarified use/availabity of the T0OUT and
T1OUT timer functions by mode. 84
Dec
2012 27 Port Alternate Function Map-
ping (Non 8-Pin Parts), Port
Alternate Function Mapping (8-
Pin Parts)
Added missing Port D data to Table 15; cor-
rected active Low status (set overlines) for
PA0 (T0OUT), PA2 (RESET) and PA5
(T1OUT) in Table 16.
40, 43
Sep
2011 26 LED Drive Enable Register Clarified statement surrounding the Alternate
Function Register as it relates to the LED
function; revised Flash Sector Protect Regis-
ter description; revised Packaging chapter.
53,
157,
245
Sep
2008 25 Overview, Address Space,
Register Map, General-Pur-
pose Input/Output, Available
Packages, Ordering Informa-
tion
Added references to F042A Series back in
Table 1, Table 5, Table 7 and Table 14. 2, 8,
16, 18,
36,
246
May
2008 24 Overview, Address Space,
Register Map, General-Pur-
pose Input/Output, Available
Packages, Ordering Informa-
tion
Changed title to Z8 Encore! XP F082A Series
and removed references to F042A Series in
Table 1, Table 5, Table 7 and Table 14.
2, 8,
16, 18,
36,
246
Dec
2007 23 Pin Description, General-Pur-
pose Input/Output, Watchdog
Timer
Updated Figure 3, Table 15, Tables 60
through 62. 9, 40,
97
Jul
2007 22 Electrical Characteristics Updated Tables 16 and 132; power con-
sumption data. 43,
229
Jun
2007 21 n/a Revision number update. All
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PS022829-0814 P R E L I M I N A R Y Table of Contents
Z8 Encore! XP® F082A Series
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Low-Power Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Low Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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PS022829-0814 P R E L I M I N A R Y Table of Contents
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Product Specification
v
Reset, Stop Mode Recovery and Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Stop Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . . . . . . . . 28
Stop Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . . . . 28
Stop Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . . . . . . . . 29
Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Shared Debug Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port A–D Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–D Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port A–D Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port A–D Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port A–D Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LED Drive Level High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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PS022829-0814 P R E L I M I N A R Y Table of Contents
Z8 Encore! XP® F082A Series
Product Specification
vi
LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Mode Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Watchdog Timer Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timer 0–1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Timer 0–1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Watchdog Timer Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . . 97
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Product Specification
vii
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 102
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . 104
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . 123
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Hardware Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
ADC Compensation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Input Buffer Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ADC Control/Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC Data Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Low Power Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Comparator Control Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Temperature Sensor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . 149
Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Flash Code Protection Against Accidental Program and Erasure . . . . . . . . . . . . . 149
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Reading the Flash Information Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Flash Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Flash Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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Trim Bit Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Trim Bit Address 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Temperature Sensor Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Watchdog Timer Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Randomized Lot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Nonvolatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
NVDS Code Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Power Failure Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Optimizing NVDS Memory Usage for Execution Speed . . . . . . . . . . . . . . . . . . . . 178
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
OCD Unlock Sequence (8-Pin Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 233
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . 240
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
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List of Figures
Figure 1. Z8 Encore! XP F082A Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 8-Pin SOIC, QFN/MLF-S,
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 20-Pin SOIC, SSOP
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 28-Pin SOIC, SSOP
or PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 10. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 11. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . 101
Figure 12. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . 101
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . . . . 105
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 107
Figure 15. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 109
Figure 16. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . . 120
Figure 17. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 18. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 19. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 125
Figure 20. Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 21. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 22. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 23. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface;
#1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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Product Specification
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Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface;
#2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 26. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 27. Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 199
Figure 28. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 201
Figure 29. Typical RC Oscillator Frequency as a Function of the External Capacitance
with a 45 k Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 30. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 31. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 32. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 33. Typical Active Mode IDD Versus System Clock Frequency . . . . . . . . . . 231
Figure 34. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 35. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 36. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 37. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 38. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
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Z8 Encore! XP® F082A Series
Product Specification
xiii
List of Tables
Table 1. Z8 Encore! XP F082A Series Family Part Selection Guide . . . . . . . . . . . . . 2
Table 2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Pin Characteristics (20- and 28-pin Devices) . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Pin Characteristics (8-Pin Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Z8 Encore! XP F082A Series Program Memory Maps . . . . . . . . . . . . . . . . 16
Table 6. Z8 Encore! XP F082A Series Flash Memory Information Area Map . . . . . 17
Table 7. Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 23
Table 9. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 28
Table 11. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Reset and Stop Mode Recovery Bit Descriptions . . . . . . . . . . . . . . . . . . . . 31
Table 13. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) . . . . . . . . . . . . . . . . . . 40
Table 16. Port Alternate Function Mapping (8-Pin Parts) . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Port A–D GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Port A–D GPIO Address Registers by Bit Description . . . . . . . . . . . . . . . . 45
Table 20. Port A–D Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Port A–D Data Direction Subregisters (PxDD) . . . . . . . . . . . . . . . . . . . . . . 46
Table 22. Port A–D Alternate Function Subregisters (PxAF) . . . . . . . . . . . . . . . . . . . 47
Table 23. Port A–D Output Control Subregisters (PxOC) . . . . . . . . . . . . . . . . . . . . . 48
Table 24. Port A–D High Drive Enable Subregisters (PxHDE) . . . . . . . . . . . . . . . . . 48
Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE) . . 49
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE) . . . . . . . . . . . . . . . . . . . . 50
Table 27. Port A–D Alternate Function Set 2 Subregisters (PxAFS2) . . . . . . . . . . . . 51
Table 28. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) . . . . . . . . . . . . 51
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Product Specification
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Table 29. Port A–C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30. Port A–D Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 31. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 32. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . . 53
Table 33. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . . 54
Table 34. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 36. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 38. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 63
Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 41. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 43. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 65
Table 44. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 66
Table 46. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 47. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 48. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 49. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 50. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 51. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 52. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 53. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 54. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 91
Table 55. Timer 0–1 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 91
Table 56. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 92
Table 57. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 92
Table 58. Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . 93
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Product Specification
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Table 59. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . . 96
Table 60. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . . 97
Table 61. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . . 97
Table 62. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . 98
Table 63. UART Control 0 Register (U0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 64. UART Control 1 Register (U0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 65. UART Status 0 Register (U0STAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 66. UART Status 1 Register (U0STAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 67. UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 68. UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 69. UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . . . . . 117
Table 70. UART Baud Rate High Byte Register (U0BRH) . . . . . . . . . . . . . . . . . . . 117
Table 71. UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . . . . . 117
Table 72. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 73. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 74. ADC Control/Status Register 1 (ADCCTL1) . . . . . . . . . . . . . . . . . . . . . . 136
Table 75. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 76. ADC Data Low Byte Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 77. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 78. Z8 Encore! XP F082A Series Flash Memory Configurations . . . . . . . . . . 146
Table 79. Flash Code Protection Using the Flash Option Bits . . . . . . . . . . . . . . . . . 150
Table 80. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 81. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 82. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 83. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 84. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 158
Table 85. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 158
Table 86. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 87. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 88. Flash Option Bits at Program Memory Address 0000H . . . . . . . . . . . . . . 162
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Product Specification
xvi
Table 89. Flash Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . 164
Table 90. Trim Options Bits at Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 91. Trim Option Bits at 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 92. Trim Option Bits at 0002H (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 93. Trim Option Bits at Address 0003H (TLVD) . . . . . . . . . . . . . . . . . . . . . . 166
Table 94. LVD Trim Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 95. Trim Option Bits at 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 96. ADC Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 97. ADC Calibration Data Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 98. Temperature Sensor Calibration High Byte at 003A (TSCALH) . . . . . . . 171
Table 99. Temperature Sensor Calibration Low Byte at 003B (TSCALL) . . . . . . . . 171
Table 100. Watchdog Calibration High Byte at 007EH (WDTCALH) . . . . . . . . . . . . 172
Table 101. Serial Number at 001C - 001F (S_NUM) . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 102. Serialization Data Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 103. Watchdog Calibration Low Byte at 007FH (WDTCALL) . . . . . . . . . . . . 173
Table 104. Lot Identification Number (RAND_LOT) . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 105. Randomized Lot ID Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 106. Write Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 107. NVDS Read Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 108. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 109. Debug Command Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 110. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 111. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 112. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 114. Recommended Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . 200
Table 115. Transconductance Values for Low, Medium and High Gain Operating
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 116. Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 117. Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 118. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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PS022829-0814 P R E L I M I N A R Y List of Tables
Z8 Encore! XP® F082A Series
Product Specification
xvii
Table 119. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 120. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 121. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 122. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 123. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 124. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 125. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 126. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 127. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 128. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 129. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 130. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 131. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 132. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 133. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 134. Internal Precision Oscillator Electrical Characteristics . . . . . . . . . . . . . . . 232
Table 135. Power-On Reset and Voltage Brown-Out Electrical Characteristics
and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 136. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 234
Table 137. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 235
Table 138. Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 139. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . 236
Table 140. Low Power Operational Amplifier Electrical Characteristics . . . . . . . . . . 238
Table 141. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 142. Temperature Sensor Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 239
Table 143. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 144. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 145. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 146. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 147. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 148. Z8 Encore! XP F082A Series Ordering Matrix . . . . . . . . . . . . . . . . . . . . . 246
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PS022829-0814 P R E L I M I N A R Y Overview
Z8 Encore! XP® F082A Series
Product Specification
1
Overview
Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller
products based upon the 8-bit eZ8 CPU. Zilogs Z8 Encore! XP F082A Series products
expand upon Zilogs extensive line of 8-bit microcontrollers. The Flash in-circuit pro-
gramming capability allows for faster development time and program changes in the field.
The new eZ8 CPU is upward compatible with existing Z8 instructions. The rich peripheral
set of the Z8 Encore! XP F082A Series makes it suitable for a variety of applications
including motor control, security systems, home appliances, personal electronic devices
and sensors.
Features
The key features of Z8 Encore! XP F082A Series products include:
20 MHz eZ8 CPU
1 KB, 2 KB, 4 KB, or 8 KB Flash memory with in-circuit programming capability
256 B, 512 B, or 1 KB register RAM
Up to 128 B nonvolatile data storage (NVDS)
Internal precision oscillator trimmed to ±1% accuracy
External crystal oscillator, operating up to 20 MHz
Optional 8-channel, 10-bit analog-to-digital converter (ADC)
Optional on-chip temperature sensor
On-chip analog comparator
Optional on-chip low-power operational amplifier (LPO)
Full-duplex UART
The UART baud rate generator (BRG) can be configured and used as a basic 16-bit timer
Infrared Data Association (IrDA)-compliant infrared encoder/decoders, integrated
with the UART
Two enhanced 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
Up to 20 vectored interrupts
6 to 25 I/O pins depending upon package
Up to thirteen 5 V-tolerant input pins
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PS022829-0814 P R E L I M I N A R Y Part Selection Guide
Z8 Encore! XP® F082A Series
Product Specification
2
Up to 8 ports capable of direct LED drive with no current limit resistor required
On-Chip Debugger (OCD)
Voltage Brown-Out (VBO) protection
Programmable low battery detection (LVD) (8-pin devices only)
Bandgap generated precision voltage references available for the ADC, comparator,
VBO and LVD
Power-On Reset (POR)
2.7 V to 3.6 V operating voltage
8-, 20- and 28-pin packages
0°C to +70°C and –40°C to +105°C for operating temperature ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP F082A Series product line.
Table 1. Z8 Encore! XP F082A Series Family Part Selection Guide
Part
Number Flash
(KB) RAM
(B) NVDS1
(B) I/O Comparator Advanced
Analog2ADC
Inputs Packages
Z8F082A 8 1024 0 6–23 Yes Yes 4–8 8-, 20- and 28-pin
Z8F081A 8 1024 0 6–25 Yes No 0 8-, 20- and 28-pin
Z8F042A 4 1024 128 6–23 Yes Yes 4–8 8-, 20- and 28-pin
Z8F041A 4 1024 128 6–25 Yes No 0 8-, 20- and 28-pin
Z8F022A 2 512 64 6–23 Yes Yes 4–8 8-, 20- and 28-pin
Z8F021A 2 512 64 6–25 Yes No 0 8-, 20- and 28-pin
Z8F012A 1 256 16 6–23 Yes Yes 4–8 8-, 20- and 28-pin
Z8F011A 1 256 16 6–25 Yes No 0 8-, 20- and 28-pin
Notes:
1. Non-volatile data storage.
2. Advanced Analog includes ADC, temperature sensor and low-power operational amplifier.
PS022829-0814 P R E L I M I N A R Y Block Diagram
Z8 Encore! XP® F082A Series
Product Specification
3
Block Diagram
Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP F082A
Series devices.
Figure 1. Z8 Encore! XP F082A Series Block Diagram
GPIO
IrDA
UART Timers ADC
Flash Memory
Flash
Controller
RAM
RAM
Controller
Interrupt
Controller
On-Chip
Debugger
eZ8
CPU WDT
POR/VBO
and Reset
Controller
XTAL/RC
Oscillator
Register Bus
Memory Busses
System
Clock
Comparator
Temperature
Sensor
NVDS
Controller
Low Power
RC Oscillator
Internal
Oscillator
Control
Oscillator
Precision
Low
Power
Op Amp
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PS022829-0814 P R E L I M I N A R Y CPU and Peripheral Overview
Z8 Encore! XP® F082A Series
Product Specification
4
CPU and Peripheral Overview
The eZ8 CPU, Zilog’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8 instruction set. The features of eZ8 CPU include:
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program
memory
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-
level programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC,
LDC, LDCI, LEA, MULT and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information about eZ8 CPU, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
10-Bit Analog-to-Digital Converter
The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit
binary number. The ADC accepts inputs from eight different analog input pins in both sin-
gle-ended and differential modes. The ADC also features a unity gain buffer when high
input impedance is required.
Low-Power Operational Amplifier
The optional low-power operational amplifier (LPO) is a general-purpose amplifier pri-
marily targeted for current sense applications. The LPO output may be routed internally to
the ADC or externally to a pin.
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PS022829-0814 P R E L I M I N A R Y CPU and Peripheral Overview
Z8 Encore! XP® F082A Series
Product Specification
5
Internal Precision Oscillator
The internal precision oscillator (IPO) is a trimmable clock source that requires no exter-
nal components.
Temperature Sensor
The optional temperature sensor produces an analog output proportional to the device tem-
perature. This signal can be sent to either the ADC or the analog comparator.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal pro-
grammable voltage reference or a second input pin. The comparator output can be used to
drive either an output pin or to generate an interrupt.
External Crystal Oscillator
The crystal oscillator circuit provides highly accurate clock frequencies with the use of an
external crystal, ceramic resonator or RC network.
Low Voltage Detector
The low voltage detector (LVD) is able to generate an interrupt when the supply voltage
drops below a user-programmable level. The LVD is available on 8-pin devices only.
On-Chip Debugger
The Z8 Encore! XP F082A Series products feature an integrated on-chip debugger (OCD)
accessed via a single-pin interface. The OCD provides a rich-set of debugging capabilities,
such as reading and writing registers, programming Flash memory, setting breakpoints and
executing code.
Universal Asynchronous Receiver/Transmitter
The full-duplex universal asynchronous receiver/transmitter (UART) is included in all Z8
Encore! XP package types. The UART supports 8- and 9-bit data modes and selectable
parity. The UART also supports multi-drop address processing in hardware. The UART
baud rate generator (BRG) can be configured and used as a basic 16-bit timer.
Timers
Two enhanced 16-bit reloadable timers can be used for timing/counting events or for
motor control operations. These timers provide a 16-bit programmable reload counter and
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PS022829-0814 P R E L I M I N A R Y CPU and Peripheral Overview
Z8 Encore! XP® F082A Series
Product Specification
6
operate in One-Shot, Continuous, Gated, Capture, Capture Restart, Compare, Capture and
Compare, PWM Single Output and PWM Dual Output modes.
General-Purpose Input/Output
The Product Line MCUs feature 6 to 25 port pins (Ports A–D) for general- purpose input/
output (GPIO). The number of GPIO pins available is a function of package and each pin
is individually programmable. 5 V tolerant input pins are available on all
I/Os on 8-pin devices and most I/Os on other package types.
Direct LED Drive
The 20- and 28-pin devices support controlled current sinking output pins capable of driv-
ing LEDs without the need for a current limiting resistor. These LED drivers are indepen-
dently programmable to four different intensity levels.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports
several protection mechanisms against accidental program and erasure, plus factory serial-
ization and read protection.
Non-Volatile Data Storage
The nonvolatile data storage (NVDS) uses a hybrid hardware/software scheme to imple-
ment a byte programmable data memory and is capable of over 100,000 write cycles.
Devices with 8 KB of Flash memory do not include the NVDS feature.
Interrupt Controller
The Z8 Encore! XP F082A Series products support up to 20 interrupts. These interrupts
consist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources.
The interrupts have three levels of programmable interrupt priority.
Reset Controller
The Z8 Encore! XP F082A Series products can be reset using the RESET pin, Power-On
Reset, Watchdog Timer (WDT) time-out, Stop Mode exit, or Voltage Brown-Out (VBO)
warning signal. The RESET pin is bidirectional, that is, it functions as reset source and as
a reset indicator.
Note:
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PS022829-0814 P R E L I M I N A R Y Pin Description
Z8 Encore! XP® F082A Series
Product Specification
8
Pin Description
The Z8 Encore! XP F082A Series products are available in a variety of packages styles
and pin configurations. This chapter describes the signals and available pin configurations
for each of the package styles. For information about physical package specifications, see
the Packaging chapter on page 245.
Available Packages
The following package styles are available for each device in the Z8 Encore! XP F082A
Series product line:
SOIC: 8-, 20- and 28-pin
PDIP: 8-, 20- and 28-pin
SSOP: 20- and 28- pin
QFN 8-pin (MLF-S, a QFN-style package with an 8-pin SOIC footprint)
In addition, the Z8 Encore! XP F082A Series devices are available both with and without
advanced analog capability (ADC, temperature sensor and op amp). Devices Z8F082A,
Z8F042A, Z8F022A and Z8F012A contain the advanced analog, while devices Z8F081A,
Z8F041A, Z8F021A and Z8F011A do not have the advanced analog capability.
Pin Configurations
Figure 2 through Figure 4 display the pin configurations for all the packages available in
the Z8 Encore! XP F082A Series. See Table 2 on page 10 for a description of the signals.
The analog input alternate functions (ANAx) are not available on the Z8F081A, Z8F041A,
Z8F021A and Z8F011A devices. The analog supply pins (AVDD and AVSS) are also not
available on these parts and are replaced by PB6 and PB7.
At reset, all Port A, B and C pins default to an input state. In addition, any alternate func-
tionality is not enabled, so the pins function as general purpose input ports until pro-
grammed otherwise. At powerup, the PD0 pin defaults to the RESET alternate function.
The pin configurations listed are preliminary and subject to change based on manufactur-
ing limitations.
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PS022829-0814 P R E L I M I N A R Y Pin Configurations
Z8 Encore! XP® F082A Series
Product Specification
9
Figure 2. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP Package
Figure 3. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 20-Pin SOIC, SSOP or PDIP Package
Figure 4. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 28-Pin SOIC, SSOP or PDIP Package
VSS
PA5/TXD0/T1OUT/ANA0/CINP/AMPOUT
PA4/RXD0/ANA1/CINN/AMPINN
PA3/CTS0/ANA2/COUT/AMPINP/T1IN
VDD
PA0/T0IN/T0OUT/XIN//DBG
PA1/T0OUT/XOUT/ANA3/VREF/CLKIN
PA2/RESET/DE0/T1OUT
2
1
3
4
7
8
6
5
PB0/ANA0/AMPOUT
PC3/COUT/LED
PC2/ANA6/LED/VREF
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET/PD0
PA7/T1OUT
PA6/T1IN/T1OUT
PB1/ANA1/AMPINN
PB2/ANA2/AMPINP
PB3/CLKIN/ANA3
VDD
PA0/T0IN/T0OUT/XIN
PA1/T0OUT/XOUT
VSS
PA2/DE0
1
PA5/TXD0
PA3/CTS0
5
10
PA4/RXD0
2
3
4
6
7
8
9
20
16
11
19
18
17
15
14
13
12
PB1/ANA1/AMPINN
PB0/ANA0/AMPOUT
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET/PD0
PC7/LED
PB2/ANA2/AMPINP
PB3/CLKIN/ANA3
PB4/ANA7
PB5/VREF
(PB6) AVDD
VDD
PA0/T0IN/T0OUT/XIN
PA1/T0OUT/XOUT
1
PC6/LED
VSS
5
10
(PB7) AVSS
PA2/DE0
PA3/CTS0
PA4/RXD0
14
PA5/TXD0
2
3
4
6
7
8
9
11
12
13
PC5/LED
PC4/LED
PA7/T1OUT
PA6/T1IN/T1OUT
28
24
19
15
27
26
25
23
22
21
20
18
17
16
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PS022829-0814 P R E L I M I N A R Y Signal Descriptions
Z8 Encore! XP® F082A Series
Product Specification
10
Signal Descriptions
Table 2 describes the Z8 Encore! XP F082A Series signals. See the Pin Configurations
section on page 8 to determine the signals available for the specific package styles.
Table 2. Signal Descriptions
Signal Mnemonic I/O Description
General-Purpose I/O Ports A–D
PA[7:0] I/O Port A. These pins are used for general-purpose I/O.
PB[7:0] I/O Port B. These pins are used for general-purpose I/O. PB6 and PB7 are
available only in those devices without an ADC.
PC[7:0] I/O Port C. These pins are used for general-purpose I/O.
PD[0] I/O Port D. This pin is used for general-purpose output only.
UART Controllers
TXD0 O Transmit Data. This signal is the transmit output from the UART and IrDA.
RXD0 I Receive Data. This signal is the receive input for the UART and IrDA.
CTS0 I Clear To Send. This signal is the flow control input for the UART.
DE O Driver Enable. This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the TXE (Transmit
Empty) bit in the UART Status 0 Register. The DE signal may be used to
ensure the external RS-485 driver is enabled when data is transmitted by
the UART.
Timers
T0OUT/T1OUT O Timer Output 0–1. These signals are outputs from the timers.
T0OUT/T1OUT O Timer Complement Output 0–1. These signals are output from the timers
in PWM Dual Output mode.
T0IN/T1IN I Timer Input 0–1. These signals are used as the capture, gating and coun-
ter inputs.
Comparator
CINP/CINN I Comparator Inputs. These signals are the positive and negative inputs to
the comparator.
COUT O Comparator Output.
Notes:
1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS.
2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
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PS022829-0814 P R E L I M I N A R Y Signal Descriptions
Z8 Encore! XP® F082A Series
Product Specification
11
Analog
ANA[7:0] I Analog Port. These signals are used as inputs to the analog-to-digital con-
verter (ADC).
VREF I/O Analog-to-digital converter reference voltage input, or buffered output for
internal reference.
Low-Power Operational Amplifier (LPO)
AMPINP/AMPINN I LPO inputs. If enabled, these pins drive the positive and negative amplifier
inputs respectively.
AMPOUT O LPO output. If enabled, this pin is driven by the on-chip LPO.
Oscillators
XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. In
addition, this pin is used with external RC networks or external clock driv-
ers to provide the system clock.
XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the XIN pin to form the oscillator.
Clock Input
CLKIN I Clock Input Signal. This pin may be used to input a TTL-level signal to be
used as the system clock.
LED Drivers
LED O Direct LED drive capability. All port C pins have the capability to drive an
LED without any other external components. These pins have programma-
ble drive strengths set by the GPIO block.
On-Chip Debugger
DBG I/O Debug. This signal is the control and data input and output to and from the
On-Chip Debugger.
Caution: The DBG pin is open-drain and requires a pull-up resistor to
ensure proper operation.
Table 2. Signal Descriptions (Continued)
Signal Mnemonic I/O Description
Notes:
1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS.
2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
mxu Table 4
PS022829-0814 P R E L I M I N A R Y Pin Characteristics
Z8 Encore! XP® F082A Series
Product Specification
12
Pin Characteristics
Table 3 describes the characteristics for each pin available on the Z8 Encore! XP F082A
Series 20- and 28-pin devices. Data in Table 3 is sorted alphabetically by the pin symbol
mnemonic.
Table 4 on page 14 provides detailed information about the characteristics for each pin
available on the Z8 Encore! XP F082A Series 8-pin devices.
All six I/O pins on the 8-pin packages are 5 V-tolerant (unless the pull-up devices are
enabled). The column in Table 3 below describes 5 V-tolerance for the 20- and 28-pin
packages only.
Reset
RESET I/O RESET. Generates a Reset when asserted (driven Low). Also serves as a
reset indicator; the Z8 Encore! XP forces this pin low when in reset. This
pin is open-drain and features an enabled internal pull-up resistor.
Power Supply
VDD I Digital Power Supply.
AVDD I Analog Power Supply.
VSS I Digital Ground.
AVSS I Analog Ground.
Table 2. Signal Descriptions (Continued)
Signal Mnemonic I/O Description
Notes:
1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS.
2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
Note:
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PS022829-0814 P R E L I M I N A R Y Pin Characteristics
Z8 Encore! XP® F082A Series
Product Specification
13
PB6 and PB7 are available only in those devices without ADC.
Table 3. Pin Characteristics (20- and 28-pin Devices)
Symbol
Mnemonic
Direction
Reset
Direction
Active
Low
or
Active
High Tristate
Output
Internal
Pull-up or
Pull-down
Schmitt-
Trigger
Input
Open Drain
Output 5 V
Tolerance
AVDD N/A N/A N/A N/A N/A N/A N/A N/A
AVSS N/A N/A N/A N/A N/A N/A N/A NA
DBG I/O I N/A Yes Yes Yes Yes No
PA[7:0] I/O I N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
PA[7:2]
unless pul-
lups
enabled
PB[7:0] I/O I N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
PB[7:6]
unless pul-
lups
enabled
PC[7:0] I/O I N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
PC[7:3]
unless pul-
lups
enabled
RESET/
PD0 I/O I/O
(defaults to
RESET)
Low (in
Reset
mode)
Yes
(PD0
only)
Programma-
ble for PD0;
always on for
RESET
Yes Programma-
ble for PD0;
always on for
RESET
Yes,
unless pul-
lups
enabled
VDD N/A N/A N/A N/A N/A N/A
VSS N/A N/A N/A N/A N/A N/A
Note:
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PS022829-0814 P R E L I M I N A R Y Pin Characteristics
Z8 Encore! XP® F082A Series
Product Specification
14
)Table 4. Pin Characteristics (8-Pin Devices)
Symbol
Mnemonic
Direction
Reset
Direction
Active
Low
or
Active
High
Tristate
Output
Internal
Pull-up or
Pull-down
Schmitt-
Trigger
Input Open Drain
Output 5 V
Tolerance
PA0/DBG I/O I (but can
change
during
reset if key
sequence
detected)
N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
Yes,
unless
pull-ups
enabled
PA1 I/O I N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
Yes,
unless
pull-ups
enabled
RESET/
PA2 I/O I/O
(defaults
to RESET)
Low (in
Reset
mode)
Yes Programma-
ble for PA2;
always on for
RESET
Yes Programma-
ble for PA2;
always on for
RESET
Yes,
unless
pull-ups
enabled
PA[5:3] I/O I N/A Yes Programma-
ble
Pull-up
Yes Yes,
Programma-
ble
Yes,
unless
pull-ups
enabled
VDD N/A N/A N/A N/A N/A N/A N/A N/A
VSS N/A N/A N/A N/A N/A N/A N/A N/A
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PS022829-0814 P R E L I M I N A R Y Address Space
Z8 Encore! XP® F082A Series
Product Specification
15
Address Space
The eZ8 CPU can access the following three distinct address spaces:
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable
code and/or data.
The Data Memory contains addresses for all memory locations that contain data only.
These three address spaces are covered briefly in the following subsections. For more
information about eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
Register File
The Register File address space in the Z8 Encore! MCU is 4 KB (4096 bytes). The Regis-
ter File is composed of two sections: control registers and general-purpose registers. When
instructions are executed, registers defined as sources are read and registers defined as
destinations are written. The architecture of the eZ8 CPU allows all general-purpose regis-
ters to function as accumulators, address pointers, index registers, stack areas, or scratch
pad memory.
The upper 256 bytes of the 4 KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256 B control register
section are reserved (unavailable). Reading from a reserved Register File address returns
an undefined value. Writing to reserved Register File addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
Z8 Encore! XP F082A Series devices contain 256 B to 1 KB of on-chip RAM. Reading
from Register File addresses outside the available RAM addresses (and not within the con-
trol register address space) returns an undefined value. Writing to these Register File
addresses produces no effect.
Program Memory
The eZ8 CPU supports 64 KB of Program Memory address space. The Z8 Encore! XP
F082A Series devices contain 1 KB to 8 KB of on-chip Flash memory in the Program
Memory address space, depending on the device. Reading from Program Memory
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PS022829-0814 P R E L I M I N A R Y Program Memory
Z8 Encore! XP® F082A Series
Product Specification
16
addresses outside the available Flash memory addresses returns FFH. Writing to these
unimplemented Program Memory addresses produces no effect. Table 5 describes the Pro-
gram Memory Maps for the Z8 Encore! XP F082A Series products.
Table 5. Z8 Encore! XP F082A Series Program Memory Maps
Program Memory Address (Hex) Function
Z8F082A and Z8F081A Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–0039 Reserved
003A–003D Oscillator Fail Trap Vectors
003E–1FFF Program Memory
Z8F042A and Z8F041A Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–0039 Reserved
003A–003D Oscillator Fail Trap Vectors
003E–0FFF Program Memory
Z8F022A and Z8F021A Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–0039 Reserved
003A–003D Oscillator Fail Trap Vectors
003E–07FF Program Memory
Z8F012A and Z8F011A Products
0000–0001 Flash Option Bits
Note: *See Table 32 on page 56 for a list of the interrupt vectors.
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PS022829-0814 P R E L I M I N A R Y Data Memory
Z8 Encore! XP® F082A Series
Product Specification
17
Data Memory
The Z8 Encore! XP F082A Series does not use the eZ8 CPU’s 64 KB Data Memory
address space.
Flash Information Area
Table 6 describes the Z8 Encore! XP F082A Series Flash Information Area. This 128 B
Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When
access is enabled, the Flash Information Area is mapped into the Program Memory and
overlays the 128 bytes at addresses FE00H to FF7FH. When the Information Area access is
enabled, all reads from these Program Memory addresses return the Information Area data
rather than the Program Memory data. Access to the Flash Information Area is read-only.
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–0039 Reserved
003A–003D Oscillator Fail Trap Vectors
003E–03FF Program Memory
Table 6. Z8 Encore! XP F082A Series Flash Memory Information Area Map
Program Memory
Address (Hex) Function
FE00–FE3F Zilog Option Bits/Calibration Data
FE40–FE53 Part Number
20-character ASCII alphanumeric code
Left-justified and filled with FFH
FE54–FE5F Reserved
FE60–FE7F Zilog Calibration Data
FE80–FFFF Reserved
Table 5. Z8 Encore! XP F082A Series Program Memory Maps (Continued)
Program Memory Address (Hex) Function
Note: *See Table 32 on page 56 for a list of the interrupt vectors.
mxu 000000000000 \m‘mLJ-Jo‘oko‘e fl CPU Cove User Manua‘ UM0128
PS022829-0814 P R E L I M I N A R Y Register Map
Z8 Encore! XP® F082A Series
Product Specification
18
Register Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP F082A Series
devices. Not all devices and package styles in the Z8 Encore! XP F082A Series support
the ADC, or all of the GPIO Ports. Consider registers for unimplemented peripherals as
Reserved.
Table 7. Register File Address Map
Address (Hex) Register Description Mnemonic Reset (Hex) Page
General-Purpose RAM
Z8F082A/Z8F081A Devices
000–3FF General-Purpose Register File RAM XX
400–EFF Reserved — XX
Z8F042A/Z8F041A Devices
000–3FF General-Purpose Register File RAM XX
400–EFF Reserved — XX
Z8F022A/Z8F021A Devices
000–1FF General-Purpose Register File RAM XX
200–EFF Reserved XX
Z8F012A/Z8F011A Devices
000–0FF General-Purpose Register File RAM XX
100–EFF Reserved XX
Timer 0
F00 Timer 0 High Byte T0H 00 89
F01 Timer 0 Low Byte T0L 01 89
F02 Timer 0 Reload High Byte T0RH FF 90
F03 Timer 0 Reload Low Byte T0RL FF 90
F04 Timer 0 PWM High Byte T0PWMH 00 91
F05 Timer 0 PWM Low Byte T0PWML 00 91
F06 Timer 0 Control 0 T0CTL0 00 85
F07 Timer 0 Control 1 T0CTL1 00 86
Notes:
1. XX = Undefined.
2. Refer to the eZ8 CPU Core User Manual (UM0128).
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PS022829-0814 P R E L I M I N A R Y Register Map
Z8 Encore! XP® F082A Series
Product Specification
19
Timer 1
F08 Timer 1 High Byte T1H 00 89
F09 Timer 1 Low Byte T1L 01 89
F0A Timer 1 Reload High Byte T1RH FF 90
Timer 1 (cont’d)
F0B Timer 1 Reload Low Byte T1RL FF 90
F0C Timer 1 PWM High Byte T1PWMH 00 91
F0D Timer 1 PWM Low Byte T1PWML 00 91
F0E Timer 1 Control 0 T1CTL0 00 85
F0F Timer 1 Control 1 T1CTL1 00 86
F10–F6F Reserved XX
UART
F40 UART Transmit/Receive Data registers TXD, RXD XX 115
F41 UART Status 0 Register U0STAT0 00 114
F42 UART Control 0 Register U0CTL0 00 110
F43 UART Control 1 Register U0CTL1 00 110
F44 UART Status 1 Register U0STAT1 00 115
F45 UART Address Compare Register U0ADDR 00 116
F46 UART Baud Rate High Byte Register U0BRH FF 117
F47 UART Baud Rate Low Byte Register U0BRL FF 117
Analog-to-Digital Converter (ADC)
F70 ADC Control 0 ADCCTL0 00 134
F71 ADC Control 1 ADCCTL1 80 136
F72 ADC Data High Byte ADCD_H XX 137
F73 ADC Data Low Byte ADCD_L XX 137
F74–F7F Reserved XX
Low Power Control
F80 Power Control 0 PWRCTL0 80 34
F81 Reserved — XX
LED Controller
F82 LED Drive Enable LEDEN 00 53
F83 LED Drive Level High Byte LEDLVLH 00 53
F84 LED Drive Level Low Byte LEDLVLL 00 54
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page
Notes:
1. XX = Undefined.
2. Refer to the eZ8 CPU Core User Manual (UM0128).
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PS022829-0814 P R E L I M I N A R Y Register Map
Z8 Encore! XP® F082A Series
Product Specification
20
F85 Reserved — XX
Oscillator Control
F86 Oscillator Control OSCCTL A0 196
F87–F8F Reserved XX
Comparator 0
F90 Comparator 0 Control CMP0 14 141
F91–FBF Reserved XX
Interrupt Controller
FC0 Interrupt Request 0 IRQ0 00 60
FC1 IRQ0 Enable High Bit IRQ0ENH 00 63
FC2 IRQ0 Enable Low Bit IRQ0ENL 00 63
FC3 Interrupt Request 1 IRQ1 00 61
FC4 IRQ1 Enable High Bit IRQ1ENH 00 65
FC5 IRQ1 Enable Low Bit IRQ1ENL 00 65
FC6 Interrupt Request 2 IRQ2 00 62
FC7 IRQ2 Enable High Bit IRQ2ENH 00 66
FC8 IRQ2 Enable Low Bit IRQ2ENL 00 67
FC9–FCC Reserved XX
FCD Interrupt Edge Select IRQES 00 68
FCE Shared Interrupt Select IRQSS 00 68
FCF Interrupt Control IRQCTL 00 69
GPIO Port A
FD0 Port A Address PAADDR 00 44
FD1 Port A Control PACTL 00 46
FD2 Port A Input Data PAIN XX 46
FD3 Port A Output Data PAOUT 00 46
GPIO Port B
FD4 Port B Address PBADDR 00 44
FD5 Port B Control PBCTL 00 46
FD6 Port B Input Data PBIN XX 46
FD7 Port B Output Data PBOUT 00 46
GPIO Port C
FD8 Port C Address PCADDR 00 44
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page
Notes:
1. XX = Undefined.
2. Refer to the eZ8 CPU Core User Manual (UM0128).
mxu \H‘W“ 03mm PP 03 » ‘h as women: ‘oo‘xl‘xl‘cn‘no 2 as N m m m m m as m V 01 oo 01 oo fl CPU Cove User Manua‘ UM0128
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Z8 Encore! XP® F082A Series
Product Specification
21
FD9 Port C Control PCCTL 00 46
FDA Port C Input Data PCIN XX 46
FDB Port C Output Data PCOUT 00 46
GPIO Port D
FDC Port D Address PDADDR 00 44
FDD Port D Control PDCTL 00 46
FDE Reserved — XX
FDF Port D Output Data PDOUT 00 46
FE0–FEF Reserved XX
Watchdog Timer (WDT)
FF0 Reset Status (Read-only) RSTSTAT X0 29
Watchdog Timer Control (Write-only) WDTCTL N/A 96
FF1 Watchdog Timer Reload Upper Byte WDTU 00 97
FF2 Watchdog Timer Reload High Byte WDTH 04 97
FF3 Watchdog Timer Reload Low Byte WDTL 00 98
FF4–FF5 Reserved XX
Trim Bit Control
FF6 Trim Bit Address TRMADR 00 161
FF7 Trim Bit Data TRMDR 00 162
Flash Memory Controller
FF8 Flash Control FCTL 00 155
FF8 Flash Status FSTAT 00 155
FF9 Flash Page Select FPS 00 156
Flash Sector Protect FPROT 00 157
FFA Flash Programming Frequency High Byte FFREQH 00 158
FFB Flash Programming Frequency Low Byte FFREQL 00 158
eZ8 CPU
FFC Flags XX See
foot-
note 2.
FFD Register Pointer RP XX
FFE Stack Pointer High Byte SPH XX
FFF Stack Pointer Low Byte SPL XX
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page
Notes:
1. XX = Undefined.
2. Refer to the eZ8 CPU Core User Manual (UM0128).
zilog 5mm m w. AHIIX‘ISCM puny
PS022829-0814 P R E L I M I N A R Y Reset, Stop Mode Recovery and Low
Z8 Encore! XP® F082A Series
Product Specification
22
Reset, Stop Mode Recovery and Low
Voltage Detection
The Reset Controller within the Z8 Encore! XP F082A Series controls Reset and Stop
Mode Recovery operation and provides indication of low supply voltage conditions. In
typical operation, the following events cause a Reset:
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash option bit to ini-
tiate a reset)
External RESET pin assertion (when the alternate RESET function is enabled by the
GPIO Register)
On-chip debugger initiated Reset (OCDCTL[0] set to 1)
When the device is in Stop Mode, a Stop Mode Recovery is initiated by either of the fol-
lowing occurrences:
Watchdog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
The low voltage detection circuitry on the device (available on the 8-pin product versions
only) performs the following functions:
Generates the VBO reset when the supply voltage drops below a minimum safe level.
Generates an interrupt when the supply voltage drops below a user-defined level (8-pin
devices only).
Reset Types
The Z8 Encore! XP F082A Series provides several different types of Reset operation. Stop
Mode Recovery is considered as a form of Reset. Table 8 lists the types of Reset and their
operating characteristics. The System Reset is longer if the external crystal oscillator is
enabled by the Flash option bits, allowing additional time for oscillator start-up.
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PS022829-0814 P R E L I M I N A R Y Reset Types
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During a System Reset or Stop Mode Recovery, the Internal Precision Oscillator requires
4 µs to start up. Then the Z8 Encore! XP F082A Series device is held in Reset for 66
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the Flash
option bits, this reset period is increased to 5000 IPO cycles. When a reset occurs because
of a low voltage condition or Power-On Reset (POR), this delay is measured from the time
that the supply voltage first exceeds the POR level. If the external pin reset remains
asserted at the end of the reset period, the device remains in reset until the pin is deas-
serted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 (or PA2 on 8-pin devices) which is shared with the reset pin. On reset,
the PD0 is configured as a bidirectional open-drain reset. The pin is internally driven low
during port reset, after which the user code may reconfigure this pin as a general purpose
output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
As the control registers are reinitialized by a system reset, the system clock after reset is
always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Type
Reset Characteristics and Latency
Control Registers eZ8
CPU Reset Latency (Delay)
System Reset Reset (as applicable) Reset 66 Internal Precision Oscillator Cycles
System Reset with Crystal
Oscillator Enabled Reset (as applicable) Reset 5000 Internal Precision Oscillator Cycles
Stop Mode Recovery Unaffected, except
WDT_CTL and
OSC_CTL registers
Reset 66 Internal Precision Oscillator Cycles
+ IPO startup time
Stop Mode Recovery with
Crystal Oscillator Enabled Unaffected, except
WDT_CTL and
OSC_CTL registers
Reset 5000 Internal Precision Oscillator Cycles
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PS022829-0814 P R E L I M I N A R Y Reset Sources
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Product Specification
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Reset Sources
Table 9 lists the possible sources of a system reset.
Power-On Reset
Z8 Encore! XP F082A Series devices contain an internal Power-On Reset circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer.
After the Z8 Encore! XP F082A Series device exits the Power-On Reset state, the eZ8
CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Reset
Status (RSTSTAT) Register is set to 1.
Figure 5 displays Power-On Reset operation. See Electrical Characteristics on page 221
for the POR threshold voltage (VPOR).
Table 9. Reset Sources and Resulting Reset Type
Operating Mode Reset Source Special Conditions
Normal or Halt modes Power-On Reset/Voltage Brown-
Out Reset delay begins after supply voltage
exceeds POR level.
Watchdog Timer time-out
when configured for Reset None.
RESET pin assertion All reset pulses less than three system clocks
in width are ignored.
On-Chip Debugger initiated Reset
(OCDCTL[0] set to 1) System Reset, except the On-Chip Debugger
is unaffected by the reset.
Stop Mode Power-On Reset/Voltage Brown-
Out Reset delay begins after supply voltage
exceeds POR level.
RESET pin assertion All reset pulses less than the specified analog
delay are ignored. See Table 131 on
page 229.
DBG pin driven Low None.
mxu Electrical Characterisxics a Flash Option Bits
PS022829-0814 P R E L I M I N A R Y Reset Sources
Z8 Encore! XP® F082A Series
Product Specification
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Voltage Brown-Out Reset
The devices in the Z8 Encore! XP F082A Series provide low Voltage Brown-Out (VBO)
protection. The VBO circuit senses when the supply voltage drops to an unsafe level
(below the VBO threshold voltage) and forces the device into the Reset state. While the
supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO
block holds the device in the Reset.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the device
progresses through a full System Reset sequence, as described in the Power-On Reset sec-
tion. Following Power-On Reset, the POR status bit in the Reset Status (RSTSTAT) Regis-
ter is set to 1. Figure 6 displays Voltage Brown-Out operation. See the Electrical
Characteristics chapter on page 226 for the VBO and POR threshold voltages (VVBO and
VPOR).
The Voltage Brown-Out circuit can be either enabled or disabled during Stop Mode. Oper-
ation during Stop Mode is set by the VBO_AO Flash option bit. See the Flash Option Bits
chapter on page 159 for information about configuring VBO_AO.
Figure 5. Power-On Reset Operation
VCC = 0.0 V
VCC = 3.3V
VPOR
VVBO
Internal Precision
Internal RESET
signal
Program
Execution
Oscillator
Start-up
POR
counter delay optional XTAL
counter delay
Oscillator
Crystal
Oscillator
Note: Not to Scale
PS022829-0814 P R E L I M I N A R Y Reset Sources
Z8 Encore! XP® F082A Series
Product Specification
26
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a Power-On Reset after recovering from a VBO condi-
tion.
Watchdog Timer Reset
If the device is operating in Normal or Halt Mode, the Watchdog Timer can initiate a Sys-
tem Reset at time-out if the WDT_RES Flash option bit is programmed to 1, i.e., the
unprogrammed state of the WDT_RES Flash option bit. If the bit is programmed to 0, it
configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT bit in the Reset Status (RSTSTAT) Register is set to signify that the reset was
initiated by the Watchdog Timer.
External Reset Input
The RESET pin has a Schmitt-Triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration may be as short as three clock periods
Figure 6. Voltage Brown-Out Reset Operation
VCC = 3.3V
VPOR
VVBO
Internal RESET
signal
Program
Execution
Program
Execution Voltage
Brown-Out
VCC = 3.3 V
System Clock
POR
counter delayNote: Not to Scale
Table 20 Low- Power Modes Table 135
PS022829-0814 P R E L I M I N A R Y Stop Mode Recovery
Z8 Encore! XP® F082A Series
Product Specification
27
and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP F082A Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the Reset Status (RSTSTAT) Register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see Table 20 on page 46), the
RESET pin functions as an open-drain (active Low) reset mode indicator in addition to the
input functionality. This reset output feature allows a Z8 Encore! XP F082A Series device
to reset other components to which it is connected, even if that reset is caused by internal
sources such as POR, VBO or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 8 has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control Register. The On-Chip Debugger block is not reset but the rest of the
chip goes through a normal system reset. The RST bit automatically clears during the sys-
tem reset. Following the system reset the POR bit in the Reset Status (RSTSTAT) Register
is set.
Stop Mode Recovery
Stop Mode is entered by execution of a Stop instruction by the eZ8 CPU. See the Low-
Power Modes chapter on page 32 for detailed Stop Mode information. During Stop Mode
Recovery (SMR), the CPU is held in reset for 66 IPO cycles if the crystal oscillator is dis-
abled or 5000 cycles if it is enabled. The SMR delay (see Table 135 on page 233) TSMR,
also includes the time required to start up the IPO.
Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer
Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any
Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-
tem clock source is required, the Stop Mode Recovery code must reconfigure the oscillator
control block such that the correct system clock source is enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
mxu Table 135
PS022829-0814 P R E L I M I N A R Y Stop Mode Recovery
Z8 Encore! XP® F082A Series
Product Specification
28
tor address. Following Stop Mode Recovery, the Stop bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
The text following provides more detailed information about each of the Stop Mode
Recovery sources.
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during Stop Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and Stop bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F082A Series device is configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
SMR pulses shorter than specified do not trigger a recovery (see Table 135 on page 233).
In this instance, the Stop bit in the Reset Status (RSTSTAT) Register is set to 1.
In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the Port pin can
initiate Stop Mode Recovery without being written to the Port Input Data Register or
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source Action
Stop Mode Watchdog Timer time-out when configured
for Reset Stop Mode Recovery
Watchdog Timer time-out when configured
for interrupt Stop Mode Recovery followed by
interrupt (if interrupts are enabled)
Data transition on any GPIO port pin enabled
as a Stop Mode Recovery source Stop Mode Recovery
Assertion of external RESET Pin System Reset
Debug Pin driven Low System Reset
Note:
Caution:
Electrical Characteristics Trim Option Bits at Address 0003H TLVD Register GPIO Mode Interrugt Controller
PS022829-0814 P R E L I M I N A R Y Low Voltage Detection
Z8 Encore! XP® F082A Series
Product Specification
29
without initiating an interrupt (if enabled for that pin).
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP F082A Series device is in Stop Mode and the external RESET
pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See
the Electrical Characteristics chapter on page 226 for details.
Low Voltage Detection
In addition to the Voltage Brown-Out (VBO) Reset described above, it is also possible to
generate an interrupt when the supply voltage drops below a user-selected value. For
details about configuring the Low Voltage Detection (LVD) and the threshold levels avail-
able, see the Trim Option Bits at Address 0003H (TLVD) Register on page 166. The LVD
function is available on the 8-pin product versions only.
When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status
(RSTSTAT) Register is set to one. This bit remains one until the low-voltage condition
goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate
an interrupt when so enabled, see the GPIO Mode Interrupt Controller chapter on page 55.
The LVD bit is not latched; therefore, enabling the interrupt is the only way to guarantee
detection of a transient low voltage event.
The LVD functionality depends on circuitry shared with the VBO block; therefore, dis-
abling the VBO also disables the LVD.
Reset Register Definitions
The following sections define the Reset registers.
Reset Status Register
The read-only Reset Status (RSTSTAT) Register, shown in Table 11, indicates the source
of the most recent Reset event, indicates a Stop Mode Recovery event and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0. This regis-
ter shares its address with the write-only Watchdog Timer Control Register.
Table 12 lists the bit settings for Reset and Stop Mode Recovery events.
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PS022829-0814 P R E L I M I N A R Y Reset Register Definitions
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Product Specification
30
Table 11. Reset Status Register (RSTSTAT)
Bit 76543210
Field POR STOP WDT EXT Reserved LVD
RESET See descriptions below 00000
R/W RRRRRRRR
Address FF0H
Bit Description
[7]
POR Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurs. This bit is reset to 0 if a WDT time-out or
Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
[6]
STOP Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurs. If the Stop and WDT bits are both set to 1,
the Stop Mode Recovery occurs because of a WDT time-out. If the Stop bit is 1 and the WDT
bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit is reset by a
Power-On Reset or a WDT time-out that occurred while not in Stop Mode. Reading this register
also resets this bit.
[5]
WDT Watchdog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurs. A POR resets this pin. A Stop Mode Recovery
from a change in an input pin also resets this bit. Reading this register resets this bit. This read
must occur before clearing the WDT interrupt.
[4]
EXT External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurs. A Power-On Reset or
a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit.
[3:1] Reserved
These bits are reserved and must be programmed to 000.
[0]
LVD Low Voltage Detection Indicator
If this bit is set to 1 the current state of the supply voltage is below the low voltage detection
threshold. This value is not latched but is a real-time indicator of the supply voltage level.
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PS022829-0814 P R E L I M I N A R Y Reset Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
31
Table 12. Reset and Stop Mode Recovery Bit Descriptions
Reset or Stop Mode Recovery Event POR STOP WDT EXT
Power-On Reset 1000
Reset using RESET pin assertion 0001
Reset using Watchdog Timer time-out 0010
Reset using the On-Chip Debugger (OCTCTL[1] set to 1) 1000
Reset from Stop Mode using DBG Pin driven Low 1000
Stop Mode Recovery using GPIO pin transition 0100
Stop Mode Recovery using Watchdog Timer time-out 0110
zilog Emmum m m, mum/5m" my the Reset Stag Mode Recovery and Low Voltage Detection
PS022829-0814 P R E L I M I N A R Y Low-Power Modes
Z8 Encore! XP® F082A Series
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32
Low-Power Modes
The Z8 Encore! XP F082A Series products contain power-saving features. The highest
level of power reduction is provided by the Stop Mode, in which nearly all device func-
tions are powered down. The next lower level of power reduction is provided by the Halt
Mode, in which the CPU is powered down.
Further power savings can be implemented by disabling individual peripheral blocks
while in Active mode (defined as being in neither Stop nor Halt Mode).
Stop Mode
Executing the eZ8 CPU’s Stop instruction places the device into Stop Mode, powering
down all peripherals except the Voltage Brown-Out detector, the Low-power Operational
Amplifier and the Watchdog Timer. These three blocks may also be disabled for additional
power savings. Specifically, the operating characteristics are:
Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT
(if previously enabled) are disabled and PA0/PA1 revert to the states programmed by
the GPIO registers
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil-
lator Control Register
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in Stop Mode by the associated Flash option bit, the Voltage
Brown-Out protection circuit continues to operate
Low-power operational amplifier continues to operate if enabled by the Power Control
Register
All other on-chip peripherals are idle
To minimize current in Stop Mode, all GPIO pins that are configured as digital inputs must
be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs configured as
outputs must also be driven to one of the supply rails. The device can be brought out of
Stop Mode using Stop Mode Recovery. For more information about Stop Mode Recovery,
see the Reset, Stop Mode Recovery and Low Voltage Detection chapter on page 22.
zilog 5mm m w. AHIIX‘ISCM puny
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Product Specification
33
Halt Mode
Executing the eZ8 CPU’s Halt instruction places the device into Halt Mode, which powers
down the CPU but leaves all other peripherals active. In Halt Mode, the operating charac-
teristics are:
Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate, if enabled
The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brown-Out reset
External RESET pin assertion
To minimize current in Halt Mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the Stop and Halt modes, it is possible to disable each peripheral on each of
the Z8 Encore! XP F082A Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
The following sections define the Power Control registers.
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block. The default state of the low-power
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PS022829-0814 P R E L I M I N A R Y Power Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
34
operational amplifier (LPO) is OFF. To use the LPO, clear the LPO bit, turning it ON.
Clearing this bit might interfere with normal ADC measurements on ANA0 (the LPO out-
put). This bit enables the amplifier even in Stop Mode. If the amplifier is not required in
Stop Mode, disable it. Failure to perform this results in Stop Mode currents greater than
specified.
This register is only reset during a POR sequence. Other system reset events do not affect it.
Table 13. Power Control Register 0 (PWRCTL0)
Bit 76543210
Field LPO Reserved VBO TEMP ADC COMP Reserved
RESET 10000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address F80H
Bit Description
[7]
LPO Low-Power Operational Amplifier Disable
0 = LPO is enabled (this applies even in Stop Mode).
1 = LPO is disabled.
[6:5] Reserved
These bits are reserved and must be programmed to 00.
[4]
VBO Voltage Brown-Out Detector Disable
This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active.
0 = VBO enabled.
1 = VBO disabled.
[3]
TEMP Temperature Sensor Disable
0 = Temperature Sensor enabled.
1 = Temperature Sensor disabled.
[2]
ADC Analog-to-Digital Converter Disable
0 = Analog-to-Digital Converter enabled.
1 = Analog-to-Digital Converter disabled.
[1]
COMP Comparator Disable
0 = Comparator is enabled.
1 = Comparator is disabled.
[0] Reserved
This bit is reserved and must be programmed to 0.
Note:
mxu
PS022829-0814 P R E L I M I N A R Y Power Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
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Asserting any power control bit disables the targeted block regardless of any enable bits
contained in the target block’s control registers.
Note:
mxu
PS022829-0814 P R E L I M I N A R Y General-Purpose Input/Output
Z8 Encore! XP® F082A Series
Product Specification
36
General-Purpose Input/Output
The Z8 Encore! XP F082A Series products support a maximum of 25 port pins (Ports
A–D) for general-purpose input/output (GPIO) operations. Each port contains control and
data registers. The GPIO control registers determine data direction, open-drain, output
drive current, programmable pull-ups, Stop Mode Recovery functionality and alternate pin
functions. Each port pin is individually programmable. In addition, the Port C pins are
capable of direct LED drive at programmable drive strengths.
GPIO Port Availability By Device
Table 14 lists the port pins available with each device and package type.
Table 14. Port Availability by Device and Package Type
Devices Package ADC Port A Port B Port C Port D Total I/O
Z8F082ASB, Z8F082APB, Z8F082AQB
Z8F042ASB, Z8F042APB, Z8F042AQB
Z8F022ASB, Z8F022APB, Z8F022AQB
Z8F012ASB, Z8F012APB, Z8F012AQB
8-pin Yes [5:0] No No No 6
Z8F081ASB, Z8F081APB, Z8F081AQB
Z8F041ASB, Z8F041APB, Z8F041AQB
Z8F021ASB, Z8F021APB, Z8F021AQB
Z8F011ASB, Z8F011APB, Z8F011AQB
8-pin No [5:0] No No No 6
Z8F082APH, Z8F082AHH, Z8F082ASH
Z8F042APH, Z8F042AHH, Z8F042ASH
Z8F022APH, Z8F022AHH, Z8F022ASH
Z8F012APH, Z8F012AHH, Z8F012ASH
20-pin Yes [7:0] [3:0] [3:0] [0] 17
Z8F081APH, Z8F081AHH, Z8F081ASH
Z8F041APH, Z8F041AHH, Z8F041ASH
Z8F021APH, Z8F021AHH, Z8F021ASH
Z8F011APH, Z8F011AHH, Z8F011ASH
20-pin No [7:0] [3:0] [3:0] [0] 17
Z8F082APJ, Z8F082ASJ, Z8F082AHJ
Z8F042APJ, Z8F042ASJ, Z8F042AHJ
Z8F022APJ, Z8F022ASJ, Z8F022AHJ
Z8F012APJ, Z8F012ASJ, Z8F012AHJ
28-pin Yes [7:0] [5:0] [7:0] [0] 23
Z8F081APJ, Z8F081ASJ, Z8F081AHJ
Z8F041APJ, Z8F041ASJ, Z8F041AHJ
Z8F021APJ, Z8F021ASJ, Z8F021AHJ
Z8F011APJ, Z8F011ASJ, Z8F011AHJ
28-pin No [7:0] [7:0] [7:0] [0] 25
PS022829-0814 P R E L I M I N A R Y Architecture
Z8 Encore! XP® F082A Series
Product Specification
37
Architecture
Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability
to accommodate alternate functions and variable port current drive strength is not dis-
played.
GPIO Alternate Functions
Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip
peripheral functions such as the timers and serial communication devices. The Port A–D
Alternate Function subregisters configure these pins for either General-Purpose I/O or
alternate function operation. When a pin is configured for alternate function, control of the
port pin direction (input/output) is passed from the Port A–D Data Direction registers to
the alternate function assigned to this pin. Table 15 on page 40 lists the alternate functions
possible with each port pin. For those pins with more one alternate function, the alternate
function is defined through Alternate Function Sets subregisters AFS1 and AFS2.
The crystal oscillator functionality is not controlled by the GPIO block. When the crystal
oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1
is overridden. In that case, those pins function as input and output for the crystal oscillator.
Figure 7. GPIO Port Pin Block Diagram
DQ
DQ
DQ
GND
VDD
Port Output Control
Port Data Direction
Port Output
Data Register
Port Input
Data Register
Port
Pin
DATA
Bus
System
Clock
System
Clock
Schmitt-Trigger
mxu Timers e the Electrical Characteristics
PS022829-0814 P R E L I M I N A R Y Direct LED Drive
Z8 Encore! XP® F082A Series
Product Specification
38
PA0 and PA6 contain two different timer functions, a timer input and a complementary
timer output. Both of these functions require the same GPIO configuration, the selection
between the two is based on the timer mode. See the Timers chapter on page 70 for more
details.
For pins with multiple alternate functions, Zilog recommends writing to the AFS1 and
AFS2 subregisters before enabling the alternate function via the AF subregister. As a re-
sult, spurious transitions through unwanted alternate function modes will be prevented.
Direct LED Drive
The Port C pins provide a current sinked output capable of driving an LED without requir-
ing an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA,
13 mA and 20 mA. This mode is enabled through the Alternate Function register and
Alternate Function Subregister AFS1 and is programmable through the LED registers.
The LED Drive Enable (LEDEN) Register turns on the drivers. The LED Drive Level
(LEDLVLH and LEDLVLL) registers select the sink current.
For correct function, the LED anode must be connected to VDD and the cathode to the
GPIO pin. Using all Port C pins in LED drive mode with maximum current may result in
excessive total current. See the Electrical Characteristics chapter on page 226 for the max-
imum total current for the applicable package.
Shared Reset Pin
On the 20- and 28-pin devices, the PD0 pin shares function with a bidirectional reset pin.
Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin
acts as a bidirectional input/open-drain output reset until the software reconfigures it. The
PD0 pin is an output-only open drain when in GPIO mode. There are no pull-up, High
Drive, or Stop Mode Recovery source features associated with the PD0 pin.
On the 8-pin product versions, the reset pin is shared with PA2, but the pin is not limited to
output-only when in GPIO mode.
If PA2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus
drives the pin low during any reset sequence. Since PA2 returns to its RESET alternate
function during system resets, driving it Low holds the chip in a reset state until the pin
is released.
Caution:
Caution:
m w: On-Chig Deblwrrer Oscillator Control Register Definitions Oscillator Control Rewister Definitions
PS022829-0814 P R E L I M I N A R Y Shared Debug Pin
Z8 Encore! XP® F082A Series
Product Specification
39
Shared Debug Pin
On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO
pin. This pin performs as a general purpose input pin on power-up, but the debug logic
monitors this pin during the reset sequence to determine if the unlock sequence occurs. If
the unlock sequence is present, the debug function is unlocked and the pin no longer func-
tions as a GPIO pin. If it is not present, the debug feature is disabled until/unless another
reset event occurs. For more details, see the On-Chip Debugger chapter on page 180.
Crystal Oscillator Override
For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When
the crystal oscillator is enabled, the GPIO settings are overridden and PA0 and PA1 are
disabled. See the Oscillator Control Register Definitions section on page 196 for details.
5 V Tolerance
All six I/O pins on the 8-pin devices are 5 V-tolerant, unless the programmable pull-ups
are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these
parts, excessive current flows through those pull-up devices and can damage the chip.
In the 20- and 28-pin versions of this device, any pin which shares functionality with an
ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0] and
PC[2:0]. All other signal pins are 5 V-tolerant and can safely handle inputs higher than
VDD except when the programmable pull-ups are enabled.
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin
devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator
Control (OSCCTL) Register such that the external oscillator is selected as the system
clock. See the Oscillator Control Register Definitions section on page 196 for details. For
8-pin devices, use PA1 instead of PB3.
Note:
mm- Pon A—D A‘Iernale Funchon Subregxslers PxAF Timer Pin Signal Ogerauon 9 art A—D Allernale Funchon Subregxslers PxAF 9 Fort A—D Allernale Funchon Subregxslers PxAF Porl A D A‘Iernale Funchon Subregxslers FxAF
PS022829-0814 P R E L I M I N A R Y External Clock Setup
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Table 15. Port Alternate Function Mapping (Non 8-Pin Parts)
Port Pin Mnemonic Alternate Function Description Alternate Function
Set Register AFS1
Port A1,2 PA0 T0IN/T0OUT Timer 0 Input/Timer 0 Output Complement N/A
Reserved
PA1 T0OUT Timer 0 Output
Reserved
PA2 DE0 UART 0 Driver Enable
Reserved
PA3 CTS0 UART 0 Clear to Send
Reserved
PA4 RXD0/IRRX0 UART 0/IrDA 0 Receive Data
Reserved
PA5 TXD0/IRTX0 UART 0/IrDA 0 Transmit Data
Reserved
PA6 T1IN/T1OUT Timer 1 Input/Timer 1 Output Complement
Reserved
PA7 T1OUT Timer 1 Output
Reserved
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not
implemented for Port A. Enabling alternate function selections automatically enables the associated alternate
function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
2. Whether PA0/PA6 takes on the timer input or timer output complement function depends on the timer configura-
tion. See the Timer Pin Signal Operation section on page 84 for details.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
4. VREF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
6. Because there is only a single alternate function for the Port PD0 pin, the Alternate Function Set registers are
not implemented for Port D. Enabling alternate function selections automatically enables the associated alter-
nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
mm Pon A—D A‘Iernale Funchon Subregxslers PxAF Timer Pin Signal Ogerauon 9 Fort A—D Allernale Funchon Subregxslers PxAF 9 art A—D Allernale Funchon Subregxslers PxAF Porl A D A‘Iernale Funchon Subregxslers FxAF
PS022829-0814 P R E L I M I N A R Y External Clock Setup
Z8 Encore! XP® F082A Series
Product Specification
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Port B3PB0 Reserved AFS1[0]: 0
ANA0/AMPOUT ADC Analog Input/LPO Output AFS1[0]: 1
PB1 Reserved AFS1[1]: 0
ANA1/AMPINN ADC Analog Input/LPO Input (N) AFS1[1]: 1
PB2 Reserved AFS1[2]: 0
ANA2/AMPINP ADC Analog Input/LPO Input (P) AFS1[2]: 1
PB3 CLKIN External Clock Input AFS1[3]: 0
ANA3 ADC Analog Input AFS1[3]: 1
PB4 Reserved AFS1[4]: 0
ANA7 ADC Analog Input AFS1[4]: 1
PB5 Reserved AFS1[5]: 0
VREF4ADC Voltage Reference AFS1[5]: 1
PB6 Reserved AFS1[6]: 0
Reserved AFS1[6]: 1
PB7 Reserved AFS1[7]: 0
Reserved AFS1[7]: 1
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Port Pin Mnemonic Alternate Function Description Alternate Function
Set Register AFS1
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not
implemented for Port A. Enabling alternate function selections automatically enables the associated alternate
function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
2. Whether PA0/PA6 takes on the timer input or timer output complement function depends on the timer configura-
tion. See the Timer Pin Signal Operation section on page 84 for details.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
4. VREF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
6. Because there is only a single alternate function for the Port PD0 pin, the Alternate Function Set registers are
not implemented for Port D. Enabling alternate function selections automatically enables the associated alter-
nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
mm Pon A—D A‘Iernale Funchon Subregxslers PxAF Timer Pin Signal Ogerauon 9 Fort A—D Allernale Funchon Subregxslers PxAF 9 Fort A—D Allernale Funchon Subregxslers PxAF Porl A—D A‘Iernale Funchon Subregxslers FxAF
PS022829-0814 P R E L I M I N A R Y External Clock Setup
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Product Specification
42
Port C5PC0 Reserved AFS1[0]: 0
ANA4/CINP/LED ADC, Comparator Input, or LED Drive AFS1[0]: 1
PC1 Reserved AFS1[1]: 0
ANA5/CINN/LED ADC, Comparator Input, or LED Drive AFS1[1]: 1
PC2 Reserved AFS1[2]: 0
ANA6/LED/VREF4ADC Analog Input, LED, or ADC Voltage
Reference AFS1[2]: 1
PC3 COUT Comparator Output AFS1[3]: 0
LED LED drive AFS1[3]: 1
PC4 Reserved AFS1[4]: 0
LED LED drive AFS1[4]: 1
PC5 Reserved AFS1[5]: 0
LED LED drive AFS1[5]: 1
PC6 Reserved AFS1[6]: 0
LED LED drive AFS1[6]: 1
PC7 Reserved AFS1[7]: 0
LED LED drive AFS1[7]: 1
Port D6PD0 RESET External Reset N/A
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Port Pin Mnemonic Alternate Function Description Alternate Function
Set Register AFS1
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not
implemented for Port A. Enabling alternate function selections automatically enables the associated alternate
function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
2. Whether PA0/PA6 takes on the timer input or timer output complement function depends on the timer configura-
tion. See the Timer Pin Signal Operation section on page 84 for details.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
4. VREF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
6. Because there is only a single alternate function for the Port PD0 pin, the Alternate Function Set registers are
not implemented for Port D. Enabling alternate function selections automatically enables the associated alter-
nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
mxu Port A—D Alternate Funcuon Subregisters PxAF
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Table 16. Port Alternate Function Mapping (8-Pin Parts)
Port Pin Mnemonic Alternate Function
Description
Alternate
Function Select
Register AFS1
Alternate
Function
Select
Register
AFS2
Port A PA0 T0IN Timer 0 Input AFS1[0]: 0 AFS2[0]: 0
Reserved AFS1[0]: 0 AFS2[0]: 1
Reserved AFS1[0]: 1 AFS2[0]: 0
T0OUT Timer 0 Output Complement AFS1[0]: 1 AFS2[0]: 1
PA1 T0OUT Timer 0 Outp ut AFS1[1]: 0 AFS2[1]: 0
Reserved AFS1[1]: 0 AFS2[1]: 1
CLKIN External Clock Input AFS1[1]: 1 AFS2[1]: 0
Analog Functions1ADC Analog Input/VREF AFS1[1]: 1 AFS2[1]: 1
PA2 DE0 UART 0 Driver Enable AFS1[2]: 0 AFS2[2]: 0
RESET External Reset AFS1[2]: 0 AFS2[2]: 1
T1OUT Timer 1 Output AFS1[2]: 1 AFS2[2]: 0
Reserved AFS1[2]: 1 AFS2[2]: 1
PA3 CTS0 UART 0 Clear to Send AFS1[3]: 0 AFS2[3]: 0
COUT Comparator Output AFS1[3]: 0 AFS2[3]: 1
T1IN Timer 1 Input AFS1[3]: 1 AFS2[3]: 0
Analog Functions2ADC Analog Input/LPO Input (P) AFS1[3]: 1 AFS2[3]: 1
PA4 RXD0 UART 0 Receive Data AFS1[4]: 0 AFS2[4]: 0
Reserved AFS1[4]: 0 AFS2[4]: 1
Reserved AFS1[4]: 1 AFS2[4]: 0
Analog Functions2ADC/Comparator Input (N)/LPO
Input (N) AFS1[4]: 1 AFS2[4]: 1
PA5 TXD0 UART 0 Transmit Data AFS1[5]: 0 AFS2[5]: 0
T1OUT Timer 1 Output Complement AFS1[5]: 0 AFS2[5]: 1
Reserved AFS1[5]: 1 AFS2[5]: 0
Analog Functions2ADC/Comparator Input (P) LPO
Output AFS1[5]: 1 AFS2[5]: 1
Notes:
1. Analog functions include ADC inputs, ADC reference, comparator inputs and LPO ports.
2. The alternate function selection must be enabled; see the Port A–D Alternate Function Subregisters (PxAF) sec-
tion on page 47 for details.
mxu GPIO Mode Imerrugt Controller
PS022829-0814 P R E L I M I N A R Y GPIO Interrupts
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GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupt sources generate an interrupt when any edge occurs
(both rising and falling). See the GPIO Mode Interrupt Controller chapter on page 55 for
more information about interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each port provide access to GPIO control, input data and output data.
Table 17 lists these port registers. Use the Port A–D Address and Control registers
together to provide access to subregisters for port configuration and control.
Table 17. GPIO Port Registers and Subregisters
Port Register Mnemonic Port Register Name
PxADDR Port A–D Address Register; selects subregisters.
PxCTL Port A–D Control Register; provides access to subregisters.
PxIN Port A–D Input Data Register.
PxOUT Port A–D Output Data Register.
Port Subregister Mnemonic Port Register Name
PxDD Data Direction.
PxAF Alternate Function.
PxOC Output Control (Open-Drain).
PxHDE High Drive Enable.
PxSMRE Stop Mode Recovery Source Enable.
PxPUE Pull-up Enable.
PxAFS1 Alternate Function Set 1.
PxAFS2 Alternate Function Set 2.
mxu
PS022829-0814 P R E L I M I N A R Y GPIO Control Register Definitions
Z8 Encore! XP® F082A Series
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Port A–D Address Registers
The Port A–D Address registers select the GPIO port functionality accessible through the
Port A–D Control registers. The Port A–D Address and Control registers combine to pro-
vide access to all GPIO port controls; see Tables 18 and 19.
Table 18. Port A–D GPIO Address Registers (PxADDR)
Bit 76543210
Field PADDR[7:0]
RESET 00H
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FD0H, FD4H, FD8H, FDCH
Bit Description
[7:0]
PADDRx Port Address
The Port Address selects one of the subregisters accessible through the Port Control Register.
Note: x indicates the specific GPIO port pin number (7–0).
Table 19. Port A–D GPIO Address Registers by Bit Description
PADDR[7:0] Port Control Subregister accessible using the Port A–D Control Registers
00H No function. Provides some protection against accidental port reconfiguration.
01H Data Direction.
02H Alternate Function.
03H Output Control (Open-Drain).
04H High Drive Enable.
05H Stop Mode Recovery Source Enable.
06H Pull-up Enable.
07H Alternate Function Set 1.
08H Alternate Function Set 2.
09H–FFH No function.
mxu
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Z8 Encore! XP® F082A Series
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Port A–D Control Registers
The Port A–D Control registers set the GPIO port operation. The value in the correspond-
ing Port A–D Address Register determines which subregister is read from or written to by
a Port A–D Control Register transaction; see Table 20.
Port A–D Data Direction Subregisters
The Port A–D Data Direction subregister is accessed through the Port A–D Control Regis-
ter by writing 01H to the Port A–D Address Register; see Table 21.
Table 20. Port A–D Control Registers (PxCTL)
Bit 76543210
Field PCTL
RESET 00H
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FD1H, FD5H, FD9H, FDDH
Bit Description
[7:0]
PCTLx Port Control
The Port Control Register provides access to all subregisters that configure the GPIO port
operation.
Note: x indicates the specific GPIO port pin number (7–0).
Table 21. Port A–D Data Direction Subregisters (PxDD)
Bit 76543210
Field DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 01H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
DDx Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–D Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–D Input Data Register.
The output driver is tristated.
Note: x indicates the specific GPIO port pin number (7–0).
utxu d in the the Port A—D Alternate Func» tion Set 1 Subregisters GPIO Alternate Func tons e Port A—D Alternate Function Set 2 Subregisters GPIO Alternate Functions
PS022829-0814 P R E L I M I N A R Y GPIO Control Register Definitions
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Port A–D Alternate Function Subregisters
The Port A–D Alternate Function Subregister, shown in Table 22, is accessed through the
Port A–D Control Register by writing 02H to the Port A–D Address Register. The Port
A–D Alternate Function subregisters enable the alternate function selection on pins. If dis-
abled, pins functions as GPIO. If enabled, select one of four alternate functions using
alternate function set subregisters 1 and 2 as described in the the Port A–D Alternate Func-
tion Set 1 Subregisters section on page 50, the GPIO Alternate Functions section on
page 37 and the Port A–D Alternate Function Set 2 Subregisters section on page 51. See
the GPIO Alternate Functions section on page 37 to determine the alternate function asso-
ciated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no associated al-
ternate function. Failure to follow this guideline can result in unpredictable operation.
Port A–D Output Control Subregisters
The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port
A–D Control Register by writing 03H to the Port A–D Address Register. Setting the bits in
the Port A–D Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 22. Port A–D Alternate Function Subregisters (PxAF)
Bit 76543210
Field AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 00H (Ports A–C); 01H (Port D); 04H (Port A of 8-pin device)
R/W R/W
Address If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
AFx Port Alternate Function Enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–D Data Direction subregister
determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set subregisters is enabled.
Port pin operation is controlled by the alternate function.
Note: x indicates the specific GPIO port pin number (7–0).
Caution:
mxu
PS022829-0814 P R E L I M I N A R Y GPIO Control Register Definitions
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Port A–D High Drive Enable Subregisters
The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the
port A–D Control Register by writing 04H to the Port A–D Address Register. Setting the
bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins
for high current output drive operation. The Port A–D High Drive Enable subregister
affects the pins directly and, as a result, alternate functions are also affected.
Table 23. Port A–D Output Control Subregisters (PxOC)
Bit 76543210
Field POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
RESET 00H (Ports A-C); 01H (Port D)
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
POCx Port Output Control
These bits function independently of the alternate function bit and always disable the drains if
set to 1.
0 = The source current is enabled for any output mode unless overridden by the alternate func-
tion (push-pull output).
1 = The source current for the associated pin is disabled (open-drain mode).
Note: x indicates the specific GPIO port pin number (7–0).
Table 24. Port A–D High Drive Enable Subregisters (PxHDE)
Bit 76543210
Field PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
PHDEx Port High Drive Enabled
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
Note: x indicates the specific GPIO port pin number (7–0).
mxu
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Product Specification
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Port A–D Stop Mode Recovery Source Enable Subregisters
The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is
accessed through the Port A–D Control Register by writing 05H to the Port A–D Address
Register. Setting the bits in the Port A–D Stop Mode Recovery Source Enable subregisters
to 1 configures the specified port pins as a Stop Mode Recovery source. During Stop
Mode, any logic transition on a port pin enabled as a Stop Mode Recovery source initiates
Stop Mode Recovery.
Table 25. Port A–D Stop Mode Recovery Source Enable Subregisters (PxSMRE)
Bit 76543210
Field PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 05H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
PSMREx Port Stop Mode Recovery Source Enabled
0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin dur-
ing Stop Mode do not initiate Stop Mode Recovery.
1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin
during Stop Mode initiates Stop Mode Recovery.
Note: x indicates the specific GPIO port pin number (7–0).
mxu GPIO Allernme Functions Port ArD Alternme Function Submnisters
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Product Specification
50
Port A–D Pull-up Enable Subregisters
The Port A–D Pull-up Enable Subregister, shown in Table 26, is accessed through the Port
A–D Control Register by writing 06H to the Port A–D Address Register. Setting the bits in
the Port A–D Pull-up Enable subregisters enables a weak internal resistive pull-up on the
specified port pins.
Port A–D Alternate Function Set 1 Subregisters
The Port A–D Alternate Function Set1 Subregister, shown in Table 27, is accessed
through the Port A–D Control Register by writing 07H to the Port A–D Address Register.
The Alternate Function Set 1 subregisters selects the alternate function available at a port
pin. Alternate Functions selected by setting or clearing bits of this register are defined in
the GPIO Alternate Functions section on page 37.
Alternate function selection on port pins must also be enabled as described in the Port
A–D Alternate Function Subregisters section on page 47.
Table 26. Port A–D Pull-Up Enable Subregisters (PxPUE)
Bit 76543210
Field PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUE0
RESET 00H (Ports A-C); 01H (Port D); 04H (Port A of 8-pin device)
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 06H in Port AD Address Register, accessible through the Port AD Control Register
Bit Description
[7:0]
PPUEx Port Pull-up Enabled
0 = The weak pull-up on the port pin is disabled.
1 = The weak pull-up on the port pin is enabled.
Note: x indicates the specific GPIO port pin number (7–0).
Note:
mxu Table 16 Pon A7D Alter» nule Funcxion Subregi. rs
PS022829-0814 P R E L I M I N A R Y GPIO Control Register Definitions
Z8 Encore! XP® F082A Series
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Port A–D Alternate Function Set 2 Subregisters
The Port A–D Alternate Function Set 2 Subregister, shown in Table 28, is accessed
through the Port A–D Control Register by writing 08H to the Port A–D Address Register.
The Alternate Function Set 2 subregisters selects the alternate function available at a port
pin. Alternate Functions selected by setting or clearing bits of this register is defined in
Table 16 on page 43.
Alternate function selection on the port pins must also be enabled. See the Port A–D Alter-
nate Function Subregisters section on page 47 for details.
Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1)
Bit 76543210
Field PAFS17 PAFS16 PAFS15 PAFS14 PAFS13 PAFS12 PAFS11 PAFS10
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 07H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7:0]
PAFSx Port Alternate Function Set 1
0 = Port Alternate Function selected, as defined in Tables 15 and 16 on page 43.
1 = Port Alternate Function selected, as defined in Tables 15 and 16 on page 43.
Note: x indicates the specific GPIO port pin number (7–0).
Table 28. Port A–D Alternate Function Set 2 Subregisters (PxAFS2)
Bit 76543210
Field PAFS27 PAFS26 PAFS25 PAFS24 PAFS23 PAFS22 PAFS21 PAFS20
RESET 00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device)
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address If 08H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit Description
[7]
PAFS2x Port Alternate Function Set 2
0 = Port Alternate Function selected, as defined in Table 16.
1 = Port Alternate Function selected, as defined in Table 16.
Note: x indicates the specific GPIO port pin number (7–0).
Note:
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Port A–C Input Data Registers
Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled
values from the corresponding port pins. The Port A–C Input Data registers are read-only.
The value returned for any unused ports is 0. Unused ports include those missing on the 8-
and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Port A–D Output Data Register
The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins.
Table 29. Port A–C Input Data Registers (PxIN)
Bit 76543210
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET XXXXXXXX
R/W RRRRRRRR
Address FD2H, FD6H, FDAH
X = Undefined.
Bit Description
[7:0]
PxIN Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates the specific GPIO port pin number (7–0).
Table 30. Port A–D Output Data Register (PxOUT)
Bit 76543210
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FD3H, FD7H, FDBH, FDFH
Bit Description
[7:0]
PxOUT Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the corre-
sponding pin is configured as an output and the pin is not configured for alternate function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates the specific GPIO port pin number (7–0).
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LED Drive Enable Register
The LED Drive Enable Register, shown in Table 31, activates the controlled current drive.
The Port C pin must first be enabled for the LED function by setting Alternate Function
sub-register AFS1 and Alternate Function register.. LEDEN bits [7:0] correspond to Port
C bits [7:0], respectively.
LED Drive Level High Register
The LED Drive Level registers contain two control bits for each Port C pin, as shown in
Table 32. These two bits select between four programmable drive levels. Each pin is indi-
vidually programmable.
Table 31. LED Drive Enable (LEDEN)
Bit 76543210
Field LEDEN[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address F82H
Bit Description
[7:0]
LEDENx LED Drive Enable
These bits determine which Port C pins are connected to an internal current sink.
0 = Tristate the Port C pin.
1 = Enable controlled current sink on the Port C pin.
Note: x indicates the specific GPIO port pin number (7–0).
Table 32. LED Drive Level High Register (LEDLVLH)
Bit 76543210
Field LEDLVLH[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address F83H
Bit Description
[7:0]
LEDLVLHx LED Level High Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.
00 = 3 mA
01 = 7 mA
10 = 13 mA
11 = 20 mA
Note: x indicates the specific GPIO port pin number (7–0).
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LED Drive Level Low Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 33).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 33. LED Drive Level Low Register (LEDLVLL)
Bit 76543210
Field LEDLVLL[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address F84H
Bit Description
[7:0]
LEDLVLLx LED Level Low Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C
pin.
00 = 3 mA
01 = 7 mA
10 = 13 mA
11 = 20 mA
Note: x indicates the specific GPIO port pin number (7–0).
8Z8 CPU Core User Manual UM0128 www.2ilog.com
PS022829-0814 P R E L I M I N A R Y GPIO Mode Interrupt Controller
Z8 Encore! XP® F082A Series
Product Specification
55
GPIO Mode Interrupt Controller
The interrupt controller on the Z8 Encore! XP F082A Series products prioritizes the inter-
rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter-
rupt controller include:
20 possible interrupt sources with 18 unique interrupt vectors:
Twelve GPIO port pin interrupt sources (two interrupt vectors are shared)
Eight on-chip peripheral interrupt sources (two interrupt vectors are shared)
Flexible GPIO interrupts:
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
Three levels of individually programmable interrupt priority
Watchdog Timer and LVD can be configured to generate an interrupt
Supports vectored and polled interrupts
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. For more information about interrupt
servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is
available for download on www.zilog.com.
Interrupt Vector Listing
Table 34 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most-significant byte (MSB) at the even Program Memory address and the
least-significant byte (LSB) at the following odd Program Memory address.
Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is
unavailable on devices not containing an ADC.
Note:
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Table 34. Trap and Interrupt Vectors in Order of Priority
Priority
Program
Memory
Vector Address Interrupt or Trap Source
Highest 0002H Reset (not an interrupt)
0004H Watchdog Timer (see Watchdog Timer)
003AH Primary Oscillator Fail Trap (not an interrupt)
003CH Watchdog Oscillator Fail Trap (not an interrupt)
0006H Illegal Instruction Trap (not an interrupt)
0008H Reserved
000AH Timer 1
000CH Timer 0
000EH UART 0 receiver
0010H UART 0 transmitter
0012H Reserved
0014H Reserved
0016H ADC
0018H Port A Pin 7, selectable rising or falling input edge or LVD (see Reset, Stop
Mode Recovery and Low Voltage Detection)
001AH Port A Pin 6, selectable rising or falling input edge or Comparator Output
001CH Port A Pin 5, selectable rising or falling input edge
001EH Port A Pin 4, selectable rising or falling input edge
0020H Port A Pin 3, selectable rising or falling input edge
0022H Port A Pin 2, selectable rising or falling input edge
0024H Port A Pin 1, selectable rising or falling input edge
0026H Port A Pin 0, selectable rising or falling input edge
0028H Reserved
002AH Reserved
002CH Reserved
002EH Reserved
0030H Port C Pin 3, both input edges
0032H Port C Pin 2, both input edges
0034H Port C Pin 1, both input edges
Lowest 0036H Port C Pin 0, both input edges
0038H Reserved
Master Interrth Enable Interrugt Vectors and Priority Interrugt Assertion Software Interrupt Assertion Watchdog Timer Interrugt Assertion
PS022829-0814 P R E L I M I N A R Y Architecture
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Product Specification
57
Architecture
Figure 8 displays the interrupt controller block diagram.
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 57
Interrupt Vectors and Priority: see page 58
Interrupt Assertion: see page 58
Software Interrupt Assertion: see page 59
Watchdog Timer Interrupt Assertion: see page 59
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts. Interrupts are globally enabled by any of the following actions:
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
Figure 8. Interrupt Controller Block Diagram
Vector
IRQ Request
High
Priority
Medium
Priority
Low
Priority
Priority
Mux
Interrupt Request Latches and Control
Port Interrupts
Internal Interrupts
mxu Table 34
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Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a Trap instruction
Illegal Instruction Trap
Primary Oscillator Fail Trap
Watchdog Oscillator Fail Trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority and Level 1 is the lowest priority. If all of
the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for
example), the interrupt priority is assigned from highest to lowest as specified in Table 34
on page 56. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 34, above. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail
Trap, Watchdog Oscillator Fail Trap and Illegal Instruction Trap always have highest
(level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt
request.
Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command and
the final LDX command are lost. See Example 1, which follows.
Caution:
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Example 1. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2. A good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request Register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is
automatically cleared to 0.
Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which fol-
lows.
Example 3. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4. A good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Watchdog Timer Interrupt Assertion
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the time-out con-
dition continues. As it operates on a different (and usually slower) clock domain than the
rest of the device, the Watchdog Timer continues to assert this interrupt for many system
clocks until the counter rolls over.
Caution:
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To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter-
rupt service routine, Zilog recommends that the service routine continues to read from
the RSTSTAT Register until the WDT bit is cleared as shown in the following example.
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt bit
BTJNZ 5, r0, CLEARWDT ; loop until bit is cleared
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-
ual interrupts, set interrupt priorities and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 35, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 Register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 0 Register (IRQ0)
Bit 76543210
Field Reserved T1I T0I U0RXI U0TXI Reserved Reserved ADCI
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC0H
Bit Description
[7] Reserved
This bit is reserved and must be programmed to 0.
[6]
T1I Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5]
T0I Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
Caution:
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Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 36, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
[4]
U0RXI UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
[3]
U0TXI UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
[2:1] Reserved
These bits are reserved and must be programmed to 00.
[0]
ADCI ADC Interrupt Request
0 = No interrupt request is pending for the analog-to-digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Table 36. Interrupt Request 1 Register (IRQ1)
Bit 76543210
Field PA7VI PA6CI PA5I PA4I PA3I PA2I PA1I PA0I
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC3H
Bit Description
[7]
PA7VI Port A Pin 7 or LVD Interrupt Request
0 = No interrupt request is pending for GPIO Port A or LVD.
1 = An interrupt request from GPIO Port A or LVD.
[6]
PA6CI Port A Pin 6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator.
1 = An interrupt request from GPIO Port A or Comparator.
[5:0]
PA5I Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x.
1 = An interrupt request from GPIO Port A pin x is awaiting service.
Note: x indicates the specific GPIO port pin number (0–5).
Bit Description (Continued)
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Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
IRQ0 Enable High and Low Bit Registers
Table 38 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters, shown in Tables 39 and 40, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register.
Table 37. Interrupt Request 2 Register (IRQ2)
Bit 76543210
Field Reserved PC3I PC2I PC1I PC0I
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC6H
Bit Description
[7:4] Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
PCxI Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin number (0–3).
Table 38. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]IRQ0ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Medium
1 1 Level 3 High
Note: x indicates register bits 0–7.
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Table 39. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit 76543210
Field Reserved T1ENH T0ENH U0RENH U0TENH Reserved Reserved ADCENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC1H
Bit Description
[7] Reserved
This bit is reserved and must be programmed to 0.
[6]
T1ENH Timer 1 Interrupt Request Enable High Bit
[5]
T0ENH Timer 0 Interrupt Request Enable High Bit
[4]
U0RENH UART 0 Receive Interrupt Request Enable High Bit
[3]
U0TENH UART 0 Transmit Interrupt Request Enable High Bit
[2:1] Reserved
These bits are reserved and must be programmed to 00.
[0]
ADCENH ADC Interrupt Request Enable High Bit
Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit 76543210
Field Reserved T1ENL T0ENL U0RENL U0TENL Reserved Reserved ADCENL
RESET 00000000
R/W R R/W R/W R/W R/W R R R/W
Address FC2H
Bit Description
[7] Reserved
This bit is reserved and must be programmed to 0.
[6]
T1ENL Timer 1 Interrupt Request Enable Low Bit
[5]
T0ENL Timer 0 Interrupt Request Enable Low Bit
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IRQ1 Enable High and Low Bit Registers
Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters, shown in Tables 41 and 42, form a priority-encoded enabling for interrupts in the
Interrupt Request 1 Register.
[4]
U0RENL UART 0 Receive Interrupt Request Enable Low Bit
[3]
U0TENL UART 0 Transmit Interrupt Request Enable Low Bit
[2:1] Reserved
These bits are reserved and must be programmed to 00.
[0]
ADCENL ADC Interrupt Request Enable Low Bit
Table 41. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]IRQ1ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Medium
1 1 Level 3 High
Note: x indicates register bits 0–7.
Bit Description (Continued)
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PS022829-0814 P R E L I M I N A R Y Interrupt Control Register Definitions
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Product Specification
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See the Shared Interrupt Select Register (IRQSS) Register on page 68 for selection of
either the LVD or the comparator as the interrupt source.
IRQ2 Enable High and Low Bit Registers
Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters, shown in Tables 44 and 45, form a priority-encoded enabling for interrupts in the
Interrupt Request 2 Register.
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit 76543210
Field PA7VENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC4H
Bit Description
[7]
PA7VENH Port A Bit[7] or LVD Interrupt Request Enable High Bit
[6]
PA6CENH Port A Bit[7] or Comparator Interrupt Request Enable High Bit
[5:0]
PAxENH Port A Bit[x] Interrupt Request Enable High Bit
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit 76543210
Field PA7VENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC5H
Bit Description
[7]
PA7VENL Port A Bit[7] or LVD Interrupt Request Enable Low Bit
[6]
PA6CENL Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
[5:0]
PAxENL Port A Bit[x] Interrupt Request Enable Low Bit
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PS022829-0814 P R E L I M I N A R Y Interrupt Control Register Definitions
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Table 44. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]IRQ2ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Medium
1 1 Level 3 High
Note: x indicates register bits 0–7.
Table 45. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit 76543210
Field Reserved C3ENH C2ENH C1ENH C0ENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC7H
Bit Description
[7:4] Reserved
These bits are reserved and must be programmed to 0000.
[3]
C3ENH Port C3 Interrupt Request Enable High Bit
[2]
C2ENH Port C2 Interrupt Request Enable High Bit
[1]
C1ENH Port C1 Interrupt Request Enable High Bit
[0]
C0ENH Port C0 Interrupt Request Enable High Bit
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PS022829-0814 P R E L I M I N A R Y Interrupt Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
67
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) Register, shown in Table 47, determines whether an
interrupt is generated for the rising edge or falling edge on the selected GPIO Port A input
pin.
Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit 76543210
Field Reserved C3ENL C2ENL C1ENL C0ENL
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FC8H
Bit Description
[7:4] Reserved
These bits are reserved and must be programmed to 0000.
[3]
C3ENL Port C3 Interrupt Request Enable Low Bit
[2]
C2ENL Port C2 Interrupt Request Enable Low Bit
[1]
C1ENL Port C1 Interrupt Request Enable Low Bit
[0]
C0ENL Port C0 Interrupt Request Enable Low Bit
Table 47. Interrupt Edge Select Register (IRQES)
Bit 76543210
Field IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FCDH
Bit Description
[7:0]
IESx Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input.
1 = An interrupt request is generated on the rising edge of the PAx input.
Note: x indicates the specific GPIO port pin number (0–7).
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PS022829-0814 P R E L I M I N A R Y Interrupt Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
68
Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) Register, shown in Table 48, determines the source
of the PADxS interrupts. The Shared Interrupt Select Register selects between Port A and
alternate sources for the individual interrupts.
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
Table 48. Shared Interrupt Select Register (IRQSS)
Bit 76543210
Field PA7VS PA6CS Reserved
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
Address FCEH
Bit Description
[7]
PA7VS PA7/LVD Selection
0 = PA7 is used for the interrupt for PA7VS interrupt request.
1 = The LVD is used for the interrupt for PA7VS interrupt request.
[6]
PA6CS PA6/Comparator Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The Comparator is used for the interrupt for PA6CS interrupt request.
[5:0] Reserved
These bits are reserved and must be programmed to 000000.
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PS022829-0814 P R E L I M I N A R Y Interrupt Control Register Definitions
Z8 Encore! XP® F082A Series
Product Specification
69
Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable
bit for all interrupts.
Table 49. Interrupt Control Register (IRQCTL)
Bit 76543210
Field IRQE Reserved
RESET 00000000
R/W R/WRRRRRRR
Address FCFH
Bit Description
[7]
IRQE Interrupt Request Enable
This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return) instruction,
or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8
CPU acknowledgement of an interrupt request, Reset or by a direct register write of a 0 to this
bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
[6:0] Reserved
These bits are reserved and must be programmed to 0000000.
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PS022829-0814 P R E L I M I N A R Y Timers
Z8 Encore! XP® F082A Series
Product Specification
70
Timers
These Z8 Encore! XP F082A Series products contain two 16-bit reloadable timers that can
be used for timing, event counting, or generation of pulse-width modulated (PWM) sig-
nals. The timers’ feature include:
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generator of the UART
(if unused) may also provide basic timing functionality. For information about using the
Baud Rate Generator as an additional timer, see the Universal Asynchronous Receiver/
Transmitter chapter on page 99.
Architecture
Figure 9 displays the architecture of the timers.
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PS022829-0814 P R E L I M I N A R Y Operation
Z8 Encore! XP® F082A Series
Product Specification
71
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001h into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000h into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFh, the timer rolls over to 0000h and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
One-Shot Mode
In One-Shot Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. The timer is automatically disabled and stops
counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer reload. If
Figure 9. Timer Block Diagram
16-Bit
PWM/Compare
16-Bit Counter
with Prescaler
16-Bit
Reload Register
Timer
Control
Compare Compare
Interrupt,
PWM,
and
Timer Output
Control
Timer
Timer Block
System
Timer
Data
Block
Output
Control
Bus
Clock
Input
Gate
Input
<