DS90UB913,914Q Datasheet by Texas Instruments

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DSP, FPGA/

µ-Processor/

ECU

Deserializer

DS90UB913Q

Serializer

FPD-Link III

Bidirectional

Control Channel

DS90UB914Q

Bidirectional

Control Bus Bidirectional

Control Bus

Parallel

Data In Parallel

Data Out

10 or 12

Megapixel

Imager/Sensor

10 or 12

GPO GPIO

HSYNC,

VSYNC

HSYNC,

VSYNC

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

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DS90UB91xQ-Q1 10- to 100-MHz, 10- and 12-Bit DC-Balanced FPD-Link III Serializer and

Deserializer With Bidirectional Control Channel

1 Features 2 Applications

1• 10-MHz to 100-MHz Input Pixel Clock Support • Front- or Rear-View Camera for Collision

Mitigation

• Single Differential Pair Interconnect • Surround View for Parking Assistance

• Programmable Data Payload:

– 10-bit Payload up to 100 MHz 3 Description

– 12-bit Payload up to 75 MHz The DS90UB91xQ-Q1 chipset offers an FPD-Link III

• Continuous Low Latency Bidirectional Control interface with a high-speed forward channel and a

Interface Channel With I2C Support at 400 kHz bidirectional control channel for data transmission

over a single differential pair. The DS90UB91xQ-Q1

• 2:1 Multiplexer to Choose Between Two Input chipsets incorporate differential signaling on both the

Imagers high-speed forward channel and bidirectional control

• Embedded Clock With DC-Balanced Coding to channel data paths. The serializer and deserializer

Support AC-Coupled Interconnects pair is targeted for connections between imagers and

• Capable of Driving up to 25 Meters Shielded video processors in an electronic control unit (ECU).

Twisted-Pair This chipset is ideally suited for driving video data

that requires up to 12-bit pixel depth plus two

• Receive Equalizer Automatically Adapts for synchronization signals along with bidirectional

Changes in Cable Loss control channel bus.

• Four Dedicated General-Purpose Input/Output There is a multiplexer at the deserializer to choose

Pins (GPIO) Available on Both Serializer and between two input imagers. The deserializer can

Deserializer have only one active input imager. The primary video

• LOCK Output Reporting Pin and AT-SPEED BIST transport converts 10- and 12-bit data over a single

Diagnosis Feature to Validate Link Integrity high-speed serial stream, along with a separate low

• 1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs latency bidirectional control channel transport that

accepts control information from an I2C port and is

on Serializer independent of video blanking period.

• Single Power Supply at 1.8 V

• ISO 10605 and IEC 61000-4-2 ESD Compliant Device Information(1)

• Automotive-Grade Product: AEC-Q100 Grade 2 PART NUMBER PACKAGE BODY SIZE (NOM)

Qualified DS90UB913Q-Q1 WQFN (32) 5.00 mm × 5.00 mm

• Temperature Range −40°C to +105°C DS90UB914Q-Q1 WQFN (48) 7.00 mm × 7.00 mm

• Small Serializer Footprint (5 mm × 5 mm) (1) For all available packages, see the orderable addendum at

the end of the data sheet.

• EMI/EMC Mitigation on Deserializer

– Programmable Spread Spectrum (SSCG)

Outputs

– Receiver Staggered Outputs

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

9.1 AC Timing Diagrams and Test Circuits................... 20

1 Features.................................................................. 110 Detailed Description ........................................... 25

2 Applications ........................................................... 110.1 Overview ............................................................... 25

3 Description ............................................................. 110.2 Functional Block Diagram ..................................... 25

4 Revision History..................................................... 210.3 Feature Description............................................... 26

5 Description continued........................................... 310.4 Device Functional Modes...................................... 33

6 Device Comparison Table..................................... 310.5 Register Maps....................................................... 41

7 Pin Configuration and Functions......................... 411 Application and Implementation........................ 56

8 Specifications......................................................... 911.1 Applications Information........................................ 56

8.1 Absolute Maximum Ratings ...................................... 911.2 Typical Application ................................................ 56

8.2 ESD Ratings.............................................................. 912 Power Supply Recommendations ..................... 60

8.3 Recommended Operating Conditions....................... 913 Layout................................................................... 60

8.4 Thermal Information................................................ 10 13.1 Layout Guidelines ................................................. 60

8.5 Electrical Characteristics ........................................ 10 13.2 Layout Example .................................................... 61

8.6 Timing Requirements: Recommended for Serializer 14 Device and Documentation Support ................. 63

PCLK ....................................................................... 14 14.1 Documentation Support ....................................... 63

8.7 AC Timing Specifications (SCL, SDA) - I2C

Compliant................................................................. 15 14.2 Related Links ........................................................ 63

8.8 Bidirectional Control Bus DC Timing Specifications 14.3 Community Resources.......................................... 63

(SCL, SDA) - I2C Compliant..................................... 15 14.4 Trademarks........................................................... 63

8.9 Switching Characteristics: Serializer....................... 16 14.5 Electrostatic Discharge Caution............................ 63

8.10 Switching Characteristics: Deserializer................. 17 14.6 Glossary................................................................ 63

8.11 Typical Characteristics.......................................... 19 15 Mechanical, Packaging, and Orderable

9 Parameter Measurement Information ................ 20 Information ........................................................... 63

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (January 2014) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Updated datasheet to new TI layout....................................................................................................................................... 1

• Added text and graphic to Power Up Requirements ........................................................................................................... 39

Changes from Revision B (April 2013) to Revision C Page

• Changed "PCLK from imager mode" value in DS90UB913Q Serializer MODE Resistor Value table from 0 kΩto 100

kΩ......................................................................................................................................................................................... 35

• Changed Falling to Rising in RRFB...................................................................................................................................... 47

• Changed Rising to Falling in RRFB...................................................................................................................................... 47

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 61

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5 Description continued

Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential

pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream

simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between

parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB

layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to

compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used

to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is

offered in a 48-pin WQFN package.

6 Device Comparison Table

PART NUMBER FPD-III FUNCTION PACKAGE TRANSMISSION MEDIA PCLK FREQUENCY

DS90UB913Q-Q1 Serializer 32-Pin RTV (WQFN) STP 10 to 100 MHz

DS90UB913A-Q1 Serializer 32-Pin RTV (WQFN) Coax or STP 25 to 100 MHz

DS90UB914Q-Q1 Deserializer 48-Pin RHS (WQFN) STP 10 to 100 MHz

DS90UB914A-Q1 Deserializer 48-Pin RHS (WQFN) Coax or STP 25 to 100 MHz

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‘5‘ TEXAS INSTRUMENTS

32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

24 23 22 21 20 19 18 17

DS90UB913Q

Serializer

VDDIO

DIN[8]

DIN[9]

DIN[10]

DIN[11]

DIN[7]

DIN[6]

DIN[5]

DIN[4]

DIN[3]

DIN[2]

DIN[1]

DIN[0]

VDDCML

VDDT

VDDPLL

PDB

DOUT-

DOUT+

HSYNC

VSYNC

PCLK

SCL

SDA

ID[x]

RES

MODE GPO[2]/

CLKOUT

GPO[1]

GPO[0]

VDDD

GPO[3]/

CLKIN

DAP = GND

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7 Pin Configuration and Functions

RTV Package

32-Pin WQFN

Top View

DS90UB913Q-Q1 Serializer Pin Functions

PIN I/O DESCRIPTION

NAME NO.

LVCMOS PARALLEL INTERFACE

19, 20, 21, Inputs,

22, 23, 24,

DIN[0:11] LVCMOS Parallel data inputs

26, 27, 29, with pulldown

30, 31, 32

Inputs,

HSYNC 1 LVCMOS Horizontal SYNC input

with pulldown

Input, LVCMOS Pixel clock input pin

PCLK 3 with pulldown Strobe edge set by TRFB control register.

Inputs,

VSYNC 2 LVCMOS Vertical SYNC input

with pulldown

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DS90UB913Q-Q1 Serializer Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

GENERAL-PURPOSE OUTPUT (GPO)

General-purpose output pins can be configured as outputs; used to control and respond

Output, to various commands. GPO[0:1] can be configured to be the outputs for input signals

GPO[1:0] 16, 15 LVCMOS coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of

the local register on the serializer.

GPO2 pin can be configured to be the output for input signal coming from the GPIO2

pin on the deserializer or can be configured to be the output of the local register on the

GPO[2]/ Output, serializer. It can also be configured to be the output clock pin when the DS90UB913Q-

CLKOUT LVCMOS Q1 device is used in the External Oscillator mode. See Applications Information for a

detailed description of the DS90UB91xQ-Q1 chipsets working with the external

oscillator.

GPO3 can be configured to be the output for input signals coming from the GPIO3 pin

on the deserializer or can be configured to be the output of the local register setting on

GPO[3]/ Input/Output, the serializer. It can also be configured to be the input clock pin when the

CLKIN LVCMOS DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications

Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working

with an external oscillator.

BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE

Input/Output, Clock line for the bidirectional control bus communication

SCL 4 Open-Drain SCL requires an external pullup resistor to VDDIO.

Input/Output, Data line for the bidirectional control bus communication

SDA 5 Open-Drain SDA requires an external pullup resistor to VDDIO.

Device mode select

Input, LVCMOS Resistor to Ground and 10-kΩpullup to 1.8-V rail. MODE pin on the serializer can be

MODE 8 with pulldown used to select whether the system is running off the PCLK from the imager or an

external oscillator. See details in Table 3.

Device ID address select

ID[x] 6 Input, analog The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to

Ground and 10-kΩpullup to 1.8-V rail. See Table 1.

CONTROL AND CONFIGURATION

Power down Mode Input Pin

PDB = H, serializer is enabled and is ON.

Input, LVCMOS

PDB 9 PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the

with pulldown PLL is shutdown, and IDD is minimized. Programmed control register data are NOT

retained and reset to default values

Input, LVCMOS Reserved

RES 7 with pulldown This pin MUST be tied LOW.

FPD-Link III INTERFACE

Input/Output, Noninverting differential output, bidirectional control channel input. The interconnect

DOUT+ 13 CML must be AC-coupled with a 100-nF capacitor.

Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must be

DOUT– 12 CML AC-coupled with a 100-nF capacitor.

POWER AND GROUND

VDDPLL 10 Power, Analog PLL Power, 1.8 V ±5%

VDDT 11 Power, Analog Tx Analog Power, 1.8 V ±5%

VDDCML 14 Power, Analog CML and bidirectional channel driver power, 1.8 V ±5%

VDDD 28 Power, Digital Digital power, 1.8 V ±5%

Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.

VDDIO 25 Power, Digital VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%

DAP must be grounded. DAP is the large metal contact at the bottom side, located at

VSS DAP Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 9

vias.

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Deserializer

ROUT[10]

ROUT[11]

VSYNC

PCLK

OEN

OSS_SEL

SCL

SDA

GPIO[3]

GPIO[2]

GPIO[0]

VDDIO1

RIN1+

RIN1-

IDx[0]

VDDR

VDDSSCG

BISTEN

VDDIO3

HSYNC GPIO[1]

VDDCML1

IDx[1]

ROUT[9]

ROUT[7]

ROUT[2]

ROUT[0]

ROUT[8]

ROUT[1]

ROUT[6]

VDDD

ROUT[5]

LOCK

PDB

VDDPLL

RES

RIN0-

RIN0+

VDDCML0

CMLOUTN

CMLOUTP

PASS

MODE

ROUT[4]

ROUT[3]

VDDIO2

DAP = GND

SEL

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RHS Package

48-Pin WQFN

Top View

DS90UB914Q-Q1 Deserializer Pin Functions

PIN I/O DESCRIPTION

NAME NO.

LVCMOS PARALLEL INTERFACE

11, 12, 13,

14, 15, 16, Outputs,

ROUT[11:0] Parallel data outputs

18, 19, 21, LVCMOS

22, 23, 24

Output,

HSYNC 10 Horizontal SYNC output

LVCMOS

Output, Pixel clock output pin

PCLK 8 LVCMOS Strobe edge set by RRFB control register

Output,

VSYNC 9 Vertical SYNC output

LVCMOS

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

General-purpose input/output pins can be used to control and respond to various

Digital commands. They may be configured to be the input signals for the corresponding

GPIO[1:0] 27, 28 Input/Output, GPOs on the serializer or they may be configured to be outputs to follow local

LVCMOS register settings.

General-purpose input/output pins GPO[2:3] can be configured to be input signals

Digital for GPOs on the serializer. In addition they can also be configured to be outputs

GPIO[3:2] 25, 26 Input/Output to follow the local register settings. When the SerDes chipsets are working with

LVCMOS an external oscillator, these pins can be configured only to be outputs to follow

the local register settings.

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DS90UB914Q-Q1 Deserializer Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE

Input/Output, Clock line for the bidirectional control bus communication

SCL 2 Open-Drain SCL requires an external pullup resistor to VDDIO.

Input/Output, Data line for bidirectional control bus communication

SDA 1 Open-Drain SDA requires an external pullup resistor to VDDIO.

Device mode select pin

Resistor-to-Ground and 10-kΩpullup to 1.8-V rail. The MODE pin on the

deserializer can be used to configure the serializer and deserializer to work in

different input PCLK range. See details in Table 8.

12-bit low-frequency mode (10- to 50-MHz operation):

In this mode, the serializer and deserializer can accept up to 12 bits DATA+2

SYNC. Input PCLK range is from 10 MHz to 50 MHz.

Input, LVCMOS

MODE 37 12-bit high-frequency mode (15- to 75-MHz operation): In this mode, the

with pullup serializer and deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK

range is from 15 MHz to 75 MHz.

10-bit mode (20- to 100-MHz operation):

In this mode, the serializer and deserializer can accept up to 10 bits DATA + 2

SYNC. Input PCLK frequency can range from 20 MHz to 100 MHz.

Refer to Table 4 in the Applications Information section on how to configure the

MODE pin on the deserializer.

The IDx[0] and IDx[1] pins on the deserializer are used to assign the I2C device

address. Resistor-to-Ground and 10-kΩpullup to 1.8-V rail. See Table 2

IDx[0:1] 35, 34 Input, analog Input pin to select the slave device address.

Input is connect to external resistor divider to set programmable Device ID

address.

CONTROL AND CONFIGURATION

Power-down mode input pin

PDB = H, deserializer is enabled and is ON.

Input, LVCMOS

PDB 30 PDB = L, deserializer is in sleep (power-down mode). When the deserializer is in

with pulldown sleep, programmed control register data are NOT retained and reset to default

values.

LOCK status output pin

Output, LOCK = H, PLL is Locked, outputs are active

LOCK 48 LVCMOS LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by

OSS_SEL control register. May be used as link status.

Input BIST enable pin

BISTEN 6 LVCMOS with BISTEN=H, BIST mode enabled

pulldown BISTEN=L, BIST mode is disabled

PASS output pin for BIST mode.

PASS = H, ERROR FREE transmission

Output,

PASS 47 PASS = L, one or more errors were detected in the received payload.

LVCOMS See Built-In Self Test section for more information. Leave open if unused. Route

to test point (pad) recommended.

Input Output enable input

OEN 5 LVCMOS with Refer to Table 5

pulldown

Input Output sleep state select pin

OSS_SEL 4 LVCMOS with Refer to Table 5

pulldown

MUX select line

Input SEL = L, RIN0± input. This selects input A as the active channel on the

SEL 46 LVCMOS with deserializer.

pulldown SEL = H, RIN1± input. This selects input B as the active channel on the

deserializer.

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DS90UB914Q-Q1 Deserializer Pin Functions (continued)

PIN I/O DESCRIPTION

NAME NO.

FPD-LINK III INTERFACE

Input/Output, Noninverting differential input, bidirectional control channel. The IO must be AC

RIN0+ 41 CML coupled with a 100-nF capacitor

Input/Output, Inverting differential input, bidirectional control channel. The IO must be AC

RIN0- 42 CML coupled with a 100-nF capacitor

Input/Output, Noninverting differential input, bidirectional control channel. The IO must be AC

RIN1+ 32 CML coupled with a 100-nF capacitor

Input/Output, Inverting differential input, bidirectional control channel. The IO must be AC

RIN1- 33 CML coupled with a 100-nF capacitor

RES 43, 44 — Reserved; This pin must always be tied low.

CMLOUTP/N 38, 39 — Route to test point or leave open if unused

POWER AND GROUND

LVCMOS I/O buffer power, The single-ended outputs and control input are

VDDIO1/2/3 29, 20, 7 Power, Digital powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%

VDDD 17 Power, Digital Digital core power, 1.8 V ±5%

VDDSSCG 3 Power, Analog SSCG PLL power, 1.8 V ±5%

VDDR 36 Power, Analog RX analog power, 1.8 V ±5%

VDDCML0/1 40, 31 Power, Analog CML and bidirectional control channel drive power, 1.8 V±5%

VDDPLL 45 Power, Analog PLL Power, 1.8 V ±5%

DAP must be grounded. DAP is the large metal contact at the bottom side,

VSS DAP Ground, DAP located at the center of the WQFN package. Connected to the ground plane

(GND) with at least 16 vias.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2) (3)

MIN MAX UNIT

Supply voltage – VDDn (1.8 V) −0.3 2.5 V

Supply voltage – VDDIO −0.3 4.0 V

LVCMOS input voltage −0.3 VDDIO + 0.3 V

CML driver I/O voltage (VDD)−0.3 VDD + 0.3 V

CML receiver I/O voltage (VDD)−0.3 VDD + 0.3 V

Junction temperature 150 °C

1/θJA above

Maximum package power dissipation capacity package °C/W

+25°

Air discharge (DOUT+, DOUT–, RIN+, RIN–) −25 25 kV

Contact discharge (DOUT+, DOUT–, RIN+, RIN–) −7 7 kV

Storage temperature Tstg −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) For soldering specifications: see product folder at www.ti.com and SNOA549.

8.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per AEC Q100-002(1) ±8000

Charged-device model (CDM), per AEC Q100-011 ±1000

Machine model (MM) ±250

Electrostatic

V(ESD) Air Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±25 000 V

discharge IEC 61000-4-2(2) Contact Discharge (DOUT+, DOUT-, RIN+, RIN-) ≥±7000

Air Discharge ≥±15 000

ISO10605(3)(4) Contact Discharge ≥±8000

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) RD= 330 Ω, CS= 150 pF

(3) RD= 330 Ω, CS= 150 / 330 pF

(4) RD= 2 KΩ, CS= 150 / 330 pF

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage (VDDn) 1.71 1.8 1.89 V

LVCMOS supply voltage (VDDIO) OR 1.71 1.8 1.89

LVCMOS supply voltage (VDDIO) OR 3.0 3.3 3.6 V

LVCMOS supply voltage (VDDIO) only serializer 2.52 2.8 3.08

VDDn (1.8 V) 25

Supply noise(1) VDDIO (1.8 V) 25 mVp-p

VDDIO (3.3 V) 50

Operating free-air temperature (TA) –40 25 105 °C

PCLK clock frequency 10 100 MHz

(1) Supply noise testing was done with minimum capacitors (as shown on Figure 49 and Figure 48) on the PCB. A sinusoidal signal is AC

coupled to the VDDn (1.8-V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the

serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than

1 MHz. The deserializer on the other hand shows no error when the noise frequency is less than 750 kHz.

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8.4 Thermal Information

DS90UB913Q-Q1 DS90UB914Q-Q1

THERMAL METRIC(1) RTV (WQFN) RHS (WQFN) UNIT

32 PINS 48 PINS

RθJA Junction-to-ambient thermal resistance 38.4 26.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 6.9 4.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

8.5 Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVCMOS DC SPECIFICATIONS 3.3V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND

OUTPUTS)

High level input

VIH VIN = 3 V to 3.6 V 2 VIN V

voltage

Low level input

VIL VIN = 3 V to 3.6 V GND 0.8 V

voltage

IIN Input current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V −20 ±1 20 µA

High level output

VOH VDDIO = 3 V to 3.6 V, IOH =−4 mA 2.4 VDDIO V

voltage

Low level output

VOL VDDIO = 3 V to 3.6 V, IOL = +4 mA GND 0.4 V

voltage

Serializer –15

GPO outputs

Output short circuit

IOS VOUT = 0 V mA

current Deserializer LVCMOS –35

outputs

TRI-STATE output PDB = 0 V,

IOZ LVCMOS outputs –20 20 µA

current VOUT = 0 V or VDD

LVCMOS DC SPECIFICATIONS 1.8V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND

OUTPUTS)

High level input

VIH VIN = 1.71 V to 1.89 V 0.65 VIN VIN

voltage V

Low level input

VIL VIN = 1.71 V to 1.89 V GND 0.35 VIN

voltage

IIN Input current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V –20 ±1 20 µA

High level output VDDIO –

VOH VDDIO = 1.71 V to 1.89 V, IOH =−4 mA VDDIO V

voltage 0.45

VDDIO = 1.71 V to 1.89

Low level output Deserializer LVCMOS

VOL V GND 0.45 V

voltage outputs

IOL = 4 mA

Serializer –11

GPO outputs

Output short circuit

IOS VOUT = 0 V mA

current Deserializer LVCMOS –17

outputs

TRI-STATE output PDB = 0 V,

IOZ LVCMOS outputs –20 20 µA

current VOUT = 0 V or VDD

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA= 25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not specified.

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Electrical Characteristics (continued)

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVCMOS DC SPECIFICATIONS 2.8-V I/O (SERIALIZER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)

High level input

VIH VIN = 2.52 V to 3.08 V 0.7 VIN VIN

voltage V

Low level input

VIL VIN = 2.52 V to 3.08 V GND 0.3 VIN

voltage

IIN Input current VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V −20 ±1 20 µA

High level output

VOH VDDIO = 2.52 V to 3.08 V, IOH =−4 mA VDDIO – 0.4 VDDIO V

voltage

VDDIO =2.52 V to 3.08

Low level output Deserializer LVCMOS

VOL V GND 0.4 V

voltage outputs

IOL = 4 mA

Serializer −11

GPO outputs

Output short circuit

IOS VOUT = 0 V mA

current Deserializer LVCMOS −20

outputs

TRI-STATE output PDB = 0 V,

IOZ LVCMOS outputs −20 20 µA

current VOUT = 0 V or VDD

CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)

Output differential

|VOD| RL= 100 Ω(see Figure 9) 268 340 412 mV

voltage

Output differential

ΔVOD RL= 100 Ω1 50 mV

voltage unbalance

Output differential

VOS RL= 100 Ω(see Figure 9) VDD – VOD/2 V

offset voltage

Offset voltage

ΔVOS RL= 100 Ω1 50 mV

unbalance

Output short

IOS DOUT± = 0 V –26 mA

circuit current

Differential internal

RTtermination Differential across DOUT+ and DOUT– 80 100 120 Ω

resistance

CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )

IIN Input current VIN = VDD or 0 V, VDD = 1.89 V −20 1 20 µA

Differential internal

RTtermination Differential across RIN+ and RIN- 80 100 120 Ω

resistance

CML RECEIVER AC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )

Minimum allowable

|Vswing| swing for 1010 Line rate = 1.4 Gbps (see Figure 11) 135 mV

pattern(4)

CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN)

Differential output

Ew0.45 UI

eye opening RL= 100 Ω

Jitter frequency > f / 40 (see Figure 20)

Differential output

EH200 mV

eye height

(4) Specification is ensured by characterization and is not tested in production.

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Electrical Characteristics (continued)

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SERIALIZER AND DESERIALIZER SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

VDDn = 1.89 V

VDDIO = 3.6 V

f = 100 MHz, 61 80 mA

10-bit mode

default registers

VDDn = 1.89 V

VDDIO = 3.6 V

RL= 100 Ωf = 75 MHz, 61 80

WORST CASE pattern 12-bit high-frequency

(see Figure 6) mode

default registers mA

VDDn = 1.89 V

VDDIO = 3.6 V

f = 50 MHz, 61 80

12-bit low-frequency

mode

Serializer (TX) default registers

VDDn supply current

IDDT (includes load VDDn = 1.89 V

current) VDDIO = 3.6 V

f = 100 MHz, 54

10-bit mode

default registers

VDDn = 1.89 V

VDDIO = 3.6 V

RL= 100 Ωf = 75 MHz, 54

RANDOM PRBS-7 12-bit high-frequency mA

pattern mode

default registers

VDD = 1.89 V

VDDIO = 3.6 V

f = 50 MHz, 54

12-bit low-frequency

mode

default registers

VDDIO = 1.89 V

f = 75 MHz, 1.5 3

12-bit high-freq mode

Serializer (TX) RL= 100 Ωdefault registers

VDDIO supply

IDDIOT WORST CASE pattern mA

current (includes VDDIO = 3.6 V

(see Figure 6)

load current) f = 75 MHz, 5 8

12-bit high-frequency

mode default registers

VDDIO = 1.89 V 300 900 µA

Serializer (TX) Default registers

PDB = 0 V; all other

IDDTZ supply current LVCMOS inputs = 0 V VDDIO = 3.6 V

power-down 300 900 µA

Default registers

VDDIO = 1.89 V 15 100 µA

Serializer (TX) Default registers

PDB = 0 V; All other

IDDIOTZ VDDIO supply LVCMOS Inputs = 0 V VDDIO = 3.6 V

current power-down 15 100 µA

Default registers

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Electrical Characteristics (continued)

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f = 100 MHz, 10-bit 22 42

mode

VDDIO = 1.89 V f = 75 MHz, 12-bit high-

CL= 8 pF 19 39 mA

freq mode

WORST CASE pattern f = 50 MHz, 12-bit low- 21 32

freq mode

f = 100 MHz, 10–bit 15

mode

VDDIO = 1.89 V f = 75 MHz, 12-bit high-

CL=8pF 12 mA

freq mode

Random pattern f = 50 MHz, 12-bit low- 14

freq mode

f = 100 MHz, 10-bit 42 55

mode

VDDIO = 3.6 V f = 75 MHz, 12-bit high-

CL= 8 pF 37 50 mA

freq mode

WORST CASE pattern f = 50 MHz, 12-bit low- 25 38

freq mode

f = 100 MHz, 10-bit 35

mode

VDDIO = 3.6 V f = 75 MHz, 12-bit high-

CL= 8 pF 30 mA

freq mode

Random pattern f = 50 MHz, 12-bit low-

Deserializer (RX) 18

freq mode

total supply current

IDDIOR (includes load f = 100 MHz, 10-bit 15

current) mode

VDDIO = 1.89 V f = 75 MHz, 12-bit high-

CL= 4 pF 11 mA

freq mode

WORST CASE pattern f = 50 MHz, 12-bit low- 16

freq mode

f = 100 MHz, 10-bit 8

mode

VDDIO = 1.89 V f = 75 MHz, 12-bit high-

CL= 4 pF 4 mA

freq mode

Random pattern f = 50 MHz, 12-bit low- 9

freq mode

f = 100 MHz, 10-bit 36

mode

VDDIO = 3.6 V f = 75 MHz, 12-bit high-

CL= 4 pF 29 mA

freq mode

WORST CASE pattern f = 50 MHz, 12-bit low- 20

freq mode

f = 100 MHz, 10-bit 29

mode

VDDIO = 3.6 V f = 75 MHz, 12-bit high-

CL= 4 pF 22 mA

freq mode

Random pattern f = 50 MHz, 12-bit low- 13

freq mode

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Electrical Characteristics (continued)

over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f = 100 MHz, 64 110

10-bit mode

f = 75 MHz,

VDDn = 1.89 V 12-bit high-frequency 67 114

CL= 4 pF mode

WORST CASE pattern f = 50 MHz,

Deserializer (RX) 12-bit low-frequency 63 96

VDDn supply current

IDDR mA

mode

(includes load

current) f = 100 MHz, 57

10-bit mode

VDDn = 1.89 V f = 75 MHz, 12–bit

CL= 4 pF 60

high-frequency mode

Random pattern f = 50 MHz, 12-bit 56

low-frequency mode

PBB = 0 V, all other VDDIO = 1.89 V 42 400

Deserializer (RX) LVCMOS Inputs=0 V Default registers

IDDRZ supply current µA

PBB = 0 V, all other VDDIO = 3.6 V

power-down 42 400

LVCMOS Inputs=0 V Default registers

Deserializer (RX) VDDIO = 1.89 V 8 40

PDB = 0 V, all other

IDDIORZ VDD supply current µA

LVCMOS Inputs = 0 V VDDIO = 3.6 V 360 800

power-down

8.6 Timing Requirements: Recommended for Serializer PCLK

over recommended operating supply and temperature ranges unless otherwise specified.(1)

TEST CONDITIONS PIN/FREQ MIN NOM MAX UNIT

10-bit mode 10 T 50

12-bit high-frequency 13.33 T 66.66

tTCP Transmit clock period mode ns

12-bit low-frequency 20 T 100

mode

Transmit clock

tTCIH 0.4T 0.5T 0.6T ns

input high time

Transmit clock

tTCIL 0.4T 0.5T 0.6T ns

input low time

20 MHz–100 MHz, 0.5T 2.5T 0.3T

10-bit mode

PCLK input transition 15 MHz to 75 MHz, 12-bit

tCLKT 0.5T 2.5T 0.3T ns

time (Figure 12) high-frequency mode

10 MHz to 50 MHz, 12-bit 0.5T 2.5T 0.3T

low-frequency mode

PCLK input jitter

tJIT0 (PCLK from imager Refer to jitter freq > f / 40 f = 10 to 100 MHz 0.1T ns

mode)

PCLK input jitter (external

tJIT1 Refer to jitter freq > f / 40 f = 10 to 100 MHz 1T ns

oscillator mode)

tJIT2 External oscillator jitter 0.1 UI

(1) Recommended input timing requirements are input specifications and not tested in production.

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8.7 AC Timing Specifications (SCL, SDA) - I2C Compliant

over recommended supply and temperature ranges unless otherwise specified. (See Figure 5)

TEST CONDITIONS MIN NOM MAX UNIT

RECOMMENDED INPUT TIMING REQUIREMENTS

Standard mode >0 100

fSCL SCL clock frequency kHz

Fast mode >0 400

Standard mode 4.7

tLOW SCL low period µs

Fast mode 1.3

Standard mode 4.0

tHIGH SCL high period µs

Fast mode 0.6

Standard mode 4

Hold time for a start or a

tHD:STA µs

repeated start condition Fast mode 0.6

Standard mode 4.7

Setup time for a start or a

tSU:STA µs

repeated start condition Fast mode 0.6

Standard mode 0 3.45

tHD:DAT Data hold time µs

Fast mode 0 900

Standard mode 250

tSU:DAT Data setup time ns

Fast mode 100

Standard mode 4

Setup time for STOP

tSU:STO µs

condition Fast mode 0.6

Standard mode 4.7

Bus free time between

tBUF µs

stop and start Fast mode 1.3

Standard mode 1000

trSCL and SDA rise time ns

Fast mode 300

Standard mode 300

tfSCL and SDA fall time ns

Fast mode 300

8.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant

over recommended supply and temperature ranges unless otherwise specified(1)

TEST CONDITIONS MIN NOM MAX UNIT

RECOMMENDED INPUT TIMING REQUIREMENTS

VIH Input high level SDA and SCL 0.7 × VDDIO VDDIO V

VIL Input low level SDA and SCL GND 0.3 × VDDIO V

VHY Input hysteresis >50 mV

VOL Output low level SDA, IOL = 0.5 mA 0 0.4 V

IIN Input current SDA or SCL, VIN = VDDOP OR GND −10 10 µA

tRSDA rise time-READ 430 ns

SDA, RPU = 10 kΩ, Cb ≤400 pF (see

Figure 5)

tFSDA fall time-READ 20 ns

tSU;DAT See Figure 5 560 ns

tHD;DAT See Figure 5 615 ns

tSP 50 ns

CIN SDA or SCL <5 pF

(1) Specification is ensured by design.

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8.9 Switching Characteristics: Serializer

over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CML low-to-high transition

tLHT RL= 100 Ω(see Figure 7) 150 330 ps

time

CML high-to-low transition

tHLT RL= 100 Ω(see Figure 7) 150 330 ps

time

tDIS Data input setup to PCLK 2 ns

Serializer data inputs (see Figure 13)

Data input hold from

tDIH 2 ns

PCLK

tPLD Serializer PLL lock time RL= 100 Ω(1) (2), (see Figure 14) 1 2 ms

RT= 100 Ω, 10-bit mode

Figure 15)

tSD Serializer delay(2) ns

RT= 100 Ω, 12-bit mode

Figure 15)

Serializer output intrinsic deterministic jitter.

Serializer output

tJIND Measured (cycle-cycle) with PRBS-7 test 0.13 UI

deterministic jitter pattern(3) (4)

Serializer output Serializer output intrinsic random jitter (cycle-

tJINR 0.04 UI

random jitter cycle). Alternating-1,0 pattern.(3) (4)

Serializer output peak-to-peak jitter includes

Peak-to-peak serializer deterministic jitter, random jitter, and jitter

tJINT 0.396 UI

output jitter transfer from serializer input. Measured

(cycle-cycle) with PRBS-7 test pattern.(3) (4)

PCLK = 100 MHz 2.2

10-bit mode. Default registers

Serializer jitter PCLK = 75 MHz

λSTXBW transfer function –3-dB 2.2 MHz

12-bit high-frequency mode. Default registers

bandwidth(5)

PCLK = 50 MHz 2.2

12-bit low-frequency mode. Default registers

PCLK = 100 MHz 1.06

10-bit mode. Default Registers

Serializer jitter PCLK = 75 MHz

δSTX transfer function 1.09 dB

12-bit high-frequency mode. Default registers

(peaking)(5)

PCLK = 50 MHz 1.16

12-bit low-frequency mode. Default registers

PCLK = 100 MHz 400

10-bit mode. Default registers

Serializer jitter PCLK = 75 MHz

δSTXf transfer function 500 kHz

12-bit high-frequency mode. Default registers

(peaking frequency)(5)

PCLK = 50 MHz 600

12-bit low-frequency mode. Default registers

(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

(2) Specification is ensured by design.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA= 25°C, and at the recommended operation conditions at the

time of product characterization and are not specified.

(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

(5) Specification is ensured by characterization and is not tested in production.

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8.10 Switching Characteristics: Deserializer

over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ MIN TYP MAX UNIT

10-bit mode 10 50

12-bit high-frequency

Receiver output PCLK (see 13.33 66.66

tRCP mode ns

clock period Figure 19)

12-bit low-frequency 10 100

mode

10-bit mode 45% 50% 55%

12-bit high-frequency 40% 50% 60%

tPDC PCLK duty cycle mode PCLK

12-bit low-frequency 40% 50% 60%

mode

LVCMOS low-to-high VDDIO: 1.71 V to 1.89 V or

tCLH 1.3 2 2.8 ns

transition time 3.0 V to 3.6 V,

CL= 8 pF (lumped load) PCLK

LVCMOS high-to-low Default registers

tCHL 1.3 2 2.8 ns

transition time (see Figure 17)(1)

LVCMOS low-to-high VDDIO: 1.71 V to 1.89 V or

tCLH 1 2.5 4 ns

transition time 3.0 V to 3.6 V, ROUT[11:0], HS,

CL= 8 pF (lumped load) VS

LVCMOS high-to-low Default registers

tCHL 1 2.5 4 ns

transition time (see Figure 17)(1)

ROUT setup data to VDDIO: 1.71 V to 1.89 V or

tROS 0.38T 0.5T ns

PCLK 3.0 V to 3.6 V, ROUT[11:0], HS,

CL= 8 pF (lumped load) VS

Default registers (see

tROH ROUT hold data to PCLK 0.38T 0.5T ns

Figure 19)

10-bit mode 154T 158T

Default registers 12-bit low-

tDD Deserializer delay frequency mode ns

(RRFB = 1) 12-bit high-

(see Figure 18)(1) 73T 75T

frequency mode

10-bit mode 15 22

With Adaptive 12-bit low-

Deserializer data lock 15 22

tDDLT Equalization (see frequency mode ms

time Figure 16)12-bit high- 15 22

frequency mode

10-bit mode 20 30

PCLK = 100 MHz

12-bit low-

PCLK frequency mode 22 35

tRCJ Receiver clock jitter ps

SSCG[3:0] = OFF(1) PCLK = 50 MHz

12-bit high-

frequency mode 45 90

PCLK = 75 MHz

10-bit mode 170 815

PCLK = 100 MHz

12-bit low-

PCLK frequency mode 180 330

tDPJ Deserializer period jitter ps

SSCG[3:0] = OFF(1) (2) PCLK= 50 MHz

12-bit high-

frequency mode 300 515

PCLK= 75 MHz

(1) Specification is ensured by characterization and is not tested in production.

(2) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.

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Switching Characteristics: Deserializer (continued)

over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ MIN TYP MAX UNIT

10-bit mode 440 1760

PCLK = 100 MHz

12-bit low-

Deserializer cycle-to- PCLK frequency mode 460 730

tDCCJ ps

cycle clock jitter SSCG[3:0] = OFF(1) (3) PCLK = 50 MHz

12-bit high-

frequency mode 565 985

PCLK = 75 MHz

Spread spectrum clocking ±0.5 to

fdev 10 MHz–100 MHz

LVCMOS output bus

deviation frequency ±1.5%

SSC[3:0] = ON (see

Spread spectrum clocking Figure 24)(1)

fmod 10 MHz–100 MHz 5 to 50 kHz

modulation frequency

(3) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.

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600

SERIAL LINE FREQUENCY (MHz)

EQUALIZER GAIN (dB)

700500400300200100

200 300 400 500 600 700

SERIAL LINE FREQUENCY (MHz)

EFFECTIVE GAIN (dB)

100

VOD-Vswing Loss

914 Equalizer Gain (dB)

Allowable Interconnect

Loss

-18

-16

-14

-12

-10

- 8

- 6

- 4

- 2

MODULATION FREQUENCY ( Hz)

1.0E+04 1.0E+07

1.0E+061.0E+05

JITTER TRANSFER (dB)

1E+04

JITTER FREQUENCY (Hz)

0.45

JITTER AMPLITUDE (UI)

1E+05 1E+06 1E+07

0.50

0.55

0.60

0.65

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8.11 Typical Characteristics

Figure 2. Typical Deserializer Input Jitter Tolerance Curve

Figure 1. Typical Serializer Jitter Transfer Function at 1.4-Gbps Line Rate

at 100 MHz

Figure 3. Maximum Equalizer Gain vs. Line Frequency Figure 4. Adaptive Equalizer – Interconnect Loss

Compensation

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PARALLEL-TO-SERIAL

DOUT+

DOUT-

10/12,

HS,VS

DIN RL

PCLK

ZDiff = 100:100:

DOUT+

DOUT-

100 nF

SCOPE

BW 8 4.0 GHz

50:

80%

20%

80%

20% Vdiff = 0V

tLHT tHLT

Vdiff

Vdiff = (DOUT+) - (DOUT-)

PCLK

(RFB = H)

DIN/ROUT

Signal Pattern

Device Pin Name

SCL

SDA

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA tSU;STO

START REPEATED

START

STOP

tHD;STA

START

tBUF

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9 Parameter Measurement Information

9.1 AC Timing Diagrams and Test Circuits

Figure 5. Bidirectional Control Bus Timing

Figure 6. Worst Case Test Pattern

Figure 7. Serializer CML Output Load and Transition Times

Figure 8. Serializer CML Output Load and Transition Times

Figure 9. Serializer VOD Diagram

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VDDIO/2

PCLK

DOUT±Output Active

tPLD

PDB

TRI-STATE TRI-STATE

Setup

VDDIO/2 Hold

tDIH

tDIS

PCLK

DINn

tTCP

VDDIO/2

VDDIO/2 VDDIO/2VDDIO/2

VDDIO

80%

20%

80%

20%

tCLKT tCLKT

PCLK

VDD

Vswing+ Vswing-

Single Ended

Differential

RIN-

(RIN+)-(RIN-)

RIN+

Vswing+

Vswing-

DOUT+

VOD+

VOD-

VOD

Single Ended

Differential

VOS

DOUT-

(DOUT+)-(DOUT-)

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AC Timing Diagrams and Test Circuits (continued)

Figure 10. Serializer VOD Diagram

Figure 11. Differential Vswing Diagram

Figure 12. Serializer Input Clock Transition Times Figure 13. Serializer Set-Up and Hold Times

Figure 14. Serializer PLL Lock Time

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1/2 VDDIO 0V

VDDIO

tROS tROH

PCLK

ROUT[n],

VS, HS 1/2 VDDIO 1/2 VDDIO

1/2 VDDIO

tRCP

SYMBOL N + 2

SYMBOL N

RIN±

PCLK

SYMBOL N - 1 SYMBOL N

| |

SYMBOL N+1

| |

ROUTn

VDDIO/2

SYMBOL N + 1 SYMBOL N + 3 SYMBOL N + 3

SYMBOL N - 2SYMBOL N - 3

tDD

80%

20%

80%

20%

tCLH

Deserializer

8 pF

lumped

tCHL

LOCK

PDB VDDIO/2

TRI-STATE

tDDLT

RIN±

VDDIO/2

SYMBOL N

SYMBOL N-1

SYMBOL N-2

SYMBOL N-3SYMBOL N-4

DOUT+-

PCLK

tSD

DIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3

| |

VDDIO/2

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AC Timing Diagrams and Test Circuits (continued)

Figure 15. Serializer Delay

Figure 16. Deserializer Data Lock Time

Figure 17. Deserializer LVCMOS Output Load and Transition Times

Figure 18. Deserializer Delay

Figure 19. Deserializer Output Set-Up and Hold Times

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TRI-STATE

RIN

(Diff.)

TRI-STATE

LOW

ROUT[0:11],

HS, VS

PCLK

(RFB = L)

LOCK

'RQ¶W&DUH

tONS

PDB= H

VIH

VIL

VIH

OEN

OSS_SEL

PASS

TRI-STATE

LOW

HIGH

ACTIVE

VIL

TRI-STATE

LOW

HIGH

HIGH LOW

LOW

tSES tONH

tSEH

TRI-STATE

VOD (+)

tBIT (1 UI)

VOD (-)

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AC Timing Diagrams and Test Circuits (continued)

Figure 20. CML Output Driver

Figure 21. Output State (Set-Up and Hold) Times

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1 / fmod

FPCLK+

FPCLK-

fdev

fdev (max)

fdev (min)

FPCLK

Frequency

Time

-18

-16

-14

-12

-10

- 8

- 6

- 4

- 2

MODULATION FREQUENCY ( Hz)

1.0E+04 1.0E+07

1.0E+061.0E+05

JITTER TRANSFER (dB)

1E+04

JITTER FREQUENCY (Hz)

0.45

JITTER AMPLITUDE (UI)

1E+05 1E+06 1E+07

0.50

0.55

0.60

0.65

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AC Timing Diagrams and Test Circuits (continued)

Figure 22. Typical Serializer Jitter Transfer Figure 23. Typical Deserializer Input Jitter

Function at 100 MHz Tolerance Curve at 1.4-Gbps Line Rate

Figure 24. Spread Spectrum Clock Output Profile

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

DIN

10 or

DS90UB913Q - SERIALIZER

Clock

Gen

Timing and

Control

DOUT-

DOUT+

Input Latch

FIFO

Decoder

Encoder

Serializer

PLL

I2C Controller

Encoder

PCLK

SDA

SCL

GPO[3:0] 4

PDB

ID[x]

HSYNC

VSYNC

RIN0-

DS90UB914Q - DESERIALIZER

RIN0+

Timing and

Control

FIFO

Encoder

I2C

Controller

Decoder

Deserializer

Decoder

Output Latch

Clock

Gen

CDR

PDB

BISTEN

OEN

RIN1-

RIN1+

ROUT

HSYNC

VSYNC

GPIO[3:0]

PCLK

LOCK

PASS

IDx[0]

SDA

SCL

2:1

SEL

MODE

MODE IDx[1]

Adaptive Eq.

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

10 Detailed Description

10.1 Overview

The DS90UB91xQ-Q1 FPD-Link III chipsets are intended to link megapixel camera imagers and video

processors in ECUs. The serializer and deserializer chipset can operate from 10-MHz to 100-MHz pixel clock

frequency. The DS90UB913Q-Q1 device transforms a 10- and 12-bit wide parallel LVCMOS data bus along with

a bidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bit

stream contains an embedded clock and DC-balanced information which enhances signal quality to support AC

coupling. The DS90UB914Q-Q1 device receives the single serial data stream and converts it back into a 10- and

12-bit wide parallel data bus together with the control channel data bus. The DS90UB91xQ-Q1 chipsets can

accept up to:

• 12 bits of DATA+2 bits SYNC for an input PCLK range of 10 MHz-50 MHz in the 12-bit low-frequency mode

• 12 bits DATA + 2 SYNC bits for an input PCLK range of 15 MHz to 75 MHz in the 12-bit high-frequency mode

• 10 bits DATA + 2 SYNC bits for an input PCLK range of 20 MHz to 100 MHz in the 10-bit mode.

The DS90UB914Q-Q1 chipset has a 2:1 multiplexer that allows customers to select between two serializer

inputs. The control channel function of the DS90UB91xQ-Q1 chipset provides bidirectional communication

between the image sensor and ECUs. The integrated bidirectional control channel transfers data bidirectionally

over the same differential pair used for video data interface. This interface offers advantages over other chipsets

by eliminating the need for additional wires for programming and control. The bidirectional control channel bus is

controlled through an I2C port. The bidirectional control channel offers asymmetrical communication and is not

dependent on video blanking intervals.

The DS90UB91xQ-Q1 chipset offer customers the choice to work with different clocking schemes. The

DS90UB91xQ-Q1 chipsets can use an external oscillator as the reference clock source for the PLL or PCLK from

the imager as primary reference clock to the PLL.

10.2 Functional Block Diagram

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DATA

PCLK

ECU

Module

DS90UB914Q

DS90UB913Q

CMOS

Image

Sensor

I2CI2C

DS90UB913Q

CMOS

Image

Sensor

I2C

Camera B

Camera A

FSYNC

GPIO

FSYNC

GPIO

DATA

PCLK

Deserializer A

Serializer B

2:1

Serializer A

DATA

PCLK

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

10.3 Feature Description

10.3.1 Serial Frame Format

The high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C and

parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,

balanced and scrambled. The 28-bit frame structure changes in the 12-bit low-frequency mode, 12-bit high

frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control

channel data is transferred over the single serial link along with the high-speed forward data. This architecture

provides a full duplex low-speed forward and backward path across the serial link together with a high-speed

forward channel without the dependence on the video blanking phase.

10.3.2 Line Rate Calculations for the DS90UB91xQ

The DS90UB913Q-Q1 device divides the clock internally by divide-by-1 in the 12-bit low-frequency mode, by

divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high-frequency mode. Conversely, the

DS90UB914Q-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus

the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to

calculate the maximum line rate in the different modes.

• For 12-bit low-frequency mode, Line rate = fPCLK × 28; that is, fPCLK= 50 MHz, line rate = 50 × 28 = 1.4 Gbps

• For 10-bit mode, Line rate = fPCLK / 2 × 28; that is, fPCLK= 100 MHz, line rate = (100 / 2) × 28 = 1.4 Gbps

• For the 12-bit high-frequency mode, Line rate = fPCLK × (2 / 3) × 28; that is, fPCLK= 75 MHz, line rate = (75) ×

(2 / 3) × 28 = 1.4 Gbps

10.3.3 Deserializer Multiplexer Input

The DS90UB914Q-Q1 offers a 2:1 multiplexer that can be used to select which camera is used as the input.

Figure 25 shows the operation of the 2:1 multiplexer in the deserializer. The selection of the camera can be pin

controlled as well as register controlled. Both the deserializer inputs cannot be enabled at the same time. If the

Serializer A is selected as the active serializer, the back-channel for Deserializer A turns ON and vice versa. To

switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the

deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the

deserializer.

Figure 25. Using the Multiplexer on the Deserializer to Enable a Two-Camera System

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS IIIIIH

Bus Activity:

Master

SDA Line

Bus Activity:

Slave

Start

Slave

Address

Start

Slave

Address

Stop

Data

0 1

7-bit Address 7-bit Address

Stop

Bus Activity:

Slave

SDA Line

Bus Activity:

Master Slave

Address Address Data

Start

7-bit Address

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Feature Description (continued)

10.3.4 Error Detection

The chipset provides error detection operations for validating data integrity in long distance transmission and

reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data

transmission error checking. The error detection operating modes support data validation of the following signals:

• Bidirectional control channel data across the serial link

• Parallel video/sync data across the serial link

The chipset provides one parity bit on the forward channel and 4 CRC bits on the back channel for error

detection purposes. The DS90UB91xQ-Q1 chipset checks the forward and back channel serial links for errors

and stores the number of detected errors in two 8-bit registers in the serializer and the deserializer respectively.

To check parity errors on the forward-channel, monitor registers 0x1A and 0x1B on the deserializer. If there is a

loss of LOCK, then the counters on registers 0x1A and 0x1B are reset.

NOTE

Whenever there is a parity error on the forward channel, the PASS pin will go low.

To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the serializer.

10.3.5 Description of Bidirectional Control Bus and I2C Modes

The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external

remote device (such as image sensor) through the bidirectional control channel. Register programming

transactions to/from the DS90UB913xQ-Q1 chipset are employed through the clock (SCL) and data (SDA) lines.

These two signals have open-drain I/Os and both lines must be pulled up to VDDIO by an external resistor.

Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not

being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the

output and allowing it to be pulled up externally. The appropriate pullup resistor values will depend upon the total

bus capacitance and operating speed. The DS90UB91xQ-Q1 I2C bus data rate supports up to 400 kbps

according to I2C fast mode specifications.

Figure 26. Write Byte

Figure 27. Read Byte

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

"HEW,

SDA

SCL

S P

START condition, or

START repeat condition STOP condition

SCL

SDA

START STOP

1 2 6 7 891 2 89

MSB

7-bit Slave Address

R/W

Direction

Bit Acknowledge

from the Device

MSB

Data Byte

*Acknowledge

or Not-ACK

ACK N/ACK

Repeated for the Lower Data Byte

and Additional Data Transfers

LSB LSB

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

Feature Description (continued)

Figure 28. Basic Operation

Figure 29. Start and Stop Conditions

10.3.6 Slave Clock Stretching

The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external

remote device (such as image sensor) through the bidirectional control.

NOTE

To communicate and synchronize with remote devices on the I2C bus through the

bidirectional control channel/MCU, the chipset utilizes bus clock stretching (holding the

SCL line low) during data transmission where the I2C slave pulls the SCL line low on the

9th clock of every I2C transfer (before the ACK signal).

The slave device will not control the clock and only stretches it until the remote peripheral has responded. The

I2C master must support clock stretching to operate with the DS90UB91xQ-Q1 chipset.

10.3.7 I2C Pass-Through

I2C pass-through provides an alternative means to independently address slave devices. The mode enables or

disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine

whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus

traffic will continue to pass through, I2C commands will be excluded to the remote I2C device. The pass-through

function also provides access and communication to only specific devices on the remote bus.

See Figure 30 for an example of this function.

If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass-through enabled will

transfer I2C commands to remote Camera A. The SER B with I2C pass-through disabled, any I2C commands will

be bypassed on the I2C bus to Camera B.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

HOST DS90UB913Q

SCL

SDA

RPU RPU

10k

RID

SCL

SDA

To other Devices

ID[x]

1.8V

VDDIO

ECU

Module

DS90UB914Q

DS90UB913Q

DIN[11:0]

,HS,VS

PCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],

HS,VS,

PCLK

I2C

SDA

SCL SDA

SCL

DES B: I2C_SLAVE

DS90UB914Q

DS90UB913Q

DIN[11:0]

,HS,VS

PCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],

HS,VS,

PCLK

I2C

SDA

SCL SDA

SCL

Camera B

Slave ID: (0xA0)

SER A: I2C _MASTER

I2C_PASS_THRU Enabled DES A: I2C_SLAVE

Camera A

Slave ID: (0xA0)

Master

SER B: I2C_MASTER

I2C_PASS_THRU Disabled

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Feature Description (continued)

Figure 30. I2C Pass-Through

10.3.8 ID[x] Address Decoder on the Serializer

The ID[x] pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) to

allow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 5

possible addresses for each serializer device. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ

resistor and a pulldown resistor (RID) of the recommended value to set the physical device address. The

recommended maximum resistor tolerance is 1%.

Figure 31. ID[x] Address Decoder on the Serializer

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

MENTS it" g5

HOST DS90UB914Q

SCL

SDA

RPU RPU

10k

RID0

SCL

SDA

To other

Devices

IDx[0]

1.8V

VDDIO

10k

RID1

1.8V

IDx[1]

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

Table 1. ID[x] Resistor Value for DS90UB913Q-Q1 Serializer

ID[x] Resistor Value — DS90UB913Q-Q1 Serializer

Resistor RID0 ΩAddress 8'b 0 appended

Address 7'b

(1% Tolerance) (WRITE)

0 k 0x58 0xB0

2 k 0x59 0xB2

4.7 k 0x5A 0xB4

8.2 k 0x5B 0xB6

14 k 0x5C 0xB8

100 k 0x5D 0xBA

10.3.9 ID[x] Address Decoder on the Deserializer

The IDx[0] and IDx[1] pins on the deserializer are used to decode and set the physical slave address of the

deserializer (I2C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible

addresses for each deserializer device. As there will be more deserializer devices connected on the same board

than serializers, more I2C device addresses have been defined for the DS90UB914Q-Q1 deserializer than the

DSDS90UB913Q-Q1 serializer. The pins must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩresistor and

two pulldown resistors (RID0 and RID1) of the recommended value to set the physical device address. The

recommended maximum resistor tolerance is 1%.

Figure 32. ID[x[ Address Decoder on the Deserializer

Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer

ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER

RESISTOR RID1 ΩRESISTOR RID0 ΩADDRESS 8'b 0 APPENDED

ADDRESS 7'b

(1%TOLERANCE) (1%TOLERANCE) (WRITE)

0 k 0 k 0x60 0xC0

0 k 3 k 0x61 0xC2

0 k 11 k 0x62 0xC4

0 k 100 k 0x63 0xC6

3 k 0 k 0x64 0xC8

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer (continued)

ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER

3 k 3 k 0x65 0xCA

3 k 11 k 0x66 0XCC

3 k 100 k 0x67 0XCE

11 k 0 k 0x68 0XD0

11 k 3 k 0x69 0XD2

11 k 11 k 0x6A 0XD4

11 k 100 k 0x6B 0XD6

100 k 0 k 0x6C 0XD8

100 k 3 k 0x6D 0XDA

100 k 11 k 0x6E 0XDC

100 k 100 k 0x6F 0XDE

10.3.10 Programmable Controller

An integrated I2C slave controller is embedded in the DS90UB913Q-Q1 serializer as well as the DS90UB914Q-

Q1 deserializer. It must be used to configure the extra features embedded within the programmable registers or it

can be used to control the set of programmable GPIOs.

10.3.11 Synchronizing Multiple Cameras

For applications requiring multiple cameras for frame-synchronization, TI recommends to utilize the General-

Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To

synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical

or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize

signal corresponds to the start and end of a frame and the start and end of a field.

NOTE

this form of synchronization timing relationship has a non-deterministic latency. After the

control data is reconstructed from the bidirectional control channel, there will be a time

variation of the GPIO signals arriving at the different target devices (between the parallel

links). The maximum latency delta (t1) of the GPIO data transmitted across multiple links

is 25 µs.

NOTE

The user must verify that the timing variations between the different links are within their

system and timing specifications.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

‘5‘ TEXAS INSTRUMENTS

DES A

GPIO[n] Input

DES B

GPIO[n] Input

SER A

GPIO[n] Output

SER B

GPIO[n] Output

ECU

Module

DS90UB914Q

DS90UB913Q

CMOS

Image

Sensor

I2CI2C

DS90UB914Q

DS90UB913Q

CMOS

Image

Sensor

I2CI2C

Camera B

Camera A

DATA

PCLK

DATA

PCLK

FSYNC

GPO

GPIO

FSYNC

GPO

GPIO

FSYNC

DATA

PCLK

DATA

PCLK

FSO FSO

FSIN FSIN

Deserializer A

Serializer A

Deserializer B

Serializer B

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

See Figure 33 for an example of synchronizing multiple cameras.

The maximum time (t1) between the rising edge of GPIO (that is, sync signal) arriving at Camera A and Camera

B is 25 µs.

Figure 33. Synchronizing Multiple Cameras

Figure 34. GPIO Delta Latency

10.3.12 General-Purpose I/O (GPIO) Descriptions

There are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB91xQ-Q1 chipsets are run

off the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configured

as outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializer

can behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured to

be the input signals feeding the output of the GPOs on the serializer. In addition the GPIOs on the deserializer

can be configured to behave as outputs of the local register on the deserializer. If the DS90UB91xQ-Q1 chipsets

are run off the external oscillator source as the reference clock, then GPO3 on the serializer is automatically

configured to be the input for the external clock and GPIO2 on the deserializer is configured to be the output of

the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and GPIO3 on

the deserializer can only behave as outputs of the local register on the deserializer. The GPIO maximum

switching rate is up to 66 kHz when configured for communication between deserializer GPIO to serializer GPO.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

600

SERIAL LINE FREQUENCY (MHz)

EQUALIZER GAIN (dB)

700500400300200100

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

10.3.13 LVCMOS VDDIO Option

1.8-V, 2.8-V, and 3.3-V serializer inputs and 1.8-V and 3.3-V deserializer outputs are user configurable to provide

compatibility with 1.8-V, 2.8-V and 3.3-V system interfaces.

10.3.14 Deserializer – Adaptive Input Equalization (AEQ)

The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media.

The level of equalization can also be manually selected through register controls. The fully-adaptive equalizer

output can be seen using the CMLOUTP/CMLOUTN pins in the deserializer.

Figure 35. Maximum Equalizer Gain vs. Line Frequency

10.3.15 EMI Reduction

10.3.15.1 Deserializer Staggered Output

The receiver staggers output switching to provide a random distribution of transitions within a defined window.

Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and

helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.

10.3.15.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer

The DS90UB914Q-Q1 parallel data and clock outputs have programmable SSCG ranges from 10 MHz to 100

MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSC

control registers on the DS90UB914Q-Q1 device. SSC profiles can be generated using bits [3:0] in register 0x02

in the deserializer.

10.4 Device Functional Modes

10.4.1 DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock

In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of

the DS90UB91xQ-Q1 chipsets. In this case, the DS90UB913Q-Q1 device should be operated by using an

external clock source as the reference clock for the DS90UB91xQ-Q1 chipsets. This is the recommended

operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q-Q1

serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel

clock from the imager are then fed into the DS90UB913Q-Q1 device. Figure 36 shows the operation of the

DS90UB1xQ-Q1 chipsets while using an external automotive grade oscillator.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

FPD Link III-

High Speed

Bi-Directional

Control Channel

Image

Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

HSYNC,

VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLK

Pixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

ROUT[9:0]

HSYNC,

VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DS90UB914Q

Deserializer

DS90UB913Q

Serializer

GPO[1:0] GPO[1:0]

2GPO[3:0]

GPIO[3:0]

Camera Data

External

Oscillator

PLL

÷2

GPO3

GPO2

Reference Clock

(Ext. OSC/2)

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

Device Functional Modes (continued)

Figure 36. DS90UB91xQ-Q1 Operation in the External Oscillator Mode

When the DS90UB913Q-Q1 device is operated using an external oscillator, the GPO3 pin on the

DS90UB913Q-Q1 is the input pin for the external oscillator. In applications where the DS90UB913Q-Q1 device is

operated from an external oscillator, the divide-by-2 circuit in the DS90UB913Q-Q1 device feeds back the

divided clock output to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to

be fixed for the 12-bit high-frequency mode and the 10-bit mode.

NOTE

In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency

must be 2. In the 12-bit high-frequency mode, the pixel clock frequency divided by the

external oscillator frequency must be 1.5.

For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the

imager needs to be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency

is 48 MHz in the 12-bit high-frequency mode, the pixel clock frequency of the imager needs to be 1.5 times of the

external oscillator frequency, that is, 72 MHz. In this mode, GPO2 and GPO3 on the serializer cannot act as the

output of the input signal coming from GPIO2 or GPIO3 on the deserializer.

10.4.2 DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock

The DS90UB91xQ-Q1 chipsets can be operated by using the pixel clock from the imager as the reference

clock.Figure 37 shows the operation of the DS90UB91xQ-Q1 chipsets using the pixel clock from the imager. If

the DS90UB913Q-Q1 device is operated using the pixel clock from the imager as the reference clock, then the

imager uses an external oscillator as its reference clock. There are 4 GPIOs on the serializer and 4 GPIOs on

the deserializer in this mode.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DS90UB913Q

HOST

SCL

SDA

RPU RPU

10k

RMODE

SCL

SDA

To other

Devices

MODE

1.8V

VDDIO

FPD-Link III

Bi-Directional

Back Channel

Image

Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

FV,LV

SDA

SCL

DOUT- RIN0-

DOUT+ RIN0+

Camera Unit

10 or 12

YUV

HSYNC

VSYNC

PCLK

Pixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

ROUT[9:0]

FV, LV

SDA

SCL

PCLK

10 or 12

YUV

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DS90UB914Q

Deserializer

DS90UB913Q

GPO GPO[3:0]

GPIO

GPIO[3:0]

Camera Data

Ext.

Oscillator

PLL RIN1-

RIN1+

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Device Functional Modes (continued)

Figure 37. DS90UB91xQ-Q1 Operation in PCLK mode

10.4.3 MODE Pin on Serializer

The mode pin on the serializer can be configured to select if the DS90UB913Q-Q1 device is to be operated from

the external oscillator or the PCLK from the imager. The pin must be pulled to VDD (1.8 V, not VDDIO) with a

10-kΩresistor and a pulldown resistor (RMODE) of the recommended value to set the modes shown in Figure 38.

The recommended maximum resistor tolerance is 1%.

Figure 38. MODE Pin Configuration on DS90UB913Q-Q1

Table 3. DS90UB913Q-Q1 Serializer MODE Resistor

Value

MODE SELECT RMODE RESISTOR VALUE

PCLK from imager mode 100 kΩ

External Oscillator mode 4.7 kΩ

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

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SCL

SDA

RPU RPU

10k

RMODE

SCL

SDA

To Other

Devices

MODE

1.8V

VDDIO

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10.4.4 MODE Pin on Deserializer

The mode pin on the deserializer can be used to configure the device to work in the 12-bit low-frequency mode,

12-bit high frequency mode or the 10-bit mode of operation. Internally, the DS90UB91xQ-Q1 chipset operates in

a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5

mode in the 12-bit high-frequency mode. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩresistor

and a pulldown resistor (RMODE) of the recommended value to set the different modes in the deserializer as

mentioned in Table 4. The deserializer automatically configures the serializer to correct mode through the back-

channel. The recommended maximum resistor tolerance is 1%

Figure 39. Mode Pin Configuration on DS90UB914Q-Q1 Deserializer

Table 4. DS90UB914Q-Q1 Deserializer MODE Resistor

Value

DS90UB914Q-Q1 DESERIALIZER MODE RESISTOR VALUE

MODE SELECT RMODE RESISTOR VALUE

12-bit low-frequency mode

10 to 50 MHz PCLK 0 Ω

10 to 12 bit DATA + 2 SYNC

12-bit low-frequency mode

15 to 75 MHz PCLK 3 kΩ

10 to 12 bit DATA + 2 SYNC

10-bit mode

20 to 100 MHz PCLK 11 kΩ

10 to 10 bit DATA + 2 SYNC

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10.4.5 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select

(OSS_SEL)

When PDB is driven HIGH, the CDR PLL of the deserializer begins locking to the serial input and LOCK is TRI-

STATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q-Q1 completes its lock

sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered

from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on

the OEN and OSS_SEL setting (Table 3). See Figure 20.

Table 5. Output States

INPUTS OUTPUTS

SERIAI INPUTS PDB OEN OSS LOCK PASS DATA, GPIO, I2S CLK

X 0 X X Z Z Z Z

X 1 0 0 L or H L L L

X 1 0 1 L or H Z Z Z

L/Osc (Register

Static 1 1 0 L L L Bit Enable)

Static 1 1 1 H Previous State L L

Active 1 1 0 H L L L

Active 1 1 1 H Valid Valid Valid

10.4.6 Multiple Device Addressing

Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C

bus. The DS90UB91xQ-Q1 provides slave ID matching/aliasing to generate different target slave addresses

when connecting more than two identical devices together on the same bus. This allows the slave devices to be

independently addressed. Each device connected to the bus is addressable through a unique ID by programming

of the SLAVE_ID_MATCH register on deserializer. This will remap the SLAVE_ID_MATCH address to the target

SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of

I2C peripherals in order to properly address the target device.

See Figure 40 for an example of multiple device addressing.

• ECU is the I2C master and has an I2C master interface

• The I2C interfaces in DES A and DES B are both slave interfaces

• The I2C protocol is bridged from DES A to SER A and from DES B to SER B

• The I2C interfaces in SER A and SER B are both master interfaces

If master controller transmits I2C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote

Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to

0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B

0xC2 will forward transaction to slave device 0xA2.

The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H).

For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I2C pass-

through function.

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DIN/

ROUT

PCLK

TRFB/RRFB: 0 TRFB/RRFB: 1

ECU

Module

DS90UB914Q

DS90UB913Q

DIN[11:0]

, HS, VS,

PCLK

CMOS

Image

Sensor

I2CI2C

SDA

SCL SDA

SCL

DES B: ID[x](0xC2)

SLAVE_ID2_MATCH(0xA4)

SLAVE_ID2_INDEX(0xA0)

SLAVE_ID2_MATCH(0xA6)

SLAVE_ID2_INDEX(0xA2)

DS90UB914Q

DS90UB913Q

CMOS

Image

Sensor

I2CI2C

SDA

SCL SDA

SCL

Camera B

Slave ID: (0xA0)

SER A: ID[x](0xB0) DES A: ID[x](0xC0)

SLAVE_ID1_MATCH(0xA0)

SLAVE_ID1_INDEX(0xA0)

SLAVE_ID2_MATCH(0xA2)

SLAVE_ID2_INDEX(0xA2)

Camera A

Slave ID: (0xA0)

Master

SER B: ID[x](0xB2)

Slave ID: (0xA2)

PC/

EEPROM

PC/

EEPROM

ROUT[11:0],

HS, VS,

PCLK

DIN[11:0]

, HS, VS,

PCLK

ROUT[11:0],

HS, VS,

PCLK

DS90UB913Q-Q1

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Figure 40. Multiple Device Addressing

10.4.7 Powerdown

The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by

the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if

the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the

SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed

driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device.

This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also

available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops.

When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output

valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration.

10.4.8 Pixel Clock Edge Select (TRFB / RRFB)

The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge

that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register

is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the

data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,

data is strobed on the falling edge of the PCLK.

Figure 41. Programmable PCLK Strobe Select

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All other 1.8V Supplies

VDD_CORE,

PDB

1.8V OR 3.3V

1.8V

1.8V OR 3.3V

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10.4.9 Power-Up Requirements and PDB Pin

When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8 V to 3.3 V) before

the other supplies (VDDn) begin to ramp. It is required to delay and release the PDB Signal after VDD (VDDn

and VDDIO) power supplies have settled to the recommended operating voltage. An external RC network can be

connected to the PDB pin to ensure PDB arrives after all the VDD has stabilized.

Figure 42. Power-Up Sequencing

10.4.10 Built-In Self Test

An optional AT-Speed, Built-In Self Test (BIST) feature supports the testing of the high-speed serial link and low-

speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for

system diagnostics.

10.4.11 BIST Configuration and Status

The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is

controlled through pins. BIST can be configured through registers using BIST Control register (0x24). Pin based

configuration is defined as follows:

• BISTEN : Enable the BIST Process

• GPIO0 and GPIO1 : Defines the BIST clock source (PCLK vs. various frequencies of internal OSC

Table 6. BIST Configuration

DESERIALIZER GPIO[0:1] OSCILLATOR SOURCE BIST FREQUENCY (MHZ)

00 External PCLK PCLK or External Oscillator

01 Internal 50

10 Internal 25

11 Internal 12.5

The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using

registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST

status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half

PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with

errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also

be read through I2C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a

new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is

deassserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be

present.

The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. So for all

practical purposes, the BIST status can be monitored from register 0x25, that is, BIST Error Count on the

DS90UB914Q-Q1 deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and

PCLK need to be present.

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X XX

PCLK

(RFB = L)

BISTEN

(DES)

PASS

DATA

(internal)

PASS

BIST Duration

Prior Result

BIST

Result

Held

PASS

FAIL

X = bit error(s)

ROUT[0:11],

HS, VS

DATA

(internal)

Case 1 - PassCase 2 - Fail

Prior Result

Normal BIST Test Normal

DES Outputs

LOCK

SSO

Normal

BIST

start

BIST

stop

BIST

Wait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal

Mode - check PASS

Step 4: DES/SER in Normal

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10.4.11.1 Sample BIST Sequence

Step 1. For the DS90UB91xQ-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of

DS90UB914Q-Q1 FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1

pins as shown in Table 4.

Step 2. The DS90UB913Q-Q1 serializer is woken up through the back channel if it is not already on. The SSO

pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer

are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST

starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the

clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload

error rate.

Step 3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data.

The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count

Step 4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 44 shows the

waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple

errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data

transmission, and so forth), thus they may be introduced by greatly extending the cable length, faulting the

interconnect, or by reducing signal condition enhancements (RX equalization).

Figure 43. AT-Speed BIST System Flow Diagram

Figure 44. BIST Timing Diagram

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10.5 Register Maps

Table 7. DS90UB913Q-Q1 Control Registers

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7-bit address of serializer; 0x58'h

7:1 DEVICE ID (0101_1000X'b) default

0x00 I2C Device ID RW 0x58'h 0: Device ID is from ID[x]

0 SER ID SEL 1: Register I2C Device ID overrides ID[x]

7 RSVD Reserved

Digital Output Drive Strength

6 RDS RW 0 1: High Drive Strength

0: Low Drive Strength

Auto Voltage Control

5 VDDIO Control RW 1 1: Enable

0: Disable

VDDIOVoltage set

4 VDDIO MODE RW 1 0: 1.8V

1: 3.3V

This register can be set only through local I2C access

0x01 Power and Reset 1: Analog power-down : Powers Down the analog block

3 ANAPWDN RW 0 in the serializer

0: No effect

2 RSVD RW 0 Reserved

1: Resets the digital block except for register values

DIGITAL values. Does not affect device I2C Bus or Device ID.

1 RW 0

RESET1 This bit is self-clearing.

0: Normal Operation

1: Digital Reset, resets the entire digital block including

0 DIGITAL RESET0 RW 1 all register values.This bit is self-clearing.

0: Normal Operation.

0x02 RESERVED

Back-channel CRC Checker Enable

RX CRC Checker

7 RW 1 1:Enabled

Enable 0:Disabled

Forward channel Parity Generator Enable

TX Parity Generator

6 RW 1 1: Enable

Enable 0: Disable

Clear CRC Error Counters.

This bit is NOT self-clearing.

5 CRC Error Reset RW 0 1: Clear Counters

0: Normal Operation

Automatically Acknowledge I2C Remote Write

The mode works when the system is LOCKed.

1: Enable: When enabled, I2C writes to the deserializer

General I2C Remote Write (or any remote I2C Slave, if I2C PASS ALL is enabled)

0x03 4 RW 0

Configuration Auto Acknowledge are immediately acknowledged without waiting for the

deserializer to acknowledge the write. The accesses are

then re-mapped to address specified in 0x06.

0: Disable

1: Enable Forward Control Channel pass-through of all

I2C accesses to I2C Slave IDs that do not match the

Serializer I2C Slave ID. The I2C accesses are then

3 I2C Pass All RW 0 remapped to address specified in register 0x06.

0: Enable Forward Control Channel pass-through only of

I2C accesses to I2C Slave IDs matching either the

remote Deserializer Slave ID or the remote Slave ID.

I2C Pass-Through Mode

2 I2C PASSTHROUGH RW 1 0: Pass-Through Disabled

1: Pass-Through Enabled

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Table 7. DS90UB913Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

1:Enabled : When enabled this registers overrides the

clock to PLL mode (External Oscillator mode or Direct

PCLK mode) defined through MODE pin and allows

1 OV_CLK2PLL RW 0 selection through register 0x35 in the serializer

0: Disabled : When disabled, Clock to PLL mode

(External Oscillator mode or Direct PCLK mode) is

General

0x03 defined through MODE pin on the serializer.

Configuration

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the Rising Clock

0 TRFB RW 1 Edge.

0: Parallel Interface Data is strobed on the Falling Clock

Edge.

0x04 RESERVED

7 RSVD RW 0 Reserved

6 RSVD RW 0 Reserved.

Allows overriding mode select bits coming from back-

channel

5 MODE_OVERRIDE RW 0 1: Overrides MODE select bits

0: Does not override MODE select bits

0x05 Mode Select Indicates that the status of mode select from deserializer

4 MODE_UP To DATE R 0 is up to date

Pin_MODE_12–bit 1: 12-bit high-frequency mode is selected.

3 R 0

High Frequency 0: 12-bit high-frequency mode is not selected.

Pin_MODE_10–bit 1: 10-bit mode is selected.

2 R 0

mode 0: 10-bit mode is not selected.

1:0 RSVD Reserved

7-bit Deserializer Device ID configures the I2C Slave ID

of the remote deserializer. A value of 0 in this field

disables I2C access to the remote deserializer. This field

is automatically configured by the Bidirectional Control

7:1 Desializer Device ID RW 0x00 Channel once RX Lock has been detected. Software

may overwrite this value, but should also assert the

0x06 DES ID FREEZE DEVICE ID bit to prevent overwriting by the

Bidirectional Control Channel.

1: Prevents auto-loading of the Deserializer Device ID by

the bidirectional control channel. The ID will be frozen at

0 Freeze Device ID RW 0 the value written.

0: Update

7-bit Remote Deserializer Device Alias ID Configures the

decoder for detecting transactions designated for an I2C

deserializer device. The transaction will be remapped to

7:1 Deserializer ALIAS ID RW 0 the address specified in the DES ID register.

0x07 DESAlias A value of 0 in this field disables access to the remote

I2C Slave.

0 RSVD Reserved

7-bit Remote Slave Device ID Configures the physical

I2C address of the remote I2C Slave device attached to

the remote deserializer. If an I2C transaction is

addressed to the Slave Alias ID, the transaction will be

7:1 SLAVE ID RW 0x00 remapped to this address before passing the transaction

0x08 SlaveID across the Bidirectional Control Channel to the

deserializer. A value of 0 in this field disables access to

the remote I2C slave.

0 RSVD Reserved

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Table 7. DS90UB913Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7-bit Remote Slave Device Alias ID Configures the

decoder for detecting transactions designated for an I2C

Slave device attached to the remote deserializer. The

7:1 SLAVE ALIAS ID RW 0x00 transaction will be remapped to the address specified in

0x09 SlaveAlias the Slave ID register. A value of 0 in this field disables

access to the remote I2C Slave.

0 RSVD Reserved

Number of back-channel CRC errors during normal

0x0A CRC Errors 7:0 CRC Error Byte 0 R 0 operation. Least Significant byte

Number of back-channel CRC errors during normal

0x0B CRC Errors 7:0 CRC Error Byte 1 R 0 operation. Most Significant byte

Revision ID

7:5 Rev-ID R 0 0x00: Production

1: RX LOCKED

4 RX Lock Detect R 0 0: RX not LOCKED

BIST CRC Error 1: CRC errors in BIST mode

3 R 0

Status 0: No CRC errors in BIST mode

1: Valid PCLK detected

2 PCLK Detect R 0 0: Valid PCLK not detected

1: CRC error is detected during communication with

0x0C General Status deserializer.

1 DES Error R 0 This bit is cleared upon loss of link or assertion of CRC

ERROR RESET in register 0x04.

0: No effect

1: Cable link detected

0: Cable link not detected

This includes any of the following faults

0 LINK Detect R 0 — Cable Open

— + and - shorted

— Short to GND

— Short to battery

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the local

7 GPO1 Output Value RW 0 GPIO direction is Output, and remote GPIO control is

disabled.

Remote GPIO Control

1: Enable GPIO control from remote deserializer. The

GPO1 Remote

6 RW 1 GPIO pin needs to be an output, and the value is

Enable received from the remote deserializer.

0: Disable GPIO control from remote deserializer.

1: Input

5 GPO1 Direction RW 0 0: Output

1: GPIO enable

4 GPO0 Enable RW 1

GPO[0] 0: Tri-state

0x0D and GPO[1] Local GPIO Output Value This value is output on the

Configuration GPIO pin when the GPIO function is enabled, the local

3 GPO0 Output Value RW 0 GPIO direction is Output, and remote GPIO control is

disabled.

Remote GPIO Control

1: Enable GPIO control from remote deserializer. The

GPO0 Remote

2 RW 1 GPIO pin needs to be an output, and the value is

Enable received from the remote deserializer.

0: Disable GPIO control from remote deserializer.

1: Input

1 GPO0 Direction RW 0 0: Output

1: GPIO enable

0 GPO0 Enable RW 1 0: Tri-state

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Table 7. DS90UB913Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

Local GPIO Output Value This value is output on the

GPIO pin when the GPIO function is enabled, the local

7 GPO3 Output Value RW 0 GPIO direction is Output, and remote GPIO control is

disabled.

Remote GPIO Control

1: Enable GPIO control from remote deserializer. The

GPO3 Remote

6 RW 0 GPIO pin needs to be an output, and the value is

Enable received from the remote deserializer.

0: Disable GPIO control from remote deserializer.

1: Input

5 GPO3 Direction RW 1 0: Output

1: GPIO enable

4 GPO3 Enable RW 1

GPO[2] 0: Tri-state

0x0E and GPO[3] Local GPIO Output Value This value is output on the

Configuration GPIO pin when the GPIO function is enabled, the local

3 GPO2 Output Value RW 0 GPIO direction is Output, and remote GPIO control is

disabled.

Remote GPIO Control

1: Enable GPIO control from remote deserializer. The

GPO2 Remote

2 RW 1 GPIO pin needs to be an output, and the value is

Enable received from the remote deserializer.

0: Disable GPIO control from remote deserializer.

1: Input

1 GPO2 Direction RW 0 0: Output

1: GPIO enable

0 GPO2 Enable RW 1 0: Tri-state

7:5 RSVD Reserved

SDA Output Delay This field configures output delay on

the SDA output. Setting this value will increase output

delay in units of 50 ns. Nominal output delay values for

SCL to SDA are:

4:3 SDA Output Delay RW 00 00 : 350 ns

01: 400 ns

10: 450 ns

11: 500 ns

Disable Remote Writes to Local Registers Setting this bit

to a 1 will prevent remote writes to local device registers

from across the control channel. This prevents writes to

2 Local Write Disable RW 0 the serializer registers from an I2C master attached to

the deserializer. Setting this bit does not affect remote

0x0F I2C Master Config access to I2C slaves at the serializer.

Speed up I2C Bus Watchdog Timer

1: Watchdog Timer expires after approximately 50

I2C Bus Timer

1 RW 0 microseconds

Speed up 0: Watchdog Timer expires after approximately 1

second.

1. Disable I2C Bus Watchdog Timer When the I2C

Watchdog Timer may be used to detect when the I2C

bus is free or hung up following an invalid termination of

I2C Bus Timer a transaction. If SDA is high and no signaling occurs for

0 RW 0

Disable approximately 1 second, the I2C bus will assumed to be

free. If SDA is low and no signaling occurs, the device

will attempt to clear the bus by driving 9 clocks on SCL

0: No effect

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Table 7. DS90UB913Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7 RSVD Reserved

Internal SDA Hold Time. This field configures the amount

6:4 SDA Hold Time RW 0x1 of internal hold time provided for the SDA input relative

0x10 I2C Control to the SCL input. Units are 50 ns.

I2C Glitch Filter Depth This field configures the maximum

3:0 I2C Filter Depth RW 0x7 width of glitch pulses on the SCL and SDA inputs that

will be rejected. Units are 10 ns.

I2C Master SCL High Time This field configures the high

pulse width of the SCL output when the serializer is the

Master on the local I2C bus. Units are 50 ns for the

nominal oscillator clock frequency. The default value is

0x11 SCL High Time 7:0 SCL High Time RW 0x82 set to provide a minimum (4µs + 1µs of rise time for

cases where rise time is very fast) SCL high time with

the internal oscillator clock running at 26MHz rather than

the nominal 20 MHz.

I2C SCL Low Time This field configures the low pulse

width of the SCL output when the serializer is the Master

on the local I2C bus. This value is also used as the SDA

setup time by the I2C Slave for providing data prior to

releasing SCL during accesses over the Bidirectional

0x12 SCL LOW Time 7:0 SCL Low Time RW 0x82 Control Channel. Units are 50 ns for the nominal

oscillator clock frequency. The default value is set to

provide a minimum (4.7 µs + 0.3 µs of fall time for cases

where fall time is very fast) SCL low time with the

internal oscillator clock running at 26 MHz rather than

the nominal 20 MHz.

General-Purpose 1: High

0x13 7:0 GPCR[7:0] RW 0

Control 0: Low

7:3 RSVD Reserved

Allows choosing different OSC clock frequencies for

forward channel frame.

OSC Clock Frequency in Functional Mode when OSC

2:1 Clock Source RW 0x0 mode is selected or when the selected clock source is

0x14 BIST Control not present, for example, missing PCLK/ External

Oscillator. See Table 9 for oscillator clock frequencies

when PCLK/ External Clock is missing.

BIST Control:

0 BIST Enable RW 0 1: Enable BIST mode

0: Disable BIST mode

0x15 - RESERVED

0x1D

The watchdog timer allows termination of a control

channel transaction if it fails to complete within a

7:1 BCC Watchdog Timer RW 0x7F programmed amount of time. This field sets the

Bidirectional Control Channel Watchdog Timeout value

BCC Watchdog

0x1E in units of 2ms. This field should not be set to 0.

Control

Disable Bidirectional Control Channel Watchdog Timer

BCC Watchdog Timer

0 RW 0 1: Disables BCC Watchdog Timer operation

Disable 0: Enables BCC Watchdog Timer operation

0x1F- RESERVED

0x29

BIST Mode CRC Number of CRC Errors in the back channel when in

0x2A CRC Errors 7:0 R 0

Errors Count BIST mode

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Table 7. DS90UB913Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

0x2B - RESERVED

0x34

7:4 RSVD Reserved

Status of mode select pin

1: Indicates External Oscillator mode is selected by

PIN_LOCK to

3 RW 0 mode-resistor

External Oscillator 0: External Oscillator mode is not selected by mode-

resistor

PLL Clock Status of mode select pin

0x35 PIN_LOCK to

Overwrite 2 RW 0 1: Indicates PCLK mode is selected by mode-resistor

Oscillator 0: PCLK mode not selected by mode-resistor

Affects only when 0x03[1]=1 (OV_CLK2PLL) and

LOCK to External 0x35[0]=0.

1 RW 0

Oscillator 1: Routes GPO3 directly to PLL

0: Allows PLL to lock to PCLK"

0 RSVD Reserved

Table 8. DS90UB914Q-Q1 Control Registers

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7-bit address of deserializer;

7:1 DEVICE ID RW 0x60'h 0x60h

0x00 I2C Device ID 0: Deserializer Device ID is set using address

Deserializer ID

0 RW 0 coming from CAD

Select 1: Register I2C Device ID overrides ID[x]

7:6 RSVD Reserved

This register can be set only through local I2C

access

5 ANAPWDN RW 0 1: Analog power-down : Powers down the

analog block in the serializer

0: No effect

4:2 RSVD Reserved

0x01 Reset Digital Reset Resets the entire digital block

except registers. This bit is self-clearing.

1 Digital Reset 1 RW 0 1: Reset

0: No effect

Digital Reset Resets the entire digital block

including registers. This bit is self-clearing.

0 Digital Reset 0 RW 0 1: Reset

0: No effect

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7 RSVD Reserved

6 RSVD Reserved

1: Output PCLK or OSC clock when not

5 Auto-Clock RW 0 LOCKED

0: Only PCLK

1: Selects 8x mode for 10-18 MHz frequency

4 SSCG LFMODE RW 0 range in SSCG

0: SSCG running at 4X mode

SSCG Select

0000: Normal Operation, SSCG OFF

0001: fmod (kHz) PCLK/2168, fdev ±0.50%

0010: fmod (kHz) PCLK/2168, fdev ±1.00%

General 0011: fmod (kHz) PCLK/2168, fdev ±1.50%

0x02 Configuration 0 0100: fmod (kHz) PCLK/2168, fdev ±2.00%

0101: fmod (kHz) PCLK/1300, fdev ±0.50%

0110: fmod (kHz) PCLK/1300, fdev ±1.00%

0111: fmod (kHz) PCLK/1300, fdev ±1.50%

3:0 SSCG RW 0 1000: fmod (kHz) PCLK/1300, fdev ±2.00%

1001: fmod (kHz) PCLK/868, fdev ±0.50%

1010: fmod (kHz) PCLK/868, fdev ±1.00%

1011: fmod (kHz) PCLK/868, fdev ±1.50%

1100: fmod (kHz) PCLK/868, fdev ±2.00%

1101: fmod (kHz) PCLK/650, fdev ±0.50%

1110: fmod (kHz) PCLK/650, fdev ±1.00%

1111: fmod (kHz) PCLK/650, fdev ±1.50%

Note: This register should be changed only

after disabling SSCG.

Forward-Channel Parity Checker Enable

RX Parity Checker

7 RW 1 1: Enable

Enable 0: Disable

Back-Channel CRC Generator Enable

TX CRC Checker

6 RW 1 1: Enable

Enable 0: Disable

General

0x03 Configuration 1 Auto voltage control

5 VDDIO Control RW 1 1: Enable (auto-detect mode)

0: Disable

VDDIO voltage set

4 VDDIO Mode RW 0 1: 3.3 V

0: 1.8 V

I2C Pass-Through Mode

3 I2C Passthrough RW 1 1: Pass-Through Enabled

0: Pass-Through Disabled

Automatically Acknowledge I2C Remote Write

When enabled, I2C writes to the deserializer (or

any remote I2C Slave, if I2C PASS ALL is

enabled) are immediately acknowledged

without waiting for the deserializer to

2 AUTO ACK RW 0 acknowledge the write. The accesses are then

remapped to address specified in 0x06. This

General allows I2C bus without LOCK.

0x03 Configuration 1 1: Enable

0: Disable

Parity Error Reset, This bit is self-clearing.

1 Parity Error Reset RW 0 1: Parity Error Reset

0: No effect

Pixel Clock Edge Select

1: Parallel Interface Data is strobed on the

0 RRFB RW 1 Rising Clock Edge.

0: Parallel Interface Data is strobed on the

Falling Clock Edge.

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

Equalization gain

0x00 = ~0.0 dB

EQ level - when 0x01 = ~4.5 dB

AEQ bypass is

EQ Feature 0x03 = ~6.5 dB

0x04 7:0 enabled EQ setting RW 0x00

Control 1 0x07 = ~7.5 dB

is provided by this 0x0F = ~8.0 dB

0x3F = ~12.5 dB

0x05 RESERVED

7:1 Remote ID RW 0x0C Remote Serializer ID

Freeze Serializer Device ID Prevent auto-

0x06 SER ID loading of the serializer Device ID from the

0 Freeze Device ID RW 0 Forward Channel. The ID will be frozen at the

value written.

7:1 7-bit Remote Serializer Device Alias ID

Configures the decoder for detecting

transactions designated for an I2C deserializer

Serializer Alias ID RW 0x00 device. The transaction will be remapped to the

0x07 SER Alias address specified in the SER ID register. A

value of 0 in this field disables access to the

remote I2C Slave.

0 RSVD Reserved

7-bit Remote Slave Device ID 0 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID0 RW 0 ID0, the transaction will be remapped to this

0x08 Slave ID[0] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 1 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID1 RW 0 ID1, the transaction will be remapped to this

0x09 Slave ID[1] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 2 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID2 RW 0x00 ID2, the transaction will be remapped to this

0x0A Slave ID[2] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 3 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID3 RW 0 ID3, the transaction will be remapped to this

0x0B Slave ID[3] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7-bit Remote Slave Device ID 4 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID4 RW 0 ID4, the transaction will be remapped to this

0x0C Slave ID[4] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 5 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID5 RW 0x00 ID5 , the transaction will be remapped to this

0x0D Slave ID[5] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 6 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID6 RW 0 ID6, the transaction will be remapped to this

0x0E Slave ID[6] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device ID 7 Configures the

physical I2C address of the remote I2C Slave

device attached to the remote serializer. If an

I2C transaction is addressed to the Slave Alias

7:1 Slave ID7 RW 0x00 ID7, the transaction will be remapped to this

0x0F Slave ID[7] address before passing the transaction across

the Bidirectional Control Channel to the

serializer.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 0

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID0 RW 0x00 transaction will be remapped to the address

0x10 Slave Alias[0] specified in the Slave ID0 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 1

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID1 RW 0x00 transaction will be remapped to the address

0x11 Slave Alias[1] specified in the Slave ID1 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

7-bit Remote Slave Device Alias ID 2

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID2 RW 0x00 transaction will be remapped to the address

0x12 Slave Alias[2] specified in the Slave ID2 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 3

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID3 RW 0x00 transaction will be remapped to the address

0x13 Slave Alias[3] specified in the Slave ID3 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 4

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID4 RW 0x00 transaction will be remapped to the address

0x14 Slave Alias[4] specified in the Slave ID4 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 5

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID5 RW 0x00 transaction will be remapped to the address

0x15 Slave Alias[5] specified in the Slave ID5 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 6

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID6 RW 0x00 transaction will be remapped to the address

0x16 Slave Alias[6] specified in the Slave ID6 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

7-bit Remote Slave Device Alias ID 7

Configures the decoder for detecting

transactions designated for an I2C Slave device

attached to the remote serializer. The

7:1 Slave Alias ID7 RW 0x00 transaction will be remapped to the address

0x17 Slave Alias[7] specified in the Slave ID7 register. A value of 0

in this field disables access to the remote I2C

Slave.

0 RSVD Reserved

Parity errors threshold on the Forward channel

during normal information. This sets the

Parity Errors Parity Error

0x18 7:0 RW 0 maximum number of parity errors that can be

Threshold Threshold Byte 0 counted using register 0x1A.

Least significant Byte.

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

Parity errors threshold on the Forward channel

during normal operation. This sets the

Parity Errors Parity Error

0x19 7:0 RW 0 maximum number of parity errors that can be

Threshold Threshold Byte 1 counted using register 0x1B.

Most significant Byte

Number of parity errors in the Forward channel

0x1A Parity Errors 7:0 Parity Error Byte 0 RW 0 during normal operation.

Least significant Byte

Number of parity errors in the Forward channel

0x1B Parity Errors 7:0 Parity Error Byte 1 RW 0 during normal operation

Most significant Byte

Revision ID

7:4 Rev-ID R 0 0x0000: Production

3 RSVD Reserved

Parity Error detected

2 Parity Error R 0 1: Parity Errors detected

0: No Parity Errors

0x1C General Status 0 1: Serial input detected

1 Signal Detect R 0: Serial input not detected

Deserializer CDR, PLL's clock to recovered

clock frequency

0 Lock R 0 1: Deserializer locked to recovered clock

0: Deserializer not locked

0 Local GPIO Output Value This value is the

7 GPIO1 Output Vaue RW output on the GPIO pin when the GPIO function

is enabled, the local GPIO direction is Output.

6 RSVD Reserved

GPIO1 Direction 1 Local GPIO Direction

5 RW 1: Input

GPIO[1] and

0x1D 0: Output

GPIO[0] Config GPIO Function Enable

4 GPIO1 Enable RW 1 1: Enable GPIO operation

0: Enable normal operation

Local GPIO Output Value This value is output

3 GPIO0 Output Value RW 0 on the GPIO pin when the GPIO function is

enabled, the local GPIO direction is Output.

2 RSVD Reserved

Local GPIO Direction

1 GPIO0 Direction RW 1 1: Input

GPIO[1] and

0x1D 0: Output

GPIO[0] Config GPIO Function Enable

0 GPIO0 Enable RW 1 1: Enable GPIO operation

0: Enable normal operation

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

Local GPIO Output Value This value is the

7 GPIO3 Output Vaue RW 0 output on the GPIO pin when the GPIO function

is enabled, the local GPIO direction is Output.

6 RSVD Reserved

Local GPIO Direction

5 GPIO3 Direction RW 1 1: Input

0: Output

GPIO Function Enable

4 GPIO3 Enable RW 1 1: Enable GPIO operation

0: Enable normal operation

GPIO[3] and

0x1E GPIO[2] Config Local GPIO Output Value This value is output

3 GPIO2 Output Value RW 0 on the GPIO pin when the GPIO function is

enabled, the local GPIO direction is Output.

2 RSVD Reserved

Local GPIO Direction

1 GPIO2 Direction RW 1 1: Input

0: Output

GPIO Function Enable

0 GPIO2 Enable RW 1 1: Enable GPIO operation

0: Enable normal operation

Allows overriding OEN and OSS select coming

from Pins

7 OEN_OSS Override RW 0 1: Overrides OEN/OSS_SEL selected by pins

0: Does NOT override OEN/OSS_SEL select

by pins

6 OEN Select RW 0 OEN configuration from register

5 OSS Select R 0 OSS_SEL configuration from register

Allows overriding mode select bits coming from

back-channel

4 MODE_OVERRIDE RW 0 1: Overrides MODE select bits

0: Does not override MODE select bits

PIN_MODE_12–bit Status of mode select pin

Mode and OSS 3 R 0

0x1F HF mode

Select PIN_MODE_10-bit Status of mode select pin

2 R 0

mode

Selects 12-bit high-frequency mode. This bit is

automatically updated by the mode settings

MODE_12–bit High

1 RW 0 from RX unless MODE_OVERRIDE is SET

Frequency 1: 12-bit high-frequency mode is selected.

0: 12-bit high-frequency mode is not selected.

Selects 10-bit mode. This bit is automatically

updated by the mode settings from RX unless

0 MODE_10–bit mode RW 0 MODE_OVERRIDE is SET

1: Enables 10-bit mode.

0: Disables 10-bit mode.

The watchdog timer allows termination of a

control channel transaction if it fails to complete

BCC Watchdog within a programmed amount of time. This field

7:1 RW 0

timer sets the Bidirectional Control Channel

Watchdog Timeout value in units of 2ms. This

BCC Watchdog

0x20 field should not be set to 0.

Control

Disable Bidirectional Control Channel

BCC Watchdog Watchdog Timer

0 RW 0

Timer Disable 1: Disables BCC Watchdog Timer operation

0: Enables BCC Watchdog Timer operation

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

I2C Pass-Through All Transactions

7 I2C pass-through all RW 0 0: Disabled

1: Enabled

Internal SDA Hold Time This field configures

the amount of internal hold time provided for

0x21 I2C Control 1 6:4 I2C SDA Hold RW 0 the SDA input relative to the SCL input. Units

are 50ns.

I2C Glitch Filter Depth This field configures the

3:0 I2C Filter Depth RW 0 maximum width of glitch pulses on the SCL and

SDA inputs that will be rejected. Units are 10ns.

Control Channel Sequence Error Detected This

bit indicates a sequence error has been

detected in forward control channel.

Forward Channel

7 R 0 1: If this bit is set, an error may have occurred

Sequence Error in the control channel operation

0: No forward channel errors have been

detected on the control channel

Clear Sequence Clears the Sequence Error Detect bit

6 RW 0

Error

5 RSVD Reserved

SDA Output Delay This field configures output

delay on the SDA output. Setting this value will

increase output delay in units of 50 ns. Nominal

output delay values for SCL to SDA are:

4:3 SDA Output Delay RW 0 00 : 350ns

01: 400ns

10: 450ns

11: 500ns

Disable Remote Writes to local registers

0x22 I2C Control 2 Setting this bit to a 1 will prevent remote writes

to local device registers from across the control

2 Local Write Disable RW 0 channel. This prevents writes to the deserializer

registers from an I2C master attached to the

serializer. Setting this bit does not affect remote

access to I2C slaves at the deserializer.

Speed up I2C Bus Watchdog Timer

1: Watchdog Timer expires after approximately

I2C Bus Timer

1 RW 0 50 µs

Speed up 0: Watchdog Timer expires after approximately

1 s.

Disable I2C Bus Watchdog Timer When the I2C

Watchdog Timer may be used to detect when

the I2C bus is free or hung up following an

invalid termination of a transaction. If SDA is

I2C Bus Timer

0 RW 0 high and no signaling occurs for approximately

Disable 1 second, the I2C bus will assumed to be free.

If SDA is low and no signaling occurs, the

device will attempt to clear the bus by driving 9

clocks on SCL

General-Purpose Scratch Register

0x23 7:0 GPCR RW 0

Control

7:4 RSVD Reserved

Bist Configured through Pin.

BIST Pin 1: Bist configured through pin.

3 RW 1

Configuration 0: Bist configured through register bit

"reg_24[0]"

0x24 BIST Control BIST Clock Source

2:1 BIST Clock Source RW 00 See Table 10

BIST Control

0 BIST Enable RW 0 1: Enabled

0: Disabled

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Table 8. DS90UB914Q-Q1 Control Registers (continued)

ADDR NAME BITS FIELD R/W DEFAULT DESCRIPTION

(HEX)

Number of Forward channel Parity errors in the

0x25 Parity Error Count 7:0 BIST Error Count R 0 BIST mode.

0x26 - RESERVED

0x3B

7:2 RSVD Reserved

Selects the divider for the OSC clock out on

PCLK when system is not locked and selected

Oscillator output

0x3C OSC OUT DIVIDER by OEN/OSSSEL 0x02[5]

divider select 1:0 RW 0

SEL 00: 50M (± 30%)

01: 25M (± 30%)

1X: 12.5M (± 30%)

0x3D - RESERVED

0x3E

7:5 RSVD Reserved

CML Output 0: CML Loop-through Driver is powered up

0x3F 4 CML OUT Enable RW 1

Enable 1: CML Loop-through Driver is powered down.

3:0 RSVD Reserved

I2C Master SCL High Time This field configures

the high pulse width of the SCL output when

the deserializer is the Master on the local I2C

bus. Units are 50 ns for the nominal oscillator

0x40 SCL High Time 7:0 SCL High Time RW 0x82 clock frequency. The default value is set to

provide a minimum (4μs + 0.3μs of rise time for

cases where rise time is very fast) SCL high

time with the internal oscillator clock running at

26MHz rather than the nominal 20MHz.

I2C SCL Low Time This field configures the low

pulse width of the SCL output when the

deserializer is the Master on the local I2C bus.

This value is also used as the SDA setup time

by the I2C Slave for providing data prior to

releasing SCL during accesses over the

0x41 SCL Low Time 7:0 SCL Low Time RW 0x82 Bidirectional Control Channel. Units are 50 ns

for the nominal oscillator clock frequency. The

default value is set to provide a minimum

(4.7µs + 0.3µs of fall time for cases where fall

time is very fast) SCL low time with the internal

oscillator clock running at 26MHz rather than

the nominal 20MHz.

7:2 RSVD Reserved

1: This bit introduces multiple errors into Back

Force Back Channel

1 RW 0 channel frame.

Error

0x42 CRC Force Error 0: No effect

1: This bit introduces ONLY one error into Back

Force One Back

0 RW 0 channel frame. Self clearing bit

Channel Error 0: No effect

0x43 - RESERVED

0x4C

7 RSVD Reserved

AEQ Test Mode Bypass AEQ and use set manual EQ value

0x4D 6 AEQ Bypass RW 0

Select using register 0x04

5:0 RSVD Reserved

AEQ / Manual Eq Read back the adaptive and manual

0x4E EQ Value 7:0 R 0

Readback Equalization value

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Table 9. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation

DS90UB913Q 10-BIT 12-BIT 12-BIT

REG 0x14 [2:1] MODE HIGH-FREQUENCY MODE LOW-FREQUENCY MODE

00 50 MHz 37.5 MHz 25 MHz

01 100 MHz 75 MHz 50 MHz

10 50 MHz 37.5 MHz 25 MHz

11 25MHz 18.75 MHz 12.5 MHz

Table 10. BIST Clock Sources

DS90UB914Q 10-BIT 12-BIT 12-BIT

REG 0x24 [2:1] MODE HIGH-FREQUENCY MODE LOW-FREQUENCY MODE

00 PCLK PCLK PCLK

01 100 MHz 75 MHz 50 MHz

10 50 MHz 37.5 MHz 25 MHz

11 25MHz 18.75 MHz 12.5 MHz

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FPD-Link III

Bi-Directional

Control Channel

Image

Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

HSYNC,

VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLK

Pixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

ROUT[9:0]

HSYNC,

VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DS90UB914Q

Deserializer

DS90UB913Q

Serializer

GPO[3:0] GPO[3:0]

GPIO[3:0]

Camera Data

DOUT-

DOUT+

RIN-

RIN+

DS90UB913Q-Q1

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11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Applications Information

The serializer and deserializer support only AC-coupled interconnects through an integrated DC-balanced

decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as

illustrated in Figure 45.

Figure 45. AC-Coupled Connection

For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC-coupling

capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/Os require a

100-nF AC-coupling capacitors to the line.

11.2 Typical Application

Figure 46. Application Block Diagram

11.2.1 Design Requirements

11.2.1.1 Transmission Media

The DS90UB91xQ-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted

pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The

interconnect (cable and connectors) should have a differential impedance of 100 Ω. The maximum length of

cable that can be used is dependent on the quality of the cable (gauge, impedance), connector, board

(discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock

jitter, PCLK frequency, and so forth). The resulting signal quality at the receiving end of the transmission media

may be assessed by monitoring the differential eye opening of the serial data stream. A differential probe should

be used to measure across the termination resistor at the CMLOUTP/N pins. Figure 20 illustrates the minimum

eye width and eye height that is necessary for bit error free operation.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

DIN10

DIN11

PCLK

PDB

DOUT+

DOUT-

VDDCML

DAP (GND)

VDDPLL

VDDT

1.8V

DS90UB913Q (SER)

C5 C10

C11

NOTE:

C1 - C2 = 0.1 PF (50 WV)

C3 ± C7 = 0.01 PF

C8 - C12 = 0.1 PF

C13 - C14 = 4.7 PF

C15 = 22 PF

C16 - C17 = >100 pF

RPU = 1 k: to 4.7 k:

RID (see ID[x] Resistor Value Table)

FB1 - FB4: Impedance = 1 k: (@ 100 MHz)

low DC resistance (<1:)

The "Optional" components shown are

provisions to provide higher system noise

immunity and will therefore result in higher

performance.

LVCMOS

Parallel

Bus

Serial

FPD-Link III

Interface

MODE

ID[X]

VDDIO

RES

LVCMOS

Control

Interface

VDDIO

1.8V

RID

10 k:

C13

FB1

FB2

VDDD C7

SCL

VDDIO

C17

RPU

C16

RPU

SDA

I2C

Bus

Interface FB3

FB4

GPO[1]

GPO[0]

GPO

Control

Interface

Optional

GPO[3]

GPO[2]

1.8V

C12

1.8V

C15

C14 1.8V

1.8V

RID

10 k:

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Typical Application (continued)

11.2.1.2 Adaptive Equalizer – Loss Compensation

The adaptive equalizer is designed to compensate for signal degradation due to the differential insertion loss of

the interconnect components. There are limits to the amount of loss that can be compensated – these limits are

defined by the gain curve of the equalizer. In addition, there is an inherent tolerance for loss defined by the delta

between the minimum VDO of the serializer and the input threshold (Vswing) of the deserializer. In order to

determine the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk,

and so forth, need to be taken into consideration. Figure 49 illustrates the maximum allowable interconnect loss

with the adaptive equalizer at its maximum gain setting (914 equalizer gain).

11.2.2 Detailed Design Procedure

Figure 47 shows the typical connection of a DS90UB913Q-Q1 serializer.

Figure 47. DS90UB913Q-Q1 Typical Connection Diagram — Pin Control

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

ROUT0

ROUT1

ROUT2

ROUT3

ROUT4

ROUT5

ROUT6

ROUT7

ROUT8

ROUT9

ROUT10

ROUT11

PDB

DAP (GND)

RIN1+

RIN1-

VDDR

VDDIO3

VDDIO1

VDDIO2

VDDIO

DS90UB914Q (Des)

C10

VDDD

MODE

RES_PIN43

C12

1.8V

Serial

FPD-Link II

Interface

PCLK

LOCK

C14 C17

C15 C19

VDDPLL

VDDCML

VDDSSCG

NOTE:

C1 - C2 = 0.1 PF (50 WV)

C3 - C10 = 0.01 PF

C11 - C16 = 0.1 PF

C17 - C18 = 4.7 PF

C19 = 22 PF

C20 - C21 = >100 pF

RPU = 1 k: to 4.7 k:

RID (see ID[x] Resistor Value Table)

FB1 - FB4: Impedance = 1 k: (@ 100 MHz)

low DC resistance (<1:)

The "Optional" components shown are

provisions to provide higher system noise

immunity and will therefore result in higher

performance.

C3 C11 C18C16

FB1

FB2

SCL

VDDIO

C21

RPU

C20

RPU

SDA

I2C

Bus

Interface FB3

FB4

IDx[0]

1.8V

RID0

10 k:

Optional

LVCMOS

Parallel

Outputs

C13

1.8V

RIN0+

RIN0-

IDx[1]

RID1

10 k:

PASS

1.8V

RMODE

10 k:

1.8V

SEL

OEN

OSS_SEL

BISTEN

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

Typical Application (continued)

Figure 48 shows a typical connection of the DS90UB914Q-Q1 deserializer.

Figure 48. DS90UB914Q-Q1 Typical Connection Diagram — Pin Control

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS \\

200 300 400 500 600 700

SERIAL LINE FREQUENCY (MHz)

EFFECTIVE GAIN (dB)

100

VOD-Vswing Loss

914 Equalizer Gain (dB)

Allowable Interconnect

Loss

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Typical Application (continued)

11.2.3 Application Curve

Figure 49. Adaptive Equalizer – Interconnect Loss Compensation

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

12 Power Supply Recommendations

This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate

power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects

between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal

description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.

In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.

13 Layout

13.1 Layout Guidelines

Printed-circuit-board layout and stack-up for the serializer and deserializer devices should be designed to provide

low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs

and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance

may be greatly improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement

provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven

especially effective at high frequencies, and makes the value and placement of external bypass capacitors less

critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors

may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range.

Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50-µF to 100-µF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with a via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size

reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of

these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple

capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At

high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing

the impedance at high frequency.

Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise

effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin

description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In

some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the

differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential

lines of 100 Ωare typically recommended for differential interconnect. The closely coupled lines help to ensure

that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines

will also radiate less.

Information on the WQFN style package is provided in Texas Instruments' Application Note: AN-1187

(SNOA401).

See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.

• Use 100-Ωcoupled differential pairs

• Use the S, 2S, and 3S rule in spacings

– S = space between the pair

– 2S = space between pairs

– 3S = space to LVCMOS signal

• Minimize the number of Vias

• Use differential connectors when operating above 500Mbps line speed

• Maintain balance of the traces

• Minimize skew within the pair

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS 4— A k Slencul Onening a] ‘k 0,2 mm C:

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

Layout Guidelines (continued)

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas

Instrument web site at: www.ti.com/lvds

13.2 Layout Example

Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste

deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve

board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow

unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 50.

Figure 50. No Pullback WQFN, Single Row Reference Diagram

Figure 50 and Figure 51 PCB layout examples are derived from the layout design of the DS90UB913Q-Q1

Serializer and DS90UB914Q-Q1 Deserializer Evaluation Kit (SNLU110). These graphics and additional layout

description are used to demonstrate both proper routing and proper solder techniques when designing in the

serializer and deserializer.

Table 11. No Pullback WQFN Stencil Aperture Summary for DS90UB913Q-Q1 and DS90UB914Q-Q1

GAP

STENCIL NUMBER OF

PCB I/O PAD PCB PCB DAP STENCIL I/O BETWEEN

PIN DAP DAP

DEVICE MKT DWG SIZE PITCH SIZE APERTURE DAP

COUNT APERTURE APERTURE

(mm) (mm) (mm) (mm) APERTURE

(mm) OPENINGS (Dim A mm)

DS90UB913Q-Q1 32 RTV 0.25 x 0.6 0.5 3.1 x 3.1 0.25 x 0.7 1.4 x 1.4 4 0.2

DS90UB914Q-Q1 48 RHS 0.25 x 0.6 0.5 5.1 x 5.1 0.25 x 0.7 1.1 x 1.1 16 0.2

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DS90UB913Q-Q1

DS90UB914Q-Q1

SNLS420D –JULY 2012–REVISED JULY 2015

www.ti.com

Figure 51. 48-Pin WQFN Stencil Example of Via and Opening Placement

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

l TEXAS INSTRUMENTS

DS90UB913Q-Q1

DS90UB914Q-Q1

www.ti.com

SNLS420D –JULY 2012–REVISED JULY 2015

14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

For related documentation, see the following:

•Absolute Maximum Ratings for Soldering,SNOA549

•AN-1187 Leadless Leadframe Package (LLP), SN0A401

•AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines,SNLA008

•Transmission Line RAPIDESIGNER Operation and Applications Guide,SNLA035

•DS90UB913Q-Q1 Serializer and DS90UB914Q-Q1 Deserializer Evaluation Kit,SNLU110

14.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 12. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

DS90UB913Q-Q1 Click here Click here Click here Click here Click here

DS90UB914Q-Q1 Click here Click here Click here Click here Click here

14.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

14.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: DS90UB913Q-Q1 DS90UB914Q-Q1

I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90UB913QSQ/NOPB ACTIVE WQFN RTV 32 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB913SQ

DS90UB913QSQE/NOPB ACTIVE WQFN RTV 32 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB913SQ

DS90UB913QSQX/NOPB ACTIVE WQFN RTV 32 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB913SQ

DS90UB914QSQ/NOPB ACTIVE WQFN RHS 48 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB914QSQ

DS90UB914QSQE/NOPB ACTIVE WQFN RHS 48 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB914QSQ

DS90UB914QSQX/NOPB ACTIVE WQFN RHS 48 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB914QSQ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS 5:. V.’

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90UB913QSQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

DS90UB913QSQE/NOPB WQFN RTV 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

DS90UB913QSQX/NOPB WQFN RTV 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

DS90UB914QSQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

DS90UB914QSQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

DS90UB914QSQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90UB913QSQ/NOPB WQFN RTV 32 1000 208.0 191.0 35.0

DS90UB913QSQE/NOPB WQFN RTV 32 250 208.0 191.0 35.0

DS90UB913QSQX/NOPB WQFN RTV 32 4500 356.0 356.0 35.0

DS90UB914QSQ/NOPB WQFN RHS 48 1000 356.0 356.0 35.0

DS90UB914QSQE/NOPB WQFN RHS 48 250 208.0 191.0 35.0

DS90UB914QSQX/NOPB WQFN RHS 48 2500 356.0 356.0 35.0

Pack Materials-Page 2

‘ El ‘ DK 9‘ t ‘ ﬂ wuuumuuw 7,1} \ I: :I i I: :I ‘ I: e j \ I: 3* ”*f’””i D L j i C ,7} ‘ I: T57} \ I: ‘ D gﬂﬂmﬂﬂﬂﬂ T u a f 93%

www.ti.com

PACKAGE OUTLINE

5.15

4.85

5.15

4.85

0.8

0.7

0.05

0.00

2X 3.5

28X 0.5

2X 3.5

32X 0.5

0.3

32X 0.30

0.18

3.1 0.1

(0.1) TYP

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/B 04/2019

0.08 C

0.1 C A B

0.05

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMM

EXPOSED

THERMAL PAD

SYMM

916

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

28X (0.5)

(1.3)

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

32X (0.6)

32X (0.24)

(4.8)

(3.1)

( 0.2) TYP

VIA

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/B 04/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SEE SOLDER MASK

DETAIL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

916

METAL EDGE

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS

$61819 ‘ i A T” w i i i 86%

www.ti.com

EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.24)

28X (0.5)

(4.8)

(0.775) TYP

4X (1.35)

(R0.05) TYP

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/B 04/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 33

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

916

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

DS90UB913,914Q Datasheet by Texas Instruments

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