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INSTRUMENTS
DS90UB913Q-Q1
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DS90UB914Q-Q1
www.ti.com
SNLS420D –JULY 2012–REVISED JULY 2015
DS90UB913Q-Q1 Serializer Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
GENERAL-PURPOSE OUTPUT (GPO)
General-purpose output pins can be configured as outputs; used to control and respond
Output, to various commands. GPO[0:1] can be configured to be the outputs for input signals
GPO[1:0] 16, 15 LVCMOS coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of
the local register on the serializer.
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the deserializer or can be configured to be the output of the local register on the
GPO[2]/ Output, serializer. It can also be configured to be the output clock pin when the DS90UB913Q-
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CLKOUT LVCMOS Q1 device is used in the External Oscillator mode. See Applications Information for a
detailed description of the DS90UB91xQ-Q1 chipsets working with the external
oscillator.
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the deserializer or can be configured to be the output of the local register setting on
GPO[3]/ Input/Output, the serializer. It can also be configured to be the input clock pin when the
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CLKIN LVCMOS DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working
with an external oscillator.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 4 Open-Drain SCL requires an external pullup resistor to VDDIO.
Input/Output, Data line for the bidirectional control bus communication
SDA 5 Open-Drain SDA requires an external pullup resistor to VDDIO.
Device mode select
Input, LVCMOS Resistor to Ground and 10-kΩpullup to 1.8-V rail. MODE pin on the serializer can be
MODE 8 with pulldown used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 3.
Device ID address select
ID[x] 6 Input, analog The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to
Ground and 10-kΩpullup to 1.8-V rail. See Table 1.
CONTROL AND CONFIGURATION
Power down Mode Input Pin
PDB = H, serializer is enabled and is ON.
Input, LVCMOS
PDB 9 PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the
with pulldown PLL is shutdown, and IDD is minimized. Programmed control register data are NOT
retained and reset to default values
Input, LVCMOS Reserved
RES 7 with pulldown This pin MUST be tied LOW.
FPD-Link III INTERFACE
Input/Output, Noninverting differential output, bidirectional control channel input. The interconnect
DOUT+ 13 CML must be AC-coupled with a 100-nF capacitor.
Input/Output, Inverting differential output, bidirectional control channel input. The interconnect must be
DOUT– 12 CML AC-coupled with a 100-nF capacitor.
POWER AND GROUND
VDDPLL 10 Power, Analog PLL Power, 1.8 V ±5%
VDDT 11 Power, Analog Tx Analog Power, 1.8 V ±5%
VDDCML 14 Power, Analog CML and bidirectional channel driver power, 1.8 V ±5%
VDDD 28 Power, Digital Digital power, 1.8 V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO 25 Power, Digital VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS DAP Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least 9
vias.
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