SI1869DH ~ Datasheet by Vishay Siliconix

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Vishay Siliconix
Si1869DH
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
www.vishay.com
1
Load Switch with Level-Shift
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
TrenchFET® Power MOSFETs: 1.8 V Rated
ESD Protected: 2000 V On Input Switch,
VON/OFF
165 m: Low RDS(on)
1.8 to 20 V Input
1.5 to 8 V Logic Level Control
Low Profile, Small Footprint SC70-6 Package
Adjustable Slew-Rate
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
Level Shift for Portable Devices
DESCRIPTION
The Si1869DH includes a p- and n-channel MOSFET in a
single SC70-6 package. The low on-resistance p-channel
TrenchFET is tailored for use as a load switch. The
n-channel, with an external resistor, can be used as a level-
shift to drive the p-channel load-switch. The n-channel
MOSFET has internal ESD protection and can be driven by
logic signals as low as 1.5 V. The Si1869DH operates on
supply lines from 1.8 V to 20 V, and can drive loads up to
1.2 A.
PRODUCT SUMMARY
VDS2 (V) RDS(on) (:)I
D (A)
1.8 to 20
0.165 at VIN = 4.5 V ± 1.2
0.222 at VIN = 2.5 V ± 1.0
0.303 at VIN = 1.8 V ± 0.7
APPLICATION CIRCUITS
VOUT
GND
LOAD
VIN
ON/OFF
R2
R2
1
2, 3
C1
6
4
6
5
R1
Q1
Q2
Si1869DH
Co
Ci
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 k:
0
5
10
15
20
25
30
35
40
0246810
R2 (kΩ)
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
trtd(on)
td(off)
tf
(Time μs)
Note: For R2 switching variations with other VIN/R1
combinations see Typical Characteristics
* Minimum R1 value should be at least 10 x R2 to ensure Q1 turn-on.
The Si1869DH is ideally suited for high-side load switching in
portable applications. The integrated n-channel level-shift
device saves space by reducing external components. The
slew rate is set externally so that rise-times can be tailored to
different load types.
COMPONENTS
R1 Pull-Up Resistor Typical 10 k: to 1 M:*
R2 Optional Slew-Rate Control Typical 0 to 100 k:*
C1 Optional Slew-Rate Control Typical 1000 pF
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Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
Vishay Siliconix
Si1869DH
FUNCTIONAL BLOCK DIAGRAM
Notes:
a. Surface mounted on FR4 board.
b. VIN = 20 V, VON/OFF = 8 V, TA = 25 °C.
c. Pulse test: pulse width d 300 μs, duty cycle d 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Marking Code
VC XX
Lot T raceability
and Date Code
Part # Code
YY
SC
70-6
Top View
6
4
1
2
3
5
S2
ON/OFF
R1, C1
D2
D2
R2
Ordering Information: Si1869DH-T1-E3 (Lead (Pb)-free)
Si1869DH-T1-GE3 (Lead (Pb)-free and Halogen-free)
D2
S2
ON/OFF
R21
4
6
5Q1
Q2
Si1869DH
R1,
C1
2, 3
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage (D2-S2) VDS - 20
VInput Voltage VIN 20
ON/OFF Voltage VON/OFF 8
Load Current Continuousa, b
IL
± 1.2
APulsedb, c ± 3
Continuous Intrinsic Diode ConductionaIS- 0.4
Maximum Power DissipationaPD1.0 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
ESD Rating, MIL-STD-883D Human Body Model (100 pF, 1500 :)ESD 2kV
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient (Continuous Current)aRthJA 100 125 °C/W
Maximum Junction-to-Foot (Q2) RthJF 44 55
SPECIFICATIONS TJ = 25 °C unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
OFF Characteristics
Reverse Leakage Current IFL VIN = 8 V, VON/OFF = 0 V 1 μA
Diode Forward Voltage VSD IS = - 0.4 A 0.4 0.6 1.1 V
ON Characteristics
Input Voltage Range VIN 1.8 20 V
Drain to Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 μA - 20
On-Resistance (P-Channel) at 1 A RDS(on)
VON/OFF = 1.5 V, VIN = 4.5 V, ID = 1.2 A 0.132 0.165
:VON/OFF = 1.5 V, VIN = 2.5 V, ID = 1.0 A 0.177 0.222
VON/OFF = 1.5 V, VIN = 1.8 V, ID = 0.7 A 0.242 0.303
On-State (P-Channel) Drain-Current ID(on)
VIN-OUT d 0.2 V, VIN = 5 V, VON/OFF = 1.5 V 1 A
VIN-OUT d 0.3 V, VIN = 3 V, VON/OFF = 1.5 V 1
— VISHAYE V // \\
Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
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Vishay Siliconix
Si1869DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
VDROP vs. IL at VIN = 4.5 V
VDROP vs. IL at VIN = 1.8 V
VDROP Variance vs. Junction Temperature
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IL (A)
(V)VDROP
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
IL (A)
(V)VDROP
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
- 0.10
- 0.06
- 0.02
0.02
0.06
0.10
- 50 - 25 0 25 50 75 100 125 150
TJ- Junction Temperature (°C)
Variance (V)
VDROP
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
VIN = 4.5 V
VIN = 1.8 V
VDROP vs. IL at VIN = 2.5 V
VDROP vs. VIN at IL = 0.7 A
On-Resistance vs. Input Voltage
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0 0.5 1.0 1.5 2.0 2.5
IL (A)
(V)VDROP
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
0.0
0.1
0.2
0.3
0.4
0.5
0123456
VIN (V)
(V)VDROP
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
0.0
0.1
0.2
0.3
0.4
0.5
0123456
- On-Resistance (Ω)
RSS(on)
VIN (V)
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
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Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
Vishay Siliconix
Si1869DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized On-Resistance
vs. Junction Temperature
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 k:
Switching Variation
R2 at VIN = 4.5 V, R1 = 300 k:
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
TJ- Junction Temperature (°C)
IL = 0.7 A
VON/OFF = 1.5 V to 8 V
VIN = 1.8 V
VIN = 4.5 V
RDS(on) - On-Resistance
(Normalized)
0
5
10
15
20
25
30
35
40
0246810
R2 (kΩ)
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
(Time μs)
trtd(on)
td(off)
tf
0
50
100
150
200
250
0 20406080100
R2 (kΩ)
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
(Time μs)
td(on)
tr
td(off)
tf
Switching Variation
R2 at VIN = 4.5 V, R1 = 20 k:
Switching Variation
R2 at VIN = 1.8 V, R1 = 20 k:
Switching Variation
R2 at VIN = 2.5 V, R1 = 300 k:
R2 (kΩ)
(Time
tr
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
tf
td(on)
td(off)
μs)
0
4
8
12
16
20
0246810
0
20
40
60
80
100
0246810
R2 (kΩ)
(Time μs)
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
td(on)
tr
tf
td(off)
0
50
100
150
200
0 20 40 60 80 100
R2 (kΩ)
(Time μs)
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 μF
C
o
= 1 μF
tf
td(off)
tr
td(on)
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Document Number: 73449
S10-0792-Rev. C, 05-Apr-10
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Vishay Siliconix
Si1869DH
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73449.
Switching Variation
R2 at VIN = 1.8 V, R1 = 300 k:
0
50
100
150
200
020406080100
R2 (kΩ)
(Time μs)
IL = 1 A
VON/OFF = 3 V
Ci = 10 μF
Co = 1 μF
tf
td(off)
tr
td(on)
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 00601110-1
10-4 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 100 °C/W
3. TJM - T
A = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
Normalized Thermal Transient Impedance, Junction-to-Foot
10-3 10-2 01110-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
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L
c
E
E1
e
D
e1
A2A
A1
1
-A-
b
-B-
23
654
Package Information
Vishay Siliconix
Document Number: 71154
06-Jul-01 www.vishay.com
1

 
Dim Min Nom Max Min Nom Max
A0.90 1.10 0.035 0.043
A1 0.10 0.004
A20.80 1.00 0.031 0.039
b0.15 0.30 0.006 0.012
c0.10 0.25 0.004 0.010
D1.80 2.00 2.20 0.071 0.079 0.087
E1.80 2.10 2.40 0.071 0.083 0.094
E11.15 1.25 1.35 0.045 0.049 0.053
e0.65BSC 0.026BSC
e11.20 1.30 1.40 0.047 0.051 0.055
L0.10 0.20 0.30 0.004 0.008 0.012
7_Nom 7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
VISHAY
AN816
Vishay Siliconix
Document Number: 71405
12-Dec-03
www.vishay.com
1
Dual-Channel LITTLE FOOTR 6-Pin SC-70 MOSFET
Copper Leadframe Version
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
The new dual 6-pin SC-70 package with a copper leadframe
enables improved on-resistance values and enhanced
thermal performance as compared to the existing 3-pin and
6-pin packages with Alloy 42 leadframes. These devices are
intended for small to medium load applications where a
miniaturized package is required. Devices in this package
come in a range of on-resistance values, in n-channel and
p-channel versions. This technical note discusses pin-outs,
package outlines, pad patterns, evaluation board layout, and
thermal performance for the dual-channel version.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
Both n-and p-channel devices are available in this package –
the drawing example below illustrates the p-channel device.
FIGURE 1.
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
S1
G1
D2
D1
G2
S2
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the SC-70
6-pin basic pad layout and dimensions. This pad pattern is
sufficient for the low-power applications for which this package
is intended. Increasing the drain pad pattern (Figure 2) yields
a reduction in thermal resistance and is a preferred footprint.
FIGURE 2. SC-70 (6 leads) Dual
48 (mil)
16 (mil)
654
321
61 (mil)
26 (mil)
8 (mil)
0.0 (mil)
23 (mil)
71 (mil)
96 (mil)
26 (mil)
87 (mil)
EVALUATION BOARD FOR THE DUAL-
CHANNEL SC70-6
The 6-pin SC-70 evaluation board (EVB) shown in Figure 3
measures 0.6 in. by 0.5 in. The copper pad traces are the same
as described in the previous section, Basic Pad Patterns. The
board allows for examination from the outer pins to the 6-pin
DIP connections, permitting test sockets to be used in
evaluation testing.
The thermal performance of the dual 6-pin SC-70 has been
measured on the EVB, comparing both the copper and Alloy
42 leadframes. This test was then repeated using the 1-inch2
PCB with dual-side copper coating.
A helpful way of displaying the thermal performance of the
6-pin SC-70 dual copper leadframe is to compare it to the
traditional Alloy 42 version.
— VISHAY \y In Uishag Siliconix O I c: O O a m 0 O Rn R“ 150 C , 25 c M 224°C/W 224°C/W 1) Mwmmum recommended pad pauem an 2) mausuy s|andavd 17mm PCB wnh RU 150 c , 25 c Anzac/w RI» 150 C , so 0 mane/w
AN816
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Document Number: 71405
12-Dec-03
FIGURE 3.
Front of Board SC70-6 Back of Board SC70-6
D1
G2
S2
S1
G1
D2
SC70ï6 DUAL vishay.com
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package is
measured as junction-to-foot thermal resistance, in which the
“foot” is the drain lead of the device as it connects with the
body. The junction-to-foot thermal resistance for this device is
typically 80_C/W, with a maximum thermal resistance of
approximately 100_C/W. This data compares favorably with
another compact, dual-channel package – the dual TSOP-6 –
which features a typical thermal resistance of 75_C/W and a
maximum of 90_C/W.
Power Dissipation
The typical RTJA for the dual-channel 6-pin SC-70 with a
copper leadframe is 224_C/W steady-state, compared to
413_C/W for the Alloy 42 version. All figures are based on the
1-inch2 FR4 test board. The following example shows how the
thermal resistance impacts power dissipation for the dual 6-pin
SC-70 package at varying ambient temperatures.
Alloy 42 Leadframe
ALLOY 42 LEADFRAME
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
413oCńW
PD+303 mW
PD+TJ(max) *TA
RqJA
PD+150oC*60oC
413oCńW
PD+218 mW
COOPER LEADFRAME
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
224oCńW
PD+558 mW
PD+TJ(max) *TA
RqJA
PD+150oC*60oC
224oCńW
PD+402 mW
Although they are intended for low-power applications,
devices in the 6-pin SC-70 dual-channel configuration will
handle power dissipation in excess of 0.5 W.
TESTING
To further aid the comparison of copper and Alloy 42
leadframes, Figures 4 and 5 illustrate the dual-channel 6-pin
SC-70 thermal performance on two different board sizes and
pad patterns. The measured steady-state values of RTJA for
the dual 6-pin SC-70 with varying leadframes are as follows:
LITTLE FOOT 6-PIN SC-70
Alloy 42 Copper
1) Minimum recommended pad pattern on
the EVB board (see Figure 3). 518_C/W 344_C/W
2) Industry standard 1-inch2 PCB with
maximum copper both sides. 413_C/W 224_C/W
The results indicate that designers can reduce thermal
resistance (TJA) by 34% simply by using the copper leadframe
device as opposed to the Alloy 42 version. In this example, a
174_C/W reduction was achieved without an increase in board
area. If an increase in board size is feasible, a further 120_C/W
reduction can be obtained by utilizing a 1-inch2. PCB area.
The Dual copper leadframe versions have the following suffix:
Dual: Si19xxEDH
Compl.: Si15xxEDH
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Time (Secs)
FIGURE 4. Dual SC70-6 Thermal Performance on EVB
Thermal Resistance (C/W)
0
1
500
100
200
100 1000
300
1010-1
10-2
10-3
10-4
10-5
Alloy 42
400
Time (Secs)
FIGURE 5. Dual SC70-6 Comparison on 1-inch2 PCB
Thermal Resistance (C/W)
0
1
500
100
200
100 1000
300
1010-1
10-2
10-3
10-4
10-5
400
Copper
Copper
Alloy
42
VISHAY»
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72602
18 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.096
(2.438)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.067
(1.702)
0.026
(0.648)
0.045
(1.143)
0.016
(0.406)
0.026
(0.648)
0.010
(0.241)
Return to Index
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Revision: 08-Feb-17 1Document Number: 91000
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