Z8 Encore! XP 64K Series Datasheet by Zilog

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zilog
Product Specification
High Performance 8-Bit Microcontrollers
Z8 Encore! XP® 64K Series
Flash Microcontrollers
PS019919-1207
Copyright ©2007 by Zilog®, Inc. All rights reserved.
www.zilog.com
ANflB ADDIEDI’TED ISO 9001:2000 FS 507510 Zilog products are designed and manue factured under an ISO registered 9001:2000 Quality Management System. For more details, ptease visit www‘zilog.com/qua|ity.
PS019919-1207
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2007 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
Warning:
PS019919-1207
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
iii
Revision History
Each instance in the Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages or appropriate links given in
the table below.
Date
Revision
Level Description
Page
No
December
2007
19 Updated Zilog logo, Disclaimer section, and implemented
style guide. Updated Table 112. Changed Z8 Encore! 64K
Series to Z8 Encore! XP 64K Series Flash
Microcontrollers throughout the document.
All
December
2006
18 Updated Table 110 and Ordering Information.228,
270
November
2006
17 Updated Part Number Suffix Designations. 275
June 2006 16 Updated Timer 0-3 Control 1 Registers. 94
October
2005
15 The paragraph tag for Ordering Information has been
changed from H1 Heading to Chapter Title.
270
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Product Specification
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Table of Contents
Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xii
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xii
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xii
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Stop Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . . 52
Stop Mode Recovery Using a GPIO Port Pin Transition HALT . . . . . . . . . . 53
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A–H Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A–H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Port A–H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port A–H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 74
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Port Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 91
Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 92
Timer 0-3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Timer 0-3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . 99
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 100
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . 101
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UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . 105
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . 106
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . 107
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . 108
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . 117
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 120
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . 128
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 142
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . 148
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . 150
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 160
I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DMA0 and DMA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . . . . . . . . . 166
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DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . 167
DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
DMAx Address High Nibble Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . . . . . . . . . 170
DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . 186
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . 189
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 192
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Flash Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Flash Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 209
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . 213
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . 226
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
General-Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . 232
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General-Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 233
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . 241
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
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Product Specification
xii
Manual Objectives
This Product Specification provides detailed operating information for the Flash devices
within Zilog’s Z8 Encore! XP® 64K Series Flash Microcontrollers Microcontroller
(MCU) products. Within this document, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, and
Z8F162x devices are referred to collectively as the Z8 Encore! XP® 64K Series Flash
Microcontrollers unless specifically stated otherwise.
About This Manual
Zilog® recommends that you read and understand everything in this manual before setting
up and using the product. However, we recognize that there are different styles of learning.
Therefore, we have designed this Product Specification to be used either as a how to
procedural manual or a reference guide to important data.
Intended Audience
This document is written for Zilog customers who are experienced at working with micro-
controllers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Courier typeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is
presented in upper case.
Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
Example: R1 is set to F8H.
Brackets
The square brackets, [ ], indicate a register or bus.
Example: For the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant
bit, and R1[0] is the least significant bit.
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Product Specification
xiii
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some
combination of smaller registers, buses, or individual bits.
Example: The 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0H is the most-significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
Example: Assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the
contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical may not be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least
significant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings and conditions in general text.
Example 1: The receiver forces the SCL line to Low.
Example 2: The Master can generate a Stop condition to abort the transfer.
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PS019919-1207 Manual Objectives
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Product Specification
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Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization sequence.
Example 3: STOP mode.
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that you understand the following safety terms, which are defined here.
Indicates a procedure or file may become corrupted if you do not follow
directions.
Caution:
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PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
1
Introduction
Zilog’s Z8 Encore! XP MCU family of products are a line of Zilog® microcontroller
products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP® 64K Series Flash
Microcontrollers, hereafter referred to collectively as the Z8 Encore! XP or the 64K Series
adds Flash memory to Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit
programming capability allows for faster development time and program changes in the
field. The new eZ8 CPU is upward compatible with existing Z8® instructions. The rich-
peripheral set of the Z8 Encore! XP makes it suitable for a variety of applications
including motor control, security systems, home appliances, personal electronic devices,
and sensors.
Features
The features of Z8 Encore! XP 64K Series Flash Microcontrollers include:
20 MHz eZ8 CPU
Up to 64 KB Flash with in-circuit programming capability
Up to 4 KB register RAM
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
Inter-integrated circuit (I2C)
Serial Peripheral Interface (SPI)
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Up to four 16-bit timers with capture, compare, and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
Three-channel DMA
Up to 60 input/output (I/O) pins
24 interrupts with configurable priority
On-Chip Debugger
Voltage Brownout (VBO) Protection
Power-On Reset (POR)
Operating voltage of 3.0 V to 3.6 V with 5 V-tolerant inputs
0 °C to +70 °C, –40 °C to +105 °C, and –40 °C to +125 °C operating temperature
ranges
PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
2
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP product line.
Table 1. Z8 Encore! XP 64K Series Flash Microcontrollers Part Selection Guide
Part
Number
Flash
(KB)
RAM
(KB) I/O
16-bit
Timers
with PWM
ADC
Inputs
UARTs
with IrDA I2CSPI
40/44-pin
packages
64/68-pin
packages
80-pin
package
Z8F1621 16 2 31 3 8 2 1 1 X
Z8F1622 16 2 46 4 12 2 1 1 X
Z8F2421 24 2 31 3 8 2 1 1 X
Z8F2422 24 2 46 4 12 2 1 1 X
Z8F3221 32 2 31 3 8 2 1 1 X
Z8F3222 32 2 46 4 12 2 1 1 X
Z8F4821 48 4 31 3 8 2 1 1 X
Z8F4822 48 4 46 4 12 2 1 1 X
Z8F4823 48 4 60 4 12 2 1 1 X
Z8F6421 64 4 31 3 8 2 1 1 X
Z8F6422 64 4 46 4 12 2 1 1 X
Z8F6423 64 4 60 4 12 2 1 1 X
Die Form
Sales
Contact
Zilog®
H
PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
3
Block Diagram
Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP 64K Series
Flash Microcontrollers.
Figure 1. Z8 Encore! XP 64K Series Flash Microcontrollers Block Diagram
CPU and Peripheral Overview
eZ8 CPU Features
The latest 8-bit eZ8 CPU meets the continuing demand for faster and more code-efficient
microcontrollers. The eZ8 CPU executes a superset of the original Z8® instruction set.
GPIO
IrDA
UARTs I
2
CTimers SPI ADC Flash
Controller
RAM
RAM
Controller
Flash
Interrupt
Controller
On-Chip
Debugger
eZ8
TM
CPU WDT with
RC Oscillator
POR/VBO
and Reset
Controller
XTAL/RC
Oscillator
Register Bus
Memory Busses
System
Clock
DMA
Memory
zilog www.2ilog.com
PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
4
The eZ8 CPU features include:
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required Program Memory
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information on the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128)
available for download at www.zilog.com.
General-Purpose Input/Output
The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for
general-purpose input/output (GPIO). Each pin is individually programmable. All ports
(except B and H) support 5 V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter converts an analog input signal to a 10-bit binary
number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.
zilog RESET
PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
5
I2C
The I2C controller makes the Z8 Encore! XP compatible with the I2C protocol. The I2C
controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock
(SCL) line.
Serial Peripheral Interface
The serial peripheral interface allows the Z8 Encore! XP to exchange data between other
peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a
full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and
operate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and
PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.
Interrupt Controller
The 64K Series products support up to 24 interrupts. These interrupts consist of 12
internal and 12 GPIO pins. The interrupts have 3 levels of programmable interrupt
priority.
Reset Controller
The Z8 Encore! can be reset using the RESET pin, Power-On Reset, Watchdog Timer,
STOP mode exit, or Voltage Brownout (VBO) warning signal.
On-Chip Debugger
The Z8 Encore! XP features an integrated On-Chip Debugger. The OCD provides a rich
set of debugging capabilities, such as reading and writing registers, programming the
Flash, setting breakpoints and executing code. A single-pin interface provides
communication to the OCD.
DMA Controller
The 64K Series features three channels of DMA. Two of the channels are for register
RAM to and from I/O operations. The third channel automatically controls the transfer of
data from the ADC to the memory.
zilog‘
PS019919-1207 Introduction
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
6
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
7
Signal and Pin Descriptions
Overview
The Z8 Encore! XP 64K Series Flash Microcontrollers product are available in a variety of
packages styles and pin configurations. This chapter describes the signals and available
pin configurations for each of the package styles. For information on physical package
specifications, see Packaging on page 265.
Available Packages
Table 2 identifies the package styles that are available for each device within the
Z8 Encore! XP 64K Series Flash Microcontrollers product line.
Table 2. Z8 Encore! XP 64K Series Flash Microcontrollers Package Options
Part Number
40-Pin
PDIP
44-pin
LQFP
44-pin
PLCC
64-pin
LQFP
68-pin
PLCC
80-pin
QFP
Z8F1621 X X X
Z8F1622 X X
Z8F2421 X X X
Z8F2422 X X
Z8F3221 X X X
Z8F3222 X X
Z8F4821 X X X
Z8F4822 X X
Z8F4823 X
Z8F6421 X X X
Z8F6422 X X
Z8F6423 X
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
8
Pin Configurations
Figure 2 through Figure 7 on page 13 display the pin configurations for all of the packages
available in the Z8 Encore! XP 64K Series Flash Microcontrollers. For description of the
signals, see Table 3 on page 14. Timer 3 is not available in the 40-pin and 44-pin pack-
ages.
Figure 2. Z8 Encore! XP 64K Series Flash Microcontrollers in 40-Pin Dual Inline Package (PDIP)
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
PD4/RXD1
PD3 / DE1
PC5 / MISO
PA3 / CTS0
PA2/DE0
PA1 /T0OUT
PA0 / T0IN
PC2 / SS
140
VDD
RESET
PC6 / T2IN *
DBG
PC1 / T1OUT
VSS
PD1
PD0
PC0 / T1INXOUT
AVSSXIN
VREFAVDD
PB2 / ANA2
PB3 / ANA3
PB7 / ANA7
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
20 21 PB6 / ANA6PB5 / ANA5
5
10
15
35
30
25
VDD
* T2OUT is not supported.
Note: Timer 3 is not supported.
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
9
Figure 3. Z8 Encore! XP 64K Series Flash Microcontrollers in 44-Pin Plastic Leaded Chip Carrier
(PLCC)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
VDD
VSS
PC7 / T2OUT
PC6 / T2IN
DBG
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
VSS
VDD
PD1
PD0
739
PC1 / T1OUT
XOUT
PC0 / T1IN
XIN
PA1 / T0OUT
PA2 / DE0
PA3 / CTS0
PC5 / MISO
PD3 / DE1
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
AVDD
PB6 / ANA6
PB5 / ANA5
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB7 / ANA7
VREF
PB2 / ANA2
PB3 / ANA3
AVSS
6401
17 29
2818
12
23
34
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
10
Figure 4. Z8 Encore! XP 64K Series Flash Microcontrollers in 44-Pin Low-Profile Quad Flat Package
(LQFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
VDD
VSS
PC7 / T2OUT
PC6 / T2IN
DBG
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
VSS
VDD
PD1
PD0
34 22
PC1 / T1OUT
XOUT
PC0 / T1IN
XIN
PA1 / T0OUT
PA2 / DE0
PA3 / CTS0
PC5 / MISO
PD3 / DE1
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
AVDD
PB6 / ANA6
PB5 / ANA5
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB7 / ANA7
VREF
PB2 / ANA2
PB3 / ANA3
AVSS
33 23
44 12
111
28
39 17
6
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
11
Figure 5. Z8 Encore! XP 64K Series Flash Microcontrollers in 64-Pin Low-Profile Quad Flat Package
(LQFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
PE7
VDD
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
PE4
PE3
VSS
PE2
49 32
PG3PE1
VDD
PE0
PA1 / T0OUT
PA2 / DE0
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PH1 / ANA9
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
48
1
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
17
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
16
VSS
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN 64
PD3 / DE1
VDD
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
33
VSS
56
40
25
8
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
12
Figure 6. Z8 Encore! XP 64K Series Flash Microcontrollers in 68-Pin Plastic Leaded Chip Carrier
(PLCC)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
VSS
PE5
PE6
PE7
VDD
PA0 / T0IN
PD2
PC2 / SS
RESET
VDD
PE4
PE3
VSS
PE2
10 60
PG3PE1
VDD
PE0
PA1 / T0OUT
PA2 / DE0
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
9
27
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
VSS
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
PD3 / DE1
VSS
PA4 / RXD0
PA5 / TXD0
VDD
PH1 / ANA9
PA6 / SCL
61
VSS
44
AVSS
43
XIN 26
1
VDD
18
35
52
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
13
Figure 7. Z8 Encore! XP 64K Series Flash Microcontrollers in 80-Pin Quad Flat Package (QFP)
PA7 / SDA
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
PG0
VSS
PG1
PG2
PE5
PA0 / T0IN
PD2
PC2 / SS
PF6
RESET
VDD
PF5
PF4
PF3
164
PE6PE4
PE7
PE3
PA1 / T0OUT
PA2 / DE0
PA3 / CTS0
VSS
VDD
PF7
PC5 / MISO
PD4 / RXD1
PD5 / TXD1
PC4 / MOSI
VSS
PB1 / ANA1
PB0 / ANA0
AVDD
PH0 / ANA8
PB4 / ANA4
PB7 / ANA7
PB6 / ANA6
PB5 / ANA5
PB3 / ANA3
80
25
VDD
PG3
PG4
PG5
PG6
PB2 / ANA2
VREF
PH3 / ANA11
PH2 / ANA10
AVSS
VSS
PE2
PE1
PE0
VSS
PD3 / DE1
VDD
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
VSS
PH1 / ANA9
65
VDD
40
PF2
PG7
PF1
PC7 / T2OUT
PC6 / T2IN
DBG
PC1 / T1OUT
PC0 / T1IN
PF0
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
VSS
41
XIN 24
5
10
15
20
30 35
45
50
55
60
70
75
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
14
Signal Descriptions
Table 3 describes the Z8 Encore! XP signals. To determine the signals available for the
specific package styles, see Pin Configurations on page 8.
Table 3. Signal Descriptions
Signal
Mnemonic I/O Description
General-Purpose I/O Ports A-H
PA[7:0] I/O Port A[7:0]. These pins are used for general-purpose I/O and support
5 V-tolerant inputs.
PB[7:0] I/O Port B[7:0]. These pins are used for general-purpose I/O.
PC[7:0] I/O Port C[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs
PD[7:0] I/O Port D[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs
PE[7:0] I/O Port E[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PF[7:0] I/O Port F[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PG[7:0] I/O Port G[7:0]. These pins are used for general-purpose I/O. These pins are
used for general-purpose I/O and support 5 V-tolerant inputs.
PH[3:0] I/O Port H[3:0]. These pins are used for general-purpose I/O.
I2C Controller
SCL O Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA I/O Serial Data. This open-drain pin transfers data between the I2C and a slave.
This pin is multiplexed with a general-purpose I/O pin. When the
general-purpose I/O pin is configured for alternate function to enable the
SDA function, this pin is open-drain.
SPI Controller
SS I/O Slave Select. This signal can be an output or an input. If the Z8 Encore! XP
64K Series Flash Microcontrollers is the SPI master, this pin may be
configured as the Slave Select output. If the Z8 Encore! XP 64K Series Flash
Microcontrollers is the SPI slave, this pin is the input slave select. It is
multiplexed with a general-purpose I/O pin.
CTS
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
15
SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! XP 64K
Series Flash Microcontrollers is the SPI master, this pin is an output. If the Z8
Encore! XP 64K Series Flash Microcontrollers is the SPI slave, this pin is an
input. It is multiplexed with a general-purpose I/O pin.
MOSI I/O Master-Out/Slave-In. This signal is the data output from the SPI master
device and the data input to the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
MISO I/O Master-In/Slave-Out. This pin is the data input to the SPI master device and
the data output from the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
UART Controllers
TXD0 / TXD1 OTransmit Data. These signals are the transmit outputs from the UARTs. The
TXD signals are multiplexed with general-purpose I/O pins.
RXD0 / RXD1 IReceive Data. These signals are the receiver inputs for the UARTs and
IrDAs. The RXD signals are multiplexed with general-purpose I/O pins.
CTS0 / CTS1 IClear To Send. These signals are control inputs for the UARTs. The CTS
signals are multiplexed with general-purpose I/O pins.
DE0 / DE1 ODriver Enable. This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the Transmit Empty (TXE)
bit in the UART Status 0 register. The DE signal may be used to ensure an
external RS-485 driver is enabled when data is transmitted by the UART.
Timers
T0OUT/T1OUT/
T2OUT/T3OUT
OTimer Output 0-3. These signals are output pins from the timers. The Timer
Output signals are multiplexed with general-purpose I/O pins. T3OUT is not
available in 44-pin package devices.
T0IN/T1IN/
T2IN/T3IN
ITimer Input 0-3. These signals are used as the capture, gating and counter
inputs. The Timer Input signals are multiplexed with general-purpose I/O
pins. T3IN is not available in 44-pin package devices.
Analog
ANA[11:0] IAnalog Input. These signals are inputs to the ADC. The ADC analog inputs
are multiplexed with general-purpose I/O pins.
VREF IAnalog-to-Digital converter reference voltage input. The VREF pin must be
left unconnected (or capacitively coupled to analog ground) if the internal
voltage reference is selected as the ADC reference voltage.
Oscillators
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic I/O Description
RESET
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
16
Pin Characteristics
Table 4 on page 17 provides detailed information on the characteristics for each pin
available on the 64K Series products and the data is sorted alphabetically by the pin
symbol mnemonic.
XIN IExternal Crystal Input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. This
signal is usable with external RC networks and an external clock driver.
XOUT OExternal Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the XIN pin to form the oscillator.
When the system clock is referred to in this manual, it refers to the frequency
of the signal at this pin. This pin must be left unconnected when not using a
crystal.
RCOUT ORC Oscillator Output. This signal is the output of the RC oscillator. It is
multiplexed with a general-purpose I/O pin. This signal must be left
unconnected when not using a crystal.
On-Chip Debugger
DBG I/O Debug. This pin is the control and data input and output to and from the On-
Chip Debugger. This pin is open-drain.
For operation of the On-Chip Debugger, all power pins (VDD and
AVDD) must be supplied with power and all ground pins (VSS and
AVSS) must be properly grounded.
The DBG pin is open-drain and must have an external pull-up resistor
to ensure proper operation.
Reset
RESET IRESET. Generates a Reset when asserted (driven Low).
Power Supply
VDD IPower Supply.
AVDD IAnalog Power Supply.
VSS IGround.
AVSS IAnalog Ground.
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic I/O Description
Caution:
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
17
Table 4. Pin Characteristics of the Z8 Encore! XP 64K Series Flash Microcontrollers
Symbol
Mnemonic Direction
Reset
Direction
Active Low
or
Active High
Tri-State
Output
Internal
Pull-up or
Pull-down
Schmitt-
Trigger
Input
Open Drain
Output
AVSS N/A N/A N/A N/A No No N/A
AVDD N/A N/A N/A N/A No No N/A
DBG I/O I N/A Yes No Yes Yes
VSS N/A N/A N/A N/A No No N/A
PA[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PB[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PC[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PD[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PE7:0] I/O I N/A Yes No Yes Yes,
Programmable
PF[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PG[7:0] I/O I N/A Yes No Yes Yes,
Programmable
PH[3:0] I/O I N/A Yes No Yes Yes,
Programmable
RESET I I Low N/A Pull-up Yes N/A
VDD N/A N/A N/A N/A No No N/A
XIN I I N/A N/A No No N/A
XOUT O O N/A Yes, in
STOP
mode
No No No
Note: x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer.
zilog‘
PS019919-1207 Signal and Pin Descriptions
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
18
zilog www.zilog.com
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PS019919-1207 Address Space
19
Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
The Register File contains addresses for the general-purpose registers and the
eZ8 CPU, peripheral, and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable
code and/or data.
The Data Memory consists of the addresses for all memory locations that hold only
data.
These three address spaces are covered briefly in the following subsections. For more
information on eZ8 CPU and its address space, refer to eZ8 CPU Core User Manual
(UM0128) available for download at www.zilog.com.
Register File
The Register File address space in the 64K Series is 4 KB (4096 bytes). The Register File
is composed of two sections—control registers and general-purpose registers. When
instructions are executed, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4 KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not
recommended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
64K Series provide 2 KB to 4 KB of on-chip RAM depending upon the device. Reading
from Register File addresses outside the available RAM addresses (and not within the
control register address space) returns an undefined value. Writing to these Register File
addresses produces no effect. To determine the amount of RAM available for the specific
64K Series device, see Part Selection Guide on page 2.
PS019919-1207 Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
20
Program Memory
The eZ8 CPU supports 64 KB of Program Memory address space. The Z8 Encore! XP
64K Series Flash Microcontrollers contains 16 KB to 64 KB of on-chip Flash in the
Program Memory address space, depending upon the device. Reading from Program
Memory addresses outside the available Flash memory addresses returns FFH. Writing to
these unimplemented Program Memory addresses produces no effect. Table 5 describes
the Program Memory maps for the 64K Series products.
Table 5. Z8 Encore! XP 64K Series Flash Microcontrollers Program Memory
Maps
Program Memory Address (Hex) Function
Z8F162x Products
0000-0001 Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-3FFF Program Memory
Z8F242x Products
0000-0001 Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-5FFF Program Memory
Z8F322x Products
0000-0001 Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-7FFF Program Memory
Z8F482x Products
PS019919-1207 Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
21
Data Memory
The Z8 Encore! XP 64K Series Flash Microcontrollers does not use the eZ8 CPU’s 64 KB
Data Memory address space.
Information Area
Table 6 on page 22 describes the Z8 Encore! XP 64K Series Flash Microcontrollers
Information Area. This 512 byte Information Area is accessed by setting bit 7 of the Page
Select Register to 1. When access is enabled, the Information Area is mapped into the
Program Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the
Information Area access is enabled, execution of LDC and LDCI instruction from these
Program Memory addresses return the Information Area data rather than the Program
Memory data. Reads of these addresses through the On-Chip Debugger also returns the
Information Area data. Execution of code from these addresses continues to correctly use
the Program Memory. Access to the Information Area is read-only.
0000-0001 Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-BFFF Program Memory
Z8F642x Products
0000-0001 Option Bits
0002-0003 Reset Vector
0004-0005 WDT Interrupt Vector
0006-0007 Illegal Instruction Trap
0008-0037 Interrupt Vectors*
0038-FFFF Program Memory
*See Ta b l e 2 3 on page 68 for a list of the interrupt vectors.
Table 5. Z8 Encore! XP 64K Series Flash Microcontrollers Program Memory
Maps (Continued)
Program Memory Address (Hex) Function
PS019919-1207 Address Space
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
22
Table 6. Z8 Encore! XP 64K Series Flash Microcontrollers Information Area Map
Program Memory
Address (Hex) Function
FE00H-FE3FH Reserved
FE40H-FE53H Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros (ASCII Null character)
FE54H-FFFFH Reserved
OOO-EFF General-Purpose Register File RAM — XX F00 Timer 0 High Byte TOH 00 90 F01 Timer 0 Low Byte TOL 01 90 F02 Timer 0 Reload High Byte TORH FF 91 F03 Timer 0 Reload Low Byte TORL FF 91 F04 Timer 0 PWM High Byte TOPWMH 00 92 F05 Timer 0 PWM Low Byte TOPWML 00 92 F06 Timer 0 Control 0 TOCTLO 00 93 F07 Timer 0 Control 1 TOCTL1 00 94 F08 Timer 1 High Byte T1H 00 90 F09 Timer 1 Low Byte T1L 01 90 FOA Timer 1 Reload High Byte T1RH FF 91 FOB Timer 1 Reload Low Byte T1RL FF 91 FOC Timer1 PWM High Byte T1PWMH 00 92 FOD Timer1 PWM Low Byte T1PWML 00 92 FOE Timer 1 Control 0 T1CTLO 00 93 FOF Timer 1 Control 1 T1CTL1 00 94 F10 Timer 2 High Byte T2H 00 90 F11 Timer 2 Low Byte T2L 01 90 F12 Timer 2 Reload High Byte T2RH FF 91 F13 Timer 2 Reload Low Byte TZRL FF 91 F14 Timer 2 PWM High Byte T2PWMH 00 92 F15 Timer 2 PWM Low Byte T2PWML 00 92 F16 Timer 2 Control 0 T2CTLO 00 93 F17 Timer 2 Control 1 T2CTL1 00 94
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PS019919-1207 Register File Address Map
23
Register File Address Map
Table 7 provides the address map for the Register File of the 64K Series products. Not all
devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports.
Consider registers for unimplemented peripherals as Reserved.
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
General-Purpose RAM
000-EFF General-Purpose Register File RAM XX
Timer 0
F00 Timer 0 High Byte T0H 00 90
F01 Timer 0 Low Byte T0L 01 90
F02 Timer 0 Reload High Byte T0RH FF 91
F03 Timer 0 Reload Low Byte T0RL FF 91
F04 Timer 0 PWM High Byte T0PWMH 00 92
F05 Timer 0 PWM Low Byte T0PWML 00 92
F06 Timer 0 Control 0 T0CTL0 00 93
F07 Timer 0 Control 1 T0CTL1 00 94
Timer 1
F08 Timer 1 High Byte T1H 00 90
F09 Timer 1 Low Byte T1L 01 90
F0A Timer 1 Reload High Byte T1RH FF 91
F0B Timer 1 Reload Low Byte T1RL FF 91
F0C Timer 1 PWM High Byte T1PWMH 00 92
F0D Timer 1 PWM Low Byte T1PWML 00 92
F0E Timer 1 Control 0 T1CTL0 00 93
F0F Timer 1 Control 1 T1CTL1 00 94
Timer 2
F10 Timer 2 High Byte T2H 00 90
F11 Timer 2 Low Byte T2L 01 90
F12 Timer 2 Reload High Byte T2RH FF 91
F13 Timer 2 Reload Low Byte T2RL FF 91
F14 Timer 2 PWM High Byte T2PWMH 00 92
F15 Timer 2 PWM Low Byte T2PWML 00 92
F16 Timer 2 Control 0 T2CTL0 00 93
F17 Timer 2 Control 1 T2CTL1 00 94
F18 Timer 3 High Byte T3H 00 90 F19 Timer 3 Low Byte T3L 01 90 F1A Timer 3 Reload High Byte T3RH FF 91 F1B Timer 3 Reload Low Byte T3RL FF 91 F1C Timer 3 PWM High Byte T3F'WMH 00 92 F1D Timer 3 PWM Low Byte T3PWML 00 92 F1 E Timer 3 Control 0 T3CTLO 00 93 F1 F Timer 3 Control 1 T3CTL1 00 94 20-3F Reserved — XX F40 UARTO Transmit Data UOTXD XX 114 UARTO Receive Data UORXD XX 115 F41 UARTO Status 0 UOSTATO 0000011 Xb 115 F42 UARTO Control 0 UOCTLO 00 117 F43 UARTO Control 1 UOCTL1 00 117 F44 UARTO Status 1 UOSTAT1 00 115 F45 UARTO Address Compare Register UOADDR 00 120 F46 UARTO Baud Rate High Byte UOBRH FF 120 F47 UARTO Baud Rate Low Byte UOBRL FF 120 F48 UART1 Transmit Data U1TXD XX 114 UART1 Receive Data U1 RXD XX 115 F49 UART1 Status 0 U1 STATO 0000011 Xb 115 F4A UART1 Control 0 U1 CTLO 00 117 F4B UART1 Control 1 U1 CTL1 00 117 F4C UART1 Status 1 U1 STAT1 00 115 F4D UART1 Address Compare Register U’iADDR 00 120 F4E UART1 Baud Rate High Byte U1BRH FF 120 F4F UART1 Baud Rate Low Byte U1BRL FF 120 '2 F50 |“C Data IZCDATA 00 156 F51 |“C Status IZCSTAT 80 157 F52 |“C Control IZCCTL 00 158 F53 |“C Baud Rate High Byte |2CBRH FF 160 F54 |“C Baud Rate Low Byte |2CBRL FF 160 F55 I“C Diagnostic State IZCDST CO 161 F56 I“C Diagnostic Control IZCDIAG 00 163 F57-F5F Reserved — XX F60 SPI Data SF'IDATA XX 137
PS019919-1207 Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
24
Timer 3 (unavailable in the 44-pin packages)
F18 Timer 3 High Byte T3H 00 90
F19 Timer 3 Low Byte T3L 01 90
F1A Timer 3 Reload High Byte T3RH FF 91
F1B Timer 3 Reload Low Byte T3RL FF 91
F1C Timer 3 PWM High Byte T3PWMH 00 92
F1D Timer 3 PWM Low Byte T3PWML 00 92
F1E Timer 3 Control 0 T3CTL0 00 93
F1F Timer 3 Control 1 T3CTL1 00 94
20-3F Reserved XX
UART 0
F40 UART0 Transmit Data U0TXD XX 114
UART0 Receive Data U0RXD XX 115
F41 UART0 Status 0 U0STAT0 0000011Xb 115
F42 UART0 Control 0 U0CTL0 00 117
F43 UART0 Control 1 U0CTL1 00 117
F44 UART0 Status 1 U0STAT1 00 115
F45 UART0 Address Compare Register U0ADDR 00 120
F46 UART0 Baud Rate High Byte U0BRH FF 120
F47 UART0 Baud Rate Low Byte U0BRL FF 120
UART 1
F48 UART1 Transmit Data U1TXD XX 114
UART1 Receive Data U1RXD XX 115
F49 UART1 Status 0 U1STAT0 0000011Xb 115
F4A UART1 Control 0 U1CTL0 00 117
F4B UART1 Control 1 U1CTL1 00 117
F4C UART1 Status 1 U1STAT1 00 115
F4D UART1 Address Compare Register U1ADDR 00 120
F4E UART1 Baud Rate High Byte U1BRH FF 120
F4F UART1 Baud Rate Low Byte U1BRL FF 120
I2C
F50 I2C Data I2CDATA 00 156
F51 I2C Status I2CSTAT 80 157
F52 I2C Control I2CCTL 00 158
F53 I2C Baud Rate High Byte I2CBRH FF 160
F54 I2C Baud Rate Low Byte I2CBRL FF 160
F55 I2C Diagnostic State I2CDST C0 161
F56 I2C Diagnostic Control I2CDIAG 00 163
F57-F5F Reserved XX
Serial Peripheral Interface (SPI)
F60 SPI Data SPIDATA XX 137
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
F61 SPI Control SF'ICTL 00 137 F62 SPI Status SPISTAT 01 139 F63 SPI Mode SPIMODE 00 140 F64 SPI Diagnostic State SF'IDST 00 141 F65 Reserved — XX F66 SPI Baud Rate High Byte SF'IBRH FF 142 F67 SPI Baud Rate Low Byte SF'IBRL FF 142 F68-F6F Reserved — XX F70 ADC Control ADCCTL 20 179 F71 Reserved — XX F72 ADC Data High Byte ADCDiH XX 180 F73 ADC Data Low Bits ADCDiL XX 180 F74-FAF Reserved — XX FBO DMAO Control DMAOCTL 00 167 FB1 DMAO l/O Address DMAOIO XX 169 FB2 DMAO End/Start Address High Nibble DMAOH XX 169 FB3 DMAO Start Address Low Byte DMAOSTART XX 170 FB4 DMAO End Address Low Byte DMAOEND XX 170 FB8 DMA1 Control DMA1CTL 00 167 FB9 DMA1 l/O Address DMA1 IO XX 169 FBA DMA1 End/Start Address High Nibble DMA1 H XX 169 FBB DMA1 Start Address Low Byte DMA1 START XX 170 FBC DMA1 End Address Low Byte DMA1 END XX 170 FBD DMAiADC Address DMAAiADDR XX 171 FBE DMAiADC Control DMAACTL 00 172 FBF DMAiADC Status DMAASTAT 00 173 FCO Interrupt Request 0 IRQO 00 71 FC1 IRQO Enable High Bit IRQOENH 00 74 FC2 IRQO Enable Low Bit IRQOENL 00 74 F03 Interrupt Request 1 IRQ1 00 72 FC4 IRQ1 Enable High Bit IRQ1ENH 00 75 FC5 IRQ1 Enable Low Bit IRQ1ENL 00 75 F06 Interrupt Request 2 IRQZ 00 73 FC7 IRQZ Enable High Bit IRQZENH 00 76 FC8 IRQZ Enable Low Bit IRQZENL 00 76 FOB—FCC Reserved — XX
PS019919-1207 Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
25
F61 SPI Control SPICTL 00 137
F62 SPI Status SPISTAT 01 139
F63 SPI Mode SPIMODE 00 140
F64 SPI Diagnostic State SPIDST 00 141
F65 Reserved XX
F66 SPI Baud Rate High Byte SPIBRH FF 142
F67 SPI Baud Rate Low Byte SPIBRL FF 142
F68-F6F Reserved XX
Analog-to-Digital Converter
F70 ADC Control ADCCTL 20 179
F71 Reserved XX
F72 ADC Data High Byte ADCD_H XX 180
F73 ADC Data Low Bits ADCD_L XX 180
F74-FAF Reserved XX
DMA 0
FB0 DMA0 Control DMA0CTL 00 167
FB1 DMA0 I/O Address DMA0IO XX 169
FB2 DMA0 End/Start Address High Nibble DMA0H XX 169
FB3 DMA0 Start Address Low Byte DMA0START XX 170
FB4 DMA0 End Address Low Byte DMA0END XX 170
DMA 1
FB8 DMA1 Control DMA1CTL 00 167
FB9 DMA1 I/O Address DMA1IO XX 169
FBA DMA1 End/Start Address High Nibble DMA1H XX 169
FBB DMA1 Start Address Low Byte DMA1START XX 170
FBC DMA1 End Address Low Byte DMA1END XX 170
DMA ADC
FBD DMA_ADC Address DMAA_ADDR XX 171
FBE DMA_ADC Control DMAACTL 00 172
FBF DMA_ADC Status DMAASTAT 00 173
Interrupt Controller
FC0 Interrupt Request 0 IRQ0 00 71
FC1 IRQ0 Enable High Bit IRQ0ENH 00 74
FC2 IRQ0 Enable Low Bit IRQ0ENL 00 74
FC3 Interrupt Request 1 IRQ1 00 72
FC4 IRQ1 Enable High Bit IRQ1ENH 00 75
FC5 IRQ1 Enable Low Bit IRQ1ENL 00 75
FC6 Interrupt Request 2 IRQ2 00 73
FC7 IRQ2 Enable High Bit IRQ2ENH 00 76
FC8 IRQ2 Enable Low Bit IRQ2ENL 00 76
FC9-FCC Reserved XX
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
FCD Interrupt Edge Select IRQES 00 78 FCE Interrupt Port Select IRQF'S 00 78 FCF Interrupt Control IRQCTL 00 79 FDO Port A Address PAADDR 00 61 FD1 Port A Control PACTL 00 62 FD2 Port A Input Data PAIN XX 66 FDB Port A Output Data PAOUT 00 66 FD4 Port B Address PBADDR 00 61 FD5 Port B Control PBCTL 00 62 FD6 Port B Input Data PBIN XX 66 FD7 Port B Output Data PBOUT 00 66 FDB Port C Address PCADDR 00 61 FD9 Port C Control PCCTL 00 62 FDA Port C Input Data PCIN XX 66 FDB Port C Output Data PCOUT 00 66 FDC Port D Address PDADDR 00 61 FDD Port D Control PDCTL 00 62 FDE Port D Input Data PDIN XX 66 FDF Port D Output Data PDOUT 00 66 FEO Port E Address PEADDR 00 61 FE1 Port E Control PECTL 00 62 FE2 Port E Input Data PEIN XX 66 FEB Port E Output Data PEOUT 00 66 FE4 Port F Address PFADDR 00 61 FE5 Port F Control PFCTL 00 62 FE6 Port F Input Data PFIN XX 66 FE7 Port F Output Data PFOUT 00 66 FEE Port G Address PGADDR 00 61 FE9 Port G Control PGCTL 00 62 FEA Port G Input Data PGIN XX 66 FEB Port G Output Data PGOUT 00 66 FEC Port H Address PHADDR 00 61 FED Port H Control PHCTL 00 62 FEE Port H Input Data PHIN XX 66
PS019919-1207 Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
26
FCD Interrupt Edge Select IRQES 00 78
FCE Interrupt Port Select IRQPS 00 78
FCF Interrupt Control IRQCTL 00 79
GPIO Port A
FD0 Port A Address PAADDR 00 61
FD1 Port A Control PACTL 00 62
FD2 Port A Input Data PAIN XX 66
FD3 Port A Output Data PAOUT 00 66
GPIO Port B
FD4 Port B Address PBADDR 00 61
FD5 Port B Control PBCTL 00 62
FD6 Port B Input Data PBIN XX 66
FD7 Port B Output Data PBOUT 00 66
GPIO Port C
FD8 Port C Address PCADDR 00 61
FD9 Port C Control PCCTL 00 62
FDA Port C Input Data PCIN XX 66
FDB Port C Output Data PCOUT 00 66
GPIO Port D
FDC Port D Address PDADDR 00 61
FDD Port D Control PDCTL 00 62
FDE Port D Input Data PDIN XX 66
FDF Port D Output Data PDOUT 00 66
GPIO Port E
FE0 Port E Address PEADDR 00 61
FE1 Port E Control PECTL 00 62
FE2 Port E Input Data PEIN XX 66
FE3 Port E Output Data PEOUT 00 66
GPIO Port F
FE4 Port F Address PFADDR 00 61
FE5 Port F Control PFCTL 00 62
FE6 Port F Input Data PFIN XX 66
FE7 Port F Output Data PFOUT 00 66
GPIO Port G
FE8 Port G Address PGADDR 00 61
FE9 Port G Control PGCTL 00 62
FEA Port G Input Data PGIN XX 66
FEB Port G Output Data PGOUT 00 66
GPIO Port H
FEC Port H Address PHADDR 00 61
FED Port H Control PHCTL 00 62
FEE Port H Input Data PHIN XX 66
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
FEF Port H Output Data PHOUT 00 66 FFO Watchdog Timer Control WDTCTL XXXOOOOOb 100 FF1 Watchdog Timer Reload Upper Byte WDTU FF 101 FF2 Watchdog Timer Reload High Byte WDTH FF 101 FF3 Watchdog Timer Reload Low Byte WDTL FF 101 FF4-FF7 Reserved — XX FFE Flash Control FCTL 00 190 FFB Flash Status FSTAT 00 190 FF9 Page Select FPS 00 191 FF9 (if enabled) Flash Sector Protect FPROT 00 192 FFA Flash Programming Frequency High Byte FFREQH 00 192 FFB Flash Programming Frequency Low Byte FFREQL 00 192 FF4-FF8 Reserved — XX FF9 Page Select RPS 00 FFA-FFB Reserved — XX FFC Flags — XX ”‘ FFD Register Pointer RP XX FFE Stack Pointer High Byte SPH XX FFF Stack Pointer Low Byte SPL XX Note: XX:Undefined
PS019919-1207 Register File Address Map
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
27
FEF Port H Output Data PHOUT 00 66
Watchdog Timer
FF0 Watchdog Timer Control WDTCTL XXX00000b 100
FF1 Watchdog Timer Reload Upper Byte WDTU FF 101
FF2 Watchdog Timer Reload High Byte WDTH FF 101
FF3 Watchdog Timer Reload Low Byte WDTL FF 101
FF4-FF7 Reserved XX
Flash Memory Controller
FF8 Flash Control FCTL 00 190
FF8 Flash Status FSTAT 00 190
FF9 Page Select FPS 00 191
FF9 (if enabled) Flash Sector Protect FPROT 00 192
FFA Flash Programming Frequency High Byte FFREQH 00 192
FFB Flash Programming Frequency Low Byte FFREQL 00 192
FF4-FF8 Reserved XX
Read-Only Memory Controller
FF9 Page Select RPS 00
FFA-FFB Reserved XX
eZ8 CPU
FFC Flags XX Refer to eZ8
CPU Core
User Manual
(UM0128)
FFD Register Pointer RP XX
FFE Stack Pointer High Byte SPH XX
FFF Stack Pointer Low Byte SPL XX
Note: XX=Undefined
Table 7. Z8 Encore! XP 64K Series Flash Microcontrollers Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
28
Control Register
Summary
Timer 0 High Byte
T0H (F00H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value [15:8]
Timer 0 Low Byte
T0L (F01H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 current count value [7:0]
Timer 0 Reload High Byte
T0RH (F02H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [15:8]
Timer 0 Reload Low Byte
T0RL (HF03 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [7:0]
Timer 0 PWM High Byte
T0PWMH (F04H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 PWM value [15:8]
Timer 0 Control 0
T0CTL0 (F06H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 0 Input signal is GPIO pin
1 = Timer 0 Input signal is Timer 3
out
Reserved
Timer 0 Control 1
T0CTL1 (F07H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 1 High Byte
T1H (F08H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [15:8]
Timer 1 Low Byte
T1L (F09H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [7:0]
Timer 1 Reload High Byte
T1RH (F0AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [15:8]
Timer 1 Reload Low Byte
T1RL (F0BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [7:0]
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
29
Timer 1 PWM High Byte
T1PWMH (F0CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [15:8]
Timer 1 PWM Low Byte
T1PWML (F0DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [7:0]
Timer 1 Control 0
T1CTL0 (F0EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 1 Input signal is GPIO pin
1 = Timer 1 Input signal is Timer 0
out
Reserved
Timer 1 Control 1
T1CTL1 (F0FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 2 High Byte
T2H (F10H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 current count value [15:8]
Timer 2 Low Byte
T2L (F11H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 current count value [7:0]
Timer 2 Reload High Byte
T2RH (F12H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 reload value [15:8]
Timer 2 Reload Low Byte
T2RL (F13H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 reload value [7:0]
Timer 2 PWM High Byte
T2PWMH (F14H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 PWM value [15:8]
Timer 2 PWM Low Byte
T2PWML (F15H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 PWM value [7:0]
Timer 2 Control 0
T2CTL0 (F16H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 2 Input signal is GPIO pin
1 = Timer 2 Input signal is Timer 1
out
Reserved
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
30
Timer 2 Control 1
T2CTL1 (F17H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 3 High Byte
T3H (F18H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 current count value [15:8]
Timer 3 Low Byte
T3L (F19H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 current count value [7:0]
Timer 3 Reload High Byte
T3RH (F1AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 reload value [15:8]
Timer 3 Reload Low Byte
T3RL (F1BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 reload value [7:0]
Timer 3 PWM High Byte
T3PWMH (F1CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 PWM value [15:8]
Timer 3 PWM Low Byte
T3PWML (F1DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 PWM value [7:0]
Timer 3 Control 0
T3CTL0 (F1EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 3 Input signal is GPIO pin
1 = Timer 3 Input signal is Timer 2
out
Reserved
Timer 3 Control 1
T3CTL1 (F1FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the
timer
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
J
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
31
UART0 Transmit Data
U0TXD (F40H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 transmitter data byte [7:0]
UART0 Receive Data
U0RXD (F40H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 receiver data byte [7:0]
UART0 Status 0
U0STAT0 (F41H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Returns the level of the CTS signal
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
Break Detect
0 = No break occurred
1 = A break occurred
Framing Error
0 = No framing error occurred
1 = A framing occurred
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
UART0 Control 0
U0CTL0 (F42H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped back to
the receiver
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as
a
transmit enable control signal
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
32
UART0 Control 1
U0CTL1 (F43H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Infrared Encoder/Decoder Enable
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors
generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does
not.
Baud Rate Registers Control
Refer to UART chapter for operation
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor
bit
1 = Send a 1 as the multiprocessor
bit
Multiprocessor Mode [0]
See Multiprocessor Mode [1] below
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
11 = Interrupt on data following an
address match
UART0 Status 1
U0STAT1 (F44H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor
bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new
frame
Reserved
UART0 Address Compare
U0ADDR (F45H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Address Compare [7:0]
UART0 Baud Rate Generator High Byte
U0BRH (F46H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor [15:8]
UART0 Baud Rate Generator Low Byte
U0BRL (F47H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor [7:0]
UART1 Transmit Data
U1TXD (F48H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 transmitter data byte[7:0]
UART1 Receive Data
U1RXD (F48H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART receiver data byte [7:0]
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
33
UART1 Status 0
U1STAT0 (F49H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Returns the level of the CTS signal
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
Break Detect
0 = No break occurred
1 = A break occurred
Framing Error
0 = No framing error occurred
1 = A framing occurred
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
UART1 Control 0
U1CTL0 (F4AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped back to
the receiver
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as
a
transmit enable control signal
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
34
UART1 Control 1
U0CTL1 (F4BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Infrared Encoder/Decoder Enable
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors
generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does
not.
Baud Rate Registers Control
Refer to UART chapter for operation
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor
bit
1 = Send a 1 as the multiprocessor
bit
Multiprocessor Mode [0]
See Multiprocessor Mode [1] below
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
11 = Interrupt on data following an
address match
UART1 Status 1
U0STAT1 (F4CH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor
bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new
frame
Reserved
UART1 Address Compare
U0ADDR (F4DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Address Compare [7:0]
UART1 Baud Rate Generator High Byte
U0BRH (F4EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Baud Rate divisor [15:8]
UART1 Baud Rate Generator Low Byte
U1BRL (F4FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Baud Rate divisor [7:0]
I2C Data
I2CDATA (F50H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C data [7:0]
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
35
I2C Status
I2CSTAT (F51H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
NACK Interrupt
0 = No action required to service
NAK
1 = START/STOP not set after NAK
Data Shift State
0 = Data is not being transferred
1 = Data is being transferred
Transmit Address State
0 = Address is not being transferred
1 = Address is being transferred
Read
0 = Write operation
1 = Read operation
10-Bit Address
0 = 7-bit address being transmitted
1 = 10-bit address being transmitted
Acknowledge
0 = Acknowledge not
transmitted/received
1 = For last byte, Acknowledge was
transmitted/received
Receive Data Register Full
0 = I2C has not received data
1 = Data register contains received
data
Transmit Data Register Empty
0 = Data register is full
1 = Data register is empty
I2C Control
I2CCTL (F52H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Signal Filter Enable
0 = Digital filtering disabled
1 = Low-pass digital filters enabled
on SDA and SCL input signals
Flush Data
0 = No effect
1 = Clears I2C Data register
Send NAK
0 = Do not send NAK
1 = Send NAK after next byte
received
from slave
Enable TDRE Interrupts
0 = Do not generate an interrupt
when
the I2C Data register is empty
1 = Generate an interrupt when the
I2C
Transmit Data register is empty
Baud Rate Generator Interrupt
0 = Interrupts behave as set by I2C
control
1 = BRG generates an interrupt
when
it counts down to zero
Send Stop Condition
0 = Do not issue Stop condition after
data transmission is complete
1 = Issue Stop condition after data
transmission is complete
Send Start Condition
0 = Do not send Start Condition
1 = Send Start Condition
I2C Enable
0 = I2C is disabled
1 = I2C is enabled
I2C Baud Rate Generator High Byte
I2CBRH (F53H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte
I2CBRL (F54H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [7:0]
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
36
SPI Data
SPIDATA (F60H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Data [7:0]
SPI Control
SPICTL (F61H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Enable
0 = SPI disabled
1 = SPI enabled
Master Mode Enabled
0 = SPI configured in Slave mode
1 = SPI configured in Master mode
Wire-OR (open-drain) Mode
0 = SPI signals not configured for
open-drain
1 = SPI signals (SCK, SS, MISO,
and
MOSI) configured for open-
drain
Clock Polarity
0 = SCK idles Low
1 = SPI idles High
Phase Select
Sets the phase relationship of the
data
to the clock.
BRG Timer Interrupt Request
0 = BRG timer function is disabled
1 = BRG time-out interrupt is
enabled
Start an SPI Interrupt Request
0 = No effect
1 = Generate an SPI interrupt
request
Interrupt Request Enable
0 = SPI interrupt requests are
disabled
1 = SPI interrupt requests are
enabled
SPI Status
SPISTAT (F62H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Slave Select
0 = If Slave, SS pin is asserted
1 = If Slave, SS pin is not asserted
Transmit Status
0 = No data transmission in progress
1 = Data transmission now in
progress
Reserved
Slave Mode Transaction Abort
0 = No slave mode transaction abort
detected
1 = Slave mode transaction abort
was
detected
Collision
0 = No multi-master collision
detected
1 = Multi-master collision was
detected
Overrun
0 = No overrun error detected
1 = Overrun error was detected
Interrupt Request
0 = No SPI interrupt request pending
1 = SPI interrupt request is pending
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Slave Select Value
If Master and SPIMODE[1] = 1:
0 = SS pin driven Low
1 = SS pin driven High
Slave Select I/O
0 = SS pin configured as an input
1 = SS pin configured as an output
(Master mode only)
Number of Data Bits Per Character
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bit
110 = 6 bits
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
37
111 = 7 bits
Diagnostic Mode Control
0 = Reading from SPIBRH, SPIBRL
returns reload values
1 = Reading from SPIBRH, SPIBRL
returns current BRG count value
Reserved
SPI Diagnostic State
SPIDST (F64H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SPI State
Transmit Clock Enable
0 = Internal transmit clock enable
signal is deasserted
1 = Internal transmit clock enable
signal is asserted
Shift Clock Enable
0 = Internal shift clock enable signal
is deasserted
1 = Internal shift clock enable signal
is asserted
SPI Baud Rate Generator High Byte
SPIBRH (F66H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [15:8]
SPI Baud Rate Generator Low Byte
SPIBRL (F67H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [7:0]
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Control
ADCCTL (F70H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Analog Input Select
0000 = ANA0 0001 = ANA1
0010 = ANA2 0011 = ANA3
0100 = ANA4 0101 = ANA5
0110 = ANA6 0111 = ANA7
1000 = ANA8 1001 = ANA9
1010 = ANA10 1011 = ANA11
11xx = Reserved
Continuous Mode Select
0 = Single-shot conversion
1 = Continuous conversion
External VREF select
0 = Internal voltage reference
selected
1 = External voltage reference
selected
Reserved
Conversion Enable
0 = Conversion is complete
1 = Begin conversion
ADC Data High Byte
ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data [9:2]
ADC Data Low Bits
ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
ADC Data [1:0]
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
38
DMA0 Control
DMA0CTL (FB0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Received Data
register
contains valid data
101 = UART1 Received Data
register
contains valid data
110 = I2C receiver contains valid
data
111 = Reserved
Word Select
0 = DMA transfers 1 byte per
request
1 = DMA transfers 2 bytes per
request
DMA0 Interrupt Enable
0 = DMA0 does not generate
interrupts
1 = DMA0 generates an interrupt
when
End Address data is transferred
DMA0 Data Transfer Direction
0 = Register File to peripheral
registers
1 = Peripheral registers to Register
File
DMA0 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to
run
DMA0 Enable
0 = DMA0 is disabled
1 = DMA0 is enabled
DMA0 I/O Address
DMA0IO (FB1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Peripheral Register Address
Low byte of on-chip peripheral
control
registers on Register File page FH
DMA0 Address High Nibble
DMA0H (FB2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [11:8]
DMA0 End Address [11:8]
DMA0 Start/Current Address Low Byte
DMA0START (FB3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [7:0]
DMA0 End Address Low Byte
DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 End Address [7:0]
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
39
DMA1 Control
DMA1CTL (FB8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Transmit Data register
is empty
101 = UART1 Transmit Data register
is empty
110 = I2C Transmit Data register
is empty
111 = Reserved
Word Select
0 = DMA transfers 1 byte per
request
1 = DMA transfers 2 bytes per
request
DMA1 Interrupt Enable
0 = DMA1 does not generate
interrupts
1 = DMA1 generates an interrupt
when
End Address data is transferred
DMA1 Data Transfer Direction
0 = Register File to peripheral
registers
1 = Peripheral registers to Register
File
DMA1 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to
run
DMA1 Enable
0 = DMA1 is disabled
1 = DMA1 is enabled
DMA1 I/O Address
DMA1IO (FB9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Peripheral Register Address
Low byte of on-chip peripheral
control
registers on Register File page FH
DMA1 Address High Nibble
DMA1H (FBAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Start Address [11:8]
DMA1 End Address [11:8]
DMA1 Start/Current Address Low Byte
DMA1START (FBBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Start Address [7:0]
DMA1 End Address Low Byte
DMA1END (FBCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 End Address [7:0]
DMA_ADC Address
DMAA_ADDR (FBDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
DMA_ADC Address
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
40
DMA_ADC Control
DMAACTL (FBEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Analog Input Number
0000 = Analog input 0 updated
0001 = Analog input 0-1 updated
0010 = Analog input 0-2 updated
0011 = Analog input 0-3 updated
0100 = Analog input 0-4 updated
0101 = Analog input 0-5 updated
0100 = Analog input 0-6 updated
0101 = Analog input 0-7 updated
1000 = Analog input 0-8 updated
1001 = Analog input 0-9 updated
1010 = Analog input 0-10 updated
1011 = Analog inputs 0-11 updated
11xx = Reserved
Reserved
Interrupt request enable
0 = DMA_ADC does not generate
interrupt requests
1 = DMA_ADC generates interrupt
requests after last analog input
DMA_ADC Enable
0 = DMA_ADC is disabled
1 = DMA_ADC is enabled
DMA Status
DMAA_STAT (FBFH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Interrupt Request Indicator
0 = DMA0 is not the source of the
IRQ
1 = DMA0 is the source of the IRQ
DMA1 Interrupt Request Indicator
0 = DMA1 is not the source of the
IRQ
1 = DMA1 is the source of the IRQ
DMA_ADC Interrupt Request
0 = DMA_ADC is not the source of
the
IRQ
1 = DMA_ADC is the source of the
IRQ
Reserved
Current ADC analog input
Identifies the analog input the ADC
is
currently converting
Interrupt Request 0
IRQ0 (FC0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Interrupt Request
SPI Interrupt Request
I2C Interrupt Request
UART 0 Transmitter Interrupt
UART 0 Receiver Interrupt Request
Timer 0 Interrupt Request
Timer 1 Interrupt Request
Timer 2 Interrupt Request
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting
service
IRQ0 Enable High Bit
IRQ0ENH (FC1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC IRQ Enable Hit Bit
SPI IRQ Enable High Bit
I2C IRQ Enable High Bit
UART 0 Transmitter IRQ Enable
UART 0 Receiver IRQ Enable High
Timer 0 IRQ Enable High Bit
Timer 1 IRQ Enable High Bit
Timer 2 IRQ Enable High Bit
i H
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
41
IRQ0 Enable Low Bit
IRQ0ENL (FC2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC IRQ Enable Hit Bit
SPI IRQ Enable Low Bit
I2C IRQ Enable Low Bit
UART 0 Transmitter IRQ Enable
UART 0 Receiver IRQ Enable Low
Timer 0 IRQ Enable Low Bit
Timer 1 IRQ Enable Low Bit
Timer 2 IRQ Enable Low Bit
Interrupt Request 1
IRQ1 (FC3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin Interrupt Request
0 = IRQ from corresponding pin [7:0]
is not pending
1 = IRQ from corresponding pin [7:0]
is awaiting service
IRQ1 Enable High Bit
IRQ1ENH (FC4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin IRQ Enable High Bit
IRQ1 Enable Low Bit
IRQ1ENL (FC5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin IRQ Enable Low Bit
Interrupt Request 2
IRQ2 (FC6H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin Interrupt Request
0 = IRQ from corresponding pin [3:0]
is not pending
1 = IRQ from corresponding pin [3:0]
is awaiting service
DMA Interrupt Request
UART 1 Transmitter Interrupt
UART 1 Receiver Interrupt Request
Timer 3 Interrupt Request
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting
service
IRQ2 Enable High Bit
IRQ2ENH (FC7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable High Bit
DMA IRQ Enable High Bit
UART 1 Transmitter IRQ Enable
UART 1 Receiver IRQ Enable High
Timer 3 IRQ Enable High Bit
IRQ2 Enable Low Bit
IRQ2ENL (FC8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin IRQ Enable Low Bit
DMA IRQ Enable Low Bit
UART 1 Transmitter IRQ Enable
UART 1 Receiver IRQ Enable Low
Timer 3 IRQ Enable Low Bit
Interrupt Edge Select
IRQES (FCDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Interrupt Edge Select
0 = Falling edge
1 = Rising edge
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
42
Interrupt Port Select
IRQPS (FCEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Port Pin Select [7:0]
0 = Port A pin is the interrupt source
1 = Port D pin is the interrupt source
Interrupt Control
IRQCTL (FCFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Interrupt Request Enable
0 = Interrupts are disabled
1 = Interrupts are enabled
Port A Address
PAADDR (FD0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port A Control
PACTL (FD1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Control[7:0]
Provides Access to Port Sub-
Registers
Port A Input Data
PAIN (FD2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Input Data [7:0]
Port A Output Data
PAOUT (FD3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Output Data [7:0]
Port B Address
PBADDR (FD4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port B Control
PBCTL (FD5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Control[7:0]
Provides Access to Port Sub-
Registers
Port B Input Data
PBIN (FD6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Input Data [7:0]
Port B Output Data
PBOUT (FD7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Output Data [7:0]
Port C Address
PCADDR (FD8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
43
Port C Control
PCCTL (FD9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Control[7:0]
Provides Access to Port Sub-
Registers
Port C Input Data
PCIN (FDAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Input Data [7:0]
Port C Output Data
PCOUT (FDBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Output Data [7:0]
Port D Address
PDADDR (FDCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port D Control
PDCTL (FDDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Control[7:0]
Provides Access to Port Sub-
Registers
Port D Input Data
PDIN (FDE H- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Input Data [7:0]
Port D Output Data
PDOUT (FDFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Output Data [7:0]
Port E Address
PEADDR (FE0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port E Control
PECTL (FE1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Control[7:0]
Provides Access to Port Sub-
Registers
Port E Input Data
PEIN (FE2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Input Data [7:0]
Port E Output Data
PEOUT (FE3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Output Data [7:0]
Port F Address
PFADDR (FE4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
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PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
44
Port F Control
PFCTL (FE5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Control[7:0]
Provides Access to Port Sub-
Registers
Port F Input Data
PFIN (FE6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Input Data [7:0]
Port F Output Data
PFOUT (FE7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Output Data [7:0]
Port G Address
PGADDR (FE8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port G Control
PGCTL (FE9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Control[7:0]
Provides Access to Port Sub-
Registers
Port G Input Data
PGIN (FEAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Input Data [7:0]
Port G Output Data
PGOUT (FEBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Output Data [7:0]
Port H Address
PHADDR (FECH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = Stop Mode Recovery enable
06H-FFH = No function
Port H Control
PHCTL (FEDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Control [3:0]
Provides Access to Port Sub-
Registers
Reserved
Port H Input Data
PHIN (FEEH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Input Data [3:0]
Reserved
Port H Output Data
PHOUT (FEFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Output Data [3:0]
Reserved
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
45
Watchdog Timer Control
WDTCTL (FF0H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SM Configuration Indicator
Reserved
EXT
0 = Reset not generated by RESET
pin
1 = Reset generated by RESET pin
WDT
0 = WDT timeout has not occurred
1 = WDT timeout occurred
STOP
0 = SMR has not occurred
1 = SMR has occurred
POR
0 = POR has not occurred
1 = POR has occurred
Watchdog Timer Reload Upper Byte
WDTU (FF1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [23:16]
Watchdog Timer Reload Middle Byte
WDTH (FF2 H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [15:8]
Watchdog Timer Reload Low Byte
WDTL (FF3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [7:0]
Flash Control
FCTL (FF8H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Command
73H = First unlock command
8CH = Second unlock command
95H = Page erase command
63H = Mass erase command
5EH = Flash Sector Protect reg
select
Flash Status
FSTAT (FF8H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Controller Status
00_0000 = Flash controller locked
00_0001 = First unlock received
00_0010 = Second unlock received
00_0011 = Flash controller unlocked
00_0100 = Flash Sector Protect
register
selected
00_1xxx = Programming in progress
01_0xxx = Page erase in progress
10_0xxx = Mass erase in progress
Reserved
Page Select
FPS (FF9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Page Select [6:0]
Identifies the Flash memory page for
Page Erase operation.
Information Area Enable
0 = Information Area access is
disabled
1 = Information Area access is
enabled
Flash Sector Protect
FPROT (FF9H - Read/Write to 1’s)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Sector Protect [7:0]
0 = Sector can be programmed or
erased from user code
1 = Sector is protected and cannot
be
programmed or erased from
user
code
Flash Frequency High Byte
FFREQH (FFAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [15:8]
Flash Frequency Low Byte
FFREQL (FFBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [7:0]
E
PS019919-1207 Control Register Summary
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
46
Flags
FLAGS (FFC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
F1 - User Flag 1
F2 - User Flag 2
H - Half Carry
D - Decimal Adjust
V - Overflow Flag
S - Sign Flag
Z - Zero Flag
C - Carry Flag
Register Pointer
RP (FFDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Working Register Page Address
Working Register Group Address
Stack Pointer High Byte
SPH (FFEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [15:8]
Stack Pointer Low Byte
SPL (FFFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [7:0]
RESET zilog
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PS019919-1207 Reset and Stop Mode Recovery
47
Reset and Stop Mode Recovery
Overview
The Reset Controller within the Z8 Encore! XP 64K Series Flash Microcontrollers con-
trols Reset and Stop Mode Recovery operation. In typical operation, the following events
cause a Reset to occur:
Power-On Reset
Voltage Brownout
Watchdog Timer time-out (when configured via the WDT_RES Option Bit to initiate
a Reset)
External RESET pin assertion
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the 64K Series devices are in STOP mode, a Stop Mode Recovery is initiated by
either of the following:
Watchdog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The 64K Series provides two different types of reset operation (system reset and Stop
Mode Recovery). The type of Reset is a function of both the current operating mode of the
64K Series devices and the source of the Reset. Table 8 lists the types of Reset and their
operating characteristics.
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
48
System Reset
During a system reset, the 64K Series devices are held in Reset for 66 cycles of the
Watchdog Timer oscillator followed by 16 cycles of the system clock. At the beginning of
Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run. The system clock begins
operating following the Watchdog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer,
Register Pointer, and Flags) and general-purpose RAM are undefined following Reset.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following pro-
vides more detailed information on the individual Reset sources. A Power-On Reset/Volt-
age Brownout event always takes priority over all other possible reset sources to ensure a
full system reset occurs.
Table 8. Reset and Stop Mode Recovery Characteristics and Latency
Reset Type
Reset Characteristics and Latency
Control Registers eZ8 CPU Reset Latency (Delay)
System reset Reset (as applicable) Reset 66 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode
Recovery
Unaffected, except
WDT_CTL register
Reset 66 WDT Oscillator cycles + 16 System Clock cycles
RESET RESET
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
49
Power-On Reset
Each device in the 64K Series contains an internal Power-On Reset circuit. The POR cir-
cuit monitors the supply voltage and holds the device in the Reset state until the supply
voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage
threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the Watchdog
Timer oscillator. After the POR counter times out, the XTAL Counter is enabled to count a
total of 16 system clock pulses. The devices are held in the Reset state until both the POR
Counter and XTAL counter have timed out. After the 64K Series devices exit the Power-
On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the
POR status bit in the Watchdog Timer Control (WDTCTL) register is set to 1.
Figure 8 displays Power-On Reset operation. For the POR threshold voltage (VPOR), see
Electrical Characteristics on page 215.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode Reset Source Reset Type
NORMAL or HALT
modes
Power-On Reset/Voltage
Brownout
system reset
Watchdog Timer time-out
when configured for Reset
system reset
RESET pin assertion system reset
On-Chip Debugger initiated Reset
(OCDCTL[0] set to 1)
system reset except the On-Chip Debugger is
unaffected by the reset
STOP mode Power-On Reset/Voltage
Brownout
system reset
RESET pin assertion system reset
DBG pin driven Low system reset
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
50
Figure 8. Power-On Reset Operation
Voltage Brownout Reset
The devices in the 64K Series provide low Voltage Brownout protection. The VBO circuit
senses when the supply voltage drops to an unsafe level (below the VBO threshold
voltage) and forces the device into the Reset state. While the supply voltage remains
below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in
the Reset state.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices
progress through a full system reset sequence, as described in the Power-On Reset section.
Following Power-On Reset, the POR status bit in the Watchdog Timer Control
(WDTCTL) register is set to 1. Figure 9 displays Voltage Brownout operation. For the
VBO and POR threshold voltages (VVBO and VPOR), see Electrical Characteristics on
page 215.
The Voltage Brownout circuit can be either enabled or disabled during STOP mode. Oper-
ation during STOP mode is set by the VBO_AO Option Bit. For information on configuring
VBO_AO, see Option Bits page 195.
VCC = 0.0 V
VCC = 3.3 V
VPOR
VVBO
Primary
Oscillator
Internal RESET
signal
Program
Execution
Oscillator
Start-up
XTAL
WDT Clock
POR
counter delaycounter delay
Not to Scale
RESET RESET RESET RESET RESET RESET
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
51
Figure 9. Voltage Brownout Reset Operation
Watchdog Timer Reset
If the device is in normal or HALT mode, the Watchdog Timer can initiate a system reset
at time-out if the WDT_RES Option Bit is set to 1. This capability is the default
(unprogrammed) setting of the WDT_RES Option Bit. The WDT status bit in the WDT
Control register is set to signify that the reset was initiated by the Watchdog Timer.
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
cycles, the devices progress through the system reset sequence. While the RESET input
pin is asserted Low, the 64K Series devices continue to be held in the Reset state. If the
RESET pin is held Low beyond the system reset time-out, the devices exit the Reset state
immediately following RESET pin deassertion. Following a system reset initiated by the
external RESET pin, the EXT status bit in the Watchdog Timer Control (WDTCTL) regis-
ter is set to 1.
VCC = 3.3 V
VPOR
VVBO
Internal RESET
Signal
Program
Execution
Program
Execution
Voltage
Brownout
VCC = 3.3 V
Primary
Oscillator
WDT Clock
XTALPOR
Counter DelayCounter Delay
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
52
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RST bit automatically clears during the system
reset. Following the system reset the POR bit in the WDT Control register is set.
Stop Mode Recovery
STOP mode is entered by the eZ8 executing a STOP instruction. For detailed STOP mode
information, see Low-Power Modes on page 47. During Stop Mode Recovery, the devices
are held in reset for 66 cycles of the Watchdog Timer oscillator followed by 16 cycles of
the system clock. Stop Mode Recovery only affects the contents of the Watchdog Timer
Control register. Stop Mode Recovery does not affect any other values in the Register File,
including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and
general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer
Control Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting
actions.
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the 64K Series devices are configured to respond to interrupts, the eZ8 CPU services the
Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence.
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source Action
STOP mode Watchdog Timer time-out
when configured for Reset
Stop Mode Recovery
Watchdog Timer time-out
when configured for interrupt
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Data transition on any GPIO Port pin
enabled as a Stop Mode Recovery
source
Stop Mode Recovery
zilog
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
53
Stop Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. The GPIO Stop
Mode Recovery signals are filtered to reject pulses less than 10 ns (typical) in duration. In
the Watchdog Timer Control register, the STOP bit is set to 1.
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The
Port Input Data registers record the Port transition only if the signal stays on
the Port pin through the end of the Stop Mode Recovery delay. Thus, short puls-
es on the Port pin can initiate Stop Mode Recovery without being written to the
Port Input Data register or without initiating an interrupt (if enabled for that
pin).
Caution:
zilog‘
PS019919-1207 Reset and Stop Mode Recovery
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
54
zilog
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PS019919-1207 Low-Power Modes
55
Low-Power Modes
Overview
The 64K Series products contain power-saving features. The highest level of power reduc-
tion is provided by STOP mode. The next level of power reduction is provided by the
HALT mode.
STOP Mode
Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In
STOP mode, the operating characteristics are:
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low.
System clock is stopped.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
The Watchdog Timer and its internal RC oscillator continue to operate, if enabled for
operation during STOP mode.
The Voltage Brownout protection circuit continues to operate, if enabled for operation
in STOP mode using the associated Option Bit.
All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND), the Voltage Brownout protection
must be disabled, and the Watchdog Timer must be disabled. The devices can be brought
out of STOP mode using Stop Mode Recovery. For more information on Stop Mode
Recovery, see Reset and Stop Mode Recovery on page 47.
STOP mode must not be used when driving the 64K Series devices with an
external clock driver source.
Caution:
RESET zilog
PS019919-1207 Low-Power Modes
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
56
HALT Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
Primary crystal oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program Counter stops incrementing.
Watchdog Timers internal RC oscillator continues to operate.
The Watchdog Timer continues to operate, if enabled.
All other on-chip peripherals continue to operate.
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brownout Reset
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
28x242i 40-pin [7:0] [7:0] [6:0] @, : 1:0] 28x242i 44-pin [7:0] [7:0] [7:0] [6:0] ' Z ’ : Z8X2422 64- and 68—pin [7:0] [7:0] [7:0] [7:0] [7:01 m E m 28x322i 40-pin [7:0] [7:0] [6:0] @, i ' ’ : 1:0] 28x322i 44-pin [7:0] [7:0] [7:0] [6:0] ' Z ’ : Z8X3222 64- and 68—pin [7:0] [7:0] [7:0] [7:0] [7:01 m E m 28x452i 40-pin [7:0] [7:0] [6:0] @, i ' ’ : 1:0] 28x452i 44-pin [7:0] [7:0] [7:0] [6:0] ' Z ’ : Z8X4822 64- and 68—pin [7:0] [7:0] [7:0] [7:0] [7:01 m E m
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
PS019919-1207 General-Purpose I/O
57
General-Purpose I/O
Overview
The 64K Series products support a maximum of seven 8-bit ports (Ports A–G) and
one 4-bit port (Port H) for general-purpose input/output (GPIO) operations. Each port con-
sists of control and data registers. The GPIO control registers are used to determine data
direction, open-drain, output drive current and alternate pin functions. Each port pin is
individually programmable. All ports (except B and H) support 5 V-tolerant inputs.
GPIO Port Availability By Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
Z8X1621 40-pin [7:0] [7:0] [6:0] [6:3,
1:0]
----
Z8X1621 44-pin [7:0] [7:0] [7:0] [6:0] ----
Z8X1622 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X2421 40-pin [7:0] [7:0] [6:0] [6:3,
1:0]
----
Z8X2421 44-pin [7:0] [7:0] [7:0] [6:0] ----
Z8X2422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X3221 40-pin [7:0] [7:0] [6:0] [6:3,
1:0]
----
Z8X3221 44-pin [7:0] [7:0] [7:0] [6:0] ----
Z8X3222 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X4821 40-pin [7:0] [7:0] [6:0] [6:3,
1:0]
----
Z8X4821 44-pin [7:0] [7:0] [7:0] [6:0] ----
Z8X4822 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
PS019919-1207 General-Purpose I/O
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
58
Architecture
Figure 10 displays a simplified block diagram of a GPIO port pin. In Figure 10, the ability
to accommodate alternate functions and variable port current drive strength are not illus-
trated.
Figure 10. GPIO Port Pin Block Diagram
Z8X4823 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Z8X6421 40-pin [7:0] [7:0] [6:0] [6:3,
1:0]
----
Z8X6421 44-pin [7:0] [7:0] [7:0] [6:0] ----
Z8X6422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X6423 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Table 11. Port Availability by Device and Package Type (Continued)
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
DQ
DQ
GND
VDD
Port Output Control
Port Data Direction
Port Output
Data Register
Port Input
Data Register
Port
Pin
DATA
Bus
System
Clock
System
Clock
Schmitt-Trigger
P36 ANA6 ADC Analog Input 6 PB7 ANA7 ADC Analog Input 7
PS019919-1207 General-Purpose I/O
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
59
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A–H Alternate Function sub-registers configure these pins for either general-purpose
I/O or alternate function operation. When a pin is configured for alternate function, control
of the port pin direction (input/output) is passed from the Port A–H Data Direction regis-
ters to the alternate function assigned to this pin. Table 12 lists the alternate functions
associated with each port pin.
Table 12. Port Alternate Function Mapping
Port Pin Mnemonic Alternate Function Description
Port A PA0 T0IN Timer 0 Input
PA1 T0OUT Timer 0 Output
PA2 DE0 UART 0 Driver Enable
PA3 CTS0 UART 0 Clear to Send
PA4 RXD0/IRRX0 UART 0/IrDA 0 Receive Data
PA5 TXD0/IRTX0 UART 0/IrDA 0 Transmit Data
PA6 SCL I2C Clock (automatically open-drain)
PA7 SDA I2C Data (automatically open-drain)
Port B PB0 ANA0 ADC Analog Input 0
PB1 ANA1 ADC Analog Input 1
PB2 ANA2 ADC Analog Input 2
PB3 ANA3 ADC Analog Input 3
PB4 ANA4 ADC Analog Input 4
PB5 ANA5 ADC Analog Input 5
PB6 ANA6 ADC Analog Input 6
PB7 ANA7 ADC Analog Input 7
PHZ ANA10 ADC Analog Inpm 10 PH3 ANA11 ADC Analog Input 11
PS019919-1207 General-Purpose I/O
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
60
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). For more information on interrupts using the GPIO pins, see Interrupt
Controller on page 67.
Port C PC0 T1IN Timer 1 Input
PC1 T1OUT Timer 1 Output
PC2 SS SPI Slave Select
PC3 SCK SPI Serial Clock
PC4 MOSI SPI Master Out/Slave In
PC5 MISO SPI Master In/Slave Out
PC6 T2IN Timer 2 In
PC7 T2OUT Timer 2 Out
Port D PD0 T3IN Timer 3 In (unavailable in 44-pin packages)
PD1 T3OUT Timer 3 Out (unavailable in 44-pin packages)
PD2 N/A No alternate function
PD3 DE1 UART 1 Driver Enable
PD4 RXD1/IRRX1 UART 1/IrDA 1 Receive Data
PD5 TXD1/IRTX1 UART 1/IrDA 1 Transmit Data
PD6 CTS1 UART 1 Clear to Send
PD7 RCOUT Watchdog Timer RC Oscillator Output
Port E PE[7:0] N/A No alternate functions
Port F PF[7:0] N/A No alternate functions
Port G PG[7:0] N/A No alternate functions
Port H PH0 ANA8 ADC Analog Input 8
PH1 ANA9 ADC Analog Input 9
PH2 ANA10 ADC Analog Input 10
PH3 ANA11 ADC Analog Input 11
Table 12. Port Alternate Function Mapping (Continued)
Port Pin Mnemonic Alternate Function Description
PxDD Da‘a Direction PxAF m PxOC W PXDD W W W Enable
PS019919-1207 General-Purpose I/O
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Product Specification
61
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 13 lists these Port registers. Use the Port A–H Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Port A–H Address Registers
The Port A–H Address registers select the GPIO Port functionality accessible through the
Port A–H Control registers. The Port A–H Address and Control registers combine to pro-
vide access to all GPIO Port control (Table 14).
Table 13. GPIO Port Registers and Sub-Registers
Port Register Mnemonic Port Register Name
PxADDR Port AH Address Register
(Selects sub-registers)
PxCTL Port AH Control Register
(Provides access to sub-registers)
PxIN Port AH Input Data Register
PxOUT Port AH Output Data Register
Port Sub-Register Mnemonic Port Register Name
PxDD Data Direction
PxAF Alternate Function
PxOC Output Control (Open-Drain)
PxDD High Drive Enable
PxSMRE Stop Mode Recovery Source
Enable
Table 14. Port AH GPIO Address Registers (PxADDR)
BITS 7 6 5 4 3 2 1 0
FIELD PADDR[7:0]
RESET 00H
R/W R/W
ADDR FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
00H No function. F'rowdes some protection against aCCidental Pon reconfiguration 03H Ouipul Control (Open-Drain) 06H-FFH No function
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Product Specification
62
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
Port A–H Control Registers
The Port A–H Control registers set the GPIO port operation. The value in the correspond-
ing Port A–H Address register determines the control sub-registers accessible using the
Port A–H Control register (Table 15).
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
PADDR[7:0]
Port Control sub-register accessible using the Port AH Control
Registers
00H No function. Provides some protection against accidental Port
reconfiguration
01H Data Direction
02H Alternate Function
03H Output Control (Open-Drain)
04H High Drive Enable
05H Stop Mode Recovery Source Enable
06H-FFH No function
Table 15. Port AH Control Registers (PxCTL)
BITS 7 6 5 4 3 2 1 0
FIELD PCTL
RESET 00H
R/W R/W
ADDR FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
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Port AH Data Direction Sub-Registers
The Port A–H Data Direction sub-register is accessed through the Port A–H Control regis-
ter by writing 01H to the Port A–H Address register (Table 16).
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A–H Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–H Input Data
Register. The output driver is tri-stated.
Port AH Alternate Function Sub-Registers
The Port A–H Alternate Function sub-register (Table 17) is accessed through the
Port A–H Control register by writing 02H to the Port A–H Address register. The Port A–H
Alternate Function sub-registers select the alternate functions for the selected pins. To
determine the alternate function associated with each port pin, see GPIO Alternate Func-
tions on page 59.
Do not enable alternate function for GPIO port pins which do not have an as-
sociated alternate function. Failure to follow this guideline may result in un-
predictable operation.
Table 16. Port AH Data Direction Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
RESET 1
R/W R/W
ADDR If 01H in Port AH Address Register, accessible through Port AH Control Register
Table 17. Port AH Alternate Function Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 0
R/W R/W
ADDR If 02H in Port AH Address Register, accessible through Port AH Control Register
Caution:
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AF[7:0]—Port Alternate Function enabled
0 = The port pin is in NORMAL mode and the DDx bit in the Port A–H Data Direction
sub-register determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the
alternate function.
Port AH Output Control Sub-Registers
The Port A–H Output Control sub-register (Table 18) is accessed through the
Port A–H Control register by writing 03H to the Port A–H Address register. Setting the
bits in the Port A–H Output Control sub-registers to 1 configures the specified port pins
for open-drain operation. These sub-registers affect the pins directly and, as a result, alter-
nate functions are also affected.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and disables the drains if set
to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Port AH High Drive Enable Sub-Registers
The Port A–H High Drive Enable sub-register (Table 19) is accessed through the Port A–
H Control register by writing 04H to the Port A–H Address register. Setting the bits in the
Port A–H High Drive Enable sub-registers to 1 configures the specified port pins for high
current output drive operation. The Port A–H High Drive Enable sub-register affects the
pins directly and, as a result, alternate functions are also affected.
Table 18. Port AH Output Control Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
RESET 0
R/W R/W
ADDR If 03H in Port AH Address Register, accessible through Port AH Control Register
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PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port AH Stop Mode Recovery Source Enable Sub-Registers
The Port A–H Stop Mode Recovery Source Enable sub-register (Table 20) is accessed
through the Port A–H Control register by writing 05H to the Port A–H Address register.
Setting the bits in the Port A–H Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this
pin during STOP mode do not initiate Stop Mode Recovery.
1 = The Port pin is configured as a Stop Mode Recovery source. Any logic transition
on this pin during STOP mode initiates Stop Mode Recovery.
Table 19. Port AH High Drive Enable Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
RESET 0
R/W R/W
ADDR If 04H in Port A-H Address Register, accessible through Port A-H Control Register
Table 20. Port AH Stop Mode Recovery Source Enable Sub-Registers
BITS 7 6 5 4 3 2 1 0
FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 0
R/W R/W
ADDR If 05H in Port AH Address Register, accessible through Port AH Control Register
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Port A–H Input Data Registers
Reading from the Port A–H Input Data registers (Table 21) returns the sampled values
from the corresponding port pins. The Port A–H Input Data registers are Read-only.
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Port A–H Output Data Register
The Port A–H Output Data register (Table 22) writes output data to the pins.
POUT[7:0]—Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alter-
nate function operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by
setting the corresponding Port Output Control register bit to 1.
Table 21. Port AH Input Data Registers (PxIN)
BITS 7 6 5 4 3 2 1 0
FIELD PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
ADDR FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
Table 22. Port AH Output Data Register (PxOUT)
BITS 7 6 5 4 3 2 1 0
FIELD POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
ADDR FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
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Interrupt Controller
Overview
The interrupt controller on the 64K Series products prioritizes the interrupt requests from
the on-chip peripherals and the GPIO port pins. The features of the interrupt controller
include the following:
24 unique interrupt vectors:
12 GPIO port pin interrupt sources
12 on-chip peripheral interrupt sources
Flexible GPIO interrupts
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control
information between the CPU and the interrupting peripheral. When the service routine is
completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information on interrupt
servicing by the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) available for
download at www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most-significant byte (MSB) at the even Program Memory address and the
least-significant byte (LSB) at the following odd Program Memory address.
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Table 23. Interrupt Vectors in Order of Priority
Priority
Program Memory
Vector Address Interrupt Source
Highest 0002H Reset (not an interrupt)
0004H Watchdog Timer (see Watchdog Timer on
page 97)
0006H Illegal Instruction Trap (not an interrupt)
0008H Timer 2
000AH Timer 1
000CH Timer 0
000EH UART 0 receiver
0010H UART 0 transmitter
0012H I2C
0014H SPI
0016H ADC
0018H Port A7 or Port D7, rising or falling input edge
001AH Port A6 or Port D6, rising or falling input edge
001CH Port A5 or Port D5, rising or falling input edge
001EH Port A4 or Port D4, rising or falling input edge
0020H Port A3 or Port D3, rising or falling input edge
0022H Port A2 or Port D2, rising or falling input edge
0024H Port A1 or Port D1, rising or falling input edge
0026H Port A0 or Port D0, rising or falling input edge
0028H Timer 3 (not available in 44-pin packages)
002AH UART 1 receiver
002CH UART 1 transmitter
002EH DMA
0030H Port C3, both input edges
0032H Port C2, both input edges
0034H Port C1, both input edges
Lowest 0036H Port C0, both input edges
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Architecture
Figure 11 displays a block diagram of the interrupt controller.
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
Executing an Enable Interrupt (EI) instruction.
Executing an Return from Interrupt (IRET) instruction.
Writing a 1 to the IRQE bit in the Interrupt Control register.
Interrupts are globally disabled by any of the following actions:
Execution of a Disable Interrupt (DI) instruction.
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller.
Writing a 0 to the IRQE bit in the Interrupt Control register.
Reset.
Vector
IRQ Request
High
Priority
Medium
Priority
Low
Priority
Priority
Mux
Interrupt Request Latches and Control
Port Interrupts
Internal Interrupts
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Executing a Trap instruction.
Illegal Instruction trap.
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then interrupt priority would be assigned from highest to lowest as specified in
Table 23 on page 68. Level 3 interrupts always have higher priority than Level 2 interrupts
which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt
priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23 on
page 68. Reset, Watchdog Timer interrupt (if enabled), and Illegal Instruction Trap always
have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the Interrupt Request register is cleared until the next interrupt
occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise
clears the interrupt request.
The following style of coding to clear bits in the Interrupt Request registers is
NOT recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to clear bits in
the Interrupt Request 0 register is recommended:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
Caution:
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The following style of coding to generate software interrupts by setting bits in
the Interrupt Request registers is NOT recommended. All incoming interrupts
that are received between execution of the first LDX command and the last
LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to set bits in the
Interrupt Request registers is recommended:
Good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
Table 24. Interrupt Request 0 Register (IRQ0)
BITS 7 6 5 4 3 2 1 0
FIELD T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI
RESET 0
R/W R/W
ADDR FC0H
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T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I2CI— I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 25. Interrupt Request 1 Register (IRQ1)
BITS 7 6 5 4 3 2 1 0
FIELD PAD7I PAD6I PAD5I PAD4I PAD3I PAD2I PAD1I PAD0I
RESET 0
R/W R/W
ADDR FC3H
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PADxI—Port A or Port D Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
where x indicates the specific GPIO Port pin number (0 through 7). For each pin, only 1 of
either Port A or Port D can be enabled for interrupts at any one time. Port selection (A or
D) is determined by the values in the Interrupt Port Select Register.
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 26) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
T3I—Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
U1RXI—UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
U1TXI—UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
DMAI—DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
PCxI—Port C Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Table 26. Interrupt Request 2 Register (IRQ2)
BITS 7 6 5 4 3 2 1 0
FIELD T3I U1RXI U1TXI DMAI PC3I PC2I PC1I PC0I
RESET 0
R/W R/W
ADDR FC6H
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where x indicates the specific GPIO Port C pin number (0 through 3).
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (see Table 28 and Table 29 on page 75) form
a priority encoded enabling for interrupts in the Interrupt Request 0 register. Priority is
generated by setting bits in each register. Table 27 describes the priority control for IRQ0.
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 27. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]IRQ0ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
1 1 Level 3 High
Note: where x indicates the register bits from 0 through 7.
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS 7 6 5 4 3 2 1 0
FIELD T2ENH T1ENH T0ENH U0RENH U0TENH I2CENH SPIENH ADCENH
RESET 0
R/W R/W
ADDR FC1H
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T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I2C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (see Table 31 and Table 32 on page 76) form
a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is
generated by setting bits in each register. Table 30 describes the priority control for IRQ1.
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS 7 6 5 4 3 2 1 0
FIELD T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
RESET 0
R/W R/W
ADDR FC2H
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]IRQ1ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
1 1 Level 3 High
Note: where x indicates the register bits from 0 through 7.
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PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit.
For selection of either Port A or Port D as the interrupt source, see Interrupt Port Select
Register on page 78.
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
For selection of either Port A or Port D as the interrupt source, see Interrupt Port Select
Register on page 78.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (see Table 34 and Table 35 on page 77) form
a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is
generated by setting bits in each register. Table 33 describes the priority control for IRQ2.
Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS 7 6 5 4 3 2 1 0
FIELD PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC4H
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS 7 6 5 4 3 2 1 0
FIELD PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC5H
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]IRQ2ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
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T3ENH—Timer 3 Interrupt Request Enable High Bit
U1RENH—UART 1 Receive Interrupt Request Enable High Bit
U1TENH—UART 1 Transmit Interrupt Request Enable High Bit
DMAENH—DMA Interrupt Request Enable High Bit
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
T3ENL—Timer 3 Interrupt Request Enable Low Bit
U1RENL—UART 1 Receive Interrupt Request Enable Low Bit
U1TENL—UART 1 Transmit Interrupt Request Enable Low Bit
DMAENL—DMA Interrupt Request Enable Low Bit
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
1 1 Level 3 High
Note: where x indicates the register bits from 0 through 7.
Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS 7 6 5 4 3 2 1 0
FIELD T3ENH U1RENH U1TENH DMAENH C3ENH C2ENH C1ENH C0ENH
RESET 0
R/W R/W
ADDR FC7H
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS 7 6 5 4 3 2 1 0
FIELD T3ENL U1RENL U1TENL DMAENL C3ENL C2ENL C1ENL C0ENL
RESET 0
R/W R/W
ADDR FC8H
Table 33. IRQ2 Enable and Priority Encoding (Continued)
IRQ2ENH[x]IRQ2ENL[x] Priority Description
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C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 36) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
IESx—Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of
the edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 37) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as
interrupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 36. Interrupt Edge Select Register (IRQES)
BITS 7 6 5 4 3 2 1 0
FIELD IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 0
R/W R/W
ADDR FCDH
Table 37. Interrupt Port Select Register (IRQPS)
BITS 7 6 5 4 3 2 1 0
FIELD PAD7SPAD6SPAD5SPAD4SPAD3SPAD2SPAD1SPAD0S
RESET 0
R/W R/W
ADDR FCEH
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PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all
interrupts.
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of
a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of
an interrupt request, or Reset.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved—Must be 0.
Table 38. Interrupt Control Register (IRQCTL)
BITS 7 6 5 4 3 2 1 0
FIELD IRQE Reserved
RESET 0
R/W R/W R
ADDR FCFH
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Timers
Overview
The 64K Series products contain up to four 16-bit reloadable timers that can be used for
timing, event counting, or generation of pulse width modulated signals. The timers’ fea-
tures include:
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I2C peripherals may also be used to provide basic timing function-
ality. For information on using the Baud Rate Generators as timers, see the respective
serial communication peripheral. Timer 3 is unavailable in the 44-pin package devices.
Architecture
Figure 12 displays the architecture of the timers.
[:44
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Figure 12. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and
stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is desired to have the Timer Output make a permanent state change upon
16-Bit
PWM/Compare
16-Bit Counter
with Prescaler
16-Bit
Reload Register
Timer
Control
Compare Compare
Interrupt,
PWM,
and
Timer Output
Control
Timer
Timer
Timer Block
System
Timer
Data
Block
Interrupt
Output
Control
Bus
Clock
Input
Gate
Input
Capture
Input
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One-Shot time-out, first set the TPOL bit in the Timer Control 1 Register to the start value
before beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the oppo-
site bit value.
Follow the steps below for configuring a timer for ONE-SHOT mode and initiating the
count:
1. Write to the Timer Control 1 register to:
Disable the timer
Configure the timer for ONE-SHOT mode
Set the prescale value
If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Reload value
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function
6. Write to the Timer Control 1 register to enable the timer and initiate counting
In ONE-SHOT mode, the system clock always provides the timer input. The timer period
is given by the following equation:
CONTINUOUS Mode
In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer
Output alternate function is enabled, the Timer Output pin changes state (from Low to
High or from High to Low) upon timer Reload.
Follow the steps below for configuring a timer for CONTINUOUS mode and initiating the
count:
1. Write to the Timer Control 1 register to:
Disable the timer
Configure the timer for CONTINUOUS mode
Set the prescale value
If using the Timer Output alternate function, set the initial output level (High or
Low)
ONE-SHOT Mode Time-Out Period (s) Reload Value Start Value()Prescale×
System Clock Frequency (Hz)
-------------------------------------------------------------------------------------------------=
zilog
PS019919-1207 Timers
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
84
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H), affecting only the first pass in CONTINUOUS mode. After the first timer
Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In CONTINUOUS mode, the system clock always provides the timer input. The timer
period is given by the following equation:
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the ONE-SHOT mode equation must be used to determine the first time-out
period.
COUNTER Mode
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the
Timer Control 1 Register selects whether the count occurs on the rising edge or the falling
edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled.
The input frequency of the Timer Input signal must not exceed one-fourth the
system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
Follow the steps below for configuring a timer for COUNTER mode and initiating the
count:
1. Write to the Timer Control 1 register to:
Disable the timer
Configure the timer for COUNTER mode
CONTINUOUS Mode Time-Out Period (s) Reload Value Prescale×
System Clock Frequency (Hz)
------------------------------------------------------------------------=
Caution:
zilog‘
PS019919-1207 Timers
Z8 Encore! XP® 64K Series Flash Microcontrollers
Product Specification
85
Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in COUNTER mode. After the first timer Reload in
COUNTER mode, counting always begins at the reset value of 0001H. Generally, in
COUNTER mode the Timer High and Low Byte registers must be written with the
value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.