TP65H035G4WSQA Datasheet by Transphorm

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TP65H035G4WSQA

650V SuperGaN® FET in TO-247 (source tab)

Features

 AEC-Q101 qualified GaN technology

 Dynamic RDS(on)eff production tested

 Robust design, defined by

— Wide gate safety margin

— Transient over-voltage capability

 Enhanced inrush current capability

 Very low QRR

 Reduced crossover loss

Benefits

 Enables AC-DC bridgeless totem-pole PFC designs

— Increased power density

— Reduced system size and weight

— Overall lower system cost

 Achieves increased efficiency in both hard- and soft-

switched circuits

 Easy to drive with commonly-used gate drivers

 GSD pin layout improves high speed design

Applications

 Automotive

 Datacom

 Broad industrial

 PV inverter

 Servo motor

Description

The TP65H035G4WSQS 650V, 35 m gallium nitride (GaN)

FET is a normally-off device using Transphorm’s Gen IV

platform. It combines a state-of-the-art high voltage GaN

HEMT with a low voltage silicon MOSFET to offer superior

reliability and performance.

The Gen IV SuperGaN® platform uses advanced epi and

patented design technologies to simplify manufacturability

while improving efficiency over silicon via lower gate charge,

output capacitance, crossover loss, and reverse recovery

charge.

Related Literature

 AN0009: Recommended External Circuitry for GaN FETs

 AN0003: Printed Circuit Board Layout and Probing

 AN0010: Paralleling GaN FETs

TP65H035G4WSQA

TO-247

(top view)

Ordering Information

Part Number Package Package

Configuration

TP65H035G4WSQA 3 lead TO-247 Source

Key Specifications

VDSS (V) 650

VDSS(TR)(V)* 800

RDS(on)eff (m) max** 41

QRR (nC) typ 150

*Pulse condition, see note on Page2

* *Dynamic on-resistance; see Figures 19 and 20

QG (nC) typ 22

Cascode Device Structure Cascode Schematic Symbol

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Thermal Resistance

Symbol Parameter Typical Unit

RJC Junction-to-case 0.8 °C/W

RJA Junction-to-ambient 40 °C/W

Absolute Maximum Ratings (Tc=25°C unless otherwise stated.)

Symbol Parameter Limit Value Unit

VDSS Drain to source voltage (TJ = -55°C to 175°C) 650

VDSS(TR) Transient drain to source voltage a 800

VGSS Gate to source voltage ±20

PD Maximum power dissipation @TC=25°C 187 W

Continuous drain current @TC=25°C b 47.2 A

Continuous drain current @TC=100°C b 33.4 A

IDM Pulsed drain current (pulse width: 10µs) 240 A

TC Operating temperature Case -55 to +175 °C

TJ Junction -55 to +175 °C

TS Storage temperature -55 to +175 °C

TSOLD Soldering peak temperature C 260 °C

Notes:

a. In off-state, spike duty cycle D<0.01, spike duration <1µs, spike duration <30µs, nonrepetitive.

b. For increased stability at high current operation, see Circuit Implementation on page 3

c. For 10 sec., 1.6mm from the case

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Circuit Implementation

Recommended gate drive: (0V, 12V) with RG= 30

Required DC Link RC Snubber (RCDCL) a Recommended Switching Node

RC Snubber (RCSN)

[4.7nF + 5] x 2 See note b and c below

Notes:

a. RCDCL should be placed as close as possible to the drain pin

b. RCSN is needed only if RG is smaller than recommendations

c. If required, please use 10Ω+100pF

Gate Ferrite Bead (FB1)

200 — 270 at 100MHz

Simplified Half-bridge Schematic

Layout Recommendations: ( See also AN0009)

Gate Loop:

 Gate Driver: SiLab Si823x/Si827x

 Keep gate loop compact

 Minimize coupling with power loop

Power loop:

 Minimize power loop path inductance

 Minimize switching node coupling with high and low power plane

 Add DC bus snubber to reduce to voltage ringing

 Add Switching node snubber for high current operation

Gate threshold voltage temperature co- V 5:400V, V 5=0V to 12V, Notes: transphzgrm

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Electrical Parameters (TJ=25°C unless otherwise stated)

Symbol Parameter Min Typ Max Unit Test Conditions

Forward Device Characteristics

VDSS(BL) Drain-source voltage 650 — — V VGS=0V

VGS(th) Gate threshold voltage 3.3 4 4.8 V

VDS=VGS, ID=1mA

VGS(th)/TJ Gate threshold voltage temperature co-

efficient — -6.5 — mV/°C

RDS(on)eff Drain-source on-resistance

— 35 41

m

VGS=10V, ID=30A

— 84 — VGS=10V, ID=30A, TJ=175°C

IDSS Drain-to-source leakage current

— 3 30

µA

VDS=650V, VGS=0V

— 30 — VDS=650V, VGS=0V, TJ=175°C

IGSS

Gate-to-source forward leakage current — — 400

VGS=20V

Gate-to-source reverse leakage current — — -400 VGS=-20V

CISS Input capacitance — 1500 —

pF VGS=0V, VDS=400V, f=1MHz

COSS Output capacitance — 147 —

CRSS Reverse transfer capacitance — 5 —

CO(er) Output capacitance, energy related b — 220 —

pF VGS=0V, VDS=0V to 400V

CO(tr) Output capacitance, time related c — 380 —

QG Total gate charge — 22 —

nC VDS=400V, VGS=0V to 10V,

ID=32A

QGS Gate-source charge — 8.4 —

QGD Gate-drain charge — 6.6 —

QOSS Output charge — 150 — nC VGS=0V, VDS=0V to 400V

tD(on) Turn-on delay — 60 —

VDS=400V, VGS=0V to 12V,

RG=30, ID=32A, ZFB=240Ω at

100MHz (See Figure 15)

tR Rise time — 10 —

tD(off) Turn-off delay — 94 —

tF Fall time — 10 —

Eoff Turn off Energy — 82 — J

Eon Turn on Energy — 206 — J

Notes:

a. Dynamic on-resistance; see Figures 19 and 20 for test circuit and conditions

b. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V

c. Equivalent capacitance to give same charging time as VDS rises from 0V to 400V

VDS=400V, VGS=0V to 12V,

RG=30, ID=32A, ZFB=180 at

100MHz

V 5:0V, T =100"C transphzgrm

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Electrical Parameters (TJ=25°C unless otherwise stated)

Symbol Parameter Min Typ Max Unit Test Conditions

Reverse Device Characteristics

IS Reverse current — — 33.4 A

VGS=0V, TC=100°C

25% duty cycle

VSD Reverse voltage

— 1.8 —

VGS=0V, IS=32A

— 1.3 — VGS=0V, IS=16A

tRR Reverse recovery time — 59 — ns IS=32A, VDD=400V,

di/dt=1000A/ms

QRR Reverse recovery charge — 150 — nC

(di/dt)RM Reverse diode di/dt b — — 3200 A/µs

Circuit implementation and

parameters on page 3

Notes:

a. Includes dynamic RDS(on) effect

b. Reverse conduction di/dt will not exceed this max value with recommended RG.

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Figure 1. Typical Output Characteristics TJ=25°C

Parameter: VGS

Figure 2. Typical Output Characteristics TJ=175°C

Parameter: VGS

Typical Characteristics (TC=25°C unless otherwise stated)

Figure 3. Typical Transfer Characteristics

VDS=20V, parameter: TJ

Figure 4. Normalized On-resistance

ID=30A, VGS=10V

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Figure 5. Typical Capacitance

VGS=0V, f=1MHz

Figure 6. Typical COSS Stored Energy

Typical Characteristics (TC=25°C unless otherwise stated)

Figure 7. Typical QOSS

Figure 8. Typical Gate Charge

IDS=32A, VDS=400V

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Figure 9. Power Dissipation

Figure 10. Current Derating

Pulse width ≤ 10µs, VGS  10V

Typical Characteristics (TC=25°C unless otherwise stated)

Figure 11. Forward Characteristics of Rev. Diode

IS=f(VSD), parameter: TJ Figure 12. Transient Thermal Resistance

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Figure 13. Safe Operating Area TC=25°C Figure 14. Inductive Switching Loss

Rg=30Ω, VDS=400V

Typical Characteristics (TC=25°C unless otherwise stated)

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Figure 16. Switching Time Waveform Figure 15. Switching Time Test Circuit

(see circuit implementation on page 3

for methods to ensure clean switching)

Figure 17. Diode Characteristics Test Circuit Figure 18. Diode Recovery Waveform

DS(on)

DS(on)eff I

R

Test Circuits and Waveforms

Figure 19. Dynamic RDS(on)eff Test Circuit Figure 20. Dynamic RDS(on)eff Waveform

T s r Before ev application note Printed Circuit Board Layoutand Probing for GaN Power SWitches Minimize circuit Inductance by keeping traces snort, both In TWist the pins of T0-220 or TO-247 to accommodate GDS Minimize lead length of T0220 and T0-247 package when Use long traces in drive circuit, long lead length of the Use shortest sense loop for probing; attach the probe and its Use differential mode probe or probe ground clip With long AN0003 at transphorrnusa.comzdesign: transphzjrm

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Design Considerations

The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while

simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switches

requires adherence to specific PCB layout guidelines and probing techniques.

Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power

Switches. The table below provides some practical rules that should be followed during the evaluation.

When Evaluating Transphorm GaN Devices:

DO DO NOT

Minimize circuit inductance by keeping traces short, both in

the drive and power loop

Twist the pins of TO-220 or TO-247 to accommodate GDS

board layout

Minimize lead length of TO-220 and TO-247 package when

mounting to the PCB

Use long traces in drive circuit, long lead length of the

devices

Use shortest sense loop for probing; attach the probe and its

ground connection directly to the test points

Use differential mode probe or probe ground clip with long

wire

See AN0003: Printed Circuit Board Layout and Probing

GaN Design Resources

The complete technical library of GaN design tools can be found at transphormusa.com/design:

 Evaluation kits

 Application notes

 Design guides

 Simulation models

 Technical papers and presentations

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Mechanical 3 Lead TO-247 Package