NCP5603 Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2007
July, 2007 - Rev. 2
1Publication Order Number:
NCP5603/D
NCP5603
High Efficiency Charge Pump
Converter / White LED Driver
The NCP5603 is an integrated circuit dedicated to the medium
power White LED applications. The power conversion is achieved by
means of a charge pump structure, using two external ceramic
capacitors, making the system extremely tiny. The device supplies a
constant voltage to the load from a low battery voltage source. It is
particularly suited for the High Efficiency LED used in low cost, low
power applications, with high extended battery life.
Features
•Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V
•Automatic Operating Mode 1X, 1.5X and 2X Improves Efficiency
•Dimmable Output Current
•Up to 350 mA Output Pulsed Current
•Selectable Output Voltage
•High Efficiency Up To 90%
•Supports 2.5 kV ESD, Human Body Model
•Supports 200 V Machine Model ESD
•Low 40 mA Short Circuit Current
•Pb-Free Package is Available
Applications
•High Power LED
•Back Light Display
•High Power Flash
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DFN10, 3x3
MN SUFFIX
CASE 485C
5603 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb-Free Package
MARKING
DIAGRAM
5603
ALYWG
G
3
C2P
Vbat
2
C1P
Vout
8GND
9
10
C1N
(Top View)
1
Fsel 4
Vsel 5
7C2N
6EN
PIN CONNECTIONS
Device Package Shipping†
ORDERING INFORMATION
NCP5603MNR2 DFN10 3000/ Tape & Reel
NCP5603MNR2G DFN10
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3000/ Tape & Reel
(Note: Microdot may be in either location)
HHL "WW W 4 W" 1 1 1 ’K‘ \‘ ’6 _ 0‘ N m u: 9 u: u: hltp://onsemi.com 2
NCP5603
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2
Vbat
C1P
3
2
9
C1
1 mF/16 V
C1N
EN/PWM
6
Fsel
4
Vsel
5
GND
8
GND
Vbat
NCP5603
C2N
C2P
C2
7
10
Vout
D1
LWT67C
R1
10 W
D2
LWT67C
R2
D3
LWT67C
R3
D4
LWT67C
R4
Figure 1. Typical Application
U1
4.7 mF/16 V
C3
GND
1
1 mF/16 V
GND
GND
C4
1 mF/16 V
VSEL
FSEL
PWM
10 W
10 W
10 W
BANDGAF .— —E] —E] : —E] T _ —E] E] % [3 fl [5] 1r 3 [6] I aim SN Figure 2. Block Diagram hltp://onsemi.com :l
NCP5603
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3
Figure 2. Block Diagram
LOGIC AND ANALOG
CONTROL
4
5
6
Vbat
Thermal Shutdown
LEVEL SHIFTER AND MOSFET DRIVE
POWER SWITCHES
Vbat
+
-
GND
Vbat
GND
BANDGAP
GND
1Vout
Vout
2C1P
9C1N
7C2N
10 C2P
3
Vbat
Vbat
Fsel
Vsel
EN
8
GND
NCP5603
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4
PIN FUNCTION DESCRIPTION
Pin Symbol Type Description
1 Vout OUTPUT, PWR This pin supplies the regulated voltage to the external LED. Since high current transients
are present in this pin, care must be observed to avoid voltage spikes in the system. Good
high frequency layout technique must be observed.
2 C1N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated
with C1P, pin 9. Using low ESR ceramic capacitor is recommended to optimize the Charge
Pump efficiency.
3 Vbat POWER This pin shall be connected to the power source, and must be decoupled to Ground by a
low ESR capacitor (2.2 mF/6.3 V ceramic or better (see Note 1)).
4 Fsel INPUT, Digital This pin is used to program the operating frequency:
Fsel = 0 → Fop = 262 kHz
Fsel = 1 → Fop = 650 kHz
5 Vsel INPUT, Digital This pin setup the output voltage:
Vsel = 0 → Vout = 4.5 V
Vsel = 1 → Vout = 5.0 V
6 EN/PWM INPUT, Digital This pin controls the activity of the NCP5603 chip:
EN/PWM = Low → the chip is deactivated, the load is disconnected
EN/PWM = High → the chip is activated and the load is connected to the
regulated output current.
The NCP5603 can operate either in a continuous mode (EN/PWM = High), or can be
controlled by a PWM pulse applied to EN/PWM to dim the output light. When EN/PWM is
Low, the external load is disconnected from the converter, providing a very low standby
current. The pull down built-in resistance makes sure the chip is deactivated even if the
EN/PWM pin is disconnected (see Note 2).
7 C2N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated
with C2P, pin 10. Using low ESR ceramic capacitor is recommended to optimize the
Charge Pump efficiency.
8 GND GROUND This pin combines the Signal ground and the Power ground and must be connected to the
system ground. Using good quality ground plane is mandatory to avoid spikes on the logic
signal lines.
9 C1P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated
with C1N, pin 2. Using low ESR ceramic capacitor is recommended to optimize the Charge
Pump efficiency.
10 C2P POWER One side of the external charge pump capacitor is connected to this pin, associated with
C2N, pin 7. Using low ESR ceramic capacitor is recommended to optimize the Charge
Pump efficiency.
1. Using ceramic 16 V working voltage capacitors is recommended to compensate the DC bias effect encountered with such type of capacitors.
2. Any external impedance connected to pin 6 shall be 10 kW or higher.
NCP5603
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5
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage Vbat 7.0 V
Power Supply Current Ibat 800 mA
Digital Input Pins Vin -0.5 V < Vbat < Vbat +0.5 V < 6.0 V V
Digital Input Pins Iin "5.0 mA
Output Voltage Vout 5.5 V
ESD Capability (Note 3)
Human Body Model
Machine Model
VESD 2.5
200
kV
V
DFN10, 3x3 Package
Power Dissipation @ Tamb = +85°C
Thermal Resistance, Junction-to-Air (RqJA)
PDS
RqJA
580
68.5
mW
°C/W
Operating Ambient Temperature Range TA-40 to +85 °C
Operating Junction Temperature Range TJ-40 to +125 °C
Maximum Junction Temperature TJmax +150 °C
Storage Temperature Range Tstg -65 to +150 °C
Latchup Current Maximum Rating 100 mA per JEDEC standard, JESD78
Moisture Sensitivity Level (MSL) 1 per IPC/JEDEC standard, J-STD-020A
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) "2.5 kV per JEDEC Standard: JESD22-A114
Machine Model (MM) "200 V per JEDEC Standard: JESD22-A115.
4. The maximum package power dissipation limit must not be exceeded.
NCP5603
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6
ELECTRICAL CHARACTERISTICS @ 2.85 V < Vbat < 5.5 V (-40°C to +85°C ambient temperature, unless otherwise noted).
Characteristic Pin Symbol Min Typ Max Unit
Power Supply 3 Vbat 2.85 - 5.5 V
Quiescent Current @ Vbat = 3.7 V, Iout = 0 mA
@ Pulsed Clock Fop = 262 kHz
@ Pulsed Clock Fop = 650 kHz
@ Continuous Clock Fop = 262 kHz
@ Continuous Clock Fop = 650 kHz
3 Iqsc
-
-
-
-
-
-
1.0
2.1
0.8
1.2
-
-
mA
Shutdown Current @ Iout = 0 mA, EN/PWM = L
@ 2.85 < Vbat < 4.2 V
@ Vbat = 5.5 V
3 Istdb
-
-
-
-
2.5
4.0
mA
Output Voltage Regulation
@ Vsel = 1, 2.85 V < Vbat < 4.3 V
@ Vsel = 0, 2.85 V < Vbat < 4.3 V
3 Vout
4.75
4.275
5.0
4.5
5.25
4.725
V
Continuous DC Load Current (Note 7)
Cin = 1.0 mF, C FLY = 1.0 mF, Cout = 1.0 mF
@ Vsel = 1, 3.2 V < Vbat < 4.3 V
@ Vsel = 0, 3.2 V < Vbat < 4.3 V
@ Vsel = 1, 2.85 V < Vbat < 4.3 V
@ Vsel = 0, 2.85 V < Vbat < 4.3 V
3 Iout
-
-
-
-
-
-
-
-
160
200
80
120
mA
Pulsed Output Current
Cin = 10 mF, C FLY = 1.0 mF, Cout = 10 mF, Vbat = 3.6 V
Pwidth = 500 ms, -40°C < TA < +65°C
3 IFLH
- 350 -
mA
Output Continuous Short Circuit Current, Vout = 0 V 3 Isch - 40 100 mA
Operating Frequency (Note 5)
@ Fsel = 0, 2.85 V < Vbat < 4.5 V
@ Fsel = 1, 2.85 V < Vbat < 4.5 V
Fop
210
500
262
650
320
1000
kHz
Output Voltage Ripple (Note 6)
Fop = 262 kHz, Iout = 60 mA (Note 7)
@ Cout = 1.0 mF
@ Cout = 4.7 mF
3 VPP
-
-
150
25
-
60
mV
Digital Input High Level 4, 5, 6 VIH 1.3 - - V
Digital Input Low level 4, 5, 6 VIL - - 0.4 V
Output Power Efficiency
@ Vbat = 3.3 V, Vout = 5.0 V, Iout = 60 mA, Fop = 262 kHz
@ Vbat = 3.9 V, Vout = 5.0 V, Iout = 160 mA, Fop = 650 kHz
Ph
-
-
75
84
-
-
%
Thermal Shut Down Protection
Hysteresis
THSD -
-
160
20
-
-
°C
5. Temperature range guaranteed by design, not production tested.
6. Smaller footprint associated to lower working voltages (10 V or 6.3 V, size 0805 or 0602) can be used, but care must be observed to prevent
DC bias effect on the capacitance final value. See capacitor manufacturer data sheets.
7. Ceramic X7R, ESR < 100 mW, SMD type capacitors are mandatory to achieve the Iout specifications. Depending upon the PCB layout, it
might be necessary to use two 2.2 mF/6.3 V/ceramic capacitors in parallel, yielding an improved Vout noise over the temperature range. On
the other hand, care must be observed to take into account the DC bias impact on the capacitance value. See ceramic capacitor manufacturer
data sheets.
8. Digital inputs undershoot < - 0.30 V to ground, Digital inputs overshoot < 0.30 V to Vbat.
cm: 4.7”!“ Load’ SflmA Vom : A 5v m 2;“; W I \AZZUMV M2 2flflmV 1.25515 cm umv chz znnv Mum.“ Chl/ EBflmV
NCP5603
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7
TYPICAL CHARACTERISTICS
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
EFFICIENCY (%)
Vin (V)
Figure 3. Operating Modes Transitions and
Output Power Efficiency @ Vout = 4.5 V/262 kHz
Figure 4. Operating Modes Transitions and
Output Power Efficiency @ Vout = 4.5 V/650 kHz
Figure 5. Operating Modes Transitions and
Output Power Efficiency @ Vout = 5.0 V/650 kHz
Figure 6. Typical Output Voltage Ripple
Figure 7. Typical Output Voltage Line Regulation Figure 8. Output Voltage Startup from Scratch
IOUT = 120 mA
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
EFFICIENCY (%)
Vbat (V)
IOUT = 120 mA
50
60
70
80
90
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
EFFICIENCY (%)
Vbat (V)
4.2
4.3
4.4
4.5
4.6
4.8
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vbat (V)
-40°C
Vout (V)
4.7
25°C
85°C
-40°C
25°C
85°C
Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S,
ILED = 25mA
IOUT = 160 mA
IOUT = 200 mA
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NCP5603
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8
TYPICAL CHARACTERISTICS
Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S,
ILED = 25mA
Figure 9. Typical PWM Dimming
Vbat
C1P
3
2
9C1N
EN/PWM
6
Fsel
4
Vsel
5
GND
8
GND
NCP5603
C2N
C1P
C2
1 mF/16 V
7
10
Vout
1
C2
1 mF/6.3 V
VCC
R1
1 W
GND
GND
Figure 10. Typical High Power Flash Circuit
C1
10 mF/10 V
C4
10 mFD1
OSRAM: LWW5SG
GOLDEN DRAGON
GND
PWR-FLASH
GND
EN
FSEL
VSEL
NCP5603
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9
0
100
200
300
400
500
2.5 3.0 3.5 4.0 4.5
Vbat (V)
Figure 11. NCP5603 Output Current
Vout = 4.5 V
FSEL = 0
Load = OSRAM / LWW5SG
PWR SWITCH = MGSF1N03
50
150
250
350
450
Iout (mA)
R = 2.2 W
R = 0 W
R = 1 W
Table 1. Ceramic Preferred Capacitors
Manufacturer Type/Series Format Value
TDK C3216X5R1C475MT 1206 4.7 mF / 16 V
TDK C2012X5R1C225MT 0805 2.2 mF / 16 V
TDK C2012X5R1C105MT 0805 1.0 mF / 16 V
gAmm Vcc M M 4mm GND R2 100k R oJ o > 23 NL27WZM GND %<—-—> GROUND hltp://onsemi.com GND
NCP5603
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10
6
1
U2A
NL27WZ14
4
3
U2B
NL27WZ14
+
+
Vbat
C1P
3
2
9C1N
EN/PWM
6
Fsel
4
Vsel
5
GND
8
GND
Vsel
Fsel
NCP5603
C2N
C1P
C2
1 mF/16 V
7
10
Vout
VCC
D1
LW67C
R6
C3
1.0 mF/16 V
GND
U1
1
GND
D2
LW67C
R7
D3
LW67C
R8
D4
LW67C
R9
82 W
TP2
TP1
Vout
ISENSE
1
1
C1
1 mF/16 V
VCC
R4
10 k
GND
R5
10 k
GND
S3
S2
Vsel
Fsel
C7
100 nF
C4
4.7 mF/16 V GND
R3
10 k
P1
200 kA
S4
GND
4 mm
J1
VCC
4 mm
J2
GND
POWER
GND
2
34
PK1
2 x 1.5 V
-
+
1
GND
Q
Q
C6
100 nF
2
1
4
5
3
6
7
RC
C
A
B
CLR
R2
100 k
R1
C5
33 nF
S1
VCC
GND
Q
Q
14
15
12
11
13
10
9
RC
C
A
B
CLR
CNT/PWM
GND
GND
C8
100 nF
GND
GROUND
Z3
R11
1.5 k
GND
VCC
R10
10 k
VCC
GND
D5
PWM
U3A
MC14538B
U3A
MC14538B
U3B
MC14538B
Figure 12. Evaluation Board Schematic Diagram
Adjust PWM
82 W
82 W
82 W
a ‘0 namely “1115mm + O + Inn! Sense “1 :> 5 3 n Selzctl’mr Source VoulSense—p a g E a g u n c Bamrycelll5V,AA 8 - . O - E _ u —— ”3 mm D Q‘Egtultju E] El“ U - hundrmrswply ‘ =E] 3 EDD; E35 :5 comcfinns * U "1 SE] 5 '— "‘ 5 W" a ~2 «man u |_H_l : \ -o El 2 4 A a a q 9 mm H u m u E h" T 4+ (Rx L821»! Normal {PWM Selcct Openfing anuncy Adjust PW'M L Selcct Outpul Voltage
NCP5603
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11
Figure 13. Evaluation Board: Silk View (Top View)
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DFN10, 3x3, 0.5P
CASE 485C
ISSUE E
DATE 11 FEB 2016
SCALE 2:1
10X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
15
10 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B
ALTERNATE CONSTRUCTION ARE NOT APPLICABLE. WET-
TABLE FLANK CONSTRUCTION IS DETAIL B AS SHOWN ON
SIDE VIEW OF PACKAGE.
B
A
0.15 CTOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN ONE
REFERENCE
0.10 C
0.08 C
(A3)
C
10X
10X
0.10 C
0.05 C
A B
NOTE 3
K
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 2.40 2.60
E3.00 BSC
E2 1.70 1.90
e0.50 BSC
L0.35 0.45
L1 0.00 0.03
DETAIL A
K0.19 TYP
2X
2X
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
XXXXX
XXXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
(Note: Microdot may be in either location)
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
2.64
1.90
0.50
0.55
10X
3.30
0.30
10X
DIMENSIONS: MILLIMETERS
PITCH
PACKAGE
OUTLINE
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ALTERNATE B−2ALTERNATE B−1
ALTERNATE A−2ALTERNATE A−1
DETAIL B
WETTABLE FLANK OPTION
CONSTRUCTION
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DFN10, 3X3 MM, 0.5 MM PITCH
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Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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