NCP,NCV5500,01 Datasheet by onsemi

LDO Voltage Regulator 0N Semlconductor® @ @ UU”UU U“U a: :u n: =1
© Semiconductor Components Industries, LLC, 2013
September, 2019 − Rev. 12
1Publication Order Number:
NCP5500/D
NCP5500, NCV5500,
NCP5501, NCV5501
LDO Voltage Regulator
500 mA
These linear low drop voltage regulators provide up to 500 mA over
a user−adjustable output range of 1.25 V to 5.0 V, or at a fixed output
voltage of 1.5 V, 3.3 V or 5.0 V, with typical output voltage accuracy
better than 3%. An internal PNP pass transistor permits low dropout
voltage and operation at full load current at the minimum input
voltage. NCV versions are qualified for demanding automotive
applications that require extended temperature operation and site and
change control. NCP5500 and NCV5500 versions include an
Enable/Shutdown function and are available in a DPAK 5 and SOIC 8
packages. NCP5501 and NCV5501 versions are available in DPAK 3
for applications that do not require logical on/off control.
This regulator family is ideal for applications that require a broad
input voltage range, and low dropout performance up to 500 mA load
using low cost ceramic capacitors. Integral protection features include
short circuit current and thermal shutdown.
Features
•Output Current up to 500 mA
•2.9% Output Voltage Accuracy
•Low Dropout Voltage (230 mV at 500 mA)
•Enable Control Pin (NCP5500 / NCV5500)
•Reverse Bias Protection
•Short Circuit Protection
•Thermal Shutdown
•Wide Operating Temperature Range
NCV5500 / NCV5501; −40°C to +125°C Ambient Temperature
NCP5500 / NCP5501; −40°C to +85°C Ambient Temperature
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•Stable with Low Cost Ceramic Capacitors
•These are Pb−Free Devices
Typical Applications
•Automotive
•Industrial and Consumer
•Post SMPS Regulation
•Point of Use Regulation
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15
DPAK 5
CENTER LEAD CROP
CASE 175AA
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
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x = P (NCP), V (NCV)
5500/1 = Device Code
y = Output Voltage
= L = 1.5 V
= T = 3.3 V
= U = 5.0 V
= W = Adjustable
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
12
3
4DPAK 3
SINGLE GAUGE
CASE 369C
13
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5
1
Pin 1. EN
2. Vin
TAB,3. GND
4. Vout
5. NC/ADJ
Pin 1. Vin
TAB,2. GND
3. Vout
5500x
ALYW
G
1
8
1
8SOIC−8
CASE 751
Pin 1. Vin
2. GND
3. GND
4. Vout
5. NC/ADJ
6. GND
7. GND
8. EN
x = Output Voltage, NCP/NCV
A = Adjustable, NCV
B = Adjustable, NCP
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
0—1: \ E ”Hi-0 0— J i Figure 1. Typical Application Circuit Figure 2. Block Diagram hllp://onsemi.com 2
NCP5500, NCV5500, NCP5501, NCV5501
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Figure 1. Typical Application Circuit
Input
OFF ON
Output
GND
NCP5500
EN* NC/ADJ*
GND RL
Cout
4.7 mF
NCV5500
R1*
R2*
Enable
NCP5501
NCV5501
Cin
10 mF
*Applicable to NCP5500/NCV5500 only.
Vout
Vin
PIN FUNCTION DESCRIPTIONS
DPAK 3 DPAK 5 SOIC−8Pin
Name Description
Pin No. Pin No. Pin No.
−1 8 EN Enable. This pin allows for on/off control of the regulator. High level turns on the
output. To disable the device, connect to ground. If this function is not in use, con-
nect to Vin.
1 2 1 Vin Positive power supply input voltage.
2, Tab 3, Tab 2, 3, 6, 7 GND Ground. This pin is internally connected to the Tab heat sink.
3 4 4 Vout Regulated output voltage.
−5 5 NC/ADJ No connection (Fixed output versions).
Voltage−adjust input (Adjustable output version). Use an external voltage divider
to set the output voltage over a range of 1.25 V to 5.0 V.
Figure 2. Block Diagram
−
+
NC / ADJ*
EN* GND
Connection for Adjustable Output
Connection for Fixed Output
Error
Amplifier
Current Limit and
Saturation Sense
Bandgap
Reference
Thermal
Shutdown
*Applicable to NCP5500/NCV5500 only.
Vout
Vin
Enable
Block*
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Min Max Unit
Input Voltage (Note 1) Vin −0.3 (Note 2) +18 V
Output, Enable Voltage Vout, EN −0.3 +16 or
Vin + 0.3
(Notes 2 and 5)
V
Maximum Junction Temperature TJ−150 °C
Storage Temperature TStg −55 +150 °C
Moisture Sensitivity Level All Packages MSL 1 −
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3) Tsld 265 Peak
°C
ESD Capability, Human Body Model (Note 4) ESDHBM 4000 −V
ESD Capability, Machine Model (Note 4) ESDMM 200 −V
ESD Capability, Charged Device Model (Note 4) ESDCDM 1000 −V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78.
1. Refer to Electrical Characteristics and Application Information for Safe Operating Area.
2. Reverse bias protection feature valid only if Vout − Vin v 7 V.
3. Pb−Free, 60 sec –150 sec above 217°C, 40 sec max at peak temperature
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD Charged Device Model tested per EIA/JES D22/C101, Field Induced Charge Model
5. Maximum = +16 V or (Vin + 0.3 V), whichever is lower.
THERMAL CHARACTERISTICS
Rating Symbol Min Max Unit
Package Dissipation
Thermal Characteristics, DPAK 3 and DPAK 5 (Note 1)
Thermal Resistance, Junction−to−Air (Note 6)
Thermal Resistance, Junction−to−Case
Thermal Characteristics, SOIC−8 (Note 1)
Thermal Resistance, Junction−to−Air (Note 6)
Thermal Reference, Junction−to−Lead
PD
RqJA
RqJC
RqJA
RYJL
Internally Limited
60
5.2
80
22
W
°C/W
°C/W
6. As measured using a copper heat spreading area of 650 mm2, 1 oz copper thickness.
OPERATING RANGES
Rating Symbol Min Max Unit
Operating Input Voltage (Note 1) Vin Vout + VDO, 2.5 V
(Note 7)
16 V
Adjustable Output Voltage Range (Adjustable Version Only) Vout 1.25 5.0 V
Operating Ambient Temperature Range
NCP5500, NCP5501
NCV5500, NCV5501
TA
−40
−40
85
125
°C
7. Minimum Vin = 2.5 V or (Vout + VDO), whichever is higher.
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ELECTRICAL CHARACTERISTICS Vin = 2.5 V or Vout + 1.0 V (whichever is higher), Cin = 10 mF, Cout = 4.7 mF, for typical values TA
= 25°C, for min/max values TA = −40°C to 85°C (NCP Version), TA = −40°C to 125°C (NCV Version) unless otherwise noted (Note 13).
Characteristic Symbol Test Conditions Min Typ Max Unit
OUTPUT
Output Voltage (Note 14)
5 V Regulator
3.3 V Regulator
1.5 V Regulator
ADJ Regulator
Vout TA = 25°C, Iout = 50 mA
VNOM±2.9%
V
V
V
Output Voltage (Note 8)
5 V Regulator
3.3 V Regulator
1.5 V Regulator
ADJ Regulator
Vout 1.0 mA < Iout < 500 mA
(−4.9%)
4.755
3.138
1.427
1.189
VNOM
5.0
3.3
1.5
1.25
(+4.9%)
5.245
3.462
1.574
1.311
V
V
V
Line Regulation REGLINE Iout = 50 mA
2.5 V or (Vout + 1.0 V) < Vin < 16 V
−1.0 0.1 1.0 %
Load Regulation REGLOAD 1.0 mA < Iout < 500 mA −1.0 0.35 1.0 %
Dropout Voltage (Note 9)
5.0 V Version
3.3 V Version
1.5 V Version (Note 10)
Adjustable Version (Note 11)
VDO Iout = 1.0 mA, DVout = −2%
Iout = 500 mA, DVout = −2%
Iout = 1.0 mA, DVout = −2%
Iout = 500 mA, DVout = −2%
Iout = 1.0 mA, DVout = −2%
Iout = 500 mA, DVout = −2%
Iout = 1.0 mA, DVout = −2%
Iout = 500 mA, DVout = −2%
−
−
−
−
−
−
−
−
5
230
5
230
−
−
5
230
90
700
90
700
1073
1073
90
700
mV
Ground Current IGND Iout = 100 mA
Iout = 500 mA
300
10
500
20
mA
mA
Disable Current in Shutdown
(NCP5500, NCV5500)
ISD Adjustable and 1.5 V versions
All other versions
30
40
50
50
mA
Current Limit Iout(LIM) Vout = 90% of Vout(nom) 500 700 900 mA
Ripple Rejection Ratio (Notes 9 & 14) RR 120 Hz
Iout = 100 mA, 1 kHz
10 kHz
−
−
−
75
75
70
−
−
−
dB
Output Noise Voltage (Notes 12 & 14) Vnf = 10 Hz to 100 kHz, Vin = 2.5 V
Vout = 1.25 V, Iout = 1.0 mA
f = 10 Hz to 100 kHz, Vin = 2.5 V
Vout = 1.25 V, Iout = 100 mA
18
35
mVrms
ENABLE (NCP5500, NCV5500 Only)
Enable Voltage VENoff
VENon
OFF (shutdown) State
ON (enabled) State 2.0
0.4 V
Enable Pin Bias Current IEN VEN = Vin, Iout = 1.0 mA −1.0 mA
ADJUST
Adjust Pin Current (Note 14) IADJ VEN = Vin, VADJ = 1.25 V, Vout = 1.25 V −60 nA
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 14) TSD Iout = 100 mA150 −210 °C
8. Deviation from nominal. For adjustable versions, Pin ADJ connected to Vout.
9. See Typical Characteristics section for additional information.
10.VDO is constrained by the minimum input voltage of 2.5 V.
11. Vout is set by external resistor divider to 5 V.
12.Vn for other fixed voltage versions, as well as adjustable versions set to other output voltages, can be calculated from the following formula:
Vn = Vn(x) * Vout / 1.25, where Vn(x) is the typical value from the table above.
13.Performance guaranteed over specified operating conditions by design, guard banded test limits, and/or characterization, production tested
at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as
possible.
14.Values are based on design and/or characterization.
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TYPICAL CHARACTERISTICS
Figure 3. Output Voltage vs. Ambient
Temperature
TA, AMBIENT TEMPERATURE (°C)
12080400−40
4.75
4.80
4.85
4.95
5.05
5.10
5.15
5.25
Vout, OUTPUT VOLTAGE (V)
4.90
5.00
5.20 Vin = 13.2 V
RL = 1 kW
Figure 4. Output Voltage vs. Ambient
Temperature
Figure 5. Output Voltage vs. Ambient
Temperature
TA, AMBIENT TEMPERATURE (°C)
12080400−40
1.42
1.44
1.46
1.48
1.50
1.54
1.56
1.58
Vout, OUTPUT VOLTAGE (V)
1.52
Vin = 13.2 V
RL = 1 kW
Figure 6. Output Voltage vs. Ambient
Temperature
Vout(nom) = 5 V
Vout(nom) = 1.5 V
Figure 7. Dropout Voltage vs. Output Current
Iout, OUTPUT CURRENT (mA)
6005004003002001000
0
100
200
300
400
500
VDO, DROPOUT VOLTAGE (mV)
TA = −40°C
TA = 25°C
TA = 125°C
Vout(nom) = 5 V
Figure 8. Dropout Voltage vs. Output Current
3.15
3.18
3.21
3.24
3.27
3.30
3.33
3.36
3.39
3.42
3.45
−40 0 40 80 120
TA, AMBIENT TEMPERATURE (°C)
Vout, OUTPUT VOLTAGE (V)
Vin = 13.2 V
RL = 1 kW
Vout(nom) = 3.3 V
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
−40 0 40 80 120
TA, AMBIENT TEMPERATURE (°C)
Vout, OUTPUT VOLTAGE (V)
Vout(nom) = 1.25 V (ADJ)
Vin = 13.2 V
RL = 1 kW
0
50
100
150
200
250
300
350
400
450
500
Iout, OUTPUT CURRENT (mA)
VDO DROPOUT VOLTAGE (mV)
TA = 125°C
TA = 25°C
TA = −40°C
Vout(nom) = 3.3 V
6005004003002001000
NCP5500, NCV5500, NCP5501, NCV5501
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TYPICAL CHARACTERISTICS
Figure 9. Ground Current vs. Output Current
Iout, OUTPUT CURRENT (mA)
7006005004003002001000
0
2
4
6
10
12
14
18
IGND, GROUND CURRENT (mA)
8
16 TA = −40°C
TA = 25°C
TA = 125°C
Vout(nom) = 5 V
Vin, INPUT VOLTAGE (V)
76543210
0
1
2
3
4
5
6
IGND, GROUND CURRENT (mA)
RL = 1 kWVout(nom) = 5 V
Vin, INPUT VOLTAGE (V)
76543210
0
1
2
3
4
5
6
IGND, GROUND CURRENT (mA)
RL = 1 kWVout(nom) = 1.5 V
Figure 10. Ground Current vs. Output Current
Figure 11. Ground Current vs. Input Voltage Figure 12. Ground Current vs. Input Voltage
Figure 13. Ground Current vs. Input Voltage Figure 14. Ground Current vs. Input Voltage
0 100 200 300 400 500 600 70
0
18
16
14
12
10
8
6
4
2
0
Iout, OUTPUT CURRENT (mA)
IGND, GROUND CURRENT (mA)
Vout(nom) = 1.25 V (ADJ)
TA = −40°C
TA = 25°C
TA = 125°C
0
1
2
3
4
5
6
01234567
Vin, INPUT VOLTAGE (V)
IGND, GROUND CURRENT (mA)
RL = 1 kWVout(nom) = 3.3 V
0
1
2
3
4
5
6
01234567
IGND, GROUND CURRENT (mA)
Vin, INPUT VOLTAGE (V)
Vout(nom) = 1.25 V (ADJ)
RL = 1 kW
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TYPICAL CHARACTERISTICS
Figure 15. Ripple Rejection vs. Frequency
f, FREQUENCY (kHz)
1001010.10.01
0
10
20
30
40
50
70
90
RR, RIPPLE REJECTION (dB)
60
80
Vin = 6 V,
DVin = 0.5 Vpp
500 mA
100 mA
1 mA
Vout(nom) = 1.5 V
Figure 16. Ripple Rejection vs. Frequency
f, FREQUENCY (kHz)
10
0
1010.10.01
0
10
20
30
40
50
70
90
RR, RIPPLE REJECTION (dB)
60
80
500 mA
100 mA
1 mA
Vout(nom) = 1.25 V (ADJ)
Iout, OUTPUT CURRENT (mA)
500450250200150100500
0
1
3
4
5
7
9
10
ESR (W)
400350300
2
6
8
Unstable Region
Stable Region
Figure 17. Output Capacitor ESR Stability vs.
Output Current
Iout, OUTPUT CURRENT (mA)
500450250200150100500
0
1
3
4
5
7
9
10
ESR (W)
400350300
2
6
8
Unstable Region
Stable Region
Figure 18. Output Capacitor ESR Stability vs.
Output Current
Figure 19. Output Capacitor ESR Stability vs.
Output Current
Cout = 1 mF to 10 mF
Vout(nom) = 5 V
Figure 20. Output Capacitor ESR Stability vs.
Output Current
Cout = 1 mF to 10 mF
Vout(nom) = 1.5 V
Iout, OUTPUT CURRENT (mA)
ESR (W)
Cout = 1 mF to 10 mF
Vout(nom) = 3.3 V
Cout = 1 mF to 10 mF
Vout(nom) = 1.25 V (ADJ)
0
1
2
3
4
5
6
7
8
9
10
11
12
0 50 100 150 200 250 300 350 400 450 50
0
500450250200150100500 400350300
0
1
2
3
4
5
6
7
8
9
10
0 50 100 150 200 250 300 350 400 450 50
0
Iout, OUTPUT CURRENT (mA)
ESR (W)
Unstable Region
Stable Region
Unstable Region
Stable Region
Vin = 6 V,
DVin = 0.5 Vpp
NOTE: Typical characteristics were measured with the same conditions as electrical characteristics, unless otherwise noted.
Figure 21. Measuring Circuits hllp://onsemi.com a °1 _T_ x _T_ ; ¥ A ¥ G °1 _T_ x. _T_ ' $52.; $5385"; ; % GND = _ IGND _ ‘0
NCP5500, NCV5500, NCP5501, NCV5501
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Figure 21. Measuring Circuits
Input
Enable
Output
ADJ
GND
NCP5500
RL
Cin
10 mF
Cin2
100 nF
EN IADJ
IGND
IQ
IEN
Iin Iout
Cout
NCV5500
Input Output
GND
RL
Cin
10 mF
Cin2
100 nF
IGND
IQ
Iin Iout
Cout
NCP5501 NCV5501
Vout
Vin
Vout
Vin
Circuit Description
The NCP5500/NCP5501/NCV5500/NCV5501 are
integrated linear regulators with a DC load current
capability of 500 mA. The output voltage is regulated by a
PNP pass transistor controlled by an error amplifier and
band gap reference. The choice of a PNP pass element
provides the lowest possible dropout voltage, particularly at
reduced load currents. Pass transistor base drive current is
controlled to prevent oversaturation. The regulator is
internally protected by both current limit and thermal
shutdown. Thermal shutdown occurs when the junction
temperature exceeds 150°C. The NCV5500 includes an
enable/shutdown pin to turn off the regulator to a low current
drain standby state.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design for enhanced temperature stability.
Saturation control of the PNP pass transistor is a function of
the load current and input voltage. Oversaturation of the
output power device is prevented, and quiescent current in
the ground pin is minimized.
Regulator Stability Considerations
The input capacitor is necessary to stabilize the input
impedance to reduce transient line influences. The output
capacitor helps determine three main characteristics of a
linear regulator: startup delay, load transient response and
loop stability. The capacitor value and type should be based
on cost, availability, size and temperature constraints. Refer
to Typical Operating Characteristics for stability regions.
Enable Input (NCP5500, NCV5500)
The enable pin is used to turn the regulator on or off. By
holding the pin at a voltage less than 0.4 V, the output of the
regulator will be turned off to a minimal current drain state.
When the voltage at the Enable pin is greater than 2.0 V, the
output of the regulator will be enabled and rise to the
regulated output voltage. The Enable pin may be connected
directly to the input pin to provide a constant enable to the
regulator.
Active Load Protection in Shutdown (NCP5500,
NCV5500)
When a linear regulator is disabled (shutdown), the output
(load) voltage should be zero. However, stray PC board
leakage paths, output capacitor dielectric absorption, and
inductively coupled power sources can cause an undesirable
regulator output voltage if load current is low or zero. The
NCV5500 features a load protection network that is active
only during Shutdown mode. This network switches in a
shunt current path (~500 mA) from Vout to Ground. This
feature also provides a controlled (“soft”) discharge path for
the output capacitor after a transition from Enable to
Shutdown.
(R + R2) (
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Calculating Resistors for the ADJ Versions
The adjustable version uses feedback resistors to adjust
the output to the desired output voltage. With Vout connected
to ADJ, the adjustable version will regulate at 1.25 V
4.9% (1250 61.25 mV).
Output voltage formula with an external resistor divider:
Vout +ǒ1.25 V *ƪ60E−9@
(R1@R2)
(R1)R2)ƫǓ@ǒ(R1)R2)
R2Ǔ
Where
R1 = value of the divider resistor connected between Vout
and ADJ,
R2 = value of the divider resistor connected between ADJ
and GND,
The term “1.25 V” has a tolerance of 4.9%; the term
“60E−9” can vary in the range 15E−9 to 60E−9.
For values of R2 less than 15 KW, the term within brackets
( [ ] ) will evaluate to less than 1 mV and can be ignored. This
simplifies the output voltage formula to:
Vout = 1.25 V * ((R1 + R2) / R2)) with a tolerance of 4.9%,
which is the tolerance of the 1.25 V output when delivering
up to 500 mA of output current.
DEFINITION OF TERMS
Dropout Voltage: The input−to−output voltage differential
at which the circuit ceases to regulate against further
reduction input voltage. Measured when the output voltage
has dropped 2% relative to the value measured at nominal
input voltage. Dropout voltage is dependent upon load
current and junction temperature.
Input Voltage: The DC voltage applied to the input
terminals with respect to ground.
Line Regulation: The change in output voltage for a change
in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Load Regulation: The change in output voltage for a change
in load current at constant chip temperature. Pulse loading
techniques are employed such that the average chip
temperature is not significantly affected.
Quiescent and Ground Current: The quiescent current is
the current which flows through the ground when the LDO
operates without a load on its output: internal IC operation,
bias, etc. When the LDO becomes loaded, this term is called
the Ground current. It is actually the difference between the
input current (measured through the LDO input pin) and the
output current.
Ripple Rejection: The ratio of the peak−to−peak input ripple
voltage to the peak−to−peak output ripple voltage.
Current Limit: Peak current that can be delivered to the
output.
Calculating Power Dissipation
The maximum power dissipation for a single output
regulator (Figure 21) is:
PD(max) +ƪVin(max) *Vout(min)ƫIout(max) )Vin(max)IGND
(eq. 1)
Where
Vin(max) is the maximum input voltage,
Vout(min) is the minimum output voltage,
Iout(max) is the maximum output current for the application,
IGND is the ground current at Iout(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA +ǒ150 C *TAǓ
PD
(eq. 2)
°
The value of RqJA can then be compared with those in the
Thermal Characteristics table. Those packages with RqJA
less than the calculated value in Equation 2 will keep the die
temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
RqJA +RqJC )RqCS )RqSA (eq. 3)
where
RqJC is the junction−to−case thermal resistance,
RqCS is the case−to−heatsink thermal resistance,
RqSA is the heatsink−to−ambient thermal resistance.
RqJC appears in the Thermal Characteristics table. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heat sink and the interface
between them. These values appear in data sheets of heat
sink manufacturers.
Thermal, mounting, and heat sink considerations are
further discussed in ON Semiconductor Application Note
AN1040/D.
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ORDERING INFORMATION
Device Nominal Output Voltage*
Package
Marking Package Shipping†
NCP5500DT15RKG
1.5
P5500LG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCV5500DT15RKG** V5500LG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCP5501DT15RKG P5501LG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCV5501DT15RKG** V5501LG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCP5501DT15G P5501LG DPAK 3
(Pb−Free)
75 Units / Rail
NCV5501DT15G** V5501LG DPAK 3
(Pb−Free)
75 Units / Rail
NCP5500DT33RKG
3.3
P5500TG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCV5500DT33RKG** V5500TG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCP5501DT33RKG P5501TG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCV5501DT33RKG** V5501TG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCP5501DT33G P5501TG DPAK 3
(Pb−Free)
75 Units / Rail
NCV5501DT33G** V5501TG DPAK 3
(Pb−Free)
75 Units / Rail
NCP5500DT50RKG
5.0
P5500UG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCV5500DT50RKG** V5500UG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCP5501DT50RKG P5501UG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCV5501DT50RKG** V5501UG DPAK 3
(Pb−Free)
2500 / Tape & Reel
NCP5501DT50G P5501UG DPAK 3
(Pb−Free)
75 Units / Rail
NCV5501DT50G** V5501UG DPAK 3
(Pb−Free)
75 Units / Rail
NCP5500DTADJRKG
Adjustable
P5500WG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCV5500DTADJRKG** V5500WG DPAK 5
(Pb−Free)
2500 / Tape & Reel
NCP5500DADJR2G Adjustable 5500B SO−8
(Pb−Free)
2500 / Tape & Reel
NCV5500DADJR2G** Adjustable 5500A SO−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact ON Semiconductor for other fixed voltages.
**NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
0N Semiwndudw" m L E j 7 UUUHU (m 0N 3mg and a 3mm CW mm Lu: ma 0N SWW a mass m Una sags mad man ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
DPAK−5, CENTER LEAD CROP
CASE 175AA
ISSUE B
DATE 15 MAY 2014
D
A
K
B
R
V
S
F
L
G
5 PL
M
0.13 (0.005) T
E
C
U
J
H
−T−SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.22
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.020 0.028 0.51 0.71
E0.018 0.023 0.46 0.58
F0.024 0.032 0.61 0.81
G0.180 BSC 4.56 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.045 BSC 1.14 BSC
R0.170 0.190 4.32 4.83
S0.025 0.040 0.63 1.01
U0.020 −−− 0.51 −−−
V0.035 0.050 0.89 1.27
Z0.155 0.170 3.93 4.32
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
XXXXXXG
ALYWW
R1 0.185 0.210 4.70 5.33
R1
GENERIC
MARKING DIAGRAMS*
1234 5
6.4
0.252
0.8
0.031
10.6
0.417
5.8
0.228
SCALE 4:1 ǒmm
inchesǓ
0.34
0.013
5.36
0.217
2.2
0.086
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SCALE 1:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
AYWW
XXX
XXXXXG
DiscreteIC
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON12855D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
DPAK−5 CENTER LEAD CROP
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" FE! «E» + ‘W uj 4‘ Lin”; i I: \, L4 \ \ ‘4, b2 N cjle D4- ., — E ' J Le 4 Ema baa A1 STYLE ‘ SIVLE 2 STYLE 3 sw mm BASE mm GAVE mm ANODE F 2 COLLECTOR 2 DRAIN 2 CATHODE 3 EMH’TER 3 SouRCE 3 ANODE a COLLECTOR 4 DRAIN a CATHODE STYLE 5 SWLE 7 STVLE a STVLE 9 mm Mn PM (we le we mm AND 2 W2 2 couscmn 2 CAIHODE 2 on 3 GATE 3 EM‘TTER a ANODE 3 RE 3 W2 4 couscmn 4 CAIHODE o c SOLDERING F ‘7 6.2!] 1:244 ’ a 2.58 01112 5-711 71* (me 'For addmonal \nlormamn on our P delafls‘ p‘ease download me ON Mounhng Techmques Reference ON Semaanauemy and are Mademavks av Semxcanduclur Campunenls lndusmes LLC dba ON Semxcanduclar ar us euaamanee m xne mnnea sxaxee andJm mhev commas ON Semaanauexar vesewes me th| to make changes wuhum Vunnev mouse to any amaune havem 0N Semanduc‘nv manee m7 wanamy represenlalmn m guarantee regardmg the sumahmy at W; manuals can any panama purpase nnv dues ON Semumnduclm assume any Mammy ansmg mac xne apphcahan m use no any pmduclnv mum and eaeamcauy meexanne any and au Mammy mc‘udmg wnnam nnmanan spema‘ cansequenha‘ m \nmdenla‘ damages ON Sennmnauexar dues nn| aanyey any hcense under Ms pa|em thls nar xne name av n|hers
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
12
3
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4
b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
e
BOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON10527D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
DPAK (SINGLE GAUGE)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semxcunduclm and ave hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Semxcanduclar Dr K: suhsxdmnes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av mhers
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
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