NB2304A Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2010
May, 2021 − Rev. 10
1Publication Order Number:
NB2304A/D
3.3 V Zero Delay
Clock Buffer
NB2304A
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in an 8 pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
250 ps, and the output−to−output skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304AI1 is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304AI2 allows the user to obtain REF,
1/2 X and 2X frequencies on each output Bank. The exact
configuration and output frequencies depend on which output drives
the feedback pin.
Features
•Zero Input − Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
•Multiple Configurations − Refer to NB2304A Configurations Table
•Input Frequency Range: 15 MHz to 133 MHz
•Multiple Low−Skew Outputs
•Output−Output Skew < 200 ps
•Device−Device Skew < 500 ps
•Two Banks of Four Outputs
•Less than 200 ps Cycle−to−Cycle Jitter (−1)
•Available in Space Saving, 8 pin 150 mil SOIC Package
•3.3 V Operation
•Advanced 0.35 m CMOS Technology
•Guaranteed Across Commercial and Industrial Temperature Ranges
•These Devices are Pb−Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAM
4lx = Specific Device Code
x = 1 or 2
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
SOIC−8
D SUFFIX
CASE 751
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
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1
8
4lx
ALYW
G
1
8
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NB2304A
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2
Figure 1. Basic Block Diagram
(see Figures 10 and 11 for device specific Block Diagrams)
FBK
CLKA1
CLKA2
CLKB1
CLKB2
REF PLL
Extra Divider (−2)B2
Table 1. CONFIGURATIONS
Device Feedback From Bank A Frequency Bank B Frequency
NB2304AI1 Bank A or Bank B Reference Reference
NB2304AI2 Bank A Reference Reference B2
NB2304AI2 Bank B 2 X Reference Reference
Figure 2. Pin Configuration
VDD
1
2
3
4
8
7
6
5
REF
CLKA1
CLKA2
GND
FBK
CLKB2
CLKB1
NB2304A
Table 2. PIN DESCRIPTION
Pin # Pin Name Description
1REF (Note 1) Input reference frequency, 5 V
tolerant input.
2CLKA1 (Note 2) Buffered clock output, Bank A.
3CLKA2 (Note 2) Buffered clock output, Bank A.
4 GND Ground.
5CLKB1 (Note 2) Buffered clock output, Bank B.
6CLKB2 (Note 2) Buffered clock output, Bank B.
7 VDD 3.3 V supply.
8 FBK PLL feedback input.
1. Weak pulldown.
2. Weak pulldown on all outputs.
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Table 3. MAXIMUM RATINGS
Parameter Min Max Unit
Supply Voltage to Ground Potential −0.5 +7.0 V
DC Input Voltage (Except REF) −0.5 VDD + 0.5 V
DC Input Voltage (REF) −0.5 7 V
Storage Temperature −65 +150 °C
Maximum Soldering Temperature (10 sec) 260 °C
Junction Temperature 150 °C
Static Discharge Voltage (per MIL−STD−883, Method 3015) > 2000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. OPERATING CONDITIONS
Parameter Description Min Max Unit
VDD Supply Voltage 3.0 3.6 V
TAOperating Temperature (Ambient Temperature) Industrial
Commercial
−40
0
85
70
°C
CLLoad Capacitance, 15 MHz to 100 MHz 30 pF
CLLoad Capacitance, from 100 MHz to 133 MHz 15 pF
CIN Input Capacitance (Note 3) 7 pF
3. Applies to both REF Clock and FBK.
Table 5. ELECTRICAL CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Parameter Description Test Conditions Min Max Unit
VIL Input LOW Voltage 0.8 V
VIH Input HIGH Voltage 2.0 V
IIL Input LOW Current VIN = 0 V 50.0 mA
IIH Input HIGH Current VIN = VDD 100.0 mA
VOL Output LOW Voltage IOL = 8 mA (−1, −2) 0.4 V
VOH Output HIGH Voltage IOH = −8 mA (−1, −2) 2.4 V
IDD Supply Current Unloaded outputs 100 MHz REF
Select inputs at VDD or GND
45 mA
Unloaded outputs, 66 MHz REF (−1, −2) 35
Unloaded outputs, 33 MHz REF (−1, −2) 20
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Table 6. SWITCHING CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
(All parameters are specified with loaded outputs)
Parameter Description Test Conditions Min Typ Max Unit
t1Output Frequency 30 pF load (all devices)
15 pF load (−1, −2)
15
15
100
133.3
MHz
t1Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT v 66.66 MHz
30 pF load
40.0 50.0 60.0 %
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
45.0 50.0 55.0
t3Output Rise Time
(−1, −2)
Measured between 0.8 V and 2.0 V
30 pF load
2.50 ns
Measured between 0.8 V and 2.0 V
15 pF load
1.50
t4Output Fall Time
(−1, −2)
Measured between 2.0 V and 0.8 V
30 pF load
2.50 ns
Measured between 2.0 V and 0.8 V
15 pF load
1.50
t5Output−to−Output Skew on same Bank
(−1, −2)
All outputs equally loaded 200 ps
Output Bank A−to−Output Bank B skew
(−1)
All outputs equally loaded 200
Output Bank A−to−Output Bank B skew
(−2)
All outputs equally loaded 400
t6Delay, REF Rising Edge to FBK Rising
Edge
Measured at VDD/2 0 ±250 ps
t7Device−to−Device Skew Measured at VDD/2 on the FBK pins of the
device
0 500 ps
tJCycle−to−Cycle Jitter
(−1)
Measured at 66.67 MHz, loaded outputs,
15 pF load
180 ps
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Cycle−to−Cycle Jitter
(−2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
400 ps
Measured at 66.67 MHz, loaded outputs,
15 pF load
380
tLOCK PLL Lock Time Stable power supply, valid clock presented
on REF and FBK pins
1.0 ms
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Zero Delay and Skew Control
For applications requiring zero input−output delay, all
outputs must be equally loaded.
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
1500
1000
500
0
−500
−1000
−1500
−30 −25 −20 −15 −10 −5 0 5 1015202530
REF INPUT TO CLKA/CLKB DELAY (ps)
OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)
To close the feedback loop of the NB2304A, the FBK pin
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output−output skew, be sure to load outputs equally.
SWITCHING WAVEFORMS
Figure 4. Duty Cycle Timing
1.4 V 1.4 V 1.4 V
t1
t2
Figure 5. All Outputs Rise/Fall Time
t3
OUTPUT
2.0 V
0.8 V
t4
2.0 V
0.8 V
3.3 V
0 V
1.4 V
1.4 V
t5
Figure 6. Output − Output Skew
OUTPUT
OUTPUT
t6
INPUT
OUTPUT
Figure 7. Input − Output Propagation Delay
VDD
2
VDD
2
Figure 8. Device − Device Skew
t7
FBK_Device 1
VDD
2
VDD
2
FBK_Device 2
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VDD
VDD
CLOAD
GND GND
OUTPUTS
Figure 9. Test Circuit #1
0.1 mF
0.1 mF
TEST CIRCUITS
Figure 10. NB2304AI1
FBK
CLKA1
CLKA2
CLKB1
CLKB2
REF PLL
Figure 11. NB2304AI2
FBK
CLKA1
CLKA2
CLKB1
CLKB2
REF PLL
B2
BLOCK DIAGRAMS
ORDERING INFORMATION
Device Marking Operating Range Package Shipping†Availability
NB2304AI1DR2G 4I1 Industrial &
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel Now
NB2304AI2DG 4I2 Industrial &
Commercial
SOIC−8
(Pb−Free)
98 Units / Tube Now
NB2304AI2DR2G 4I2 Industrial &
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
DESCRIPTION:
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PAGE 1 OF 2
SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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DOCUMENT NUMBER:
DESCRIPTION:
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SOIC−8 NB
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