MC14504B Datasheet by onsemi

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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9 1Publication Order Number:
MC14504B/D
MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non−inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels VDD and VCC.
The VCC level sets the input signal levels while VDD selects the output
voltage levels.
Features
UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
Input Threshold Can Be Shifted for TTL Compatibility
No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
3 to 18 Vdc Operation for VDD and VCC
Diode Protected Inputs to VSS
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VCC DC Supply Voltage Range 0.5 to +18.0 V
VDD DC Supply Voltage Range 0.5 to +18.0 V
Vin Input Voltage Range
(DC or Transient) 0.5 to +18.0 V
Vout Output Voltage Range
(DC or Transient) 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10 mA
PDPower Dissipation, per Package
(Note 1) 500 mW
TAAmbient Temperature Range 55 to +125 °C
Tstg Storage Temperature Range 65 to +150 °C
TLLead Temperature
(8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
14504BG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Indicator
SOEIAJ−16
F SUFFIX
CASE 966
MC14504B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
1
16
14
504B
ALYWG
G
1
16
(Note: Microdot may be in either location)
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Eout
MODE
Fin
Fout
VDD
Din
Dout
Ein
Bout
Ain
Aout
VCC
VSS
Cin
Cout
Bin
SOIC−16 SOEIAJ−16
TSSOP−16
MC14504B
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2
LOGIC DIAGRAM
INPUT
VDD
OUTPUT
LEVEL
SHIFTER
MODE
VCC
TTL/CMOS
MODE SELECT
Mode Select Input Logic
Levels Output Logic
Levels
1 (VCC) TTL CMOS
0 (VSS) CMOS CMOS
1/6 of package shown.
ORDERING INFORMATION
Device Package Shipping
MC14504BDG SOIC−16
(Pb−Free) 48 Units / Rail
NLV14504BDG*
MC14504BDR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14504BDR2G*
MC14504BDTG TSSOP−16
(Pb−Free) 96 Units / Rail
NLV14504BDTG*
MC14504BDTR2G TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14504BDTR2G*
MC14504BFELG SOEIAJ−16
(Pb−Free) 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14504B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbo
l
VCC
Vdc VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min Typ
(Note 2) Max Min Max
Output Voltage “0” Leve
l
Vin = 0 V
“1” Leve
l
Vin = VCC
VOL
5.0
10
1 5
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Level
(VOL = 1.0 Vdc) TTL−CMOS
(VOL = 1.5 Vdc) TTL−CMOS
(VOL = 1.0 Vdc) CMOS−CMOS
(VOL = 1.5 Vdc) CMOS−CMOS
(VOL = 1.5 Vdc) CMOS−CMOS
VIL 5.0
5.0
5.0
5.0
10
10
15
10
15
15
0.8
0.8
1.5
1.5
3.0
1.3
1.3
2.25
2.25
4.5
0.8
0.8
1.5
1.5
3.0
0.8
0.8
1.4
1.5
2.9
Vdc
Input Voltage “1” Level
(VOH = 9.0 Vdc) TTL−CMOS
(VOH = 13.5 Vdc) TTL−CMOS
(VOH = 9.0 Vdc) CMOS−CMOS
(VOH = 13.5 Vdc) CMOS−CMOS
(VOH = 13.5 Vdc) CMOS−CMOS
VIH 5.0
5.0
5.0
5.0
10
10
15
10
15
15
2.0
2.0
3.6
3.6
7.1
2.0
2.0
3.5
3.5
7.0
1.5
1.5
2.75
2.75
5.5
2.0
2.0
3.5
3.5
7.0
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sin
k
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
5.0
5.0
10
15
– 3.0
0.64
– 1.6
– 4.2
– 2.4
0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
– 1.7
0.36
– 0.9
– 2.4
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current Iin 15 ±0.1 ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package)
CMOS−CMOS Mode
IDD or
ICC
5.0
10
15
0.05
0.10
0.20
0.0005
0.0010
0.0015
0.05
0.10
0.20
1.5
3.0
6.0
mAdc
Quiescent Current
(Per Package)
TTL−CMOS Mode
IDD 5.0
5.0
5.0
5.0
10
15
0.5
1.0
2.0
0.0005
0.0010
0.0015
0.5
1.0
2.0
3.8
7.5
15
mAdc
Quiescent Current
(Per Package)
TTL−CMOS Mode
ICC 5.0
5.0
5.0
5.0
10
15
5.0
5.0
5.0
2.5
2.5
2.5
5.0
5.0
5.0
6.0
6.0
6.0
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Egg
MC14504B
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4
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic Symbol Shifting Mode VCC
Vdc VDD
Vdc
Limits
Unit
Min Typ
(Note 3) Max
Propagation Delay, High to Low tPHL TTL – CMOS
VDD > VCC
5.0
5.0 10
15
140
140 280
280 ns
CMOS – CMOS
VDD > VCC
5.0
5.0
10
10
15
15
120
120
70
240
240
140
CMOS – CMOS
VCC > VDD
10
15
15
5.0
5.0
10
185
185
175
370
370
350
Propagation Delay, Low to High tPLH TTL – CMOS
VDD > VCC
5.0
5.0 10
15
170
160 340
320 ns
CMOS – CMOS
VDD > VCC
5.0
5.0
10
10
15
15
170
170
100
340
340
200
CMOS – CMOS
VCC > VDD
10
15
15
5.0
5.0
10
275
275
145
550
550
290
Output Rise and Fall Time tTLH, tTHL ALL −
5.0
10
15
100
50
40
200
100
80
ns
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TTL to CMOS Mode
Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary TTL to CMOS Mode
20151050
VDD, SUPPLY VOLTAGE (Vdc)
7
6
5
4
3
2
1
0
VSp, INPUT SWITCHPOINT VOLTAGE (Vdc)
20151050
VDD, SUPPLY VOLTAGE (Vdc)
7
6
5
4
3
2
1
0
VSp, INPUT SWITCHPOINT VOLTAGE (Vdc)
VCC = 10 V
VCC = 5 V
VCC = 5 V
VDD, SUPPLY VOLTAGE (Vdc)
20
15
10
5
0
20151050
VCC, SUPPLY VOLTAGE (Vdc)
VDD, SUPPLY VOLTAGE (Vdc)
20
15
10
5
0
20151050
VCC, SUPPLY VOLTAGE (Vdc)
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MC14504B
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5
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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MC14504B
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6
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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MC14504B
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7
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LEQ1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
MC14504B/D
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