Virtex-5 Family Overview

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DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 1
© 2006–2010, 2014, 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All
other trademarks are the property of their respective owners.
Virtex-5 FPGA Electrical Characteristics
Virtex®-5 FPGAs are available in -3, -2, -1 speed grades,
with -3 having the highest performance. Virtex-5 FPGA DC
and AC characteristics are specified for both commercial
and industrial grades. Except the operating temperature
range or unless otherwise noted, all the DC and AC
electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade
industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades
and/or devices might be available in the industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Virtex-5 FPGA data sheet, part of an overall set of
documentation on the Virtex-5 family of FPGAs, is available
on the Xilinx website:
Virtex-5 Family Overview
Virtex-5 FPGA User Guide
Virtex-5 FPGA Configuration Guide
Virtex-5 FPGA XtremeDSP™ Design Considerations
Virtex-5 FPGA Packaging and Pinout Specification
Embedded Processor Block in Virtex-5 FPGAs Reference
Guide
Virtex-5 FPGA RocketIO™ GTP Transceiver User Guide
Virtex-5 FPGA RocketIO GTX Transceiver User Guide
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User
Guide
Virtex-5 FPGA Integrated Endpoint Block User Guide for
PCI Express® Designs
Virtex-5 FPGA System Monitor User Guide
Virtex-5 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-5 FPGA DC Characteristics
0
Virtex-5 FPGA Data Sheet:
DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 00 Product Specification
Table 1: Absolute Maximum Ratings
Symbol Description Units
VCCINT Internal supply voltage relative to GND –0.5 to 1.1 V
VCCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0 V
VCCO Output drivers supply voltage relative to GND –0.5 to 3.75 V
VBATT Key memory battery backup supply –0.5 to 4.05 V
VREF Input reference voltage –0.5 to 3.75 V
VIN(3)
3.3V I/O input voltage relative to GND(4) (user and dedicated I/Os) –0.75 to 4.05 V
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(5)
–0.95 to 4.4
(Commercial Temperature) V
–0.85 to 4.3
(Industrial Temperature)
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) –0.75 to VCCO +0.5 V
IIN
Current applied to an I/O pin, powered or unpowered ±100 mA
Total current applied to all I/O pins, powered or unpowered ±100 mA
VTS
Voltage applied to 3-state 3.3V output(4) (user and dedicated I/Os) –0.75 to 4.05 V
Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os) –0.75 to VCCO +0.5 V
TSTG Storage temperature (ambient) –65 to 150 °C
TSOL Maximum soldering temperature(2) +220 °C
TJMaximum junction temperature(2) +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute
Maximum Ratings conditions for extended periods of time might affect device reliability.
2. For soldering guidelines, refer to UG112: Device Package User Guide. For thermal considerations, refer to UG195: Virtex-5 FPGA Packaging and
Pinout Specification on the Xilinx website.
3. 3.3V I/O absolute maximum limit applied to DC and AC signals.
4. For 3.3V I/O operation, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
5.
For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20% of a data period
.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 2
Table 2: Recommended Operating Conditions
Symbol Description Temperature Range Min Max Units
VCCINT
Internal supply voltage relative to GND, TJ=0°C to +85°C Commercial 0.95 1.05 V
Internal supply voltage relative to GND, TJ=–40°C to +100°C Industrial 0.95 1.05 V
VCCAUX(1) Auxiliary supply voltage relative to GND, TJ=0°C to +85°C Commercial 2.375 2.625 V
Auxiliary supply voltage relative to GND, TJ= –40°C to +100°C Industrial 2.375 2.625 V
VCCO(2,4,5) Supply voltage relative to GND, TJ=0°C to +85°C Commercial 1.14 3.45 V
Supply voltage relative to GND, TJ=–40°C to +100°C Industrial 1.14 3.45 V
VIN
3.3V supply voltage relative to GND, TJ=0°C to +85°C Commercial GND – 0.20 3.45 V
3.3V supply voltage relative to GND, TJ= –40°C to +100°C Industrial GND – 0.20 3.45 V
2.5V and below supply voltage relative to GND,
TJ=0°C to +85°C
Commercial GND – 0.20 VCCO +0.2 V
2.5V and below supply voltage relative to GND,
TJ= –40°C to +100°C
Industrial GND – 0.20 VCCO +0.2 V
IIN(6) Maximum current through any pin in a powered or unpowered
bank when forward biasing the clamp diode
Commercial 10 mA
Industrial 10 mA
VBATT(3) Battery voltage relative to GND, TJ=0°C to +85°C Commercial 1.0 3.6 V
Battery voltage relative to GND, TJ= –40°C to +100°C Industrial 1.0 3.6 V
Notes:
1. Recommended maximum voltage drop for VCCAUX is 10 mV/ms.
2. Configuration data is retained even if VCCO drops to 0V.
3. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
5. The configuration supply voltage VCC_CONFIG is also known as VCCO_0.
6. A total of 100 mA per bank should not be exceeded.
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Data Rate Min Typ Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 V
IREF VREF leakage current per pin 10 µA
ILInput or output leakage current per pin (sample-tested) 10 µA
CIN Input capacitance (sample-tested) 8pF
IRPU(1)
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.3V 20 150 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =2.5V 10 90 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.8V 5 45 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.5V 3 30 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.2V 2 15 µA
IRPD(1) Pad pull-down (when selected) @ VIN =2.5V 5 110 µA
IBATT(2) Battery supply current 150 nA
n Temperature diode ideality factor 1.0002 n
r Series resistance 5.0 Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum value specified for worst case process at 25°C.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 3
Important Note
Typical values for quiescent supply current are now specified at nominal voltage, 85°C junction temperatures (Tj). Xilinx
recommends analyzing static power consumption at Tj= 85°C because the majority of designs operate near the high end of
the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent
supply current at Tj= 25°C. Quiescent supply current is specified by speed grade for Virtex-5 devices. Use the XPOWER™
Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for
conditions other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current
Symbol Description Device Speed and Temperature Grade Units
-3 (C) -2 (C & I) -1 (C & I)
ICCINTQ Quiescent VCCINT supply current XC5VLX20T N/A 406 253 mA
XC5VLX30 480 480 300 mA
XC5VLX30T 507 507 317 mA
XC5VLX50 651 651 449 mA
XC5VLX50T 689 689 475 mA
XC5VLX85 1072 1072 833 mA
XC5VLX85T 1115 1115 866 mA
XC5VLX110 1391 1391 1109 mA
XC5VLX110T 1448 1448 1154 mA
XC5VLX155 2615 2615 2141 mA
XC5VLX155T 2674 2674 2188 mA
XC5VLX220 N/A 2783 2278 mA
XC5VLX220T N/A 2844 2328 mA
XC5VLX330 N/A 4193 3432 mA
XC5VLX330T N/A 4267 3492 mA
XC5VSX35T 720 720 554 mA
XC5VSX50T 1092 1092 840 mA
XC5VSX95T N/A 1924 1475 mA
XC5VSX240T N/A 4137 3168 mA
XC5VTX150T N/A 2067 2067 mA
XC5VTX240T N/A 2881 2881 mA
XC5VFX30T 1024 1024 1024 mA
XC5VFX70T 1658 1658 1658 mA
XC5VFX100T 2875 2875 2875 mA
XC5VFX130T 3041 3041 3041 mA
XC5VFX200T N/A 3755 3755 mA
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 4
ICCOQ Quiescent VCCO supply current XC5VLX20T N/A 2 2 mA
XC5VLX30 1.5 1.5 1.5 mA
XC5VLX30T 1.5 1.5 1.5 mA
XC5VLX50 2 2 2 mA
XC5VLX50T 2 2 2 mA
XC5VLX85 3 3 3 mA
XC5VLX85T 3 3 3 mA
XC5VLX110 4 4 4 mA
XC5VLX110T 4 4 4 mA
XC5VLX155 8 8 8 mA
XC5VLX155T 8 8 8 mA
XC5VLX220 N/A 8 8 mA
XC5VLX220T N/A 8 8 mA
XC5VLX330 N/A 12 12 mA
XC5VLX330T N/A 12 12 mA
XC5VSX35T 1.5 1.5 1.5 mA
XC5VSX50T 2 2 2 mA
XC5VSX95T N/A 4 4 mA
XC5VSX240T N/A 12 12 mA
XC5VTX150T N/A 7 7 mA
XC5VTX240T N/A 7 7 mA
XC5VFX30T 4 4 4 mA
XC5VFX70T 6 6 6 mA
XC5VFX100T 7 7 7 mA
XC5VFX130T 8 8 8 mA
XC5VFX200T N/A 10 10 mA
Table 4: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device Speed and Temperature Grade Units
-3 (C) -2 (C & I) -1 (C & I)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 5
ICCAUXQ Quiescent VCCAUX supply current XC5VLX20T N/A 32 32 mA
XC5VLX30 38 38 38 mA
XC5VLX30T 43 43 43 mA
XC5VLX50 57 57 57 mA
XC5VLX50T 62 62 62 mA
XC5VLX85 93 93 93 mA
XC5VLX85T 98 98 98 mA
XC5VLX110 125 125 125 mA
XC5VLX110T 130 130 130 mA
XC5VLX155 172 172 172 mA
XC5VLX155T 177 177 177 mA
XC5VLX220 N/A 229 229 mA
XC5VLX220T N/A 236 236 mA
XC5VLX330 N/A 345 345 mA
XC5VLX330T N/A 353 353 mA
XC5VSX35T 49 49 49 mA
XC5VSX50T 74 74 74 mA
XC5VSX95T N/A 131 131 mA
XC5VSX240T N/A 300 300 mA
XC5VTX150T N/A 180 180 mA
XC5VTX240T N/A 300 300 mA
XC5VFX30T606060mA
XC5VFX70T 110 110 110 mA
XC5VFX100T 150 150 150 mA
XC5VFX130T 180 180 180 mA
XC5VFX200T N/A 250 250 mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as
commercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE)
or XPOWER Analyzer (XPA) tools.
Table 4: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device Speed and Temperature Grade Units
-3 (C) -2 (C & I) -1 (C & I)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 6
Power-On Power Supply Requirements
Xilinx® FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
recommended power-on sequence of VCCINT, VCCAUX, and
VCCO. The I/O will remain 3-stated through power-on if the
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.
Table 5 shows the minimum current required by Virtex-5
devices for proper power-on and configuration.
If the current minimums shown in Table 5 are met, the
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
The FPGA must be configured after VCCINT is applied.
Once initialized and configured, use the XPOWER tools to
estimate current drain on these supplies.
Table 5: Power-On Current for Virtex-5 Devices
Device ICCINTMIN ICCAUXMIN ICCOMIN Units
Typ(1) Typ(1) Typ(1)
XC5VLX20T 172 54 50 mA
XC5VLX30 235 76 50 mA
XC5VLX30T 246 86 50 mA
XC5VLX50 320 114 50 mA
XC5VLX50T 336 124 50 mA
XC5VLX85 492 186 100 mA
XC5VLX85T 515 196 100 mA
XC5VLX110 623 250 100 mA
XC5VLX110T 651 260 100 mA
XC5VLX155 695 351 100 mA
XC5VLX155T 728 368 100 mA
XC5VLX220 1023 458 150 mA
XC5VLX220T 1056 472 150 mA
XC5VLX330 1470 690 150 mA
XC5VLX330T 1509 706 150 mA
XC5VSX35T 307 98 50 mA
XC5VSX50T 472 148 50 mA
XC5VSX95T 804 262 100 mA
XC5VSX240T 1632 662 150 mA
XC5VTX150T 969 386 150 mA
XC5VTX240T 1245 572 150 mA
XC5VFX30T 358 116 50 mA
XC5VFX70T 695 232 100 mA
XC5VFX100T 749 298 100 mA
XC5VFX130T 1111 392 150 mA
XC5VFX200T 1222 534 150 mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. The maximum startup current can be obtained using the
XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools
and adding the quiescent plus dynamic current consumption.
Table 5: Power-On Current for Virtex-5 Devices
Device ICCINTMIN ICCAUXMIN ICCOMIN Units
Typ(1) Typ(1) Typ(1)
Table 6: Power Supply Ramp Time
Symbol Description Ramp Time Units
VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms
VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms
VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 7
SelectIO™ DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
LVTTL –0.3 0.8 2.0 3.45 0.4 2.4 Note(3) Note(3)
LVCMOS33,
LVDCI33
–0.3 0.8 2.0 3.45 0.4 VCCO – 0.4 Note(3) Note(3)
LVCMOS25,
LVDCI25
–0.3 0.7 1.7 VCCO +0.3 0.4 V
CCO – 0.4 Note(3) Note(3)
LVCMOS18,
LVDCI18
–0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO – 0.45 Note(4) Note(4)
LVCMOS15,
LVDCI15
–0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(4) Note(4)
LVCMOS12 –0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(6) Note(6)
PCI33_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5)
PCI66_3(5) –0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5)
PCI-X(5) –0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5)
GTLP –0.3 VREF –0.1 V
REF + 0.1 0.6 N/A 36 N/A
GTL –0.3 VREF –0.05 V
REF +0.05 0.4 N/A 32 N/A
HSTL I_12 –0.3 VREF –0.1 V
REF +0.1 V
CCO + 0.3 25% VCCO 75% VCCO 6.3 6.3
HSTL I(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO –0.4 8 8
HSTL II(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO –0.4 16 16
HSTL III(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO – 0.4 24 –8
HSTL IV(2) –0.3 VREF –0.1 V
REF +0.1 V
CCO +0.3 0.4 V
CCO – 0.4 48 –8
DIFF HSTL I(2) –0.3 50% VCCO – 0.1 50% VCCO +0.1 V
CCO +0.3 –
DIFF HSTL II(2) –0.3 50% VCCO – 0.1 50% VCCO +0.1 V
CCO +0.3 –
SSTL2 I –0.3 VREF –0.15 V
REF +0.15 V
CCO +0.3 V
TT –0.61 V
TT + 0.61 8.1 –8.1
SSTL2 II –0.3 VREF –0.15 V
REF +0.15 V
CCO +0.3 V
TT –0.81 V
TT + 0.81 16.2 –16.2
DIFF SSTL2 I –0.3 50% VCCO
0.15
50%
VCCO +0.15
VCCO +0.3 –
DIFF SSTL2 II –0.3 50% VCCO
0.15
50%
VCCO +0.15
VCCO +0.3 –
SSTL18 I –0.3 VREF – 0.125 VREF + 0.125 VCCO +0.3 V
TT –0.47 V
TT + 0.47 6.7 –6.7
SSTL18 II –0.3 VREF – 0.125 VREF +0.125 V
CCO +0.3 V
TT –0.60 V
TT + 0.60 13.4 –13.4
DIFF SSTL18 I –0.3 50% VCCO
0.125
50%
VCCO +0.125
VCCO +0.3 –
DIFF SSTL18 II –0.3 50% VCCO
0.125
50%
VCCO +0.125
VCCO +0.3 –
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
6. Supported drive strengths of 2, 4, 6, or 8 mA.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 8
HT DC Specifications (HT_25)
LVDS DC Specifications (LVDS_25)
Extended LVDS DC Specifications (LVDSEXT_25)
Table 8: HT DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOD Differential Output Voltage RT = 100 Ω across Q and Q signals 495 600 715 mV
Δ VOD Change in VOD Magnitude –15 15 mV
VOCM Output Common Mode Voltage RT = 100 Ω across Q and Q signals 495 600 715 mV
Δ VOCM Change in VOCM Magnitude –15 15 mV
VID Input Differential Voltage 200 600 1000 mV
Δ VID Change in VID Magnitude –15 15 mV
VICM Input Common Mode Voltage 440 600 780 mV
Δ VICM Change in VICM Magnitude –15 15 mV
Table 9: LVDS DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.825 V
VODIFF Differential Output Voltage (Q – Q),
Q = High (Q –Q), Q = High
RT = 100 Ω across Q and Q signals 247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.125 1.250 1.375 V
VIDIFF Differential Input Voltage (Q – Q),
Q = High (Q –Q), Q = High
100 350 600 mV
VICM Input Common-Mode Voltage 0.3 1.2 2.2 V
Table 10: Extended LVDS DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.785 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.715 V
VODIFF Differential Output Voltage (Q – Q),
Q = High (Q –Q), Q = High
RT = 100 Ω across Q and Q signals 350 820 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.125 1.250 1.375 V
VIDIFF Differential Input Voltage (Q – Q),
Q = High (Q –Q), Q = High
Common-mode input voltage = 1.25V 100 1000 mV
VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.3 1.2 2.2 V
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 9
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see UG190:
Virtex-5 FPGA User Guide, Chapter 6, SelectIO Resources.
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information.
Table 11: LVPECL DC Specifications
Symbol DC Parameter Min Typ Max Units
VOH Output High Voltage VCC – 1.025 1.545 VCC –0.88 V
VOL Output Low Voltage VCC 1.81 0.795 VCC –1.62 V
VICM Input Common-Mode Voltage 0.6 2.2 V
VIDIFF Differential Input Voltage(1,2) 0.100 1.5 V
Notes:
1. Recommended input maximum voltage not to exceed VCCO +0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
Table 12: Processor Block Switching Characteristics
Clock Name Description Speed Grade Units
-3 -2 -1
CPMC440CLK CPU clock 550 475 400 MHz
CPMINTERCONNECTCLK Xbar clock 366.6 316.6 266.6 MHz
CPMPPCS0PLBCLK Slave 0 PLB clock(1) 183.3 158.3 133.3 MHz
CPMPPCS1PLBCLK Slave 1 PLB clock(1) 183.3 158.3 133.3 MHz
CPMPPCMPLBCLK Master PLB clock(1) 183.3 158.3 133.3 MHz
CPMMCCLK Memory interface clock(1)(2) 366.6 316.6 266.6 MHz
CPMFCMCLK FCM clock(1) 275 237.5 200 MHz
CPMDCRCLK FPGA logic DCR clock(1) 183.3 158.3 133.3 MHz
CPMDMA0LLCLK DMA0 LL clock(1) 250 250 200 MHz
CPMDMA1LLCLK DMA1 LL clock(1) 250 250 200 MHz
CPMDMA2LLCLK DMA2 LL clock(1) 250 250 200 MHz
CPMDMA3LLCLK DMA3 LL clock(1) 250 250 200 MHz
JTGC440TCK JTAG clock 50 50 50 MHz
CPMC440TIMERCLOCK Timer clock 275 237.5 200 MHz
Notes:
1. Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent.
2. Refer to DS567 for maximum clock speed of designs using the DDR2 Memory Controller for PowerPC® 440 Processors.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 10
Table 13: Processor Block MIB Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMMCCLK 1.146 1.247 1.463 ps
TCK_ADDRESS CPMMCCLK 1.017 1.136 1.38 ps
TCK_DATA CPMMCCLK 1.076 1.172 1.38 ps
TCONTROL_CK CPMMCCLK 0.736 0.844 0.941 ps
TDATA_CK CPMMCCLK 0.834 0.95 1.058 ps
Table 14: Processor Block PLBM Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMPPCMPLBCLK 0.971 1.095 1.354 ps
TCK_ADDRESS CPMPPCMPLBCLK 1.215 1.372 1.673 ps
TCK_DATA CPMPPCMPLBCLK 1.115 1.257 1.535 ps
TCONTROL_CK CPMPPCMPLBCLK 1.7 1.79 1.86 ps
TDATA_CK CPMPPCMPLBCLK 0.774 0.914 1.059 ps
Table 15: Processor Block PLBS0 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMPPCS0PLBCLK 1.063 1.196 1.462 ps
TCK_DATA CPMPPCS0PLBCLK 1.052 1.189 1.461 ps
TCONTROL_CK CPMPPCS0PLBCLK 1.307 1.545 1.836 ps
TADDRESS_CK CPMPPCS0PLBCLK 1.253 1.492 1.787 ps
TDATA_CK CPMPPCS0PLBCLK 0.825 0.971 1.124 ps
Table 16: Processor Block PLBS1 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMPPCS1PLBCLK 1.083 1.234 1.525 ps
TCK_DATA CPMPPCS1PLBCLK 1.146 1.298 1.615 ps
TCONTROL_CK CPMPPCS1PLBCLK 1.335 1.596 1.921 ps
TADDRESS_CK CPMPPCS1PLBCLK 1.328 1.568 1.864 ps
TDATA_CK CPMPPCS1PLBCLK 0.821 0.969 1.127 ps
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Product Specification 11
Table 17: Processor Block DMA0 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMDMA0LLCLK 1.256 1.42 1.665 ps
TCK_DATA CPMDMA0LLCLK 1.312 1.472 1.712 ps
TCONTROL_CK CPMDMA0LLCLK 0.453 0.558 0.716 ps
TDATA_CK CPMDMA0LLCLK –0.105 –0.105 –0.104 ps
Table 18: Processor Block DMA1 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMDMA1LLCLK 1.127 1.266 1.474 ps
TCK_DATA CPMDMA1LLCLK 1.266 1.418 1.645 ps
TCONTROL_CK CPMDMA1LLCLK 0.447 0.555 0.717 ps
TDATA_CK CPMDMA1LLCLK –0.014 0.01 0.046 ps
Table 19: Processor Block DMA2 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMDMA2LLCLK 1.101 1.235 1.437 ps
TCK_DATA CPMDMA2LLCLK 1.127 1.262 1.463 ps
TCONTROL_CK CPMDMA2LLCLK 0.771 0.924 1.155 ps
TDATA_CK CPMDMA2LLCLK 0.135 0.142 0.168 ps
Table 20: Processor Block DMA3 Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMDMA3LLCLK 1.094 1.242 1.462 ps
TCK_DATA CPMDMA3LLCLK 1.056 1.184 1.376 ps
TCONTROL_CK CPMDMA3LLCLK 0.636 0.767 0.965 ps
TDATA_CK CPMDMA3LLCLK 0.087 0.119 0.116 ps
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 12
Table 21: Processor Block DCR Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMDCRCLK
TCK_ADDRESS CPMDCRCLK
TCK_DATA CPMDCRCLK
TCONTROL_CK CPMDCRCLK
TADDRESS_CK CPMDCRCLK
TDATA_CK CPMDCRCLK
Table 22: Processor Block FCM Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CPMFCMCLK 0.967 1.084 1.324 ps
TCK_DATA CPMFCMCLK 1.041 1.158 1.4 ps
TCK_INSTRUCTION CPMFCMCLK 0.701 0.818 1.06 ps
TCONTROL_CK CPMFCMCLK 1.057 1.218 1.395 ps
TDATA_CK CPMFCMCLK 0.608 0.698 0.768 ps
TRESULT_CK CPMFCMCLK 0.608 0.698 0.768 ps
Table 23: Processor Block MISC Switching Characteristics
Clock Name Description Reference Clock Speed Grade Units
-3 -2 -1
Clock-to-out and setup relative to clock
TCK_CONTROL CLK1
TCK_ADDRESS CLK2
TCK_DATA CLK3
TCONTROL_CK CLK4
TADDRESS_CK CLK5
TDATA_CK CLK6
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 13
GTP_DUAL Tile Specifications
GTP_DUAL Tile DC Characteristics
Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles
Symbol Description Units
MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND –0.5 to 1.32 V
MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND –0.5 to 1.32 V
MGTAVTTRX Analog supply voltage for the GTP_DUAL receivers relative to GND –0.5 to 1.32 V
MGTAVCC Analog supply voltage for the GTP_DUAL common circuits relative to GND –0.5 to 1.1 V
MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
–0.5 to 1.32 V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 25: Recommended Operating Conditions for GTP_DUAL Tiles(1)(2)
Symbol Description Min Max Units
MGTAVCCPLL(1) Analog supply voltage for the GTP_DUAL shared PLL relative to GND 1.14 1.26 V
MGTAVTTTX(1) Analog supply voltage for the GTP_DUAL transmitters relative to GND 1.14 1.26 V
MGTAVTTRX(1) Analog supply voltage for the GTP_DUAL receivers relative to GND 1.14 1.26 V
MGTAVCC(1) Analog supply voltage for the GTP_DUAL common circuits relative to GND 0.95 1.05 V
MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
1.14 1.26 V
Notes:
1. Each voltage listed requires the filter circuit described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
2. Voltages are specified for the temperature range of TJ = –40°C to +100°C.
Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles(1)
Symbol Description Min Typ Max Units
IMGTAVTTTX GTP_DUAL tile transmitter termination supply current(2) 71 90 mA
IMGTAVCCPLL GTP_DUAL tile shared PLL supply current 36 60 mA
IMGTAVTTRXC GTP_DUAL tile resistor termination calibration supply current 0.1 0.5 mA
IMGTAVTTRX GTP_DUAL tile receiver termination supply current(3) 0.1 0.5 mA
IMGTAVCC GTP_DUAL tile internal analog supply current 56 110 mA
MGTRREF Precision reference resistor for internal calibration termination 49.9 ± 1% tolerance Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2. ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings.
3. AC coupled TX/RX link.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 14
GTP_DUAL Tile DC Input and Output Levels
Table 28 summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5 FPGAs. Figure 1 shows the single-
ended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage.
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details.
Table 27: GTP_DUAL Tile Quiescent Supply Current
Symbol Description Typ(1) Max Units
IAVTTTXQ Quiescent MGTAVTTTX (transmitter termination) supply current 8.5 18 mA
IAVCCPLLQ Quiescent MGTAVCCPLL (PLL) supply current 8 18 mA
IAVTTRXQ Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
0.1 0.8 mA
IAVCCQ Quiescent MGTAVCC (analog) supply current 2.5 11 mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Device powered and unconfigured.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4. GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTP_DUAL tiles in the target LXT or SXT device.
Table 28: GTP_DUAL Tile DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPIN
Differential peak-to-peak input
voltage
External AC coupled 3.2 Gb/s 150 2000 mV
External AC coupled >3.2 Gb/s 180 2000 mV
VIN
Absolute input voltage DC coupled –400 MGTAVTTRX
+ 400
up to 1320
mV
VCMIN Common mode input voltage DC coupled
MGTAVTTRX = 1.2V
800 mV
DVPPOUT Differential peak-to-peak output
voltage(1)
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
1400 mV
VSEOUT Single-ended output voltage
swing(1)
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
700 mV
VCMOUT Common mode output voltage Equation based
MGTAVTTTX = 1.2V
1200 – VSEOUT/2 mV
RIN Differential input resistance 90 100 120 Ω
ROUT Differential output resistance 90 100 120 Ω
TOSKEW Transmitter output skew 15 ps
CEXT Recommended external AC coupling capacitor(2) 75 100 200 nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 FPGA RocketIO GTP
Transceiver User Guide and can result in values lower than reported in this table.
2. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
Figure 1: Single-Ended Output Voltage Swing
0
+V P
NVSEOUT
ds202_01_051607
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 15
Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 FPGA
RocketIO GTP Transceiver User Guide for further details.
X-Ref Target - Figure 2
Figure 2: Peak-to-Peak Differential Output Voltage
Table 29: GTP_DUAL Tile Clock DC Input Specifications(1)
Symbol DC Parameter Conditions Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 200 800 2000 mV
VISE Single-ended input voltage 100 400 1000 mV
RIN Differential input resistance 80 105 130 Ω
CEXT Required external AC coupling capacitor 75 100 200 nF
Notes:
1. VMIN = 0V and VMAX = 1200mV
X-Ref Target - Figure 3
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
0
+V
–V
P–N
DVPPOUT
ds202_02_081809
0
+V P
N
VISE
ds202_03_052708
0
+V
–V
P – N
VIDIFF
ds202_04_052708
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 16
GTP_DUAL Tile Switching Characteristics
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Symbol Description Speed Grade Units
-3 -2 -1
FGTPMAX Maximum GTP transceiver data rate 3.75 3.75 3.2 Gb/s
FGPLLMAX Maximum PLL frequency 2.0 2.0 2.0 GHz
FGPLLMIN Minimum PLL frequency 1.0 1.0 1.0 GHz
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
FGTPDRPCLK GTP DCLK (DRP clock) maximum frequency 200 175 150 MHz
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range(1) CLK 60 350 MHz
TRCLK Reference clock rise time 20% – 80% 200 400 ps
TFCLK Reference clock fall time 80% – 20% 200 400 ps
TDCREF Reference clock duty cycle(2) CLK 40 50 60 %
TGJTT Reference clock total jitter, peak-peak(3) CLK 40 ps
TLOCK Clock recovery frequency acquisition
time
Initial PLL lock 1 ms
TPHASE Clock recovery phase acquisition time Lock to data after PLL has
locked to the reference clock
200 µs
Notes:
1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to
1Gb/s.
2. For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
3. Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification TGJTT.
X-Ref Target - Figure 5
Figure 5: Reference Clock Timing Parameters
ds202_05_100506
80%
20%
T
FCLK
T
RCLK
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 17
Table 33: GTP_DUAL Tile User Clock Switching Characteristics(1)
Symbol Description Conditions Speed Grade Units
-3 -2 -1
FTXOUT TXOUTCLK maximum frequency 375 375 320 MHz
FRXREC RXRECCLK maximum frequency 375 375 320 MHz
TRX RXUSRCLK maximum frequency 375 375 320 MHz
TRX2 RXUSRCLK2 maximum frequency RXDATAWIDTH = 0 350 350 320 MHz
RXDATAWIDTH = 1 187.5 187.5 160 MHz
TTX TXUSRCLK maximum frequency 375 375 320 MHz
TTX2 TXUSRCLK2 maximum frequency TXDATAWIDTH = 0 350 350 320 MHz
TXDATAWIDTH = 1 187.5 187.5 160 MHz
Notes:
1. Clocking must be implemented as described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
Symbol Description Min Typ Max Units
FGTPTX Serial data rate range 0.1 FGTPMAX Gb/s
TRTX TX Rise time 140 ps
TFTX TX Fall time 120 ps
TLLSKEW TX lane-to-lane skew(1) 855 ps
VTXOOBVDPP Electrical idle amplitude 20 mV
TTXOOBTRANS Electrical idle transition time 40 ns
TJ3.75 Total Jitter(2) 3.75 Gb/s 0.35 UI
DJ3.75 Deterministic Jitter(2) 0.19 UI
TJ3.2 Total Jitter(2) 3.20 Gb/s 0.35 UI
DJ3.2 Deterministic Jitter(2) 0.19 UI
TJ2.5 Total Jitter(2) 2.50 Gb/s 0.30 UI
DJ2.5 Deterministic Jitter(2) 0.14 UI
TJ2.0 Total Jitter(2) 2.00 Gb/s 0.30 UI
DJ2.0 Deterministic Jitter(2) 0.14 UI
TJ1.25 Total Jitter(2) 1.25 Gb/s 0.20 UI
DJ1.25 Deterministic Jitter(2) 0.10 UI
TJ1.00 Total Jitter(2) 1.00 Gb/s 0.20 UI
DJ1.00 Deterministic Jitter(2) 0.10 UI
TJ500 Total Jitter(2) 500 Mb/s 0.10 UI
DJ500 Deterministic Jitter(2) 0.04 UI
TJ100 Total Jitter(2) 100 Mb/s 0.02 UI
DJ100 Deterministic Jitter(2) 0.01 UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
3. All jitter values are based on a Bit-Error Ratio of 1e–12.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 18
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol Description Min Typ Max Units
FGTPRX Serial data rate RX oversampler not enabled 0.5 FGTPMAX Gb/s
RX oversampler enabled 0.1 0.5 Gb/s
RXOOBVDPP OOB detect threshold
peak-to-peak OOBDETECT_THRESHOLD = 100 60 105 165 mV
RXSST Receiver spread-spectrum
tracking(1) Modulated @ 33 KHz –5000 0 ppm
RXRL Run length (CID) Internal AC capacitor bypassed 150 UI
RXPPMTOL Data/REFCLK PPM offset
tolerance(2)
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 1(3)
–200 200 ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 2(3)
–200 200 ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 4(3) –100 100 ppm
CDR 2nd-order loop enabled –1000 1000 ppm
SJ Jitter Tolerance(4)
JT_SJ3.75 Sinusoidal Jitter(5) 3.75 Gb/s 0.30 UI
JT_SJ3.2 Sinusoidal Jitter(5) 3.20 Gb/s 0.40 UI
JT_SJ2.50 Sinusoidal Jitter(5) 2.50 Gb/s 0.40 UI
JT_SJ2.00 Sinusoidal Jitter(5) 2.00 Gb/s 0.40 UI
JT_SJ1.00 Sinusoidal Jitter(5) 1.00 Gb/s 0.30 UI
JT_SJ500 Sinusoidal Jitter(5) 500 Mb/s 0.30 UI
JT_SJ500 Sinusoidal Jitter(5) 500 Mb/s OS 0.30 UI
JT_SJ100 Sinusoidal Jitter(5) 100 Mb/s OS 0.30 UI
SJ Jitter Tolerance with Stressed Eye(4)
JT_TJSE3.2 Total Jitter with Stressed
Eye(6)
3.20 Gb/s 0.87 UI
JT_SJSE3.2 Sinusoidal Jitter with
Stressed Eye(6)
3.20 Gb/s 0.30 UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1 only.
2. Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3. CDR 1st-order step size set to 2.
4. All jitter values are based on a Bit Error Ratio of 1e–12.
5. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
6. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 19
GTX_DUAL Tile Specifications
GTX_DUAL Tile DC Characteristics
Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles
Symbol Description Units
MGTAVCCPLL Analog supply voltage for the GTX_DUAL shared PLL relative to GND –0.5 to 1.1 V
MGTAVTTTX Analog supply voltage for the GTX_DUAL transmitters relative to GND –0.5 to 1.32 V
MGTAVTTRX Analog supply voltage for the GTX_DUAL receivers relative to GND –0.5 to 1.32 V
MGTAVCC Analog supply voltage for the GTX_DUAL common circuits relative to GND –0.5 to 1.1 V
MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
–0.5 to 1.32 V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 37: Recommended Operating Conditions for GTX_DUAL Tiles(1)(2)
Symbol Description Min Max Units
MGTAVCCPLL(1) Analog supply voltage for the GTX_DUAL shared PLL relative to GND 0.95 1.05 V
MGTAVTTTX(1) Analog supply voltage for the GTX_DUAL transmitters relative to GND 1.14 1.26 V
MGTAVTTRX(1) Analog supply voltage for the GTX_DUAL receivers relative to GND 1.14 1.26 V
MGTAVCC(1) Analog supply voltage for the GTX_DUAL common circuits relative to GND 0.95 1.05 V
MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
1.14 1.26 V
Notes:
1. Each voltage listed requires the filter circuit described in UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
2. Voltages are specified for the temperature range of TJ = –40°C to +100°C.
Table 38: DC Characteristics Over Recommended Operating Conditions for GTX_DUAL Tiles(1)
Symbol Description Min Typ Max Units
IMGTAVTTTX GTX_DUAL tile transmitter termination supply current(2) 43.3 86.3 mA
IMGTAVCCPLL GTX_DUAL tile shared PLL supply current 38.0 99.4 mA
IMGTAVTTRXC GTX_DUAL tile resistor termination calibration supply current 0.1 0.5 mA
IMGTAVTTRX GTX_DUAL tile receiver termination supply current(3) 40.3 56.5 mA
IMGTAVCC GTX_DUAL tile internal analog supply current 80.5 179.5 mA
MGTRREF Precision reference resistor for internal calibration termination 59.0 ± 1% tolerance Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2. ICC numbers are given per GTX_DUAL tile with both GTX transceivers operating with default settings.
3. AC coupled TX/RX link.
4. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
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Product Specification 20
GTX_DUAL Tile DC Input and Output Levels
Table 40 summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5 FPGAs. Figure 6 shows the single-
ended output voltage swing. Figure 7 shows the peak-to-peak differential output voltage.
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details.
Table 39: GTX_DUAL Tile Quiescent Supply Current
Symbol Description Typ(1) Max Units
IAVTTTXQ Quiescent MGTAVTTTX (transmitter termination) supply current 8.2 21.6 mA
IAVCCPLLQ Quiescent MGTAVCCPLL (PLL) supply current 0.8 4.8 mA
IAVTTRXQ Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
1.2 12.0 mA
IAVCCQ Quiescent MGTAVCC (analog) supply current 9.0 50.4 mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Device powered and unconfigured.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4. GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTX_DUAL tiles in the target TXT or FXT device.
Table 40: GTX_DUAL Tile DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPIN
Differential peak-to-peak input
voltage
External AC coupled 4.25 Gb/s 125 1800 mV
External AC coupled >4.25 Gb/s 125 1800 mV
VIN Absolute input voltage DC coupled
MGTAVTTRX = 1.2V
–400 MGTAVTTRX +400
up to 1320
mV
VCMIN Common mode input voltage DC coupled
MGTAVTTRX = 1.2V
800 mV
DVPPOUT Differential peak-to-peak output
voltage(1) TXBUFDIFFCTRL = 111 1400 mV
VSEOUT Single-ended output voltage
swing(1)
TXBUFDIFFCTRL = 111 700 mV
VCMOUT Common mode output voltage Equation based
MGTAVTTTX = 1.2V
1200 – DVPPOUT/4 mV
RIN Differential input resistance 85 100 120 Ω
ROUT Differential output resistance 85 100 120 Ω
TOSKEW Transmitter output skew 2 8 ps
CEXT Recommended external AC coupling capacitor(2) 75 100 200 nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG198:Virtex-5 FPGA RocketIO GTX
Transceiver User Guide and can result in values lower than reported in this table.
2. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 6
Figure 6: Single-Ended Output Voltage Swing
0
+V P
NVSEOUT
ds202_01_051607
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 21
Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
RocketIO GTX Transceiver User Guide for further details.
X-Ref Target - Figure 7
Figure 7: Peak-to-Peak Differential Output Voltage
Table 41: GTX_DUAL Tile Clock DC Input Level Specification(1)
Symbol DC Parameter Conditions Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 210 800 2000 mV
VISE Single-ended input voltage 105 400 1000 mV
RIN Differential input resistance 90 105 130 Ω
CEXT Required external AC coupling capacitor 100 nF
Notes:
1. VMIN = 0V and VMAX = 1200mV
X-Ref Target - Figure 8
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 9
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
0
+V
–V
P–N
DVPPOUT
ds202_02_081809
0
+V P
N
VISE
ds202_03_052708
0
+V
–V
P – N
VIDIFF
ds202_04_052708
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 22
GTX_DUAL Tile Switching Characteristics
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Symbol Description Speed Grade Units
-3 -2 -1
FGTXMAX Maximum GTX transceiver data rate 6.5 6.5 4.25 Gb/s
FGPLLMAX Maximum PLL frequency 3.25 3.25 3.25 GHz
FGPLLMIN Minimum PLL frequency 1.48 1.48 1.48 GHz
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
FGTXDRPCLK GTX DCLK (DRP clock) maximum frequency 200 175 150 MHz
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range(1) CLK 60 650 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle CLK 40 50 60 %
TGJTT Reference clock total jitter (2, 3) At 100 KHz –145 dBc/Hz
At 1 MHz –150 dBc/Hz
TLOCK Clock recovery frequency acquisition
time
Initial PLL lock 0.25 1 ms
TPHASE Clock recovery phase acquisition time Lock to data after PLL has
locked to the reference clock
200 µs
Notes:
1. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2. GTX_DUAL jitter characteristics measured using a clock with specification TGJTT. A reference clock with higher phase noise can be used
with link margin trade off.
3. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see Table 46 and Table 47.
X-Ref Target - Figure 10
Figure 10: Reference Clock Timing Parameters
ds202_05_100506
80%
20%
T
FCLK
T
RCLK
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 23
Table 45: GTX_DUAL Tile User Clock Switching Characteristics(1)
Symbol Description Conditions Device Speed Grade Units
-3 -2 -1
FTXOUT TXOUTCLK maximum frequency Internal 20-bit datapath FXT 325 325 212.5 MHz
TXT - 325 212.5 MHz
Internal 16-bit datapath FXT 406.25 406.25 265.625 MHz
TXT - 406.25 265.625 MHz
FRXREC RXRECCLK maximum frequency FXT 406.25 406.25 265.625 MHz
TXT - 406.25 265.625 MHz
TRX RXUSRCLK maximum frequency FXT 406.25 406.25 265.625 MHz
TXT - 406.25 265.625 MHz
TRX2 RXUSRCLK2 maximum frequency 1 byte interface FXT 375 312.5 235.625 MHz
2 byte interface 406.25 390.625 265.625 MHz
4 byte interface 203.125 203.125 132.813 MHz
1 byte interface TXT - 312.5 235.625 MHz
2 byte interface - 265.625 265.625 MHz
4 byte interface - 203.125 132.813 MHz
TTX TXUSRCLK maximum frequency FXT 406.25 406.25 265.625 MHz
TXT - 406.25 265.625 MHz
TTX2 TXUSRCLK2 maximum frequency 1 byte interface FXT 375 312.5 235.625 MHz
2 byte interface 406.25 390.625 265.625 MHz
4 byte interface 203.125 203.125 132.813 MHz
1 byte interface TXT - 312.5 235.625 MHz
2 byte interface - 265.625 265.625 MHz
4 byte interface - 203.125 132.813 MHz
Notes:
1. Clocking must be implemented as described in UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTXTX Serial data rate range 0.15 FGTXMAX Gb/s
TRTX TX Rise time 20%–80% 120 ps
TFTX TX Fall time 80%–20% 120 ps
TLLSKEW TX lane-to-lane skew(1) 350 ps
VTXOOBVDPP Electrical idle amplitude 15 mV
TTXOOBTRANSITION Electrical idle transition time 75 ns
TJ6.5 Total Jitter(2) 6.5 Gb/s 0.33 UI
DJ6.5 Deterministic Jitter(2) 0.17 UI
TJ5.0 Total Jitter(2) 5.0 Gb/s 0.33 UI
DJ5.0 Deterministic Jitter(2) 0.15 UI
TJ4.25 Total Jitter(2) 4.25 Gb/s 0.33 UI
DJ4.25 Deterministic Jitter(2) 0.14 UI
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 24
TJ3.75 Total Jitter(2) 3.75 Gb/s 0.34 UI
DJ3.75 Deterministic Jitter(2) 0.16 UI
TJ3.2 Total Jitter(2) 3.2 Gb/s 0.20 UI
DJ3.2 Deterministic Jitter(2) 0.10 UI
TJ3.2L Total Jitter(2) 3.2 Gb/s(3) 0.36 UI
DJ3.2L Deterministic Jitter(2) 0.16 UI
TJ2.5 Total Jitter(2) 2.5 Gb/s 0.20 UI
DJ2.5 Deterministic Jitter(2) 0.08 UI
TJ1.25 Total Jitter(2) 1.25 Gb/s 0.15 UI
DJ1.25 Deterministic Jitter(2) 0.06 UI
TJ750 Total Jitter(2)(4) 750 Mb/s 0.10 UI
DJ750 Deterministic Jitter(2)(4) 0.03 UI
TJ150 Total Jitter(2)(4) 150 Mb/s 0.02 UI
DJ150 Deterministic Jitter(2)(4) 0.01 UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
3. PLL frequency at 1.6 GHz and OUTDIV = 1.
4. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
Symbol Description Min Typ Max Units
FGTXRX Serial data rate RX oversampler not enabled 0.75 FGTXMAX Gb/s
RX oversampler enabled 0.15 0.75 Gb/s
TRXELECIDLE
TIme for RXELECIDLE to
respond to loss or
restoration of data
OOBDETECT_THRESHOLD = 110
75 ns
RXOOBVDPP OOB detect threshold
peak-to-peak OOBDETECT_THRESHOLD = 110 55 135 mV
RXSST Receiver spread-spectrum
tracking(1) Modulated @ 33 KHz –5000 0 ppm
RXRL Run length (CID) Internal AC capacitor bypassed 512 UI
RXPPMTOL Data/REFCLK PPM offset
tolerance(2)
CDR 2nd-order loop disabled –200 200 ppm
CDR 2nd-order loop enabled –2000 2000 ppm
SJ Jitter Tolerance(3)
JT_SJ6.5 Sinusoidal Jitter(4) 6.5 Gb/s 0.44 UI
JT_SJ5.0 Sinusoidal Jitter(4) 5.0 Gb/s 0.44 UI
JT_SJ4.25 Sinusoidal Jitter(4) 4.25 Gb/s 0.44 UI
JT_SJ3.75 Sinusoidal Jitter(4) 3.75 Gb/s 0.44 UI
JT_SJ3.2 Sinusoidal Jitter(4) 3.2 Gb/s 0.45 UI
JT_SJ3.2L Sinusoidal Jitter(4) 3.2 Gb/s(5) 0.45 UI
JT_SJ2.5 Sinusoidal Jitter(4) 2.5 Gb/s 0.50 UI
JT_SJ1.25 Sinusoidal Jitter(4) 1.25 Gb/s 0.50 UI
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics (Cont’d)
Symbol Description Condition Min Typ Max Units
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 25
CRC Block Switching Characteristics
Ethernet MAC Switching Characteristics
Consult UG194: Virtex-5 FPGA Tri-mode Ethernet Media Access Controller User Guide for further information.
Endpoint Block for PCI Express Designs Switching Characteristics
Consult UG197: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
JT_SJ750 Sinusoidal Jitter(4)(6) 750 Mb/s 0.57 UI
JT_SJ150 Sinusoidal Jitter(4)(6) 150 Mb/s 0.57 UI
SJ Jitter Tolerance with Stressed Eye(3)
JT_TJSE4.25 Total Jitter with Stressed
Eye(7)
4.25 Gb/s 0.69 UI
JT_SJSE4.25 Sinusoidal Jitter with
Stressed Eye(7) 4.25 Gb/s 0.1 UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3. All jitter values are based on a Bit Error Ratio of 1e–12.
4. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
5. PLL frequency at 1.6 GHz and OUTDIV = 1.
6. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
7. Composite jitter with RX equalizer enabled. DFE disabled.
Table 48: CRC Block Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
FCRC CRCCLK maximum frequency 325 325 270 MHz
Table 49: Maximum Ethernet MAC Performance
Symbol Description Conditions Speed Grade Units
-3 -2 -1
FTEMACCLIENT Client interface maximum frequency 10 Mb/s – 8-bit width 1.25 1.25 1.25 MHz
100 Mb/s – 8-bit width 12.5 12.5 12.5 MHz
1000 Mb/s – 8-bit width 125 125 125 MHz
2000 Mb/s – 16-bit width 125 125 125 MHz
FTEMACPHY Physical interface maximum frequency 10 Mb/s – 4-bit width 2.5 2.5 2.5 MHz
100 Mb/s – 4-bit width 25 25 25 MHz
1000 Mb/s – 8-bit width 125 125 125 MHz
2000 Mb/s – 8-bit width 250 250 250 MHz
Table 50: Maximum Performance for PCI Express Designs
Symbol Description Speed Grade Units
-3 -2 -1
FPCIECORE Core clock maximum frequency 250 250 250 MHz
FPCIEUSER User clock maximum frequency 250 250 250 MHz
Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d)
Symbol Description Min Typ Max Units
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 26
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter Symbol Comments/Conditions Min Typ Max Units
AVDD = 2.5V ± 2%, VREFP =2.5V, V
REFN = 0V, ADCCLK = 5.2 MHz, TA=T
MIN to TMAX, Typical values at TA=+25°C
DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode,
and Common Mode = 0V
Resolution 10 Bits
Integral Nonlinearity INL ±2 LSBs
Differential Nonlinearity DNL No missing codes (TMIN to TMAX)
Guaranteed Monotonic
±0.9 LSBs
Unipolar Offset Error(1) Uncalibrated ±2 ±30 LSBs
Bipolar Offset Error(1) Uncalibrated measured in bipolar mode ±2 ±30 LSBs
Gain Error(1) Uncalibrated ±0.2 ±2 %
Bipolar Gain Error(1) Uncalibrated measured in bipolar mode ±0.2 ±2 %
Total Unadjusted Error
(Uncalibrated)
TUE Deviation from ideal transfer function.
VREFP –V
REFN =2.5V
±10 LSBs
Total Unadjusted Error
(Calibrated)
TUE Deviation from ideal transfer function.
VREFP –V
REFN =2.5V
±1 ±2 LSBs
Calibrated Gain Temperature
Coefficient
Variation of FS code with temperature ±0.01 LSB/°C
DC Common-Mode Reject CMRRDC V
N = VCM =0.5V ± 0.5V,
VP–V
N=100mV
70 dB
Conversion Rate(2)
Conversion Time - Continuous tCONV Number of CLK cycles 26 32
Conversion Time - Event tCONV Number of CLK cycles 21
T/H Acquisition Time tACQ Number of CLK cycles 4
DRP Clock Frequency DCLK DRP clock frequency 8 250 MHz
ADC Clock Frequency ADCCLK Derived from DCLK 1 5.2 MHz
CLK Duty cycle 40 60 %
Analog Inputs(3)
Dedicated Analog Inputs
Input Voltage Range
VP - VN
Unipolar Operation 0 1 Volts
Differential Inputs –0.25 +0.25
Unipolar Common Mode Range (FS input) 0 +0.5
Differential Common Mode Range (FS input) +0.3 +0.7
Bandwidth 20 MHz
Auxiliary Analog Inputs
Input Voltage Range
VAUXP[0] /VAUXN[0] to VAUXP[15]
/VAUXN[15]
Unipolar Operation 0 1 Volts
Differential Operation –0.25 +0.25
Unipolar Common Mode Range (FS input) 0 +0.5
Differential Common Mode Range (FS input) +0.3 +0.7
Bandwidth 10 kHz
Input Leakage Current A/D not converting, ADCCLK stopped ±1.0 µA
Input Capacitance 10 pF
On-chip Supply Monitor Error VCCINT and VCCAUX with calibration enabled ±1.0 % Reading
On-chip Temperature Monitor
Error
–40°C to +125°C with calibration enabled ±4 °C
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 27
External Reference Inputs(4)
Positive Reference Input
Voltage Range
VREFP Measured Relative to VREFN 2.45 2.5 2.55 Volts
Negative Reference Input
Voltage Range
VREFN Measured Relative to AGND –50 0 100 mV
Input current IREF ADCCLK =5.2 MHz 100 µA
Power Requirements
Analog Power Supply AVDD Measured Relative to AVSS 2.45 2.5 2.55 Volts
Analog Supply Current AIDD ADCCLK =5.2 MHz 5 13 mA
Notes:
1. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See UG192: Virtex-5 FPGA System
Monitor User Guide.
2. See "System Monitor Timing" in UG192: Virtex-5 FPGA System Monitor User Guide.
3. See "Analog Inputs" in UG192: Virtex-5 FPGA System Monitor User Guide for a detailed description.
4. Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer
function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing the supply voltage and reference to vary by ±2% is permitted.
Table 51: Analog-to-Digital Specifications (Cont’d)
Parameter Symbol Comments/Conditions Min Typ Max Units
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 28
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page 30. Table 52 shows internal (register-to-register)
performance.
Table 52: Register-to-Register Performance
Description
Register-to-Register (with I/O Delays)
UnitsSpeed Grade
-3 -2 -1
Basic Functions
16:1 Multiplexer 550 500 450 MHz
32:1 Multiplexer 550 500 450 MHz
64:1 Multiplexer 511 467 407 MHz
9 x 9 Logic Multiplier with 4 pipe stages 468 438 428 MHz
9 x 9 Logic Multiplier with 5 pipe stages 550 500 428 MHz
16-bit Adder 550 500 450 MHz
32-bit Adder 550 500 447 MHz
64-bit Adder 423 377 323 MHz
Register to LUT to Register 550 500 450 MHz
16-bit Counter 550 500 450 MHz
32-bit Counter 550 500 450 MHz
64-bit Counter 428 381 333 MHz
Memory
Cascaded block RAM (64K) 500 450 400 MHz
Block RAM Pipelined
Single-Port 512 x 36 bits 550 500 450 MHz
Single-Port 4096 x 4 bits 550 500 450 MHz
Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits 550 500 450 MHz
Distributed RAM
Single-Port 16 x 8 550 500 450 MHz
Single-Port 32 x 8 550 500 450 MHz
Single-Port 64 x 8 550 500 450 MHz
Dual-Port 16 x 8 MHz
Shift Register Chain
16-bit 550 500 450 MHz
32-bit 550 500 450 MHz
64-bit 550 500 438 MHz
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 29
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter 550 500 450 MHz
DSP48E Dual 24-bit Adder/Subtracter 550 500 450 MHz
DSP48E 48-bit Adder/Subtracter 550 500 450 MHz
DSP48E 48-bit Counter 550 500 450 MHz
DSP48E 48-bit Comparator 550 500 450 MHz
DSP48E 25 x 18 bit Pipelined Multiplier 550 500 450 MHz
DSP48E Direct 4-tap FIR Filter Pipelined 510 458 397 MHz
DSP48E Systolic n-tap FIR Filter Pipelined 550 500 450 MHz
Notes:
1. Device used is the XC5VLX50T- FF1136
Table 53: Interface Performances
Description Speed Grade
-3 -2 -1
Networking Applications
SFI-4.1 (SDR LVDS Interface)(1) 710 MHz 710 MHz 645 MHz
SPI-4.2 (DDR LVDS Interface)(2) 1.25 Gb/s 1.25 Gb/s 1.0 Gb/s
Memory Interfaces
DDR(3) 200 MHz 200 MHz 200 MHz
DDR2(4) 333 MHz 300 MHz 267 MHz
QDR II SRAM(5) 300 MHz 300 MHz 250 MHz
RLDRAM II(6) 333 MHz 300 MHz 250 MHz
Notes:
1. Performance defined using design implementation described in application note XAPP856: SFI-4.1 16-Channel SDR Interface with Bus
Alignment
2. Performance defined using design implementation described in application note XAPP860: 16-Channel, DDR LVDS Interface with Real-time
Window Monitoring
3. Performance defined using design implementation described in application note XAPP851: DDR SDRAM Controller
4. Performance defined using design implementation described in application note XAPP858: High-Performance DDR2 SDRAM Interface Data
Capture
5. Performance defined using design implementation described in application note XAPP853: QDRII SRAM Interface
6. Performance defined using design implementation described in application note XAPP852: Synthesizable RLDRAM II Controller
Table 52: Register-to-Register Performance (Cont’d)
Description
Register-to-Register (with I/O Delays)
UnitsSpeed Grade
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 30
Switching Characteristics
All values represented in this data sheet are based on
speed specification version 1.62. Switching characteristics
are specified on a per-speed-grade basis and can be
designated as Advance, Preliminary, or Production. Each
designation is defined as follows:
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
Table 54 correlates the current status of each Virtex-5
device on a per speed grade basis.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values.
For more specific, more precise, and worst-case
guaranteed data, use the values reported by the static
timing analyzer and back-annotate to the simulation net list.
Unless otherwise noted, values apply to all Virtex-5 devices.
Table 54: Virtex-5 Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XC5VLX20T -2, -1
XC5VLX30 -3, -2, -1
XC5VLX30T -3, -2, -1
XC5VLX50 -3, -2, -1
XC5VLX50T -3, -2, -1
XC5VLX85 -3, -2, -1
XC5VLX85T -3, -2, -1
XC5VLX110 -3, -2, -1
XC5VLX110T -3, -2, -1
XC5VLX155 -3, -2, -1
XC5VLX155T -3, -2, -1
XC5VLX220 -2, -1
XC5VLX220T -2, -1
XC5VLX330 -2, -1
XC5VLX330T -2, -1
XC5VSX35T -3, -2, -1
XC5VSX50T -3, -2, -1
XC5VSX95T -2, -1
XC5VSX240T -2, -1
XC5VTX150T -2, -1
XC5VTX240T -2, -1
XC5VFX30T -3, -2, -1
XC5VFX70T -3, -2, -1
XC5VFX100T -3, -2, -1
XC5VFX130T -3, -2, -1
XC5VFX200T -2, -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 31
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed
grade) is released to production before a speed
specification is released with the correct label (Advance,
Preliminary, Production). Any labeling discrepancies are
corrected in subsequent speed specification releases.
Table 55 lists the production released Virtex-5 family
member, speed grade, and the minimum corresponding
supported speed specification version and ISE® software
revisions. The ISE software and speed specifications listed
are the minimum releases required for production. All
subsequent releases of software and speed specifications
are valid.
Table 55: Virtex-5 Device Production Software
and Speed Specification Release
Device Speed Grade Designations
-3 -2 -1
XC5VLX20T N/A ISE 10.1 SP2 v1.61
XC5VLX30 ISE 9.2i SP4 v1.58
XC5VLX30T ISE 9.2i SP4 v1.58
XC5VLX50 ISE 9.2i SP4 v1.58
XC5VLX50T ISE 9.2i SP4 v1.58
XC5VLX85 ISE 9.2i SP4 v1.58
XC5VLX85T ISE 9.2i SP4 v1.58
XC5VLX110 ISE 9.2i SP4 v1.58
XC5VLX110T ISE 9.2i SP4 v1.58
XC5VLX155 ISE 10.1 SP2 v1.61
XC5VLX155T ISE 10.1 SP2 v1.61
XC5VLX220 N/A ISE 9.2i SP4 v1.58
XC5VLX220T N/A ISE 9.2i SP4 v1.58
XC5VLX330 N/A ISE 9.2i SP4 v1.58
XC5VLX330T N/A ISE 9.2i SP4 v1.58
XC5VSX35T ISE 9.2i SP4 v1.58
XC5VSX50T ISE 9.2i SP4 v1.58
XC5VSX95T N/A ISE 9.2i SP4 v1.58
XC5VSX240T N/A ISE 10.1 SP3 v1.63
XC5VTX150T N/A ISE 10.1 SP3 v1.63
XC5VTX240T N/A ISE 10.1 SP3 v1.63
XC5VFX30T ISE 10.1 SP3 v1.63
XC5VFX70T ISE 10.1 SP3 v1.63
XC5VFX100T ISE 10.1 SP3 v1.63
XC5VFX130T ISE 10.1 SP3 v1.63
XC5VFX200T N/A ISE 10.1 SP3 v1.63
Notes:
1. Blank entries indicate a device and/or speed grade in advance or
preliminary status.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 32
IOB Pad Input/Output/3-State Switching Characteristics
Table 56 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
TIOPI is described as the delay from IOB pad through the
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
TIOOP is described as the delay from the O pin to the IOB
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
TIOTP is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 57 summarizes the value of TIOTPHZ. TIOTPHZ is
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
Table 56: IOB Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
UnitsSpeed Grade Speed Grade Speed Grade
-3 -2 -1 -3 -2 -1 -3 -2 -1
LVDS_25 0.80 0.90 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns
LVDSEXT_25 1.01 1.16 1.30 1.17 1.34 1.49 1.17 1.34 1.49 ns
HT_25 0.80 0.90 1.06 1.10 1.26 1.40 1.10 1.26 1.40 ns
BLVDS_25 0.80 0.90 1.06 1.24 1.38 1.58 1.24 1.38 1.58 ns
RSDS_25 (point to point) 0.80 0.90 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns
ULVDS_25 0.80 0.90 1.06 1.10 1.27 1.41 1.10 1.27 1.41 ns
PCI33_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns
PCI66_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns
PCI-X 0.62 0.70 0.82 1.40 1.56 1.80 1.40 1.56 1.80 ns
GTL 0.76 0.85 1.00 1.47 1.63 1.86 1.47 1.63 1.86 ns
GTLP 0.76 0.85 1.00 1.51 1.68 1.93 1.51 1.68 1.93 ns
HSTL_I 0.76 0.85 1.00 1.42 1.57 1.79 1.42 1.57 1.79 ns
HSTL_II 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns
HSTL_III 0.76 0.85 1.00 1.44 1.60 1.85 1.44 1.60 1.85 ns
HSTL_IV 0.76 0.85 1.00 1.44 1.60 1.83 1.44 1.60 1.83 ns
HSTL_I _18 0.76 0.85 1.00 1.40 1.55 1.77 1.40 1.55 1.77 ns
HSTL_II _18 0.76 0.85 1.00 1.36 1.51 1.72 1.36 1.51 1.72 ns
HSTL_III _18 0.76 0.85 1.00 1.45 1.61 1.85 1.45 1.61 1.85 ns
HSTL_IV_18 0.76 0.85 1.00 1.41 1.57 1.81 1.41 1.57 1.81 ns
SSTL2_I 0.76 0.85 1.00 1.48 1.64 1.87 1.48 1.64 1.87 ns
SSTL2_II 0.76 0.85 1.00 1.40 1.55 1.76 1.40 1.55 1.76 ns
LVTTL, Slow, 2 mA 0.62 0.70 0.82 4.10 4.47 5.01 4.10 4.47 5.01 ns
LVTTL, Slow, 4 mA 0.62 0.70 0.82 2.87 3.09 3.41 2.87 3.09 3.41 ns
LVTTL, Slow, 6 mA 0.62 0.70 0.82 2.66 2.91 3.29 2.66 2.91 3.29 ns
LVTTL, Slow, 8 mA 0.62 0.70 0.82 2.09 2.30 2.61 2.09 2.30 2.61 ns
LVTTL, Slow, 12 mA 0.62 0.70 0.82 1.94 2.15 2.46 1.94 2.15 2.46 ns
LVTTL, Slow, 16 mA 0.62 0.70 0.82 1.84 2.04 2.34 1.84 2.04 2.34 ns
LVTTL, Slow, 24 mA 0.62 0.70 0.82 1.87 2.07 2.38 1.87 2.07 2.38 ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 33
LVTTL, Fast, 2 mA 0.62 0.70 0.82 3.32 3.61 4.05 3.32 3.61 4.05 ns
LVTTL, Fast, 4 mA 0.62 0.70 0.82 2.32 2.55 2.90 2.32 2.55 2.90 ns
LVTTL, Fast, 6 mA 0.62 0.70 0.82 2.10 2.31 2.63 2.10 2.31 2.63 ns
LVTTL, Fast, 8 mA 0.62 0.70 0.82 1.65 1.82 2.09 1.65 1.82 2.09 ns
LVTTL, Fast, 12 mA 0.62 0.70 0.82 1.47 1.63 1.89 1.47 1.63 1.89 ns
LVTTL, Fast, 16 mA 0.62 0.70 0.82 1.41 1.57 1.81 1.41 1.57 1.81 ns
LVTTL, Fast, 24 mA 0.62 0.70 0.82 1.36 1.52 1.74 1.36 1.52 1.74 ns
LVCMOS33, Slow, 2 mA 0.62 0.70 0.82 3.63 3.96 4.44 3.63 3.96 4.44 ns
LVCMOS33, Slow, 4 mA 0.62 0.70 0.82 2.82 3.09 3.49 2.82 3.09 3.49 ns
LVCMOS33, Slow, 6 mA 0.62 0.70 0.82 2.61 2.86 3.24 2.61 2.86 3.24 ns
LVCMOS33, Slow, 8 mA 0.62 0.70 0.82 2.06 2.26 2.57 2.06 2.26 2.57 ns
LVCMOS33, Slow, 12 mA 0.62 0.70 0.82 1.95 2.14 2.42 1.95 2.14 2.42 ns
LVCMOS33, Slow, 16 mA 0.62 0.70 0.82 1.86 2.04 2.31 1.86 2.04 2.31 ns
LVCMOS33, Slow, 24 mA 0.62 0.70 0.82 1.87 2.07 2.35 1.87 2.07 2.35 ns
LVCMOS33, Fast, 2 mA 0.62 0.70 0.82 2.94 3.20 3.59 2.94 3.20 3.59 ns
LVCMOS33, Fast, 4 mA 0.62 0.70 0.82 2.27 2.50 2.84 2.27 2.50 2.84 ns
LVCMOS33, Fast, 6 mA 0.62 0.70 0.82 2.06 2.27 2.59 2.06 2.27 2.59 ns
LVCMOS33, Fast, 8 mA 0.62 0.70 0.82 1.61 1.79 2.05 1.61 1.79 2.05 ns
LVCMOS33, Fast, 12 mA 0.62 0.70 0.82 1.45 1.61 1.86 1.45 1.61 1.86 ns
LVCMOS33, Fast, 16 mA 0.62 0.70 0.82 1.40 1.56 1.80 1.40 1.56 1.80 ns
LVCMOS33, Fast, 24 mA 0.62 0.70 0.82 1.35 1.51 1.74 1.35 1.51 1.74 ns
LVCMOS25, Slow, 2 mA 0.61 0.70 0.82 3.67 3.97 4.42 3.67 3.97 4.42 ns
LVCMOS25, Slow, 4 mA 0.61 0.70 0.82 2.37 2.60 2.94 2.37 2.60 2.94 ns
LVCMOS25, Slow, 6 mA 0.61 0.70 0.82 2.19 2.41 2.74 2.19 2.41 2.74 ns
LVCMOS25, Slow, 8 mA 0.61 0.70 0.82 2.05 2.26 2.56 2.05 2.26 2.56 ns
LVCMOS25, Slow, 12 mA 0.61 0.70 0.82 2.10 2.31 2.63 2.10 2.31 2.63 ns
LVCMOS25, Slow, 16 mA 0.61 0.70 0.82 1.84 2.02 2.30 1.84 2.02 2.30 ns
LVCMOS25, Slow, 24 mA 0.61 0.70 0.82 1.83 2.04 2.34 1.83 2.04 2.34 ns
LVCMOS25, Fast, 2 mA 0.61 0.70 0.82 3.14 3.41 3.82 3.14 3.41 3.82 ns
LVCMOS25, Fast, 4 mA 0.61 0.70 0.82 1.89 2.08 2.37 1.89 2.08 2.37 ns
LVCMOS25, Fast, 6 mA 0.61 0.70 0.82 1.74 1.92 2.20 1.74 1.92 2.20 ns
LVCMOS25, Fast, 8 mA 0.61 0.70 0.82 1.66 1.83 2.09 1.66 1.83 2.09 ns
LVCMOS25, Fast, 12 mA 0.61 0.70 0.82 1.52 1.69 1.94 1.52 1.69 1.94 ns
LVCMOS25, Fast, 16 mA 0.61 0.70 0.82 1.43 1.60 1.85 1.43 1.60 1.85 ns
LVCMOS25, Fast, 24 mA 0.61 0.70 0.82 1.40 1.54 1.76 1.40 1.54 1.76 ns
Table 56: IOB Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
UnitsSpeed Grade Speed Grade Speed Grade
-3 -2 -1 -3 -2 -1 -3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 34
LVCMOS18, Slow, 2 mA 0.67 0.76 0.89 4.20 4.56 5.09 4.20 4.56 5.09 ns
LVCMOS18, Slow, 4 mA 0.67 0.76 0.89 3.03 3.32 3.75 3.03 3.32 3.75 ns
LVCMOS18, Slow, 6 mA 0.67 0.76 0.89 2.37 2.61 2.97 2.37 2.61 2.97 ns
LVCMOS18, Slow, 8 mA 0.67 0.76 0.89 2.15 2.37 2.69 2.15 2.37 2.69 ns
LVCMOS18, Slow, 12 mA 0.67 0.76 0.89 1.95 2.16 2.47 1.95 2.16 2.47 ns
LVCMOS18, Slow, 16 mA 0.67 0.76 0.89 1.93 2.14 2.45 1.93 2.14 2.45 ns
LVCMOS18, Fast, 2 mA 0.67 0.76 0.89 3.41 3.71 4.16 3.41 3.71 4.16 ns
LVCMOS18, Fast, 4 mA 0.67 0.76 0.89 2.36 2.61 2.98 2.36 2.61 2.98 ns
LVCMOS18, Fast, 6 mA 0.67 0.76 0.89 1.87 2.06 2.35 1.87 2.06 2.35 ns
LVCMOS18, Fast, 8 mA 0.67 0.76 0.89 1.69 1.87 2.13 1.69 1.87 2.13 ns
LVCMOS18, Fast, 12 mA 0.67 0.76 0.89 1.51 1.68 1.93 1.51 1.68 1.93 ns
LVCMOS18, Fast, 16 mA 0.67 0.76 0.89 1.44 1.61 1.86 1.44 1.61 1.86 ns
LVCMOS15, Slow, 2 mA 0.73 0.83 0.98 3.50 3.84 4.34 3.50 3.84 4.34 ns
LVCMOS15, Slow, 4 mA 0.73 0.83 0.98 2.17 2.40 2.74 2.17 2.40 2.74 ns
LVCMOS15, Slow, 6 mA 0.73 0.83 0.98 1.99 2.20 2.52 1.99 2.20 2.52 ns
LVCMOS15, Slow, 8 mA 0.73 0.83 0.98 1.91 2.12 2.43 1.91 2.12 2.43 ns
LVCMOS15, Slow, 12 mA 0.73 0.83 0.98 1.74 1.95 2.25 1.74 1.95 2.25 ns
LVCMOS15, Slow, 16 mA 0.73 0.83 0.98 1.71 1.91 2.20 1.71 1.91 2.20 ns
LVCMOS15, Fast, 2 mA 0.73 0.83 0.98 2.80 3.07 3.48 2.80 3.07 3.48 ns
LVCMOS15, Fast, 4 mA 0.73 0.83 0.98 1.76 1.95 2.23 1.76 1.95 2.23 ns
LVCMOS15, Fast, 6 mA 0.73 0.83 0.98 1.62 1.80 2.06 1.62 1.80 2.06 ns
LVCMOS15, Fast, 8 mA 0.73 0.83 0.98 1.57 1.74 2.00 1.57 1.74 2.00 ns
LVCMOS15, Fast, 12 mA 0.73 0.83 0.98 1.43 1.60 1.86 1.43 1.60 1.86 ns
LVCMOS15, Fast, 16 mA 0.73 0.83 0.98 1.37 1.53 1.77 1.37 1.53 1.77 ns
LVCMOS12, Slow, 2 mA 0.84 0.96 1.14 3.58 3.98 4.58 3.58 3.98 4.58 ns
LVCMOS12, Slow, 4 mA 0.84 0.96 1.14 2.10 2.33 2.66 2.10 2.33 2.66 ns
LVCMOS12, Slow, 6 mA 0.84 0.96 1.14 2.00 2.18 2.45 2.00 2.18 2.45 ns
LVCMOS12, Slow, 8 mA 0.84 0.96 1.14 1.91 2.14 2.48 1.91 2.14 2.48 ns
LVCMOS12, Fast, 2 mA 0.84 0.96 1.14 3.05 3.38 3.87 3.05 3.38 3.87 ns
LVCMOS12, Fast, 4 mA 0.84 0.96 1.14 1.71 1.91 2.20 1.71 1.91 2.20 ns
LVCMOS12, Fast, 6 mA 0.84 0.96 1.14 1.58 1.78 2.08 1.58 1.78 2.08 ns
LVCMOS12, Fast, 8 mA 0.84 0.96 1.14 1.52 1.70 1.97 1.52 1.70 1.97 ns
LVDCI_33 0.62 0.70 0.82 1.50 1.66 1.90 1.50 1.66 1.90 ns
LVDCI_25 0.61 0.70 0.82 1.55 1.71 1.93 1.55 1.71 1.93 ns
LVDCI_18 0.67 0.76 0.89 1.65 1.78 1.99 1.65 1.78 1.99 ns
LVDCI_15 0.73 0.83 0.98 1.58 1.75 2.02 1.58 1.75 2.02 ns
Table 56: IOB Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
UnitsSpeed Grade Speed Grade Speed Grade
-3 -2 -1 -3 -2 -1 -3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 35
LVDCI_DV2_25 0.61 0.70 0.82 1.36 1.51 1.74 1.36 1.51 1.74 ns
LVDCI_DV2_18 0.67 0.76 0.89 1.43 1.60 1.85 1.43 1.60 1.85 ns
LVDCI_DV2_15 0.73 0.83 0.98 1.48 1.65 1.91 1.48 1.65 1.91 ns
GTL_DCI 0.76 0.85 1.00 1.36 1.47 1.65 1.36 1.47 1.65 ns
GTLP_DCI 0.76 0.85 1.00 1.37 1.52 1.76 1.37 1.52 1.76 ns
LVPECL_25 0.80 0.90 1.06 1.28 1.42 1.62 1.28 1.42 1.62 ns
HSTL_I_12 0.76 0.85 1.00 1.45 1.61 1.85 1.45 1.61 1.85 ns
HSTL_I_DCI 0.76 0.85 1.00 1.41 1.56 1.77 1.41 1.56 1.77 ns
HSTL_II_DCI 0.76 0.85 1.00 1.34 1.48 1.69 1.34 1.48 1.69 ns
HSTL_II_T_DCI 0.76 0.85 1.00 1.41 1.56 1.77 1.41 1.56 1.77 ns
HSTL_III_DCI 0.76 0.85 1.00 1.57 1.72 1.95 1.57 1.72 1.95 ns
HSTL_IV_DCI 0.76 0.85 1.00 1.34 1.46 1.64 1.34 1.46 1.64 ns
HSTL_I_DCI_18 0.76 0.85 1.00 1.36 1.50 1.70 1.36 1.50 1.70 ns
HSTL_II_DCI_18 0.76 0.85 1.00 1.30 1.43 1.64 1.30 1.43 1.64 ns
HSTL_II _T_DCI_18 0.76 0.85 1.00 1.36 1.50 1.70 1.36 1.50 1.70 ns
HSTL_III_DCI_18 0.76 0.85 1.00 1.55 1.69 1.91 1.55 1.69 1.91 ns
HSTL_IV_DCI_18 0.76 0.85 1.00 1.31 1.44 1.62 1.31 1.44 1.62 ns
DIFF_HSTL_I_18 0.80 0.90 1.06 1.40 1.55 1.77 1.40 1.55 1.77 ns
DIFF_HSTL_I_DCI_18 0.80 0.90 1.06 1.36 1.50 1.70 1.36 1.50 1.70 ns
DIFF_HSTL_I 0.80 0.90 1.06 1.42 1.57 1.79 1.42 1.57 1.79 ns
DIFF_HSTL_I_DCI 0.80 0.90 1.06 1.41 1.56 1.77 1.41 1.56 1.77 ns
DIFF_HSTL_II_18 0.80 0.90 1.06 1.36 1.51 1.72 1.36 1.51 1.72 ns
DIFF_HSTL_II_DCI_18 0.80 0.90 1.06 1.30 1.43 1.64 1.30 1.43 1.64 ns
DIFF_HSTL_II 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns
DIFF_HSTL_II_DCI 0.80 0.90 1.06 1.34 1.48 1.69 1.34 1.48 1.69 ns
SSTL2_I_DCI 0.76 0.85 1.00 1.42 1.56 1.78 1.42 1.56 1.78 ns
SSTL2_II_DCI 0.76 0.85 1.00 1.34 1.48 1.70 1.34 1.48 1.70 ns
SSTL2_II_T_DCI 0.76 0.85 1.00 1.42 1.56 1.78 1.42 1.56 1.78 ns
SSTL18_I 0.76 0.85 1.00 1.46 1.61 1.84 1.46 1.61 1.84 ns
SSTL18_II 0.76 0.85 1.00 1.39 1.53 1.75 1.39 1.53 1.75 ns
SSTL18_I_DCI 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns
SSTL18_II_DCI 0.76 0.85 1.00 1.30 1.44 1.64 1.30 1.44 1.64 ns
SSTL18_II_T_DCI 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns
Table 56: IOB Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
UnitsSpeed Grade Speed Grade Speed Grade
-3 -2 -1 -3 -2 -1 -3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 36
DIFF_SSTL2_I 0.80 0.90 1.06 1.48 1.64 1.87 1.48 1.64 1.87 ns
DIFF_SSTL2_I_DCI 0.80 0.90 1.06 1.42 1.56 1.78 1.42 1.56 1.78 ns
DIFF_SSTL18_I 0.80 0.90 1.06 1.46 1.61 1.84 1.46 1.61 1.84 ns
DIFF_SSTL18_I_DCI 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns
DIFF_SSTL2_II 0.80 0.90 1.06 1.40 1.55 1.76 1.40 1.55 1.76 ns
DIFF_SSTL2_II_DCI 0.80 0.90 1.06 1.34 1.48 1.70 1.34 1.48 1.70 ns
DIFF_SSTL18_II 0.80 0.90 1.06 1.39 1.53 1.75 1.39 1.53 1.75 ns
DIFF_SSTL18_II_DCI 0.80 0.90 1.06 1.30 1.44 1.64 1.30 1.44 1.64 ns
Table 57: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol Description Speed Grade Units
-3 -2 -1
TIOTPHZ T input to Pad high-impedance 0.88 1.01 1.12 ns
Table 56: IOB Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
UnitsSpeed Grade Speed Grade Speed Grade
-3 -2 -1 -3 -2 -1 -3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 37
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 58 shows the test setup parameters used for measuring input delay.
Table 58: Input Delay Measurement Methodology
Description I/O Standard Attribute VL(1,2) VH(1,2) VMEAS(1,4,5) VREF(1,3,5)
LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL 0 3.0 1.4
LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 0 3.3 1.65
LVCMOS, 2.5V LVCMOS25 0 2.5 1.25
LVCMOS, 1.8V LVCMOS18 0 1.8 0.9
LVCMOS, 1.5V LVCMOS15 0 1.5 0.75
LVCMOS, 1.2V LVCMOS12 0 1.2 0.6
PCI (Peripheral Component Interconnect),
33 MHz, 3.3V
PCI33_3 Per PCI™ Specification
PCI, 66 MHz, 3.3V PCI66_3 Per PCI Specification
PCI-X, 133 MHz, 3.3V PCIX Per PCI-X™ Specification
GTL (Gunning Transceiver Logic) GTL VREF –0.2 V
REF +0.2 V
REF 0.80
GTL Plus GTLP VREF –0.2 V
REF +0.2 V
REF 1.0
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II VREF –0.5 V
REF +0.5 V
REF 0.75
HSTL, Class III & IV HSTL_III, HSTL_IV VREF –0.5 V
REF +0.5 V
REF 0.90
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0.5 V
REF +0.5 V
REF 0.90
HSTL, Class III & IV, 1.8V HSTL_III_18, HSTL_IV_18 VREF –0.5 V
REF +0.5 V
REF 1.08
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II VREF –1.00 V
REF +1.00 V
REF 1.5
SSTL, Class I & II, 2.5V SSTL2_I, SSTL2_II VREF –0.75 V
REF +0.75 V
REF 1.25
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF –0.5 V
REF +0.5 V
REF 0.90
AGP-2X/AGP (Accelerated Graphics Port) AGP VREF –(0.2xV
CCO)V
REF +(0.2xV
CCO)V
REF AGP Spec
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6)
LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 1.2 – 0.125 1.2 + 0.125 0(6)
LDT (HyperTransport), 2.5V LDT_25 0.6 – 0.125 0.6 + 0.125 0(6)
LVPECL (Low-Voltage Positive Emitter-Coupled
Logic), 2.5V
LVPECL_25 1.15 – 0.3 1.15 – 0.3 0(6)
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI
standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values
listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 11.
6. The value given is the differential input voltage.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 38
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 11 and Figure 12.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters VREF , RREF , CREF , and VMEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 59.
2. Record the time to VMEAS .
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to VMEAS .
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
X-Ref Target - Figure 11
Figure 11: Single Ended Test Setup
VREF
RREF
VMEAS
(voltage level when taking
delay measurement)
CREF
(probe capacitance)
FPGA Output
DS202_06_111608
X-Ref Target - Figure 12
Figure 12: Differential Test Setup
RREF VMEAS
+
CREF
FPGA Output
ds202_12_042808
Table 59: Output Delay Measurement Methodology
Description I/O Standard
Attribute
RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0
LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 1M 0 1.65 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 (rising edge) 25 10(2) 0.94 0
PCI33_3 (falling edge) 25 10(2) 2.03 3.3
PCI, 66 MHz, 3.3V PCI66_3 (rising edge) 25 10(2) 0.94 0
PCI66_3 (falling edge) 25 10(2) 2.03 3.3
PCI-X, 133 MHz, 3.3V PCIX (rising edge) 25 10(3) 0.94
PCIX (falling edge 25 10(3) 2.03 3.3
GTL (Gunning Transceiver Logic) GTL 25 0 0.8 1.2
GTL Plus GTLP 25 0 1.0 1.5
HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 VREF 0.75
HSTL, Class II HSTL_II 25 0 VREF 0.75
HSTL, Class III HSTL_III 50 0 0.9 1.5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 39
HSTL, Class IV HSTL_IV 25 0 0.9 1.5
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8
HSTL, Class IV, 1.8V HSTL_IV_18 25 0 1.1 1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 VREF 0.9
SSTL, Class II, 1.8V SSTL18_II 25 0 VREF 0.9
SSTL, Class I, 2.5V SSTL2_I 50 0 VREF 1.25
SSTL, Class II, 2.5V SSTL2_II 25 0 VREF 1.25
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 100 0 0(4) 1.2
LVDSEXT (LVDS Extended Mode), 2.5V LVDS_25 100 0 0(4) 1.2
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(4) 0
LDT (HyperTransport), 2.5V LDT_25 100 0 0(4) 0.6
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25 100 0 0(4) 0
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33 1M 0 1.65 0
LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0
LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 1M 0 0.9 0
LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 1M 0 0.75 0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI 50 0 VREF 0.75
HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 50 0 0.9 1.5
HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18 50 0 VREF 0.9
HSTL, Class III & IV, 1.8V, with DCI HSTL_III_DCI_18,
HSTL_IV_DCI_18
50 0 1.1 1.8
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 VREF 0.9
SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 VREF 1.25
GTL (Gunning Transceiver Logic) with DCI GTL_DCI 50 0 0.8 1.2
GTL Plus with DCI GTLP_DCI 50 0 1.0 1.5
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
4. The value given is the differential input voltage.
Table 59: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard
Attribute
RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 40
Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Setup/Hold
TICE1CK/TICKCE1 CE1 pin Setup/Hold with respect to CLK 0.43
–0.24
0.49
–0.24
0.59
–0.24
ns
TISRCK/TICKSR SR/REV pin Setup/Hold with respect to CLK 0.85
–0.20
1.00
–0.20
1.22
–0.20
ns
TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay 0.34
–0.12
0.37
–0.12
0.39
–0.12
ns
TIDOCKD/TIOCKDD DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.31
–0.09
0.33
–0.09
0.36
–0.08
ns
Combinatorial
TIDI D pin to O pin propagation delay, no Delay 0.24 0.26 0.30 ns
TIDID DDLY pin to O pin propagation delay (using IODELAY) 0.20 0.22 0.26 ns
Sequential Delays
TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.44 0.50 0.58 ns
TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) 0.41 0.46 0.55 ns
TICKQ CLK to Q outputs 0.47 0.52 0.60 ns
TRQ SR/REV pin to OQ/TQ out 1.12 1.28 1.53 ns
TGSRQ Global Set/Reset to Q outputs 7.30 7.30 10.10 ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.78 0.95 1.20 ns, Min
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 41
Table 61: OLOGIC Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Setup/Hold
TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.30
–0.21
0.36
–0.21
0.44
–0.21
ns
TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.16
–0.07
0.19
–0.07
0.23
–0.07
ns
TOSRCK/TOCKSR SR/REV pin Setup/Hold with respect to CLK 0.93
–0.20
1.02
–0.20
1.16
–0.20
ns
TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.28
–0.18
0.34
–0.18
0.41
–0.18
ns
TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.20
–0.06
0.23
–0.06
0.29 –
0.06
ns
Combinatorial
TDOQ D1 to OQ out or T1 to TQ out 0.62 0.70 0.83 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.61 0.62 0.62 ns
TRQ SR/REV pin to OQ/TQ out 1.63 1.89 2.27 ns
TGSRQ Global Set/Reset to Q outputs 7.30 7.30 10.10 ns
Set/Reset
TRPW Minimum Pulse Width, SR/REV inputs 0.80 0.98 1.25 ns, Min
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 42
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV 0.10
0.00
0.11
0.00
0.12
0.00
ns
TISCCK_CE / TISCKC_CE(2) CE pin Setup/Hold with respect to CLK (for CE1) 0.43
–0.24
0.49
–0.24
0.59
–0.24
ns
TISCCK_CE2 / TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV (for CE2) 0.03
0.11
0.04
0.13
0.06
0.15
ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D D pin Setup/Hold with respect to CLK 0.34
–0.12
0.37
–0.12
0.39
–0.12
ns
TISDCK_DDLY /TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
0.31
–0.09
0.33
–0.09
0.36
–0.08
ns
TISDCK_DDR /TISCKD_DDR D pin Setup/Hold with respect to CLK at DDR mode 0.34
–0.12
0.37
–0.12
0.39
–0.12
ns
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
0.31
–0.09
0.33
–0.09
0.36
–0.08
ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.46 0.51 0.60 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.20 0.22 0.26 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 43
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Setup/Hold
TOSDCK_D/TOSCKD_D D input Setup/Hold with respect to CLKDIV 0.21
–0.02
0.24
–0.02
0.30
–0.02
ns
TOSDCK_T/TOSCKD_T(1) T input Setup/Hold with respect to CLK 0.28
–0.18
0.34
–0.18
0.41
–0.18
ns
TOSDCK_T2/TOSCKD_T2(1) T input Setup/Hold with respect to CLKDIV 0.21
–0.03
0.24
–0.03
0.28
–0.03
ns
TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.16
–0.07
0.19
–0.07
0.23
–0.07
ns
TOSCCK_S SR (Reset) input Setup with respect to CLKDIV 0.52 0.58 0.70 ns
TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.20
–0.06
0.23
–0.06
0.29
–0.06
ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.59 0.60 0.61 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.61 0.62 0.62 ns
Combinatorial
TOSDO_TTQ T input to TQ Out 0.62 0.70 0.83 ns
TOSCO_OQ Asynchronous Reset to OQ 1.57 1.82 2.19 ns
TOSCO_TQ Asynchronous Reset to TQ 1.63 1.89 2.27 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 44
Input/Output Delay Switching Characteristics
CLB Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
IDELAYCTRL
TIDELAYCTRLCO_RDY Reset to Ready for IDELAYCTRL 3.00 3.00 3.00 µs
FIDELAYCTRL_REF REFCLK frequency 200.00 200.00 200.00 MHz
IDELAYCTRL_REF_PRECISION REFCLK precision ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum Reset pulse width 50.00 50.00 50.00 ns
IODELAY
TIDELAYRESOLUTION IODELAY Chain Delay Resolution 1/(64 x FREF x1e
6)(1) ps
TIDELAYPAT_JIT
Pattern dependent period jitter in delay chain
for clock pattern
000Note2
Pattern dependent period jitter in delay chain
for random data pattern (PRBS 23)
±5 ±5 ±5 Note 2
TIODELAY_CLK_MAX Maximum frequency of CLK input to IODELAY 300 250 250 MHz
TIODCCK_CE / TIODCKC_CE CE pin Setup/Hold with respect to CK 0.29
–0.06
0.34
–0.06
0.42
–0.06
ns
TIODCK_INC/ TIODCKC_INC INC pin Setup/Hold with respect to CK 0.18
0.02
0.20
0.04
0.24
0.06
ns
TIODCK_RST/ TIODCKC_RST RST pin Setup/Hold with respect to CK 0.25
–0.12
0.28
–0.12
0.33
–0.12
ns
TIODDO_T TSCONTROL delay to MUXE/MUXF switching
and through IODELAY
Note 3 Note 3 Note 3
TIODDO_IDATAIN Propagation delay through IODELAY Note 3 Note 3 Note 3
TIODDO_ODATAIN Propagation delay through IODELAY Note 3 Note 3 Note 3
Notes:
1. Average Tap Delay at 200 MHz = 78 ps.
2. Units in ps, peak-to-peak per tap, in High Performance mode.
3. Delay depends on IODELAY tap setting. See TRACE report for actual values.
Table 65: CLB Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Combinatorial Delays
TILO An – Dn LUT address to A 0.08 0.09 0.10 ns, Max
An – Dn LUT address to AMUX/CMUX 0.20 0.22 0.25 ns, Max
An – Dn LUT address to BMUX_A 0.31 0.35 0.40 ns, Max
TITO An – Dn inputs to A – D Q outputs 0.67 0.77 0.90 ns, Max
TAXA AX inputs to AMUX output 0.39 0.44 0.53 ns, Max
TAXB AX inputs to BMUX output 0.46 0.52 0.61 ns, Max
TAXC AX inputs to CMUX output 0.31 0.36 0.42 ns, Max
TAXD AX inputs to DMUX output 0.55 0.62 0.73 ns, Max
TBXB BX inputs to BMUX output 0.36 0.41 0.48 ns, Max
TBXD BX inputs to DMUX output 0.45 0.51 0.59 ns, Max
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 45
TCXB CX inputs to CMUX output 0.33 0.36 0.42 ns, Max
TCXD CX inputs to DMUX output 0.37 0.42 0.49 ns, Max
TDXD DX inputs to DMUX output 0.38 0.42 0.49 ns, Max
TOPCYA An input to COUT output 0.43 0.50 0.59 ns, Max
TOPCYB Bn input to COUT output 0.39 0.44 0.51 ns, Max
TOPCYC Cn input to COUT output 0.33 0.37 0.43 ns, Max
TOPCYD Dn input to COUT output 0.30 0.34 0.40 ns, Max
TAXCY AX input to COUT output 0.36 0.42 0.50 ns, Max
TBXCY BX input to COUT output 0.26 0.30 0.37 ns, Max
TCXCY CX input to COUT output 0.20 0.22 0.26 ns, Max
TDXCY DX input to COUT output 0.20 0.22 0.26 ns, Max
TBYP CIN input to COUT output 0.09 0.10 0.11 ns, Max
TCINA CIN input to AMUX output 0.24 0.27 0.31 ns, Max
TCINB CIN input to BMUX output 0.27 0.30 0.35 ns, Max
TCINC CIN input to CMUX output 0.29 0.32 0.36 ns, Max
TCIND CIN input to DMUX output 0.31 0.35 0.41 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.35 0.40 0.47 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK/TCKDI AX – DX input to CLK on A – D Flip Flops 0.36
0.19
0.41
0.21
0.49
0.24
ns, Min
TRCK DX input to CLK when used as REV 0.37 0.42 0.51 ns, Min
TCECK/TCKCE CE input to CLK on A – D Flip Flops 0.18
–0.04
0.20
–0.04
0.23
–0.04
ns, Min
TSRCK/TCKSR SR input to CLK on A – D Flip Flops 0.41
–0.19
0.49
–0.19
0.59
–0.19
ns, Min
TCINCK/TCKCIN CIN input to CLK on A – D Flip Flops 0.14
0.14
0.16
0.16
0.18
0.19
ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.90 0.90 0.90 ns, Min
TRQ Delay from SR or REV input to AQ – DQ flip-flops 0.74 0.86 1.03 ns, Max
TCEO Delay from CE input to AQ DQ flip-flops 0.46 0.52 0.63 ns, Max
FTOG Toggle frequency (for export control) 1412 1265 1098 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
Table 65: CLB Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 46
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Sequential Delays
TSHCKO Clock to A – B outputs 1.08 1.26 1.54 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 1.19 1.38 1.68 ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH A – D inputs to CLK 0.72
0.20
0.84
0.22
1.03
0.26
ns, Min
TAS/TAH Address An inputs to clock 0.41
0.20
0.46
0.22
0.54
0.27
ns, Min
TWS/TWH WE input to clock 0.34
–0.06
0.39
–0.04
0.46
–0.02
ns, Min
TCECK/TCKCE CE input to CLK 0.36
–0.08
0.42
–0.07
0.51
–0.06
ns, Min
Clock CLK
TMPW Minimum pulse width 0.70 0.82 1.00 ns, Min
TMCP Minimum clock period 1.40 1.64 2.00 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case, but if a “0” is
listed, there is no positive hold time.
2. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
Table 67: CLB Shift Register Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Sequential Delays
TREG Clock to A – D outputs 1.23 1.43 1.73 ns,
Max
TREG_MUX Clock to AMUX – DMUX output 1.33 1.55 1.87 ns,
Max
TREG_M31 Clock to DMUX output via M31 output 0.99 1.15 1.38 ns,
Max
Setup and Hold Times Before/After Clock CLK
TWS/TWH WE input 0.21
–0.06
0.24
–0.04
0.29
–0.02
ns, Min
TCECK/TCKCE CE input to CLK 0.23
–0.08
0.27
–0.07
0.33
–0.06
ns, Min
TDS/TDH A – D inputs to CLK 0.57
0.07
0.66
0.09
0.78
0.11
ns, Min
Clock CLK
TMPW Minimum pulse width 0.60 0.70 0.85 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 47
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Block RAM and FIFO Clock to Out Delays
TRCKO_DO and TRCKO_DOR(1) Clock CLK to DOUT output (without output
register)(2,3)
1.79 1.92 2.19 ns, Max
Clock CLK to DOUT output (with output register)(4,5) 0.61 0.69 0.82 ns, Max
Clock CLK to DOUT output with ECC (without output
register)(2,3)
2.64 3.03 3.61 ns, Max
Clock CLK to DOUT output with ECC (with output
register)(4,5)
0.66 0.77 0.93 ns, Max
Clock CLK to DOUT output with Cascade (without
output register)(2) 2.10 2.44 2.94 ns, Max
Clock CLK to DOUT output with Cascade (with output
register)(4)
0.91 1.07 1.30 ns, Max
TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) 0.76 0.87 1.02 ns, Max
TRCKO_POINTERS Clock CLK to FIFO pointer outputs(7) 1.10 1.26 1.48 ns, Max
TRCKO_ECCR Clock CLK to BITERR (with output register) 0.66 0.77 0.93 ns, Max
TRCKO_ECC Clock CLK to BITERR (without output register) 2.48 2.85 3.41 ns, Max
Clock CLK to ECCPARITY in standard ECC mode 1.29 1.47 1.74 ns, Max
Clock CLK to ECCPARITY in ECC encode only mode 0.77 0.89 1.05 ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDR/TRCKC_ADDR ADDR inputs(8) 0.34
0.30
0.40
0.32
0.48
0.36
ns, Min
TRDCK_DI/TRCKD_DI DIN inputs(9) 0.27
0.28
0.30
0.28
0.35
0.29
ns, Min
TRDCK_DI_ECC/TRCKD_DI_ECC DIN inputs with ECC in standard mode(9) 0.33
0.32
0.37
0.33
0.42
0.36
ns, Min
DIN inputs with ECC encode only(9 0.68
0.32
0.72
0.33
0.77
0.36
ns, Min
TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.32
0.15
0.36
0.15
0.42
0.15
ns, Min
TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.15
0.22
0.16
0.24
0.18
0.27
ns, Min
TRCCK_SSR/TRCKC_SSR Synchronous Set/ Reset (SSR) input 0.17
0.23
0.21
0.25
0.26
0.28
ns, Min
TRCCK_WE/TRCKC_WE Write Enable (WE) input 0.44
0.16
0.51
0.17
0.63
0.18
ns, Min
TRCCK_WREN/TRCKC_WREN WREN/RDEN FIFO inputs(10) 0.36
0.30
0.41
0.34
0.48
0.40
ns, Min
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 48
DSP48E Switching Characteristics
Reset Delays
TRCO_FLAGS Reset RST to FIFO Flags/Pointers(11) 1.10 1.26 1.48 ns, Max
Maximum Frequency
FMAX Block RAM in all modes 550 500 450 MHz
FMAX_CASCADE Block RAM in cascade configuration 500 450 400 MHz
FMAX_FIFO FIFO in all modes 550 500 450 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration 415 375 325 MHz
Notes:
1. TRACE will report all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
10. These parameters also apply to RDEN.
11. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Table 69: DSP48E Switching Characteristics
Symbol Description Speed Units
-3 -2 -1
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
{A, B, ACIN, BCIN} input to {A, B}
register CLK
0.17
0.17
0.21
0.23
0.26
0.30
ns
TDSPDCK_CC/TDSPCKD_CC C input to C register CLK 0.14
0.26
0.16
0.31
0.20
0.37
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to M register
CLK
1.30
0.19
1.44
0.19
1.71
0.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
{A, B, ACIN, BCIN} input to P register
CLK using multiplier
2.39
–0.30
2.74
–0.30
3.25
–0.30
ns
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
{A, B, ACIN, BCIN} input to P register
CLK not using multiplier
1.35
–0.10
1.54
–0.10
1.83
–0.10
ns
TDSPDCK_CP/TDSPCKD_CP C input to P register CLK 1.30
–0.13
1.42
–0.13
1.70
–0.13
ns
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
1.06
0.11
1.17
0.11
1.31
0.11
ns
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
{CEA1, CEA2A, CEB1B, CEB2B} input
to {A, B} register CLK
0.24
0.21
0.28
0.25
0.33
0.31
ns
TDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.19
0.17
0.21
0.21
0.26
0.28
ns
Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 49
TDSPCCK_CEMM/TDSPCKC_CEMM CEM input to M register CLK 0.25
0.18
0.29
0.21
0.36
0.26
ns
TDSPCCK_CEPP/TDSPCKC_CEPP CEP input to P register CLK 0.56
0.01
0.63
0.01
0.73
0.01
ns
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
{RSTA, RSTB} input to {A, B} register
CLK
0.24
0.23
0.28
0.26
0.33
0.31
ns
TDSPCCK_RSTCC/ TDSPCKC_RSTCC RSTC input to C register CLK 0.19
0.17
0.21
0.21
0.26
0.28
ns
TDSPCCK_RSTMM/ TDSPCKC_RSTMM RSTM input to M register CLK 0.25
0.18
0.29
0.21
0.36
0.26
ns
TDSPCCK_RSTPP/TDSPCKC_RSTPP RSTP input to P register CLK 0.56
0.01
0.63
0.01
0.73
0.01
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M {A, B} input to {P, CARRYOUT} output
using multiplier
2.78 3.22 3.84 ns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output
not using multiplier
1.59 1.77 2.22 ns
TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT} {C, CARRYIN} input to
{P, CARRYOUT} output
1.50 1.67 2.08 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT} {A, B} input to
{ACOUT, BCOUT} output
1.00 1.12 1.31 ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
2.78 3.22 3.84 ns
TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT,
BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM
{A, B} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
1.72 1.92 2.42 ns
TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT,
CRYINPCOUT, CRYINCRYCOUT,
CRYINMULTSIGNOUT}
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
1.63 1.82 2.28 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
{ACIN, BCIN} input to {P, CARRYOUT}
output using multiplier
2.78 3.22 3.84 ns
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
{ACIN, BCIN} input to {P, CARRYOUT}
output not using multiplier
1.59 1.77 2.22 ns
TDSPDO_{ACINACOUT, BCINBCOUT} {ACIN, BCIN} input to {ACOUT, BCOUT}
output
1.00 1.12 1.31 ns
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_M
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
2.78 3.22 3.84 ns
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT,
BCINMULTSIGNOUT}_NM
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
1.72 1.92 2.42 ns
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP,
PCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {P, CARRYOUT} output
1.30 1.45 1.82 ns
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol Description Speed Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 50
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
CRYCINCRYCOUT, MULTSIGNINCRYCOUT,
PCINMULTSIGNOUT, CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
1.43 1.60 2.02 ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP} CLK (PREG) to {P, CARRYOUT} output 0.45 0.48 0.56 ns
TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} CLK (PREG) to {CARRYCASCOUT,
PCOUT, MULTSIGNOUT} output
0.48 0.53 0.62 ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM} CLK (MREG) to {P, CARRYOUT} output 1.81 2.10 2.47 ns
TDSPCKO_{PCOUTM, CRYCOUTM,
MULTSIGNOUTM}
CLK (MREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
1.91 2.13 2.66 ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
3.09 3.57 4.23 ns
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
1.90 2.11 2.63 ns
TDSPCKO_{PC, CRYOUTC} CLK (CREG) to {P, CARRYOUT} output 1.89 2.11 2.62 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB} CLK (AREG, BREG) to {ACOUT,
BCOUT}
0.61 0.68 0.79 ns
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
3.09 3.57 4.23 ns
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
2.03 2.27 2.82 ns
TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
2.03 2.26 2.82 ns
Maximum Frequency
FMAX With all registers used 550 500 450 MHz
FMAX_PATDET With pattern detector 515 465 410 MHz
FMAX_MULT_NOMREG Two register multiply without MREG 374 324 275 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with
pattern detect
345 300 254 MHz
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol Description Speed Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 51
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
Power-up Timing Characteristics
TPL Program Latency 3 3 3 ms, Max
TPOR Power-on-Reset 10
50
10
50
10
50
ms, Min/Max
TICCK CCLK (output) delay 400 400 400 ns, Min
TPROGRAM Program Pulse Width 250 250 250 ns, Min
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD DIN Setup/Hold, slave mode 4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TDSCCK/TSCCKD DIN Setup/Hold, master mode 4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TCCO DOUT 7.5 7.5 7.5 ns, Max
FMCCK Maximum Frequency, master mode with
respect to nominal CCLK.
100 100 100 MHz,
Max
FMCCKTOL Frequency Tolerance, master mode with
respect to nominal CCLK.
±50 ±50 ±50 %
FMSCCK Slave mode external CCLK 100 100 100 MHz
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold 3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCSCCK/TSMCCKCS CS_B Setup/Hold 3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCCKW/TSMWCCK RDWR_B Setup/Hold 8.0
0.5
8.0
0.5
8.0
0.5
ns, Min
TSMCKCSO CSO_B clock to out
(330 Ω pull-up resistor required)
10 10 10 ns, Min
TSMCO CCLK to DATA out in readback 9.0 9.0 9.0 ns, Max
TSMCKBY CCLK to BUSY out in readback 7.5 7.5 7.5 ns, Max
FSMCCK Maximum Frequency with respect to nominal
CCLK.
100 100 100 MHz, Max
FRBCCK Maximum Readback Frequency with respect
to nominal CCLK
60 60 60 MHz, Max
FMCCKTOL Frequency Tolerance with respect to nominal
CCLK.
±50 ±50 ±50 %
Boundary-Scan Port Timing Specifications
TTAPTCK TMS and TDI Setup time before TCK 1.0 1.0 1.0 ns, Min
TTCKTAP TMS and TDI Hold time after TCK 2.0 2.0 2.0 ns, Min
TTCKTDO TCK falling edge to TDO output valid 6 6 6 ns, Max
FTCK Maximum configuration TCK clock frequency 66 66 66 MHz, Max
FTCKB Maximum boundary-scan TCK clock
frequency
66 66 66 MHz, Max
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 52
BPI Master Flash Mode Programming Switching
TBPICCO(4) ADDR[25:0], RS[1:0], FCS_B, FOE_B,
FWE_B outputs valid after CCLK rising edge
10 10 10 ns
TBPIDCC/TBPICCD Setup/Hold on D[15:0] data input pins 3.0
0.5
3.0
0.5
3.0
0.5
ns
TINITADDR Minimum period of initial ADDR[25:0] address
cycles
3.0 3.0 3.0 CCLK cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK
edge
4.0
0.0
4.0
0.0
4.0
0.0
ns
TSPICCM MOSI clock to out 10 10 10 ns
TSPICCFC FCS_B clock to out 10 10 10 ns
TFSINIT/TFSINITH FS[2:0] to INIT_B rising edge Setup and Hold 2 2 2 µs
CCLK Output (Master Modes)
TMCCKL Master CCLK clock minimum Low time 3.0 3.0 3.0 ns, Min
TMCCKH Master CCLK clock minimum High time 3.0 3.0 3.0 ns, Min
CCLK Input (Slave Modes)
TSCCKL Slave CCLK clock minimum Low time 2.0 2.0 2.0 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.0 2.0 2.0 ns, Min
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
FDCK Maximum frequency for DCLK 500 450 400 MHz
TDMCCK_DADDR/TDMCKC_DADDR DADDR Setup/Hold 1.2
0.0
1.35
0.0
1.56
0.0
ns
TDMCCK_DI/TDMCKC_DI DI Setup/Hold 1.2
0.0
1.35
0.0
1.56
0.0
ns
TDMCCK_DEN/TDMCKC_DEN DEN Setup/Hold time 1.2
0.0
1.35
0.0
1.56
0.0
ns
TDMCCK_DWE/TDMCKC_DWE DWE Setup/Hold time 1.2
0.0
1.35
0.0
1.56
0.0
ns
TDMCKO_DO CLK to out of DO(3) 1.0 1.12 1.3 ns
TDMCKO_DRDY CLK to out of DRDY 1.0 1.12 1.3 ns
Notes:
1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2. To support longer delays in configuration, use the design solutions described in UG190: Virtex-5 FPGA User Guide.
3. DO will hold until next DRP operation.
4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Table 70: Configuration Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 53
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description Devices Speed Grade Units
-3 -2 -1
TBCCCK_CE/TBCCKC_CE(1) CE pins Setup/Hold All 0.27
0.00
0.27
0.00
0.31
0.00
ns
TBCCCK_S/TBCCKC_S(1) S pins Setup/Hold All 0.27
0.00
0.27
0.00
0.31
0.00
ns
TBCCKO_O(2) BUFGCTRL delay from
I0/I1 to O
LX20T N/A 0.24 0.30 ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX70T,
FX100T, and FX130T
0.19 0.22 0.25 ns
FX30T 0.23 0.23 0.25 ns
LX155 and LX155T 0.12 0.14 0.30 ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A 0.22 0.25 ns
Maximum Frequency
FMAX Global clock tree (BUFG)
LX20T N/A 667 600 MHz
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, and
FX70T
710 667 600 MHz
LX155, LX155T, and FX100T 650 600 550 MHz
FX130T 550 500 450 MHz
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A 500 450 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description Speed Grade Units
-3 -2 -1
TBUFIOCKO_O Clock to out delay from I to O 1.08 1.16 1.29 ns
Maximum Frequency
FMAX I/O clock tree (BUFIO) 710 710 644 MHz
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 54
Table 73: Regional Clock Switching Characteristics (BUFR)
Symbol Description Devices Speed Grade Units
-3 -2 -1
TBRCKO_O Clock to out delay from
I to O
LX20T N/A 0.79 0.90 ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX100T, and
FX130T
0.56 0.59 0.67 ns
FX30T 0.72 0.78 0.86 ns
FX70T 0.69 0.74 0.83 ns
LX155 and LX155T 0.73 0.80 0.90 ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A 0.59 0.67 ns
TBRCKO_O_BYP
Clock to out delay from I to
O with Divide Bypass
attribute set
LX20T N/A 0.29 0.30 ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, FX70T,
FX100T, and FX130T
0.23 0.24 0.26 ns
LX155 and LX155T 0.24 0.26 0.30 ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A 0.24 0.26 ns
TBRDO_CLRO Propagation delay from
CLR to O
All 0.61 0.70 0.82 ns
Maximum Frequency
FMAX Regional clock tree
(BUFR)
All 300 250 250 MHz
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 55
PLL Switching Characteristics
Table 74: PLL Specification
Symbol Description Speed Grade Units
-3 -2 -1
FINMAX Maximum Input Clock Frequency 710 710 645 MHz
FINMIN Minimum Input Clock Frequency 19 19 19 MHz
FINJITTER Maximum Input Clock Period Jitter <20% of clock input period or 1 ns Max
FINDUTY Allowable Input Duty Cycle: 19—49 MHz 25/75 %
Allowable Input Duty Cycle: 50—199 MHz 30/70 %
Allowable Input Duty Cycle: 200—399 MHz 35/65 %
Allowable Input Duty Cycle: 400—499 MHz 40/60 %
Allowable Input Duty Cycle: >500 MHz 45/55 %
FVCOMIN Minimum PLL VCO Frequency 400 400 400 MHz
FVCOMAX Maximum PLL VCO Frequency 1440 1200 1000 MHz
FBANDWIDTH Low PLL Bandwidth at Typical(1) 111MHz
High PLL Bandwidth at Typical(1) 444MHz
TSTAPHAOFFSET Static Phase Offset of the PLL Outputs 120 120 120 ps
TOUTJITTER PLL Output Jitter(2) Note 1
TOUTDUTY PLL Output Clock Duty Cycle Precision(3) ±150 ±200 ±200 ps
TLOCKMAX PLL Maximum Lock Time(4) 100 100 100 µs
FOUTMAX
PLL Maximum Output Frequency for LX20T devices N/A 667 600 MHz
PLL Maximum Output Frequency for LX30, LX30T, LX50,
LX50T, LX85, LX85T, LX110, LX110T, SX35T, SX50T, FX30T,
and FX70Tdevices
710 667 600 MHz
PLL Maximum Output Frequency for LX155, LX155T, and
FX100T devices
650 600 550 MHz
PLL Maximum Output Frequency for FX130T devices 550 500 450 MHz
PLL Maximum Output Frequency for LX220, LX220T, LX330,
LX330T, SX95T, SX240T, TX150T, TX240T, and FX200T
devices
N/A 500 450 MHz
FOUTMIN PLL Minimum Output Frequency(5) 3.125 3.125 3.125 MHz
TEXTFDVAR External Clock Feedback Variation < 20% of clock input period or 1 ns Max
RSTMINPULSE Minimum Reset Pulse Width 5 5 5 ns
FPFDMAX Maximum Frequency at the Phase Frequency Detector 550 500 450 MHz
FPFDMIN Minimum Frequency at the Phase Frequency Detector 19 19 19 MHz
TFBDELAY Maximum External Delay in the Feedback Path 3 ns Max or one CLKIN cycle
Notes:
1. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. Values for this parameter are available in the Architecture Wizard.
3. Includes global clock buffer.
4. The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time has
expired.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 56
Table 75: PLL in PMCD Mode Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
TPLLCCK_REL/TPLLCKC_REL REL Setup and Hold for all Outputs 0.00
0.60
0.00
0.60
0.00
0.60
ns
TPLLCCKO Maximum Clock Propagation Delay 4.6 4.6 5.2 ns
CLKIN_FREQ_MAX Maximum Input Frequency 710 710 645 MHz
CLKIN_FREQ_MIN Minimum Input Frequency 1 1 1 MHz
CLKIN_DUTY_CYCLE Allowable Input Duty Cycle: 1—49 MHz 25/75 %
Allowable Input Duty Cycle: 50—199 MHz 30/70 %
Allowable Input Duty Cycle: 200—399 MHz 35/65 %
Allowable Input Duty Cycle: 400—499 MHz 40/60 %
Allowable Input Duty Cycle: >500 MHz 45/55 %
RES_REL_PULSE_MIN Minimum Pulse Width for RST and REL 5 5 5 ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 57
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol Description Speed Grade Units
-3 -2 -1
Outputs Clocks (Low Frequency Mode)
F1XLFMSMIN CLK0, CLK90, CLK180, CLK270 32.00 32.00 32.00 MHz
F1XLFMSMAX 150.00 135.00 120.00 MHz
F2XLFMSMIN CLK2X, CLK2X180 64.00 64.00 64.00 MHz
F2XLFMSMAX 300.00 270.00 240.00 MHz
FDVLFMSMIN CLKDV 2.0 2.0 2.0 MHz
FDVLFMSMAX 100.00 90.00 80.00 MHz
FFXLFMSMIN CLKFX, CLKFX180 32.00 32.00 32.00 MHz
FFXLFMSMAX 180.00 160.00 140.00 MHz
Input Clocks (Low Frequency Mode)
FDLLLFMSMIN CLKIN (using DLL outputs)(1, 3, 4) 32.00 32.00 32.00 MHz
FDLLLFMSMAX 150.00 135.00 120.00 MHz
FCLKINLFFXMSMIN CLKIN (using DFS outputs only)(2, 3, 4) 1.00 1.00 1.00 MHz
FCLKINLFFXMSMAX 180.00 160.00 140.00 MHz
FPSCLKLFMSMIN PSCLK 1.00 1.00 1.00 KHz
FPSCLKLFMSMAX 550.00 500.00 450.00 MHz
Outputs Clocks (High Frequency Mode)
F1XHFMSMIN CLK0, CLK90, CLK180, CLK270 120.00 120.00 120.00 MHz
F1XHFMSMAX 550.00 500.00 450.00 MHz
F2XHFMSMIN CLK2X, CLK2X180 240.00 240.00 240.00 MHz
F2XHFMSMAX 550.00 500.00 450.00 MHz
FDVHFMSMIN CLKDV 7.5 7.5 7.5 MHz
FDVHFMSMAX 366.67 333.34 300.00 MHz
FFXHFMSMIN CLKFX, CLKFX180 140.00 140.00 140.00 MHz
FFXHFMSMAX 400.00 375.00 350.00 MHz
Input Clocks (High Frequency Mode)
FDLLHFMSMIN CLKIN (using DLL outputs)(1, 3, 4) 120.00 120.00 120.00 MHz
FDLLHFMSMAX 550.00 500.00 450.00 MHz
FCLKINHFFXMSMIN CLKIN (using DFS outputs only)(2, 3, 4) 25.00 25.00 25.00 MHz
FCLKINHFFXMSMAX 400.00 375.00 350.00 MHz
FPSCLKHFMSMIN PSCLK 1.00 1.00 1.00 KHz
FPSCLKHFMSMAX 550.00 500.00 450.00 MHz
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 58
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
Symbol Description Speed Grade Units
-3 -2 -1
Outputs Clocks (Low Frequency Mode)
F1XMRMIN CLK0, CLK90, CLK180, CLK270 19.00 19.00 19.00 MHz
F1XMRMAX 32.00 32.00 32.00 MHz
F2XMRMIN CLK2X, CLK2X180 38.00 38.00 38.00 MHz
F2XMRMAX 64.00 64.00 64.00 MHz
FDLLMRMIN CLKDV 1.191.191.19MHz
FDLLMRMAX 21.34 21.34 21.34 MHz
FFXMRMIN CLKFX, CLKFX180 19.00 19.00 19.00 MHz
FFXMRMAX 40.00 40.00 40.00 MHz
Input Clocks (Low Frequency Mode)
FCLKINDLLMRMIN CLKIN (using DLL outputs)(1, 3, 4) 19.00 19.00 19.00 MHz
FCLKINDLLMRMAX 32.00 32.00 32.00 MHz
FCLKINFXMRMIN CLKIN (using DFS outputs only)(2, 3, 4) 1.00 1.00 1.00 MHz
FCLKINFXMRMAX 40.00 40.00 40.00 MHz
FPSCLKMRMIN PSCLK 1.00 1.00 1.00 KHz
FPSCLKMRMAX 300.00 270.00 240.00 MHz
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 59
Table 78: Input Clock Tolerances
Symbol Description Frequency Range Value Units
Duty Cycle Input Tolerance (in %)
TDUTYCYCRANGE_1 PSCLK only < 1 MHz 25 - 75 %
TDUTYCYCRANGE_1_50 PSCLK and CLKIN 1 - 50 MHz 25 - 75 %
TDUTYCYCRANGE_50_100 50 - 100 MHz 30 - 70 %
TDUTYCYCRANGE_100_200 100 - 200 MHz 40 - 60 %
TDUTYCYCRANGE_200_400 200 - 400 MHz(4) 45 - 55 %
TDUTYCYCRANGE_400 > 400 MHz 45 - 55 %
Input Clock Cycle-Cycle Jitter (Low Frequency Mode) Speed Grade Units
-3 -2 -1
TCYCLFDLL CLKIN (using DLL outputs)(1) 300.00 300.00 345.00 ps
TCYCLFFX CLKIN (using DFS outputs)(2) 300.00 300.00 345.00 ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
TCYCHFDLL CLKIN (using DLL outputs)(1) 150.00 150.00 173.00 ps
TCYCHFFX CLKIN (using DFS outputs)(2) 150.00 150.00 173.00 ps
Input Clock Period Jitter (Low Frequency Mode)
TPERLFDLL CLKIN (using DLL outputs)(1) 1.00 1.00 1.15 ns
TPERLFFX CLKIN (using DFS outputs)(2) 1.00 1.00 1.15 ns
Input Clock Period Jitter (High Frequency Mode)
TPERHFDLL CLKIN (using DLL outputs)(1) 1.00 1.00 1.15 ns
TPERHFFX CLKIN (using DFS outputs)(2) 1.00 1.00 1.15 ns
Feedback Clock Path Delay Variation
TCLKFB_DELAY_VAR CLKFB off-chip feedback 1.00 1.00 1.15 ns
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. If both DLL and DFS outputs are used, follow the more restrictive specifications.
4. This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the
DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed
grade devices. The GTX transceivers drive the DCMs at the following frequencies: 450 MHz for -1 speed grade devices or 500 MHz for -2
speed grade devices.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 60
Output Clock Jitter
Output Clock Phase Alignment
Table 79: Output Clock Jitter
Symbol Description Constraints Speed Grade Units
-3 -2 -1
Clock Synthesis Period Jitter
TPERJITT_0 CLK0 ±120 ±120 ±120 ps
TPERJITT_90 CLK90 ±120 ±120 ±120 ps
TPERJITT_180 CLK180 ±120 ±120 ±120 ps
TPERJITT_270 CLK270 ±120 ±120 ±120 ps
TPERJITT_2X CLK2X, CLK2X180 ±200 ±200 ±230 ps
TPERJITT_DV1 CLKDV (integer division) ±150 ±150 ±180 ps
TPERJITT_DV2 CLKDV (non-integer division) ±300 ±300 ±345 ps
TPERJITT_FX CLKFX, CLKFX180 Note 1 Note 1 Note 1 ps
Notes:
1. Values for this parameter are available in the Architecture Wizard.
Table 80: Output Clock Phase Alignment
Symbol Description Constraints Speed Grade Units
-3 -2 -1
Phase Offset Between CLKIN and CLKFB
TIN_FB_OFFSET CLKIN/CLKFB ±50 ±50 ±60 ps
Phase Offset Between Any DCM Outputs(1)
TOUT_OFFSET_1X CLK0, CLK90, CLK180, CLK270 ±140 ±140 ±160 ps
TOUT_OFFSET_2X CLK2X, CLK2X180, CLKDV ±150 ±150 ±200 ps
TOUT_OFFSET_FX CLKFX, CLKFX180 ±160 ±160 ±220 ps
Duty Cycle Precision(2)
TDUTY_CYC_DLL DLL outputs(3) ±150 ±150 ±180 ps
TDUTY_CYC_FX DFS outputs(4) ±150 ±150 ±180 ps
Notes:
1. All phase offsets are in respect to group CLK1X.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG).
3. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
4. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
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Product Specification 61
Table 81: Miscellaneous Timing Parameters
Symbol Description Speed Grade
-3 -2 -1 Units
Time Required to Achieve LOCK
TDLL_240 DLL output – Frequency range > 240 MHz (1) 80.00 80.00 80.00 µs
TDLL_120_240 DLL output – Frequency range 120 - 240 MHz (1) 250.00 250.00 250.00 µs
TDLL_60_120 DLL output – Frequency range 60 - 120 MHz (1) 900.00 900.00 900.00 µs
TDLL_50_60 DLL output – Frequency range 50 - 60 MHz(1) 1300.00 1300.00 1300.00 µs
TDLL_40_50 DLL output – Frequency range 40 - 50 MHz (1) 2000.00 2000.00 2000.00 µs
TDLL_30_40 DLL output – Frequency range 30 - 40 MHz (1) 3600.00 3600.00 3600.00 µs
TDLL_24_30 DLL output – Frequency range 24 - 30 MHz(1) 5000.00 5000.00 5000.00 µs
TDLL_30 DLL output – Frequency range < 30 MHz (1) 5000.00 5000.00 5000.00 µs
TFX_MIN DFS outputs(2) 10.00 10.00 10.00 ms
TFX_MAX 10.00 10.00 10.00 ms
TDLL_FINE_SHIFT Multiplication factor for DLL lock time with Fine Shift 2.00 2.00 2.00
Fine Phase Shifting
TRANGE_MS Absolute shifting range in maximum speed mode 7.00 7.00 7.00 ns
TRANGE_MR Absolute shifting range in maximum range mode 10.00 10.00 10.00 ns
Delay Lines
TTAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 7.00 7.00 7.00 ps
TTAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 30.00 30.00 30.00 ps
TTAP_MR_MIN Tap delay resolution (Min) in maximum range mode 10.00 10.00 10.00 ps
TTAP_MR_MAX Tap delay resolution (Max) in maximum range mode 40.00 40.00 40.00 ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82: Frequency Synthesis
Attribute Min Max
CLKFX_MULTIPLY 2 33
CLKFX_DIVIDE 1 32
Table 83: DCM Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1
TDMCCK_PSEN/ TDMCKC_PSEN PSEN Setup/Hold 1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC PSINCDEC Setup/Hold 1.20
0.00
1.35
0.00
1.56
0.00
ns
TDMCKO_PSDONE Clock to out of PSDONE 1.00 1.12 1.30 ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 62
Virtex-5 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 84. Values are expressed in nanoseconds unless otherwise noted.
Table 84: Global Clock Input to Output Delay Without DCM or PLL
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
TICKOF Global Clock and OUTFF without DCM or PLL XC5VLX20T N/A 5.98 6.69 ns
XC5VLX30 5.54 6.04 6.73 ns
XC5VLX30T 5.54 6.04 6.73 ns
XC5VLX50 5.59 6.09 6.79 ns
XC5VLX50T 5.59 6.09 6.79 ns
XC5VLX85 5.78 6.28 6.99 ns
XC5VLX85T 5.78 6.28 6.99 ns
XC5VLX110 5.84 6.35 7.06 ns
XC5VLX110T 5.84 6.35 7.06 ns
XC5VLX155 6.16 6.68 7.52 ns
XC5VLX155T 6.16 6.68 7.52 ns
XC5VLX220 N/A 6.99 7.71 ns
XC5VLX220T N/A 6.99 7.71 ns
XC5VLX330 N/A 7.17 7.91 ns
XC5VLX330T N/A 7.17 7.91 ns
XC5VSX35T 5.72 6.22 6.92 ns
XC5VSX50T 5.77 6.27 6.97 ns
XC5VSX95T N/A 6.59 7.30 ns
XC5VSX240T N/A 7.24 7.98 ns
XC5VTX150T N/A 6.58 7.30 ns
XC5VTX240T N/A 6.88 7.61 ns
XC5VFX30T 5.73 6.21 6.89 ns
XC5VFX70T 5.82 6.33 7.04 ns
XC5VFX100T 6.21 6.73 7.44 ns
XC5VFX130T 6.28 6.80 7.52 ns
XC5VFX200T N/A 7.17 7.91 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 63
Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in System-Synchronous Mode
TICKOFDCM Global Clock and OUTFF with DCM XC5VLX20T N/A 2.53 2.93 ns
XC5VLX30 2.33 2.56 2.93 ns
XC5VLX30T 2.33 2.56 2.93 ns
XC5VLX50 2.35 2.58 2.95 ns
XC5VLX50T 2.35 2.58 2.95 ns
XC5VLX85 2.41 2.63 3.00 ns
XC5VLX85T 2.41 2.63 3.00 ns
XC5VLX110 2.46 2.69 3.06 ns
XC5VLX110T 2.46 2.69 3.06 ns
XC5VLX155 2.51 2.74 3.10 ns
XC5VLX155T 2.51 2.74 3.10 ns
XC5VLX220 N/A 2.83 3.18 ns
XC5VLX220T N/A 2.83 3.18 ns
XC5VLX330 N/A 3.00 3.37 ns
XC5VLX330T N/A 3.00 3.37 ns
XC5VSX35T 2.44 2.67 3.03 ns
XC5VSX50T 2.46 2.69 3.05 ns
XC5VSX95T N/A 2.64 3.00 ns
XC5VSX240T N/A 3.00 3.36 ns
XC5VTX150T N/A 2.77 3.15 ns
XC5VTX240T N/A 2.78 3.15 ns
XC5VFX30T 2.55 2.82 3.20 ns
XC5VFX70T 2.48 2.74 3.12 ns
XC5VFX100T 2.33 2.59 3.00 ns
XC5VFX130T 2.40 2.67 3.07 ns
XC5VFX200T N/A 2.87 3.27 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 64
Table 86: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in Source-Synchronous Mode
TICKOFDCM_0 Global Clock and OUTFF with DCM XC5VLX20T N/A 3.74 4.20 ns
XC5VLX30 3.45 3.71 4.15 ns
XC5VLX30T 3.45 3.71 4.15 ns
XC5VLX50 3.47 3.73 4.17 ns
XC5VLX50T 3.47 3.73 4.17 ns
XC5VLX85 3.60 3.86 4.29 ns
XC5VLX85T 3.60 3.86 4.29 ns
XC5VLX110 3.65 3.92 4.36 ns
XC5VLX110T 3.65 3.92 4.36 ns
XC5VLX155 3.91 4.18 4.62 ns
XC5VLX155T 3.91 4.18 4.62 ns
XC5VLX220 N/A 4.41 4.85 ns
XC5VLX220T N/A 4.41 4.85 ns
XC5VLX330 N/A 4.58 5.04 ns
XC5VLX330T N/A 4.58 5.04 ns
XC5VSX35T 3.63 3.89 4.33 ns
XC5VSX50T 3.65 3.91 4.35 ns
XC5VSX95T N/A 4.16 4.59 ns
XC5VSX240T N/A 4.65 5.11 ns
XC5VTX150T N/A 4.07 4.51 ns
XC5VTX240T N/A 4.30 4.74 ns
XC5VFX30T 3.74 4.05 4.50 ns
XC5VFX70T 3.67 3.96 4.41 ns
XC5VFX100T 3.82 4.10 4.53 ns
XC5VFX130T 3.99 4.29 4.74 ns
XC5VFX200T N/A 4.60 5.03 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 65
Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode
TICKOFPLL Global Clock and OUTFF with PLL XC5VLX20T N/A 2.36 2.73 ns
XC5VLX30 2.03 2.30 2.70 ns
XC5VLX30T 2.03 2.30 2.70 ns
XC5VLX50 2.20 2.47 2.86 ns
XC5VLX50T 2.20 2.47 2.86 ns
XC5VLX85 2.21 2.49 2.88 ns
XC5VLX85T 2.21 2.49 2.88 ns
XC5VLX110 2.25 2.53 2.92 ns
XC5VLX110T 2.25 2.53 2.92 ns
XC5VLX155 2.34 2.60 3.01 ns
XC5VLX155T 2.34 2.60 3.01 ns
XC5VLX220 N/A 2.74 3.12 ns
XC5VLX220T N/A 2.74 3.12 ns
XC5VLX330 N/A 2.89 3.27 ns
XC5VLX330T N/A 2.89 3.27 ns
XC5VSX35T 2.02 2.28 2.62 ns
XC5VSX50T 2.12 2.36 2.76 ns
XC5VSX95T N/A 2.29 2.69 ns
XC5VSX240T N/A 2.96 3.34 ns
XC5VTX150T N/A 2.54 2.92 ns
XC5VTX240T N/A 2.67 3.04 ns
XC5VFX30T 2.44 2.67 3.06 ns
XC5VFX70T 2.48 2.71 3.10 ns
XC5VFX100T 2.41 2.70 3.10 ns
XC5VFX130T 2.48 2.75 3.17 ns
XC5VFX200T N/A 2.96 3.35 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 66
Table 88: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode
TICKOFPLL_0 Global Clock and OUTFF with PLL XC5VLX20T N/A 4.31 4.88 ns
XC5VLX30 3.96 4.32 4.82 ns
XC5VLX30T 3.96 4.32 4.82 ns
XC5VLX50 4.05 4.40 4.91 ns
XC5VLX50T 4.05 4.40 4.91 ns
XC5VLX85 4.07 4.40 4.88 ns
XC5VLX85T 4.07 4.40 4.88 ns
XC5VLX110 4.11 4.44 4.92 ns
XC5VLX110T 4.11 4.44 4.92 ns
XC5VLX155 4.31 4.66 5.16 ns
XC5VLX155T 4.31 4.66 5.16 ns
XC5VLX220 N/A 4.85 5.29 ns
XC5VLX220T N/A 4.85 5.29 ns
XC5VLX330 N/A 5.00 5.44 ns
XC5VLX330T N/A 5.00 5.44 ns
XC5VSX35T 4.19 4.54 5.03 ns
XC5VSX50T 4.20 4.54 5.02 ns
XC5VSX95T N/A 4.68 5.14 ns
XC5VSX240T N/A 5.07 5.51 ns
XC5VTX150T N/A 4.51 4.95 ns
XC5VTX240T N/A 4.71 5.14 ns
XC5VFX30T 4.23 4.56 5.04 ns
XC5VFX70T 4.22 4.54 5.02 ns
XC5VFX100T 4.35 4.70 5.19 ns
XC5VFX130T 4.49 4.86 5.40 ns
XC5VFX200T N/A 5.04 5.55 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 67
Table 89: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in System-Synchronous Mode
TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XC5VLX20T N/A 2.45 2.84 ns
XC5VLX30 2.25 2.48 2.84 ns
XC5VLX30T 2.25 2.48 2.84 ns
XC5VLX50 2.27 2.50 2.86 ns
XC5VLX50T 2.27 2.50 2.86 ns
XC5VLX85 2.33 2.55 2.91 ns
XC5VLX85T 2.33 2.55 2.91 ns
XC5VLX110 2.38 2.61 2.97 ns
XC5VLX110T 2.38 2.61 2.97 ns
XC5VLX155 2.43 2.66 3.01 ns
XC5VLX155T 2.43 2.66 3.01 ns
XC5VLX220 N/A 2.75 3.09 ns
XC5VLX220T N/A 2.75 3.09 ns
XC5VLX330 N/A 2.92 3.28 ns
XC5VLX330T N/A 2.92 3.28 ns
XC5VSX35T 2.36 2.59 2.94 ns
XC5VSX50T 2.38 2.61 2.96 ns
XC5VSX95T N/A 2.56 2.91 ns
XC5VSX240T N/A 2.92 3.27 ns
XC5VTX150T N/A 2.69 3.06 ns
XC5VTX240T N/A 2.70 3.06 ns
XC5VFX30T 2.47 2.74 3.11 ns
XC5VFX70T 2.40 2.66 3.03 ns
XC5VFX100T 2.25 2.51 2.91 ns
XC5VFX130T 2.32 2.59 2.98 ns
XC5VFX200T N/A 2.79 3.18 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 68
Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in Source-Synchronous Mode
TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XC5VLX20T N/A 3.66 4.11 ns
XC5VLX30 3.37 3.63 4.06 ns
XC5VLX30T 3.37 3.63 4.06 ns
XC5VLX50 3.39 3.65 4.08 ns
XC5VLX50T 3.39 3.65 4.08 ns
XC5VLX85 3.52 3.78 4.20 ns
XC5VLX85T 3.52 3.78 4.20 ns
XC5VLX110 3.57 3.84 4.27 ns
XC5VLX110T 3.57 3.84 4.27 ns
XC5VLX155 3.83 4.10 4.53 ns
XC5VLX155T 3.83 4.10 4.53 ns
XC5VLX220 N/A 4.33 4.76 ns
XC5VLX220T N/A 4.33 4.76 ns
XC5VLX330 N/A 4.50 4.95 ns
XC5VLX330T N/A 4.50 4.95 ns
XC5VSX35T 3.55 3.81 4.24 ns
XC5VSX50T 3.57 3.83 4.26 ns
XC5VSX95T N/A 4.08 4.50 ns
XC5VSX240T N/A 4.57 5.02 ns
XC5VTX150T N/A 3.99 4.42 ns
XC5VTX240T N/A 4.22 4.65 ns
XC5VFX30T 3.66 3.97 4.41 ns
XC5VFX70T 3.59 3.88 4.32 ns
XC5VFX100T 3.74 4.02 4.44 ns
XC5VFX130T 3.91 4.21 4.65 ns
XC5VFX200T N/A 4.52 4.94 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 69
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 91. Values are expressed in nanoseconds unless otherwise noted.
Table 91: Global Clock Setup and Hold Without DCM or PLL
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF(2) without DCM or PLL
XC5VLX20T N/A 1.63
–0.41
1.86
–0.41
ns
XC5VLX30 1.49
–0.35
1.60
–0.35
1.77
–0.35
ns
XC5VLX30T 1.49
–0.35
1.60
–0.35
1.76
–0.35
ns
XC5VLX50 1.48
–0.30
1.59
–0.30
1.76
–0.30
ns
XC5VLX50T 1.48
–0.30
1.59
–0.30
1.76
–0.30
ns
XC5VLX85 1.75
–0.49
1.89
–0.49
2.09
–0.49
ns
XC5VLX85T 1.75
–0.49
1.89
–0.49
2.09
–0.49
ns
XC5VLX110 1.74
–0.43
1.88
–0.43
2.09
–0.43
ns
XC5VLX110T 1.73
–0.43
1.88
–0.43
2.09
–0.43
ns
XC5VLX155 2.06
–0.50
2.36
–0.50
2.78
–0.49
ns
XC5VLX155T 2.06
–0.50
2.36
–0.50
2.78
–0.49
ns
XC5VLX220 N/A 2.57
–0.74
2.86
–0.74
ns
XC5VLX220T N/A 2.57
–0.74
2.86
–0.74
ns
XC5VLX330 N/A 2.55
–0.56
2.85
–0.56
ns
XC5VLX330T N/A 2.57
–0.56
2.86
–0.56
ns
XC5VSX35T 1.47
–0.16
1.59
–0.16
1.76
–0.16
ns
XC5VSX50T 1.62
–0.31
1.74
–0.31
1.93
–0.31
ns
XC5VSX95T N/A 2.10
–0.44
2.32
–0.44
ns
XC5VSX240T N/A 2.01
0.18
2.28
0.18
ns
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Product Specification 70
TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF(2) without DCM or PLL
XC5VTX150T N/A 2.35
–0.82
2.59
–0.82
ns
XC5VTX240T N/A 2.59
–0.85
2.87
–0.85
ns
XC5VFX30T 2.05
–0.27
2.25
–0.27
2.57
–0.27
ns
XC5VFX70T 1.85
–0.30
2.06
–0.30
2.35
–0.30
ns
XC5VFX100T 2.20
–0.42
2.38
–0.42
2.66
–0.42
ns
XC5VFX130T 2.33
–0.55
2.59
–0.54
2.95
–0.54
ns
XC5VFX200T N/A 2.52
–0.43
2.81
–0.43
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Table 91: Global Clock Setup and Hold Without DCM or PLL (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
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Product Specification 71
Table 92: Global Clock Setup and Hold With DCM in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in
System-Synchronous Mode
XC5VLX20T N/A 1.47
–0.56
1.59
–0.56
ns
XC5VLX30 1.53
–0.50
1.70
–0.50
1.88
–0.50
ns
XC5VLX30T 1.53
–0.50
1.70
–0.50
1.88
–0.50
ns
XC5VLX50 1.52
–0.48
1.68
–0.48
1.86
–0.48
ns
XC5VLX50T 1.52
–0.48
1.68
–0.48
1.86
–0.48
ns
XC5VLX85 1.58
–0.43
1.76
–0.43
1.95
–0.43
ns
XC5VLX85T 1.57
–0.43
1.76
–0.43
1.95
–0.43
ns
XC5VLX110 1.58
–0.37
1.76
–0.37
1.95
–0.37
ns
XC5VLX110T 1.58
–0.37
1.76
–0.37
1.95
–0.37
ns
XC5VLX155 2.02
–0.32
2.16
–0.32
2.38
–0.32
ns
XC5VLX155T 2.02
–0.32
2.16
–0.32
2.38
–0.32
ns
XC5VLX220 N/A 2.17
–0.27
2.44
–0.27
ns
XC5VLX220T N/A 2.17
–0.27
2.44
–0.27
ns
XC5VLX330 N/A 2.17
–0.10
2.44
–0.10
ns
XC5VLX330T N/A 2.17
–0.10
2.44
–0.10
ns
XC5VSX35T 1.60
–0.39
1.78
–0.39
1.98
–0.39
ns
XC5VSX50T 1.58
–0.37
1.76
–0.37
1.95
–0.37
ns
XC5VSX95T N/A 2.34
–0.41
2.35
–0.41
ns
XC5VSX240T N/A 2.25
–0.10
2.54
–0.10
ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 72
TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in
System-Synchronous Mode
XC5VTX150T N/A 1.85
–0.33
2.05
–0.33
ns
XC5VTX240T N/A 2.11
–0.32
2.35
–0.32
ns
XC5VFX30T 1.80
–0.28
1.89
–0.28
2.02
–0.28
ns
XC5VFX70T 1.76
–0.36
1.86
–0.36
1.98
–0.36
ns
XC5VFX100T 2.27
–0.51
2.35
–0.51
2.49
–0.49
ns
XC5VFX130T 2.33
–0.43
2.48
–0.43
2.72
–0.42
ns
XC5VFX200T N/A 2.30
–0.23
2.43
–0.21
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 92: Global Clock Setup and Hold With DCM in System-Synchronous Mode (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 73
Table 93: Global Clock Setup and Hold With DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
XC5VLX20T N/A 0.12
0.64
0.14
0.72
ns
XC5VLX30 0.27
0.62
0.27
0.62
0.27
0.66
ns
XC5VLX30T 0.27
0.62
0.27
0.62
0.27
0.66
ns
XC5VLX50 0.26
0.64
0.26
0.64
0.26
0.68
ns
XC5VLX50T 0.25
0.64
0.26
0.64
0.26
0.68
ns
XC5VLX85 0.23
0.76
0.24
0.76
0.24
0.80
ns
XC5VLX85T 0.23
0.76
0.24
0.76
0.24
0.80
ns
XC5VLX110 0.23
0.82
0.24
0.82
0.24
0.87
ns
XC5VLX110T 0.23
0.82
0.24
0.82
0.24
0.87
ns
XC5VLX155 0.12
1.08
0.14
1.08
0.16
1.13
ns
XC5VLX155T 0.12
1.08
0.14
1.08
0.16
1.13
ns
XC5VLX220 N/A 0.21
1.31
0.22
1.36
ns
XC5VLX220T N/A 0.21
1.31
0.22
1.36
ns
XC5VLX330 N/A 0.21
1.48
0.22
1.55
ns
XC5VLX330T N/A 0.21
1.48
0.22
1.55
ns
XC5VSX35T 0.25
0.80
0.27
0.80
0.27
0.84
ns
XC5VSX50T 0.24
0.82
0.25
0.82
0.25
0.86
ns
XC5VSX95T N/A 0.24
1.06
0.24
1.11
ns
XC5VSX240T N/A 0.20
1.55
0.21
1.62
ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 74
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
XC5VTX150T N/A 0.25
0.97
0.25
1.03
ns
XC5VTX240T N/A 0.24
1.20
0.24
1.26
ns
XC5VFX30T 0.16
0.91
0.18
0.95
0.19
1.01
ns
XC5VFX70T 0.13
0.83
0.14
0.86
0.14
0.92
ns
XC5VFX100T 0.21
0.98
0.21
1.00
0.21
1.05
ns
XC5VFX130T 0.19
1.15
0.21
1.19
0.24
1.25
ns
XC5VFX200T N/A 0.14
1.50
0.16
1.55
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 93: Global Clock Setup and Hold With DCM in Source-Synchronous Mode (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 75
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VLX20T N/A 1.74
–0.82
2.02
–0.82
ns
XC5VLX30 1.53
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX30T 1.52
–0.80
1.68
–0.80
1.90
–0.79
ns
XC5VLX50 1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX50T 1.50
–0.64
1.65
–0.63
1.89
–0.62
ns
XC5VLX85 1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX85T 1.83
–0.63
1.95
–0.62
2.09
–0.61
ns
XC5VLX110 1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX110T 1.83
–0.58
1.96
–0.57
2.10
–0.57
ns
XC5VLX155 1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX155T 1.91
–0.49
2.09
–0.49
2.37
–0.47
ns
XC5VLX220 N/A 1.93
–0.36
2.09
–0.36
ns
XC5VLX220T N/A 1.93
–0.36
2.09
–0.36
ns
XC5VLX330 N/A 2.09
–0.21
2.33
–0.21
ns
XC5VLX330T N/A 2.12
–0.21
2.34
–0.21
ns
XC5VSX35T 1.82
–0.82
2.02
–0.82
2.33
–0.82
ns
XC5VSX50T 1.96
–0.72
2.07
–0.72
2.20
–0.72
ns
XC5VSX95T N/A 2.17
–0.80
2.35
–0.79
ns
XC5VSX240T N/A 2.11
–0.14
2.33
–0.14
ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 76
TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VTX150T N/A 1.82
–0.56
1.95
–0.56
ns
XC5VTX240T N/A 2.05
–0.43
2.26
–0.43
ns
XC5VFX30T 1.82
–0.40
1.93
–0.40
2.09
–0.40
ns
XC5VFX70T 1.79
–0.30
1.90
–0.30
2.07
–0.30
ns
XC5VFX100T 1.81
–0.43
1.91
–0.40
2.09
–0.38
ns
XC5VFX130T 1.79
–0.29
1.95
–0.28
2.14
–0.24
ns
XC5VFX200T N/A 2.06
–0.14
2.29
–0.14
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 77
Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in
Source-Synchronous Mode
XC5VLX20T N/A –0.26
1.21
–0.25
1.40
ns
XC5VLX30 –0.33
1.13
–0.33
1.22
–0.33
1.34
ns
XC5VLX30T –0.33
1.13
–0.33
1.22
–0.33
1.34
ns
XC5VLX50 –0.24
1.21
–0.24
1.30
–0.23
1.42
ns
XC5VLX50T –0.24
1.21
–0.24
1.30
–0.23
1.42
ns
XC5VLX85 –0.25
1.23
–0.23
1.30
–0.22
1.39
ns
XC5VLX85T –0.25
1.23
–0.23
1.30
–0.22
1.39
ns
XC5VLX110 –0.26
1.27
–0.24
1.34
–0.23
1.43
ns
XC5VLX110T –0.26
1.27
–0.25
1.34
–0.23
1.43
ns
XC5VLX155 –0.15
1.48
–0.12
1.56
–0.10
1.67
ns
XC5VLX155T –0.16
1.48
–0.12
1.56
–0.10
1.67
ns
XC5VLX220 N/A –0.34
1.75
–0.30
1.80
ns
XC5VLX220T N/A –0.34
1.75
–0.31
1.80
ns
XC5VLX330 N/A –0.34
1.90
–0.30
1.95
ns
XC5VLX330T N/A –0.34
1.90
–0.30
1.95
ns
XC5VSX35T –0.19
1.36
–0.18
1.44
–0.16
1.54
ns
XC5VSX50T –0.27
1.37
–0.26
1.44
–0.25
1.53
ns
XC5VSX95T N/A –0.26
1.58
–0.24
1.65
ns
XC5VSX240T N/A –0.35
1.97
–0.31
2.02
ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 78
TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in
Source-Synchronous Mode
XC5VTX150T N/A –0.31
1.41
–0.29
1.47
ns
XC5VTX240T N/A –0.31
1.61
–0.29
1.66
ns
XC5VFX30T –0.10
1.40
–0.09
1.46
–0.08
1.55
ns
XC5VFX70T –0.12
1.38
–0.10
1.44
–0.09
1.53
ns
XC5VFX100T –0.18
1.51
–0.18
1.60
–0.18
1.71
ns
XC5VFX130T –0.12
1.66
–0.11
1.76
–0.09
1.92
ns
XC5VFX200T N/A –0.12
1.94
–0.10
2.06
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 79
Table 96: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade Units
-3 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCMPLL/
TPHDCMPLL
No Delay Global Clock and IFF(2) with
DCM and PLL in System-Synchronous Mode
XC5VLX20T N/A 1.67
–0.64
1.78
–0.64
ns
XC5VLX30 1.72
–0.58
1.89
–0.58
2.07
–0.58
ns
XC5VLX30T 1.72
–0.58
1.89
–0.58
2.06
–0.58
ns
XC5VLX50 1.69
–0.56
1.86
–0.56
2.04
–0.56
ns
XC5VLX50T 1.69
–0.56
1.86
–0.56
2.04
–0.56
ns
XC5VLX85 1.74
–0.51
1.93
–0.51
2.13
–0.51
ns
XC5VLX85T 1.74
–0.51
1.93
–0.51
2.13
–0.51
ns
XC5VLX110 1.73
–0.45
1.93
–0.45
2.13
–0.45
ns
XC5VLX110T 1.73
–0.45
1.93
–0.45
2.13
–0.45
ns
XC5VLX155 2.14
–0.40
2.31
–0.40
2.55
–0.40
ns
XC5VLX155T 2.14
–0.40
2.31
–0.40
2.55
–0.40
ns
XC5VLX220 N/A 2.32
–0.35
2.61
–0.35
ns
XC5VLX220T N/A 2.32
–0.35
2.61
–0.35
ns
XC5VLX330 N/A 2.29
–0.18
2.60
–0.18
ns
XC5VLX330T N/A 2.32
–0.18
2.61
–0.18
ns
XC5VSX35T 1.78
–0.47
1.97
–0.47
2.16
–0.47
ns
XC5VSX50T 1.76
–0.45
1.94
–0.45
2.14
–0.45
ns
XC5VSX95T N/A 2.51
–0.49
2.53
–0.49
ns
XC5VSX240T N/A 2.39
–0.18
2.70
–0.18
ns
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 80
TPSDCMPLL/
TPHDCMPLL
No Delay Global Clock and IFF(2) with
DCM and PLL in System-Synchronous Mode
XC5VTX150T N/A 2.00
–0.41
2.22
–0.41
ns
XC5VTX240T N/A 2.25
–0.40
2.51
–0.40
ns
XC5VFX30T 1.97
–0.36
2.08
–0.36
2.21
–0.36
ns
XC5VFX70T 1.92
–0.44
2.03
–0.44
2.16
–0.44
ns
XC5VFX100T 2.40
–0.59
2.51
–0.59
2.66
–0.58
ns
XC5VFX130T 2.46
–0.51
2.64
–0.51
2.89
–0.51
ns
XC5VFX200T N/A 2.44
–0.31
2.59
–0.30
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 96: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016 www.xilinx.com
Product Specification 81
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade Units
-3-2-1
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 32.
TPSDCMPLL_0/
TPHDCMPLL_0
No Delay Global Clock and IFF(2) with DCM and
PLL in Source-Synchronous Mode
XC5VLX20T N/A 0.32
0.56
0.33
0.63
ns
XC5VLX30 0.45
0.54
0.46
0.54
0.46
0.57
ns
XC5VLX30T 0.45
0.54
0.46
0.54
0.46
0.57
ns
XC5VLX50 0.43
0.56
0.44
0.56
0.44
0.59
ns
XC5VLX50T 0.43
0.56
0.44
0.56
0.44
0.59
ns
XC5VLX85 0.40
0.68
0.42
0.68
0.42
0.71
ns
XC5VLX85T 0.39
0.68
0.42
0.68
0.42
0.71
ns
XC5VLX110 0.38
0.74
0.41
0.74
0.41
0.78
ns
XC5VLX110T 0.38
0.74
0.41
0.74
0.41
0.78
ns
XC5VLX155 0.24
1.00
0.29
1.00
0.33
1.04
ns
XC5VLX155T 0.24
1.00
0.29
1.00
0.33
1.04
ns
XC5VLX220 N/A 0.36
1.23
0.38