USD

W25Q128JV-DTR Datasheet

Winbond Electronics

View All Related Products | Download PDF Datasheet

Datasheet

W25Q128JV-DTR
Publication Release Date: March 02, 2018
-Revision C
3V 128M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI & DTR
For Industrial & Industrial Plus Grade
W25Q128JV-DTR
Table of Contents
1. GENERAL DESCRIPTIONS ............................................................................................................. 5
2. FEATURES ....................................................................................................................................... 5
3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6
3.1 Pin Configuration SOIC 208-mil ........................................................................................... 6
3.2 Pad Configuration WSON 6x5-mm / 8x6-mm ...................................................................... 6
3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm ................................................... 6
3.4 Pin Configuration SOIC 300-mil ........................................................................................... 7
3.5 Pin Description SOIC 300-mil ............................................................................................... 7
3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
3.7 Ball Description TFBGA 8x6-mm ......................................................................................... 8
4. PIN DESCRIPTIONS ........................................................................................................................ 9
4.1 Chip Select (/CS) .................................................................................................................. 9
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9
4.3 Write Protect (/WP) .............................................................................................................. 9
4.4 HOLD (/HOLD) ..................................................................................................................... 9
4.5 Serial Clock (CLK) ................................................................................................................ 9
4.6 Reset (/RESET) .................................................................................................................... 9
5. BLOCK DIAGRAM .......................................................................................................................... 10
6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1 SPI / QPI Operations .......................................................................................................... 11
6.1.1 Standard SPI Instructions ..................................................................................................... 11
6.1.2 Dual SPI Instructions ............................................................................................................ 11
6.1.3 Quad SPI Instructions ........................................................................................................... 12
6.1.4 QPI Instructions .................................................................................................................... 12
6.1.5 SPI / QPI DTR Read Instructions ......................................................................................... 12
6.1.6 Hold Function ....................................................................................................................... 12
6.1.7 Software Reset & Hardware /RESET pin .............................................................................. 13
6.2 Write Protection .................................................................................................................. 14
6.2.1 Write Protect Features ......................................................................................................... 14
7. STATUS AND CONFIGURATION REGISTERS ............................................................................ 15
7.1 Status Registers ................................................................................................................. 15
7.1.1 Erase/Write In Progress (BUSY) Status Only ................................................................ 15
7.1.2 Write Enable Latch (WEL) Status Only .......................................................................... 15
7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable ................................ 15
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 2 - -Revision C
7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable ....................................... 16
7.1.5 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable ....................................... 16
7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable ............................................ 16
7.1.7 Status Status Register Protect Protect (SRP, SRL) ............................................................. 17
7.1.8 Erase/Program Suspend Status (SUS)
Status Only......................................................... 0
7.1.9 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable ............ 0
7.1.10 Quad Enable (QE) Volatile/Non-Volatile Writable .......................................................... 0
7.1.11 Write Protect Selection (WPS) Volatile/Non-Volatile Writable ..................................... 19
7.1.12 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable ......................... 19
7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable .............. 19
7.1.14 Reserved Bits Non Functional ...................................................................................... 20
7.1.15 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 0) ............................. 21
7.1.16 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 1) ............................. 22
7.1.17 W25Q128JV Individual Block Memory Protection (WPS=1) .............................................. 23
8. INSTRUCTIONS ............................................................................................................................. 24
8.1 Device ID and Instruction Set Tables ................................................................................. 24
8.1.1 Manufacturer and Device Identification ................................................................................ 24
8.1.2 Instruction Set Table 1 (Standard SPI Instructions)(1)........................................................... 25
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions) ........................................................... 26
8.1.4 Instruction Set Table 3 (QPI Instructions)(11) ........................................................................ 27
8.1.5 Instruction Set Table 4 (DTR with SPI Instructions) ............................................................. 28
8.1.6 Instruction Set Table 5 (DTR with QPI Instructions) ............................................................. 28
8.2 Instruction Descriptions ...................................................................................................... 30
8.2.1 Write Enable (06h) ............................................................................................................... 30
8.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 30
8.2.3 Write Disable (04h) ............................................................................................................... 31
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 32
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 33
8.2.6 Read Data (03h) ................................................................................................................... 35
8.2.7 Fast Read (0Bh) ................................................................................................................... 36
8.2.8 DTR Fast Read (0Dh) ........................................................................................................... 38
8.2.9 Fast Read Dual Output (3Bh) ............................................................................................... 40
8.2.10 Fast Read Quad Output (6Bh) ............................................................................................ 41
8.2.11 Fast Read Dual I/O (BBh) ................................................................................................... 42
8.2.12 DTR Fast Read Dual I/O (BDh) .......................................................................................... 44
8.2.13 Fast Read Quad I/O (EBh) ................................................................................................. 46
8.2.14 DTR Fast Read Quad I/O (EDh) ......................................................................................... 48
8.2.15 Set Burst with Wrap (77h) .................................................................................................. 52
8.2.16 Page Program (02h) ........................................................................................................... 53
8.2.17 Quad Input Page Program (32h) ........................................................................................ 55
W25Q128JV-DTR
8.2.18 Sector Erase (20h) ............................................................................................................. 56
8.2.19 32KB Block Erase (52h) ..................................................................................................... 57
8.2.20 64KB Block Erase (D8h) ..................................................................................................... 58
8.2.21 Chip Erase (C7h / 60h) ....................................................................................................... 59
8.2.22 Erase / Program Suspend (75h) ......................................................................................... 60
8.2.23 Erase / Program Resume (7Ah) ......................................................................................... 62
8.2.24 Power-down (B9h) .............................................................................................................. 63
8.2.25 Release Power-down / Device ID (ABh) ............................................................................. 64
8.2.26 Read Manufacturer / Device ID (90h) ................................................................................. 66
8.2.27 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 67
8.2.28 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 68
8.2.29 Read Unique ID Number (4Bh)........................................................................................... 69
8.2.30 Read JEDEC ID (9Fh) ........................................................................................................ 70
8.2.31 Erase Security Registers (44h) ........................................................................................... 71
8.2.32 Read SFDP Register (5Ah) ................................................................................................ 72
8.2.33 Program Security Registers (42h) ...................................................................................... 73
8.2.34 Read Security Registers (48h) ........................................................................................... 74
8.2.35 Set Read Parameters (C0h) ............................................................................................... 75
8.2.36 Burst Read with Wrap (0Ch) ............................................................................................... 76
8.2.37 DTR Burst Read with Wrap (0Eh) ...................................................................................... 77
8.2.38 Enter QPI Mode (38h) ......................................................................................................... 78
8.2.39 Exit QPI Mode (FFh) ........................................................................................................... 79
8.2.40 Individual Block/Sector Lock (36h) ..................................................................................... 80
8.2.41 Individual Block/Sector Unlock (39h) .................................................................................. 81
8.2.42 Read Block/Sector Lock (3Dh) ........................................................................................... 82
8.2.43 Global Block/Sector Lock (7Eh) .......................................................................................... 83
8.2.44 Global Block/Sector Unlock (98h) ....................................................................................... 83
8.2.45 Enable Reset (66h) and Reset Device (99h) ...................................................................... 84
9. ELECTRICAL CHARACTERISTICS ............................................................................................... 85
9.1 Absolute Maximum Ratings (1) ............................................................................................ 85
9.2 Operating Ranges............................................................................................................... 85
9.3 Power-Up Power-Down Timing and Requirements ............................................................ 86
9.4 DC Electrical Characteristics- ............................................................................................. 87
9.5 AC Measurement Conditions .............................................................................................. 88
9.6 AC Electrical Characteristics(6) ........................................................................................... 89
9.7 Serial Output Timing ........................................................................................................... 91
9.8 Serial Input Timing .............................................................................................................. 91
9.9 /HOLD Timing ..................................................................................................................... 91
9.10 /WP Timing ......................................................................................................................... 91
10. PACKAGE SPECIFICATIONS ........................................................................................................ 92
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 4 - -Revision C
10.1 8-Pin SOIC 208-mil (Package Code S) .............................................................................. 92
10.2 8-Pad WSON 6x5-mm (Package Code P) ......................................................................... 93
10.3 8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 94
10.4 16-Pin SOIC 300-mil (Package Code F) ............................................................................ 95
10.5 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) ............................................ 96
10.6 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) ............................................... 97
11. ORDERING INFORMATION .......................................................................................................... 98
11.1 Valid Part Numbers and Top Side Marking ........................................................................ 99
12. REVISION HISTORY .................................................................................................................... 100
W25Q128JV-DTR
1. GENERAL DESCRIPTIONS
The W25Q128JV (128M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current
consumption as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV
has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See Figure 2.)
The W25Q128JV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI Quad
Peripheral Interface (QPI) as well as Double Transfer Rate(DTR) : Serial Clock, Chip Select, Serial Data
I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 133MHz are supported
allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad
I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These 3transfer rates can outperform
standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for
efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing
true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID, a
64-bit Unique Serial Number and three 256-bytes Security Registers.
2. FEATURES
New Family of SpiFlash Memories
W25Q128JV: 128M-bit / 16M-byte
Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
QPI: CLK, /CS, IO0, IO1, IO2, IO3
SPI/QPI DTR(Double Transfer Rate) Read
Software & Hardware Reset(1)
Highest Performance Serial Flash
133MHz Single, Dual/Quad SPI clocks
266/532MHz equivalent Dual/Quad SPI
66MB/S continuous data transfer rate
Min. 100K Program-Erase cycles per sector
More than 20-year data retention
Efficient “Continuous Read” and QPI Mode
Continuous Read with 8/16/32/64-Byte Wrap
As few as 8 clocks to address memory
Quad Peripheral Interface (QPI) reduces
instruction overhead
Allows true XIP (execute in place) operation
Low Power, Wide Temperature Range
Single 2.7 to 3.6V supply
<1µA Power-down (typ.)
-40°C to +85°C operating range
-40°C to +105°C operating range
Flexible Architecture with 4KB sectors
Uniform Sector/Block Erase (4K/32K/64K-Byte)
Program 1 to 256 byte per programmable page
Erase/Program Suspend & Resume
Advanced Security Features
Software and Hardware Write-Protect
Power Supply Lock-Down and OTP protection
Top/Bottom, Complement array protection
Individual Block/Sector array protection
64-Bit Unique ID for each device
Discoverable Parameters (SFDP) Register
3X256-Bytes Security Registers with OTP locks
Volatile & Non-volatile Status Register Bits
Space Efficient Packaging
8-pin SOIC 208-mil
8-pad WSON 6x5-mm / 8x6-mm
16-pin SOIC 300-mil (additional /RESET pin)
24-ball TFBGA 8x6-mm (6x4/5x5 ball array)
Contact Winbond for KGD and other options
Note: 1. Hardware /RESET pin is only available on
SOIC16 or TFBGA packages
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 6 - -Revision C
3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC 208-mil
1
2
3
4
8
7
6
5
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD or /RESET
(IO3)
DI (IO0)
CLK
Top View
Figure 1a. W25Q128JV Pin Assignments, 8-pin SOIC 208-mil (Package Code S)
3.2 Pad Configuration WSON 6x5-mm / 8x6-mm
1
2
3
4
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD or /RESET
(IO3)
DI (IO0)
CLK
Top View
8
7
6
5
Figure 1b. W25Q128JV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code P / E)
3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm
PIN NO.
I/O
FUNCTION
1
I
Chip Select Input
2
I/O
Data Output (Data Input Output 1)(1)
3
I/O
Write Protect Input ( Data Input Output 2)(2)
4
Ground
5
I/O
Data Input (Data Input Output 0)(1)
6
I
Serial Clock Input
7
I/O
Hold or Reset Input (Data Input Output 3)(2)
8
Power Supply
Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual
SPI.
W25Q128JV-DTR
3.4 Pin Configuration SOIC 300-mil
1
2
3
4
/CS
DO (IO1) /WP (IO2)
GND
VCC
/HOLD (IO3)
DI (IO0)
CLK
Top View
NC
/RESET
NC
NC
NC
NC
NC
NC5
6
7
8
10
9
11
12
13
14
15
16
Figure 1c. W25Q128JV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.5 Pin Description SOIC 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
2
VCC
Power Supply
3
/RESET
I
Reset Input(3)
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
9
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
16
CLK
I
Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin
can be left floating, if Rest function is not needed.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 8 - -Revision C
3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
D1
/HOLD(IO3)DI(IO0)DO(IO1)
/WP (IO2)
D2 D3 D4
NC
E1
NCNCNC
E2 E3 E4
NC
F1
NCNCNC
F2 F3 F4
NC
A1
/RESETNCNC
A2 A3 A4
NC
B1
VCCGNDCLK
B2 B3 B4
NC
C1
NC/CS
C2 C3 C4
NC
Top View
Package Code C
Top View
D1
/HOLD(IO3)DI(IO0)DO(IO1)
/WP (IO2)
D2 D3 D4
NC
E1
NCNCNC
E2 E3 E4
NC
/RESETNCNC
A2 A3 A4
B1
VCCGNDCLK
B2 B3 B4
NC
C1
NC/CS
C2 C3 C4
NC
D5
E5
A5
B5
C5
NC
NC
NC
NC
NC
Package Code B
Figure 1d. W25Q128JV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)
3.7 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
A4
/RESET
I
Reset Input
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
Chip Select Input
C4
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD
(IO3)
I/O
Hold Input (Data Input Output 3)(2)
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
W25Q128JV-DTR
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
58). If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q128JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin
configuration of Quad I/O operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See Figure 1a-e for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC
and TFBGA package, a dedicated /RESET pin is provided and it is independent of QE bit setting.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 10 - -Revision C
5. BLOCK DIAGRAM
Figure 2. W25Q128JV Serial Flash Memory Block Diagram
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
Column Decode
And 256-Byte Page Buffer
Beginning
Page Address Ending
Page Address
W25Q128FV
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
DO (IO1)
DI (IO0)
/CS
CLK
/HOLD (IO3) or
/RESET (IO3)
/WP (IO2)
High Voltage
Generators
xx0F00h xx0FFFh
Sector 0 (4KB)
xx0000h xx00FFh
xx1F00h xx1FFFh
Sector 1 (4KB)
xx1000h xx10FFh
xx2F00h xx2FFFh
Sector 2 (4KB)
xx2000h xx20FFh
xxDF00h xxDFFFh
Sector 13 (4KB)
xxD000h xxD0FFh
xxEF00h xxEFFFh
Sector 14 (4KB)
xxE000h xxE0FFh
xxFF00h xxFFFFh
Sector 15 (4KB)
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 1 - 3
Write Protect Logic and Row Decode
000000h 0000FFh
SFDP Register
00FF00h 00FFFFh
Block 0 (64KB)
000000h 0000FFh
3FFF00h 3FFFFFh
Block 63 (64KB)
3F0000h 3F00FFh
40FF00h 40FFFFh
Block 64 (64KB)
400000h 4000FFh
7FFF00h 7FFFFFh
Block 127 (64KB)
7F0000h 7F00FFh
80FF00h 80FFFFh
Block 128 (64KB)
800000h 8000FFh
FFFF00h FFFFFFh
Block 255 (64KB)
FF0000h FF00FFh
W25Q128JV
W25Q128JV-DTR
6. FUNCTIONAL DESCRIPTIONS
6.1 SPI / QPI Operations
Power Up
Standard SPI
Dual SPI
Quad SPI
QPI
Enable QPI (38h) Disable QPI (FFh)
SPI Reset
(66h + 99h)
QPI Reset
(66h + 99h)
Device Initialization
& Status Register Refresh
(Non-Volatile Cells)
Hardware
Reset
Hardware
Reset
Figure 3. W25Q128JV Serial Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25Q128JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25Q128JV supports Dual SPI operation when using instructions such as Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh). These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 12 - -Revision C
6.1.3 Quad SPI Instructions
The W25Q128JV supports Quad SPI operation when using instructions such as Fast Read Quad Output
(6Bh), and Fast Read Quad I/O (EBh). These instructions allow data to be transferred to or from the
device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant
improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or
execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
6.1.4 QPI Instructions
The W25Q128JV supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only
one mode can be active at any given time. Enter QPI (38h)” and Exit QPI (FFh)” instructions are used to
switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction,
the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile
Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and
DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.
6.1.5 SPI / QPI DTR Read Instructions
To effectively improve the read operation throughput without increasing the serial clock frequency,
W25Q128JV introduces multiple DTR (Double Transfer Rate) Read instructions that support
Standard/Dual/Quad SPI and QPI modes. The byte-long instruction code is still latched into the device on
the rising edge of the serial clock similar to all other SPI/QPI instructions. Once a DTR instruction code is
accepted by the device, the address input and data output will be latched on both rising and falling edges
of the serial clock.
6.1.6 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q128JV operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to
determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD,
when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
W25Q128JV-DTR
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
6.1.7 Software Reset & Hardware /RESET pin
The W25Q128JV can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) &
Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS
(tRST) to reset. No command will be accepted during the reset period.
For the WSON-8 and TFBGA package types, W25Q128JV can also be configured to utilize a hardware
/RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or
RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described
above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period
of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase operation
will be interrupted and data corruption may happen. While /RESET is low, the device will not accept any
command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four
data I/O pins.
For the SOIC-16 package, W25Q128JV provides a dedicated /RESET pin in addition to the /HOLD (IO3)
pin as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset
the device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will not affect
the function of this dedicated /RESET pin.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the
status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).
Note:
1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is
recommended to ensure reliable operation.
2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is not needed,
this pin can be left floating in the system.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 14 - -Revision C
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q128JV
provides several means to protect the data from inadvertent writes.
6.2.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Registers
Additional Individual Block/Sector Locks for array protection
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special flow. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q128JV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP, SRL) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings allow
a portion or the entire memory array to be configured as read only. Used in conjunction with the Write
Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See
Status Register section for further information. Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q128JV also provides another Write Protect method using the Individual Block Locks. Each
64KB block (except the top and bottom blocks, total of 254 blocks) and each 4KB sector within the
top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is
0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or
Program commands issued to the corresponding sector or block will be ignored. When the device is
powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from
Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector
or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of
the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
W25Q128JV-DTR
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q128JV. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, output driver strength, and power-up. The Write Status Register
instruction can be used to configure the device write protection features, Quad SPI setting, Security
Register OTP locks, Hold/Reset functions, and output driver strength. Write access to the Status Register is
controlled by the state of the non-volatile Status Register Protect bits (SRP, SRL), the Write Enable
instruction, and during Standard/Dual SPI operations, the /WP pin.
7.1 Status Registers
SRP SEC TB BP2BP1BP0 WEL BUSY
TOP/BOTTOM PROTECT
WRITE ENABLE LATCH
S7 S6 S5 S4 S3 S2 S1 S0
SECTOR PROTECT
BLOCK PROTECT BITS
ERASE/WRITE IN PROGRESS
(Volatile/Non-Volatile Writable)
(Status-Only)
(Status-Only)
(Volatile/Non-Volatile Writable)
(Volatile/Non-Volatile Writable)
Figure 4a. Status Register-1
7.1.1 Erase/Write In Progress (BUSY) Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2 Write Enable Latch (WEL) Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
7.1.3 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 16 - -Revision C
7.1.4 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP, SRL and WEL bits.
7.1.5 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
7.1.6 Complement Protect (CMP) Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when
CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please
refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
W25Q128JV-DTR
7.1.7 Status Status Register Protect Protect (SRP, SRL)
The Status Register Protect bits (SRP) are non-volatile read/write bits in the status register (S7). The SRP
bit controls the method of write protection: software protection or hardware protection. The Status Register
Lock bits (SRL) are non-volatile/volatile read/write bits in the status register (S8). The SRL bit controls the
method of write protection: temporary lock-down or permanently one time program.
SRL
SRP
/WP
Status
Register
Description
0
0
X
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
1
0
Hardware
Protected
When /WP pin is low the Status Register locked and cannot be
written to.
0
1
1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1
X
X
Power Supply
Lock-Down
Status Register is protected and cannot be written to again until
the next power-down, power-up cycle.(1)
1
X
X
One Time
Program(2)
Status Register is permanently protected and cannot be written
to. (enabled by adding prefix command AAh, 55h)
Note:
1. When SRL =1, a power-down, power-up cycle will change SRL =0 state.
2. Please contact Winbond for details regarding the special instruction sequence
W25Q128JV-DTR
Publication Release Date: August 30, 2015
- 18 - Preliminary-Revision A3
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
SUS
CMP
LB
3
LB
2
LB
1
(
R
)
QE
SRL
Status Register Lock
(
Volatile
/
Non
-
Volatile Writable
)
Complement Protect
(
Volatile
/
Non
-
Volatile Writable
)
Security Register Lock Bits
(
Volatile
/
Non
-
Volatile OTP Writable
)
Reserved
Quad Enable
(
Volatile
/
Non
-
Volatile Writable
)
Suspend Status
(
Status
-
Only
)
Figure 4b. Status Register-2
7.1.8 Erase/Program Suspend Status (SUS) Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.9 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
7.1.10 Quad Enable (QE) Volatile/Non-Volatile Writable
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering
options “IM” & “JM”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default for
Quad Enabled part numbers with ordering option “IQ” & “JQ), the Quad IO2 and IO3 pins are enabled,
and /WP and /HOLD functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,
QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a
“1” to a “0”.
W25Q128JV-DTR
R
S23 S22 S21 S20 S19 S18 S17 S16
HOLD
/RST DRV 1 DRV0 WPS
Output Driver Strength
Write Protect Selection
/HOLD or /RESET Function
R
Reserved
Reserved
( Volatile/Non- Volatile Writable)
( Volatile/Non- Volatile Writable)
( Volatile/Non- Volatile Writable)
R( ) R( )
Reserved
Figure 4c. Status Register-3
7.1.11 Write Protect Selection (WPS) Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The
default value for all Individual Block Lock bits is 1 upon device power on or after reset.
7.1.12 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25% (default)
7.1.13 /HOLD or /RESET Pin Function (HOLD/RST) Volatile/Non-Volatile Writable
The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on
the hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when
HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when
QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data
I/O pin.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 20 - -Revision C
7.1.14 Reserved Bits Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
W25Q128JV-DTR
7.1.15 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1)
W25Q128JV (128M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
252 thru 255
FC0000h FFFFFFh
256KB
Upper 1/64
0
0
0
1
0
248 thru 255
F80000h FFFFFFh
512KB
Upper 1/32
0
0
0
1
1
240 thru 255
F00000h FFFFFFh
1MB
Upper 1/16
0
0
1
0
0
224 thru 255
E00000h FFFFFFh
2MB
Upper 1/8
0
0
1
0
1
192 thru 255
C00000h FFFFFFh
4MB
Upper 1/4
0
0
1
1
0
128 thru 255
800000h FFFFFFh
8MB
Upper 1/2
0
1
0
0
1
0 thru 3
000000h 03FFFFh
256KB
Lower 1/64
0
1
0
1
0
0 thru 7
000000h 07FFFFh
512KB
Lower 1/32
0
1
0
1
1
0 thru 15
000000h 0FFFFFh
1MB
Lower 1/16
0
1
1
0
0
0 thru 31
000000h 1FFFFFh
2MB
Lower 1/8
0
1
1
0
1
0 thru 63
000000h 3FFFFFh
4MB
Lower 1/4
0
1
1
1
0
0 thru 127
000000h 7FFFFFh
8MB
Lower 1/2
X
X
1
1
1
0 thru 255
000000h FFFFFFh
16MB
ALL
1
0
0
0
1
255
FFF000h FFFFFFh
4KB
U - 1/4096
1
0
0
1
0
255
FFE000h FFFFFFh
8KB
U - 1/2048
1
0
0
1
1
255
FFC000h FFFFFFh
16KB
U - 1/1024
1
0
1
0
X
255
FF8000h FFFFFFh
32KB
U - 1/512
1
1
0
0
1
0
000000h 000FFFh
4KB
L - 1/4096
1
1
0
1
0
0
000000h 001FFFh
8KB
L - 1/2048
1
1
0
1
1
0
000000h 003FFFh
16KB
L - 1/1024
1
1
1
0
X
0
000000h 007FFFh
32KB
L - 1/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 22 - -Revision C
7.1.16 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 1)
STATUS REGISTER(1)
W25Q128JV (128M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
0 thru 255
000000h - FFFFFFh
16MB
ALL
0
0
0
0
1
0 thru 251
000000h - FBFFFFh
16,128KB
Lower 63/64
0
0
0
1
0
0 thru 247
000000h F7FFFFh
15,872KB
Lower 31/32
0
0
0
1
1
0 thru 239
000000h - EFFFFFh
15MB
Lower 15/16
0
0
1
0
0
0 thru 223
000000h - DFFFFFh
14MB
Lower 7/8
0
0
1
0
1
0 thru 191
000000h - BFFFFFh
12MB
Lower 3/4
0
0
1
1
0
0 thru 127
000000h - 7FFFFFh
8MB
Lower 1/2
0
1
0
0
1
4 thru 255
040000h - FFFFFFh
16,128KB
Upper 63/64
0
1
0
1
0
8 thru 255
080000h - FFFFFFh
15,872KB
Upper 31/32
0
1
0
1
1
16 thru 255
100000h - FFFFFFh
15MB
Upper 15/16
0
1
1
0
0
32 thru 255
200000h - FFFFFFh
14MB
Upper 7/8
0
1
1
0
1
64 thru 255
400000h - FFFFFFh
12MB
Upper 3/4
0
1
1
1
0
128 thru 255
800000h - FFFFFFh
8MB
Upper 1/2
X
X
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 thru 255
000000h FFEFFFh
16,380KB
L - 4095/4096
1
0
0
1
0
0 thru 255
000000h FFDFFFh
16,376KB
L - 2047/2048
1
0
0
1
1
0 thru 255
000000h FFBFFFh
16,368KB
L - 1023/1024
1
0
1
0
X
0 thru 255
000000h FF7FFFh
16,352KB
L - 511/512
1
1
0
0
1
0 thru 255
001000h FFFFFFh
16,380KB
U - 4095/4096
1
1
0
1
0
0 thru 255
002000h FFFFFFh
16,376KB
U - 2047/2048
1
1
0
1
1
0 thru 255
004000h FFFFFFh
16,368KB
U -1023/1024
1
1
1
0
X
0 thru 255
008000h FFFFFFh
16,352KB
U - 511/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
W25Q128JV-DTR
7.1.17 W25Q128JV Individual Block Memory Protection (WPS=1)
Sector 0 (4KB)
Sector 1 (4KB)
Sector 14 (4KB)
Sector 15 (4KB)
Block 1 (64KB)
Block 254 (64KB)
Sector 0 (4KB)
Sector 1 (4KB)
Sector 14 (4KB)
Sector 15 (4KB)
Block 0
(64KB) Block 255
(64KB)
Individual Block Locks:
32 Sectors (Top/Bottom)
254 Blocks
Individual Block Lock:
36h + Address
Individual Block Unlock:
39h + Address
Read Block Lock:
3Dh + Address
Global Block Lock:
7Eh
Global Block Unlock:
98h
Figure 4d. Individual Block/Sector Locks
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 24 - -Revision C
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q128JV consists of 47 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
The QPI instruction set of the W25Q128JV consists of 36 basic instructions that are fully controlled
through the SPI bus (see Instruction Set Table 3). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all
four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI
instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with
every two serial clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5
through 57. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the memory is being programmed or erased, or when the Status Register is
being written, all instructions except for Read Status Register will be ignored until the program or erase
cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
Device ID
(ID7 - ID0)
(ID15 - ID0)
Instruction
ABh, 90h, 92h, 94h
9Fh
W25Q128JV
17h
7018h
W25Q128JV-DTR
8.1.2 Instruction Set Table 1 (Standard SPI Instructions)(1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Number of Clock(1-1-1)
8
8
8
8
8
8
8
Write Enable
06h
Volatile SR Write Enable
50h
Write Disable
04h
Release Power-down / ID
ABh
Dummy
Dummy
Dummy
(ID7-ID0)(2)
Manufacturer/Device ID
90h
Dummy
Dummy
00h
(MF7-MF0)
(ID7-ID0)
JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)
Read Unique ID
4Bh
Dummy
Dummy
Dummy
Dummy
(UID63-0)
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Page Program
02h
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0(3)
Sector Erase (4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase (32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase (64KB)
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/60h
Read Status Register-1
05h
(S7-S0)(2)
Write Status Register-1(4)
01h
(S7-S0)(4)
Read Status Register-2
35h
(S15-S8)(2)
Write Status Register-2
31h
(S15-S8)
Read Status Register-3
15h
(S23-S16)(2)
Write Status Register-3
11h
(S23-S16)
Read SFDP Register
5Ah
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Erase Security Register(5)
44h
A23-A16
A15-A8
A7-A0
Program Security Register(5)
42h
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0(3)
Read Security Register(5)
48h
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Global Block Lock
7Eh
Global Block Unlock
98h
Read Block Lock
3Dh
A23-A16
A15-A8
A7-A0
(L7-L0)
Individual Block Lock
36h
A23-A16
A15-A8
A7-A0
Individual Block Unlock
39h
A23-A16
A15-A8
A7-A0
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
B9h
Enter QPI Mode
38h
Enable Reset
66h
Reset Device
99h
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 26 - -Revision C
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Number of Clock(1-1-2)
8
8
8
8
4
4
4
4
4
Fast Read Dual Output
3Bh
A23-A16
A15-A8
A7-A0
Dummy
Dummy
(D7-D0)(7)
Number of Clock(1-2-2)
8
4
4
4
4
4
4
4
4
Fast Read Dual I/O
BBh
A23-A16(6)
A15-A8(6)
A7-A0(6)
M7-M0
(D7-D0)(7)
Mftr./Device ID Dual I/O
92h
A23-A16(6)
A15-A8(6)
00(6)
Dummy(14)
(MF7-MF0)
(ID7-ID0)(7)
Number of Clock(1-1-4)
8
8
8
8
2
2
2
2
2
Quad Input Page Program
32h
A23-A16
A15-A8
A7-A0
(D7-D0)(9)
(D7-D0)(3)
Fast Read Quad Output
6Bh
A23-A16
A15-A8
A7-A0
Dummy
Dummy
Dummy
Dummy
(D7-D0)(10)
Number of Clock(1-4-4)
8
2(8)
2(8)
2(8)
2
2
2
2
2
Mftr./Device ID Quad I/O
94h
A23-A16
A15-A8
00
Dummy(14)
Dummy
Dummy
(MF7-MF0)
(ID7-ID0)
Fast Read Quad I/O
EBh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
Dummy
(D7-D0)
Set Burst with Wrap
77h
Dummy
Dummy
Dummy
W7-W0
W25Q128JV-DTR
8.1.4 Instruction Set Table 3 (QPI Instructions)(11)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Number of Clock (4-4-4)
2
2
2
2
2
2
2
Write Enable
06h
Volatile SR Write Enable
50h
Write Disable
04h
Release Power-down / ID
ABh
Dummy
Dummy
Dummy
(ID7-ID0)(2)
Manufacturer/Device ID
90h
Dummy
Dummy
00h
(MF7-MF0)
(ID7-ID0)
JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)
Set Read Parameters
C0h
P7-P0
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
Dummy(12)
(D7-D0)
Burst Read with Wrap(13)
0Ch
A23-A16
A15-A8
A7-A0
Dummy(12)
(D7-D0)
Fast Read Quad I/O
EBh
A23-A16
A15-A8
A7-A0
M7-M0(12)
(D7-D0)
Page Program
02h
A23-A16
A15-A8
A7-A0
D7-D0(9)
D7-D0(3)
Sector Erase (4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase (32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase (64KB)
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/60h
Read Status Register-1
05h
(S7-S0)(2)
Write Status Register-1(4)
01h
(S7-S0)(4)
Read Status Register-2
35h
(S15-S8)(2)
Write Status Register-2
31h
(S15-S8)
Read Status Register-3
15h
(S23-S16)(2)
Write Status Register-3
11h
(S23-S16)
Global Block Lock
7Eh
Global Block Unlock
98h
Read Block Lock
3Dh
A23-A16
A15-A8
A7-A0
(L7-L0)
Individual Block Lock
36h
A23-A16
A15-A8
A7-A0
Individual Block Unlock
39h
A23-A16
A15-A8
A7-A0
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
B9h
Enable Reset
66h
Reset Device
99h
Exit QPI Mode
FFh
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 28 - -Revision C
8.1.5 Instruction Set Table 4 (DTR with SPI Instructions)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Number of Clock(1-1-1)
8
4
4
4
6
4
4
DTR Fast Read
0Dh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Number of Clock(1-2-2)
8
2
2
2
6
2
2
DTR Fast Read Dual I/O
BDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
.
Number of Clock(1-4-4)
8
1
1
1
8
1
1
DTR Fast Read Quad
EDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
.
8.1.6 Instruction Set Table 5 (DTR with QPI Instructions)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Number of Clock (4-4-4)
2
1
1
1
8
1
1
DTR Read with Wrap(13)
0Eh
A23-A16
A15-A8
A7-0
Dummy
(D7-D0)
DTR Fast Read
0Dh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
DTR Fast Read
EDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
W25Q128JV-DTR
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format: Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. QPI Command, Address, Data input/output format:
CLK # 0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
12. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is
controlled by read parameter P7 P4.
13. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 P0.
14. The first dummy is M7-M0 should be set to Fxh
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 30 - -Revision C
8.2 Instruction Descriptions
8.2.1 Write Enable (06h)
The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Mode 0
Mode 3
Instruction (06h)
High Impedance
/CS
CLK Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO0
IO1
IO2
IO3
06h
Instruction
Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)
8.2.2 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable
for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only
valid for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Mode 0
Mode 3
Instruction (50h)
High Impedance
/CS
CLK Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO0
IO1
IO2
IO3
50h
Instruction
Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)
W25Q128JV-DTR
8.2.3 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Mode 0
Mode 3
Instruction (04h)
High Impedance
/CS
CLK Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO0
IO1
IO2
IO3
04h
Instruction
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 32 - -Revision C
8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code 05h” for Status Register-1, “35h” for Status
Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits
are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown
in Figure 8. Refer to section 7.1 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (05h/35h/15h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
76543210765432107
Status Register-1/2/3 out Status Register-1/2/3 out
* *
= MSB
*
Figure 8a. Read Status Register Instruction (SPI Mode)
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
05h/35h/15h
2345
4040
5 1
6 2
7 3
5 1
6 2
7 3
4
5
6
7
SR-1/2/3
out SR-1/2/3
out
Instruction
Figure 8b. Read Status Register Instruction (QPI Mode)
W25Q128JV-DTR
8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRL in Status
Register-2; HOLD/RST, DRV1, DRV0, and WPS in Status Register-3. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-
volatile OTP bits, once it is set to 1, it cannot be cleared to 0.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRL and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these
bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values
will be lost, and the non-volatile Status Register bit values will be restored.
During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status
Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the
Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter
and operate in the QPI mode.refer to section 7.1 for Status Register descriptions.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction
(01h/31h/11h)
High Impedance
8 9 10 11 12 13 14 15
76543210
Register-1/2/3 in
Mode 0
Mode 3
*
= MSB
*
Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 34 - -Revision C
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
01/31/11h
2 3
4 0
5 1
6 2
7 3
SR1/2/3
in
Mode 0
Mode 3
Instruction
Figure 9b. Write Status Register-1/2/3 Instruction (QPI Mode)
The W25Q128JV is also backward compatible to Winbond’s previous generations of serial flash
memories, in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)”
command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after
the sixteenth bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after the eighth
clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status
Register-2 will not be affected (Previous generations will clear CMP and QE bits).
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (01h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7654321015 14 13 12 11 10 9 8
Status Register 1 in Status Register 2 in
Mode 0
Mode 3
* *
= MSB
*
Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
01h
2 3 4 5
4 0 12 8
5 1
6 2
7 3
13 9
14 10
15 11
SR1 in SR2 in
Mode 0
Mode 3
Instruction
Figure 9d. Write Status Register-1/2 Instruction (QPI Mode)
W25Q128JV-DTR
8.2.6 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as
the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR
(see AC Electrical Characteristics).
The Read Data (03h) instruction is only supported in Standard SPI mode.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (03h)
High Impedance
8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
765432107
24-Bit Address
23 22 21 3 2 1 0
Data Out 1
*
*
= MSB
*
Figure 14. Read Data Instruction (SPI Mode only)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 36 - -Revision C
8.2.7 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DO pin is a “don’t care”.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (0Bh)
High Impedance
8 9 10 28 29 30 31
24-Bit Address
23 22 21 3 2 1 0
Data Out 1
*
/CS
CLK
DI
(IO0)
DO
(IO1)
32 33 34 35 36 37 38 39
Dummy Clocks
High Impedance
40 41 42 44 45 46 47 48 49 50 51 52 53 54 55
765432107
Data Out 2
*
76543210
*
4331
0
= MSB
*
Figure 16a. Fast Read Instruction (SPI Mode)
W25Q128JV-DTR
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide
range of applications with different needs for either maximum Fast Read frequency or minimum data
access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can
be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset
instruction is 2.
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
0Bh
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0 Dummy*
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13
4
5
6
7
IOs switch from
Input to Output
* "Set Read Parameters" instruction (C0h) can set
the number of dummy clocks.
Instruction
Figure 16b. Fast Read Instruction (QPI Mode)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 38 - -Revision C
8.2.8 DTR Fast Read (0Dh)
The DTR Fast Read instruction is similar to the Fast Read instruction except that the 24-bit address input
and the data output require DTR (Double Transfer Rate) operation. This is accomplished by adding six
“dummy” clocks after the 24-bit address as shown in Figure 17. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DO pin is a “don’t care”.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (0Dh)
High Impedance
8 9 10 17 18 19
24-Bit Address
Data Out 1
*
/CS
CLK
DI
(IO0)
DO
(IO1)
20 21 22 23 24 25 26 27
6 Dummy Clocks
High Impedance
28 29 30 32 33 34 35 36 37 383119
= MSB
*
23 22 21 20 19 18 5 4 3 2 1 0
0
*
D
7D
6D
5D
4D
3D
2D
1D
0
Data Out 2
*
D
7D
6D
5D
4D
3D
2D
1D
0
Data Out 3
*
D
7D
6D
5D
4D
3D
2D
1D
0D
7
Figure 17a. DTR Fast Read Instruction (SPI Mode)
W25Q128JV-DTR
DTR Fast Read (0Dh) in QPI Mode
The DTR Fast Read instruction is also supported in QPI mode.
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
0Dh
2 3
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
4
4 0
5 1
6 2
7 3
A15-8 A7-0
Instruction
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4
5
6
7
IOs switch from
Input to Output
Byte 3
5 11 13 14
8 Dummy
Clocks
12
***
*
= MSB
*
Figure 17b. DTR Fast Read Instruction (QPI Mode)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 40 - -Revision C
8.2.9 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to
RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (3Bh)
High Impedance
8 9 10 28 29 30
32 33 34 35 36 37 38 39
6420
24-Bit Address
23 22 21 3 2 1 0
*
*
31
31
/CS
CLK
DI
(IO0)
DO
(IO1)
Dummy Clocks
0
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
7531
High Impedance
6 4 2 0
7 5 3 1
6420
7531
6420
7531
IO0 switches from
Input to Output
6
7
Data Out 1 *Data Out 2 *Data Out 3 *Data Out 4
= MSB
*
Figure 18. Fast Read Dual Output Instruction (SPI Mode only)
W25Q128JV-DTR
8.2.10 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast
Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummyclocks after the 24-bit address
as shown in Figure 20. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
CLK Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (6Bh)
High Impedance
8 9 10 28 29 30
32 33 34 35 36 37 38 39
4 0
24-Bit Address
23 22 21 3 2 1 0
*
31
31
/CS
CLK
Dummy Clocks
0
40 41 42 43 44 45 46 47
5 1
High Impedance
4
5
Byte 1
High Impedance
High Impedance
6 2
7 3
High Impedance
6
7
High Impedance
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Byte 2 Byte 3 Byte 4
IO0 switches from
Input to Output
IO0
IO1
IO2
IO3
IO0
IO1
IO2
IO3
= MSB
*
Figure 20. Fast Read Quad Output Instruction (SPI Mode only)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 42 - -Revision C
8.2.11 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 22a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 22b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return
the device to normal operation.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (BBh)
8 9 10 12 13 14
24 25 26 27 28 29 30 31
6 4 2 0
*
*
23
/CS
CLK
DI
(IO0)
DO
(IO1)
0
32 33 34 35 36 37 38 39
7 5 3 1
*
6420
7531
6420
7531
6 4 2 0
7 5 3 1
* *
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6420
7531
6 4 2 0
7 5 3 1
11 15 16 17 18 20 21 2219 23
1
A23-16 A15-8 A7-0 M7-0
Byte 1 Byte 2 Byte 3 Byte 4
= MSB
**
Figure 22a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)
W25Q128JV-DTR
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 8 9 10 12 13 14
24 25 26 27 28 29 30 31
6 4 2 0
*
*
15
/CS
CLK
DI
(IO0)
DO
(IO1)
0
7 5 3 1
*
6 4 2 0
7 5 3 1
6420
7531
6 4 2 0
7 5 3 1
* *
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
11 15
1
A23-16 A15-8 A7-0 M7-0
Byte 1 Byte 2 Byte 3 Byte 4
01234567
16 17 18 20 21 2219 23
*
= MSB
*
Figure 22b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 44 - -Revision C
8.2.12 DTR Fast Read Dual I/O (BDh)
The DTR Fast Read Dual I/O (BDh) instruction allows for improved random access while maintaining two
IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
DTR Fast Read Dual I/O with “Continuous Read Mode”
The DTR Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 23a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 23b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh/FFFFFh on IO0 for the next instruction (16/20 clocks), to ensure M4 = 1
and return the device to normal operation.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (BDh)
8 9 10
6420
*
*
15
/CS
CLK
DI
(IO0)
DO
(IO1)
0
7531
*
6420
7531
6420
7531
6420
7531
* *
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6420
7531
6420
7531
11 12 13 14 15
1
A23-16 A15-8 A7-0 M7-0
Byte 1 Byte 2 Byte 3 Byte 4
= MSB
**
16 17 18 19 20 21 22 23 24 25 26 27
Figure 23a. DTR Fast Read Dual I/O (Initial instruction or previous M5-410, SPI Mode only)
W25Q128JV-DTR
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2
6420
*
*
7
/CS
CLK
DI
(IO0)
DO
(IO1)
0
7531
*
6420
7531
6420
7531
6420
7531
* *
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6420
7531
6420
7531
34567
1
A23-16 A15-8 A7-0 M7-0
Byte 1 Byte 2 Byte 3 Byte 4
= MSB
**
8 9 10 11 12 13 14 15 16 17 18 19
Figure 23b. DTR Fast Read Dual I/O (Previous instruction set M5-4=10, SPI Mode only)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 46 - -Revision C
8.2.13 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 24a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
Figure 24a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode)
M7-0
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15 16 17 18 19 20 21 22 23
Dummy Dummy
Instruction (EBh)
W25Q128JV-DTR
M7-0
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15
Dummy Dummy
Figure 24b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. Refer to section 8.2.37 for detail descriptions.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 48 - -Revision C
8.2.14 DTR Fast Read Quad I/O (EDh)
The DTR Fast Read Quad I/O (EDh) instruction is similar to the Fast Read Dual I/O (BBh) instruction
except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four
Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
DTR Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23/A31-0), as shown in Figure 27a.
The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 27b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh/3FFh on IO0 for the next instruction (8/10 clocks), to
ensure M4 = 1 and return the device to normal operation.
Figure 27a. DTR Fast Read Quad I/O (Initial instruction or previous M5-410, SPI Mode)
M7-0
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
9 10 11
4
5
6
7
IOs switch from
Input to Output
Byte 3
12 17 19 20
7 Dummy
Clocks
Instruction (EDh)
18
***
= MSB
** *
W25Q128JV-DTR
M7-0
/CS
CLK Mode 0
Mode 3
IO0
IO1
IO2
IO3
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
0
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
123
4
5
6
7
IOs switch from
Input to Output
Byte 3
11 12
7 Dummy
Clocks
* * *
= MSB
** *
4 10
Figure 27b. Fast Read Quad I/O (Previous instruction set M5-4=10, SPI Mode)
DTR Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EDh. The Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following EDh commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. Refer to section 8.2.37 for detail descriptions.
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 50 - -Revision C
DTR Fast Read Quad I/O (EDh) in QPI Mode
The DTR Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. In QPI
mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting,
the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Aroundfeature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap (0Ch)
instruction must be used. Please refer to 8.3.37 for details.
Figure 27c. DTR Fast Read Quad I/O (Initial instruction or previous M5-410, QPI Mode)
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
EDh
2 3
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
4
4 0
5 1
6 2
7 3
A15-8 A7-0
Instruction M7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
5
4
5
6
7
IOs switch from
Input to Output
Byte 3
6 11 13 14
7 Dummy
Clocks
12
* * * *
*
= MSB
*
W25Q128JV-DTR
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 24c. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)”
instruction to accommodate a wide range of applications with different needs for either maximum Fast
Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy
clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-
0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous
Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Aroundfeature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap (0Ch)
instruction must be used. Please refer to 8.2.37 for details.
Figure 24c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode)
M7-0*
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
EBh
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
* "Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Byte 3
Instruction
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 52 - -Revision C
8.2.15 Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read
Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used.
W6, W5
W4 = 0
W4 =1 (DEFAULT)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0 0
Yes
8-byte
No
N/A
0 1
Yes
16-byte
No
N/A
1 0
Yes
32-byte
No
N/A
1 1
Yes
64-byte
No
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” instructions
will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around”
function and return to normal read operation, another Set Burst with Wrap instruction should be issued to
set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation
with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode
and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 8.2.37 and 8.8.2.38
for details.
Wrap Bit
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
2 3 4 5
X X
X X
X X
X X
don't
care
6 7 8 9
don't
care don't
care
10 11 12 13 14 15
Instruction (77h)
Mode 0
Mode 3
X X
X X
X X
X X
X X
X X
X X
X X
w4 X
w5 X
w6 X
X X
Figure 28. Set Burst with Wrap Instruction (SPI Mode only)
W25Q128JV-DTR
8.2.16 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code 02h” followed by a 24-bit address (A23-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 29.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks cannot exceed the remaining
page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI
(IO0)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (02h)
8 9 10 28 29 30 39
24-Bit Address
23 22 21 3 2 1
*
/CS
CLK
DI
(IO0)
40 41 42 43 44 45 46 47
Data Byte 2
48 49 50 52 53 54 55
2072
7 6 5 4 3 2 1 0
5139
0
31
0
32 33 34 35 36 37 38
Data Byte 1
7654321
*
Mode 0
Mode 3
Data Byte 3
2073
2074
2075
2076
2077
2078
2079
0
Data Byte 256
*
76543210
*
76543210
*
= MSB
*
Figure 29a. Page Program Instruction (SPI Mode)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 54 - -Revision C
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
02h
Instruction
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0 Byte1 Byte 2 Byte 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13
Byte 255 Byte 256
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Mode 0
Mode 3
516
517
518
519
Figure 29b. Page Program Instruction (QPI Mode)
W25Q128JV-DTR
8.2.17 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since
the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write
Enable instruction must be executed before the device will accept the Quad Page Program instruction
(Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the
instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins.
The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.
All other functions of Quad Page Program are identical to standard Page Program. The Quad Page
Program instruction sequence is shown in Figure 30.
/CS
CLK Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (32h)
8 9 10 28 29 30
32 33 34 35 36 37
4 0
24-Bit Address
23 22 21 3 2 1 0
*
31
31
/CS
CLK
5 1
Byte 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Byte 2 Byte 3 Byte
256
0 4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
536
537
538
539
540
541
542
543
Mode 0
Mode 3
Byte
253 Byte
254 Byte
255
IO0
IO1
IO2
IO3
IO0
IO1
IO2
IO3
* * * * * * *
= MSB
*
Figure 30. Quad Input Page Program Instruction (SPI Mode only)
W25Q128JV-DTR
Publication Release Date: March 27, 2018
- 56 - -Revision C
8.2.18 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase
instruction sequence is shown in Figure 31a & 31b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI
(IO0)
DO
(IO1)
Mode 0
Mode 3 0 1 2 3 4 5 6 7
Instruction (20h)
High Impedance
8 9 29 30 31
24-Bit Address
23 22 210
*
Mode 0
Mode 3
= MSB
*
Figure 31a. Sector Erase Instruction (SPI Mode)
/CS
CLK Mode 0
Mode 3 0 1
IO0
IO1
IO2
IO3
20h
Instruction
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7
4 0
5 1
6 2
7 3
A15-8 A7-0
Mode 0
Mode 3
Figure 31b. Sector Erase Instruction (QPI Mode)
W25Q128JV-DTR
8.2.19 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 32a & 32b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished