STM32F405xx, STM32F407xx Datasheet

STMicroelectronics

View All Related Products | Download PDF Datasheet

Datasheet

This is information on a product in full production.
September 2016 DocID022152 Rev 8 1/202
STM32F405xx
STM32F407xx
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Datasheet - production data
Features
Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 168 MHz,
memory protection unit, 210 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
Up to 1 Mbyte of Flash memory
Up to 192+4 Kbytes of SRAM including 64-
Kbyte of CCM (core coupled memory) data
RAM
Flexible static memory controller supporting
Compact Flash, SRAM, PSRAM, NOR and
NAND memories
LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
1.8 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low-power operation
Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
3×12-bit, 2.4 MSPS A/D converters: up to 24
channels and 7.2 MSPS in triple interleaved
mode
2×12-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 168 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
Debug mode
Serial wire debug (SWD) & JTAG
interfaces
Cortex-M4 Embedded Trace Macrocell™
Up to 140 I/O ports with interrupt capability
Up to 136 fast I/Os up to 84 MHz
Up to 138 5 V-tolerant I/Os
Up to 15 communication interfaces
Up to 3 × I2C interfaces (SMBus/PMBus)
Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO
7816 interface, LIN, IrDA, modem control)
Up to 3 SPIs (42 Mbits/s), 2 with muxed
full-duplex I2S to achieve audio class
accuracy via internal audio PLL or external
clock
2 × CAN interfaces (2.0B Active)
SDIO interface
Advanced connectivity
USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
UFBGA176
(10 × 10 mm)
LQFP176 (24 × 24 mm)
WLCSP90
(4.223x3.969 mm)
&"'!
www.st.com
STM32F405xx, STM32F407xx
2/202 DocID022152 Rev 8
8- to 14-bit parallel camera interface up to
54 Mbytes/s
True random number generator
CRC calculation unit
96-bit unique ID
RTC: subsecond accuracy, hardware calendar
Table 1. Device summary
Reference Part number
STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE
STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG,
STM32F407VE, STM32F407ZE, STM32F407IE
DocID022152 Rev 8 3/202
STM32F405xx, STM32F407xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM . . 20
2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 20
2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 21
2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23
2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29
2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 29
2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 34
2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 36
2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 36
2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Contents STM32F405xx, STM32F407xx
4/202 DocID022152 Rev 8
2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 37
2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 38
2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 82
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 82
5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 83
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 106
DocID022152 Rev 8 5/202
STM32F405xx, STM32F407xx Contents
5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 112
5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.20 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 161
5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 162
5.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.1 WLCSP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3 LQPF100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.5 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.6 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 186
A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 188
A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
List of tables STM32F405xx, STM32F407xx
6/202 DocID022152 Rev 8
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 14
Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7. STM32F40xxx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 10. register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 81
Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 82
Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 82
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 20. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 85
Table 21. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 90
Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 91
Table 26. Typical current consumption in Run mode, code with data processing
running from Flash memory, regulator ON (ART accelerator enabled
except prefetch), VDD = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 27. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 28. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 29. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 30. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 31. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 32. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 34. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 36. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 37. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 38. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 39. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 40. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 41. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 42. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 43. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 44. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DocID022152 Rev 8 7/202
STM32F405xx, STM32F407xx List of tables
Table 45. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 46. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 47. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 48. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 49. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 50. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 51. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 52. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 53. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 54. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 55. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 57. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 58. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 59. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 64. Dynamic characteristics: Eternity MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 66. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 70. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 71. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 72. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 74. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 143
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 144
Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 78. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 80. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 83. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 84. Switching characteristics for PC Card/CF read and write cycles
in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 85. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 86. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 88. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 89. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 91. WLCSP90 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
List of tables STM32F405xx, STM32F407xx
8/202 DocID022152 Rev 8
Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 95. UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch
ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . . 178
Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 98. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 99. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
DocID022152 Rev 8 9/202
STM32F405xx, STM32F407xx List of figures
List of figures
Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64 . . . . . . . . . . 16
Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Compatible board design between STM32F2 and STM32F40xxx
for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. STM32F40xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25
Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Startup in regulator OFF mode: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. STM32F40xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. STM32F40xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. STM32F40xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. STM32F40xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. STM32F40xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. STM32F40xxx WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 18. STM32F40xxx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 24. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 87
Figure 25. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 87
Figure 26. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 88
Figure 27. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 88
Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 91
Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 92
Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 39. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
List of figures STM32F405xx, STM32F407xx
10/202 DocID022152 Rev 8
Figure 40. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 41. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 42. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 43. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 44. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 129
Figure 45. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 46. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 47. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 48. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 49. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 50. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 137
Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 138
Figure 53. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 143
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 144
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 58. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 59. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 61. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 62. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 153
Figure 63. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 154
Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 156
Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 157
Figure 68. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 69. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 70. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 160
Figure 71. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 160
Figure 72. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 73. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 74. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 75. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 76. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 77. WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 78. LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 167
Figure 79. LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 80. LPQF64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 170
Figure 82. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 83. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 84. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 173
Figure 85. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
DocID022152 Rev 8 11/202
STM32F405xx, STM32F407xx List of figures
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 86. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 87. UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 88. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 89. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . . 180
Figure 91. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 182
Figure 92. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 93. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 94. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 186
Figure 95. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 187
Figure 96. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 97. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 98. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 99. RMII with a 25 MHz crystal and PHY with PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Introduction STM32F405xx, STM32F407xx
12/202 DocID022152 Rev 8
1 Introduction
This datasheet provides the description of the STM32F405xx and STM32F407xx lines of
microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the
STM32F4xx reference manual which is available from the STMicroelectronics website
www.st.com.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214) available from www.st.com.
DocID022152 Rev 8 13/202
STM32F405xx, STM32F407xx Description
2 Description
The STM32F405xx and STM32F407xx family is based on the high-performance ARM®
Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4
core features a Floating point unit (FPU) single precision which supports all ARM single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances application security.
The STM32F405xx and STM32F407xx family incorporates high-speed embedded
memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of
backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
a true random number generator (RNG). They also feature standard and advanced
communication interfaces.
Up to three I2Cs
Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals
can be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Four USARTs plus two UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
Two CANs
An SDIO/MMC interface
Ethernet and the camera interface available on STM32F407xx devices only.
New advanced peripherals include an SDIO, an enhanced flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more), a camera
interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features
and peripheral counts for the list of peripherals available on each part number.
The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature
range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the
device operates in the 0 to 70 °C temperature range using an external power supply
supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F405xx and STM32F407xx family offers devices in various packages ranging
from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.
These features make the STM32F405xx and STM32F407xx microcontroller family suitable
for a wide range of applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
STM32F405xx, STM32F407xx Description
DocID022152 Rev 8 14/202
Figure 5 shows the general block diagram of the device family.
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts
Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix
Flash memory in
Kbytes 1024 512 512 1024 512 1024 512 1024
SRAM in
Kbytes
System 192(112+16+64)
Backup 4
FSMC memory
controller No Yes(1)
Ethernet No Yes
Timers
General-
purpose 10
Advanced
-control 2
Basic 2
IWDG Yes
WWDG Yes
RTC Yes
Random number
generator Yes
Description STM32F405xx, STM32F407xx
15/202 DocID022152 Rev 8
Communi
cation
interfaces
SPI / I2S 3/2 (full duplex)(2)
I2C 3
USART/
UART 4/2
USB
OTG FS Yes
USB
OTG HS Yes
CAN 2
SDIO Yes
Camera interface No Yes
GPIOs 51 72 82 114 72 82 114 140
12-bit ADC
Number of channels
3
16 13 16 24 13 16 24 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU
frequency 168 MHz
Operating voltage 1.8 to 3.6 V(3)
Operating
temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144 UFBGA176
LQFP176
1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip
Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this
package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF).
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)
Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix
Description STM32F405xx, STM32F407xx
16/202 DocID022152 Rev 8
2.1 Full compatibility throughout the family
The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin-
to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to
try different memory densities, peripherals, and performances (FPU, higher frequency) for a
greater degree of freedom during the development cycle.
The STM32F405xx and STM32F407xx devices maintain a close compatibility with the
whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The
STM32F405xx and STM32F407xx, however, are not drop-in replacements for the
STM32F10xxx devices: the two families do not have the same power scheme, and so their
power pins are different. Nonetheless, transition from the STM32F10xxx to the
STM32F40xxx family remains simple as only a few pins are impacted.
Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the
STM32F40xxx, STM32F2, and STM32F10xxx families.
Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64






 
633
633
633
633
7RESISTORORSOLDERINGBRIDGE
PRESENTFORTHE34-&XX
CONFIGURATIONNOTPRESENTINTHE
34-&XXCONFIGURATION
AI
DocID022152 Rev 8 17/202
STM32F405xx, STM32F407xx Description
Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx
for LQFP100 package
Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx
for LQFP144 package
DLG







 

966
966
9''
966
966
966
UHVLVWRURUVROGHULQJEULGJH
SUHVHQWIRUWKH670)[[[
FRQILJXUDWLRQQRWSUHVHQWLQWKH
670)[[FRQILJXUDWLRQ
966
966
7ZRUHVLVWRUVFRQQHFWHGWR
966IRUWKH670)[[
966IRUWKH670)[[
966RU1&IRUWKH670)[[
966IRU670)[[
9''IRU670)[[
DLG








966
UHVLVWRURUVROGHULQJEULGJH
SUHVHQWIRUWKH670)[[
FRQILJXUDWLRQQRWSUHVHQWLQWKH
670)[[FRQILJXUDWLRQ

966

7ZRUHVLVWRUVFRQQHFWHGWR
966IRUWKH670)[[
9669''RU1&IRUWKH670)[[
9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[
966
9''
966
966
3'5B21
966
9''
966IRU670)[[
9''IRU670)[[
6LJQDOIURP
H[WHUQDOSRZHU
VXSSO\
VXSHUYLVRU
1RWSRSXODWHGZKHQ
UHVLVWRURUVROGHULQJ
EULGJHSUHVHQW
1RWSRSXODWHGIRU670)[[
Description STM32F405xx, STM32F407xx
18/202 DocID022152 Rev 8
Figure 4. Compatible board design between STM32F2 and STM32F40xxx
for LQFP176 and BGA176 packages
069






7ZRUHVLVWRUVFRQQHFWHGWR
9669''RU1&IRUWKH670)[[
9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[
3'5B21
966
9''
6LJQDOIURPH[WHUQDO
SRZHUVXSSO\
VXSHUYLVRU
DocID022152 Rev 8 19/202
STM32F405xx, STM32F407xx Description
2.2 Device overview
Figure 5. STM32F40xxx block diagram
1. The camera interface and ethernet are available only on STM32F407xx devices.
069
*3,23257$
$+%$3%
$)
3$>@
7,03:0
FRPSOFKDQQHOV7,0B&+>@1
FKDQQHOV7,0B&+>@(75
%.,1DV$)
5;7;&.
&76576DV$)
026,0,62
6&.166DV$)
$3% 0+]
DQDORJLQSXWVFRPPRQ
WRWKH$'&V
9''5()B$'&
026,6'0,626'BH[W6&.&.
166:60&.DV$)
7;5;
'$&B287
DV$)
,7)
::'*
.%%.365$0
57&B$)
26&B,1
26&B287
9''$966$
1567
E
6',200&
'>@
&0'&.DV$)
9%$7 WR9
'0$
6&/6'$60%$DV$)
-7$*6:
$50&RUWH[0
0+]
19,&
(70
038
75$&(&/.
75$&('>@
(WKHUQHW0$&

'0$
),)2
0,,RU50,,DV$)
0',2DV$)
86%
27*+6
'3'0
8/3,&.'>@',56731;7
,'9%8662)
'0$
6WUHDPV
),)2
$57$&&(/
&$&+(
65$0.%
&/.1(>@$>@
'>@2(1:(1
1%/>@1/15(*
1:$,7,25'<&'
,1711,,6DV$)
51*
&DPHUD
LQWHUIDFH
+6<1&96<1&
38,;&/.'>@
3+<
86%
27*)6
'3
'0
,'9%8662)
),)2
$+%0+]
3+<
),)2
#9
''$
#9
''$
3253'5
%25
6XSSO\
VXSHUYLVLRQ
#9
''$
39'
,QW
325
UHVHW
;7$/N+]
0$1 $*7
57&
5& +6
)&/.
5& / 6
3:5
LQWHUIDFH
,:'*
#9
%$7
$:8
5HVHW
FORFN
FRQWURO
3 / /
3&/.[
9'' WR9
966
9&$39&3$
9ROWDJH
UHJXODWRU
WR9
9'' 3RZHUPDQDJPW
57&B$)
%DFNXSUHJLVWHU
$+%EXVPDWUL[60
/6
FKDQQHOVDV$)
'$&
'$&
)ODVK
XSWR
0%
65$0365$0125)ODVK
3&&DUG$7$1$1')ODVK
([WHUQDOPHPRU\
FRQWUROOHU)60&
7,0
7,0
7,0
7,0
7,0
7,0
7,0
7,0
7,0
86$57
86$57
8$57
8$57
63,6
,&60%86
,&60%86
,&60%86
E[&$1
E[&$1
63,
(;7,7:.83
'%86
),)2
)38
$3%0+]PD[
65$0.%
&&0GDWD5$0.%
$+%
$+%0+]
1-7567-7',
-7&.6:&/.
-7'26:'-7'2
,%86
6%86
'0$
),)2
'0$
6WUHDPV
),)2
3%>@
3&>@
3'>@
3(>@
3)>@
3*>@
3+>@
3,>@
*3,23257%
*3,23257&
*3,23257'
*3,23257(
*3,23257)
*3,23257*
*3,23257+
*3,23257,
7,03:0 E
FRPSOFKDQQHOV7,0B&+>@1
FKDQQHOV7,0B&+>@(75
%.,1DV$)
FKDQQHODV$)
FKDQQHODV$)
5;7;&.
&76576DV$)
DQDORJLQSXWVFRPPRQ
WRWKH$'&
DQDORJLQSXWVIRU$'&
'$&B287
DV$)
E
E
6&/6'$60%$DV$)
6&/6'$60%$DV$)
026,6'0,626'BH[W6&.&.
166:60&.DV$)
7;5;
5;7;DV$)
5;7;DV$)
5;7;DV$)
&76576DV$)
5;7;DV$)
&76576DV$)
FKDQQHODV$)
VPFDUG
LU'$
VPFDUG
LU'$
E
E
E
FKDQQHODV$)
FKDQQHOVDV$)
E
E
E
E
FKDQQHOV
FKDQQHOV(75DV$)
FKDQQHOV(75DV$)
FKDQQHOV(75DV$)
'0$
$+%$3%
/6
26&B,1
26&B287
+&/.[
;7$/26&
0+]
),)2
63,6
1,25',2:5,17>@
$'&
$'&
$'&
7HPSHUDWXUHVHQVRU
,)
7,0 E
7,0 E
7,0E
VPFDUG
LU'$ 86$57
LU'$ 86$57
VPFDUG
$3%0+]
#9
''
#9
''
#9
''$
Description STM32F405xx, STM32F407xx
20/202 DocID022152 Rev 8
2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM
The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software.
Figure 5 shows the general block diagram of the STM32F40xxx family.
Note: Cortex-M4 with FPU is binary compatible with Cortex-M3.
2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the ARM Cortex-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 210 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 168 MHz.
2.2.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
2.2.4 Embedded Flash memory
The STM32F40xxx devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for
storing programs and data.
DocID022152 Rev 8 21/202
STM32F405xx, STM32F407xx Description
2.2.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.2.6 Embedded SRAM
All STM32F40xxx products embed:
Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.2.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Description STM32F405xx, STM32F407xx
22/202 DocID022152 Rev 8
Figure 6. Multi-AHB matrix
2.2.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC.
!2-
#ORTEX-
'0
$-!
'0
$-!
-!#
%THERNET
53"/4'
(3
"USMATRIX3
)#/$%
$#/$%
!##%,
&LASH
MEMORY
32!-
+BYTE
32!-
+BYTE
!("
PERIPHERALS
!("
&3-#
3TATIC-EM#TL
)BUS
$BUS
3BUS
$-!?0)
$-!?-%-
$-!?-%-
$-!?0
%4(%2.%4?-
53"?(3?-
AID
##-DATA2!-
+BYTE
!0"
!0"
PERIPHERALS
DocID022152 Rev 8 23/202
STM32F405xx, STM32F407xx Description
2.2.9 Flexible static memory controller (FSMC)
The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip
Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM,
NOR Flash and NAND Flash.
Functionality overview:
Write FIFO
Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
2.2.10 Nested vectored interrupt controller (NVIC)
The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to
manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16
interrupt lines of the Cortex®-M4 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.2.11 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
2.2.12 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL
Description STM32F405xx, STM32F407xx
24/202 DocID022152 Rev 8
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
buses is 168 MHz while the maximum frequency of the high-speed APB domains is
84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.2.13 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
2.2.14 Power supply schemes
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 21: Power supply scheme for more details.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced
temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF).
Refer to Table 2 in order to identify the packages supporting this option.
2.2.15 Power supply supervisor
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On all other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
threshold levels, or to disable BOR permanently. Three BOR thresholds are available
through option bytes. The device remains in reset mode when VDD is below a specified
threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.
DocID022152 Rev 8 25/202
STM32F405xx, STM32F407xx Description
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
this external power supply supervisor. Refer to Figure 7: Power supply supervisor
interconnection with internal reset OFF.
Figure 7. Power supply supervisor interconnection with internal reset OFF
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
The VDD specified threshold, below which the device must be maintained under reset, is
1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the
0 to 70 °C temperature range.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry is disabled
The embedded programmable voltage detector (PVD) is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD
All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset
through the PDR_ON signal.
069
1567
9''
3'5B21
([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYHZKHQ
9''9
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
Description STM32F405xx, STM32F407xx
26/202 DocID022152 Rev 8
Figure 8. PDR_ON and NRST control with internal reset OFF
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
2.2.16 Voltage regulator
The regulator has four operating modes:
Regulator ON
Main regulator mode (MR)
Low-power regulator (LPR)
– Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when regulator is ON:
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
Refer to Table 14: General operating conditions.
LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost)
069
9''
WLPH
3'5 9
WLPH
1567
3'5B21 3'5B21
5HVHWE\RWKHUVRXUFHWKDQ
SRZHUVXSSO\VXSHUYLVRU
DocID022152 Rev 8 27/202
STM32F405xx, STM32F407xx Description
Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to
Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions.
All packages have regulator ON feature.
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not manage internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
Refer to Figure 21: Power supply scheme
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The standby mode is not available
Figure 9. Regulator OFF
Ăŝϭϴϰϵϴsϰ
([WHUQDO9
&$3B
SRZHU
VXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYH
ZKHQ9
&$3B
0LQ9

9

9
&$3B
9
&$3B
%<3$66B5(*
9
''
3$ 1567
ƉƉůŝĐĂƚŝŽŶƌĞƐĞƚ
ƐŝŐŶĂů;ŽƉƚŝŽŶĂůͿ
9
''
9

Description STM32F405xx, STM32F407xx
28/202 DocID022152 Rev 8
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see
Figure 11).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then
a reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
(see Table 14: General operating conditions).
Figure 10. Startup in regulator OFF mode: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.
DLH
9''
WLPH
0LQ9
3'5 9RU9
9&$3B9&$3B
9
1567
WLPH
DocID022152 Rev 8 29/202
STM32F405xx, STM32F407xx Description
Figure 11. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.
2.2.17 Regulator ON/OFF and internal reset ON/OFF availability
2.2.18 Real-time clock (RTC), backup SRAM and backup registers
The backup domain of the STM32F405xx and STM32F407xx includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
9''
WLPH
0LQ9
9&$3B9&$3B
9
3$DVVHUWHGH[WHUQDOO\
1567
WLPH DLG
3'5 9RU9
Table 3. Regulator ON/OFF and internal reset ON/OFF availability
Regulator ON Regulator OFF Internal reset ON Internal reset
OFF
LQFP64
LQFP100 Yes No
Yes No
LQFP144
Yes
PDR_ON set to
VDD
Yes
PDR_ON
connected to an
external power
supply supervisor
WLCSP90
UFBGA176
LQFP176
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
Description STM32F405xx, STM32F407xx
30/202 DocID022152 Rev 8
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
2.2.19 Low-power modes
The STM32F405xx and STM32F407xx support three low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V12 domain is powered off. The PLL,
the HSI RC and the HSE crystal oscillators are also switched off. After entering
DocID022152 Rev 8 31/202
STM32F405xx, STM32F407xx Description
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the V12 domain is controlled by an external power.
2.2.20 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.2.21 Timers and watchdogs
The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight
general-purpose timers, two basic timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complemen-
tary output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
Advanced
-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 Yes 84 168
Description STM32F405xx, STM32F407xx
32/202 DocID022152 Rev 8
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 42 84
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 42 84
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No 84 168
TIM10
,
TIM11
16-bit Up
Any integer
between 1
and 65536
No 1 No 84 168
TIM12 16-bit Up
Any integer
between 1
and 65536
No 2 No 42 84
TIM13
,
TIM14
16-bit Up
Any integer
between 1
and 65536
No 1 No 42 84
Basic TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No 42 84
Table 4. Timer feature comparison (continued)
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complemen-
tary output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
DocID022152 Rev 8 33/202
STM32F405xx, STM32F407xx Description
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F40xxx
devices (see Table 4 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F40xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
Description STM32F405xx, STM32F407xx
34/202 DocID022152 Rev 8
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
2.2.22 Inter-integrated circuit interface (I²C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz). They support
the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware
CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
2.2.23 Universal synchronous/asynchronous receiver transmitters (USART)
The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous
receiver transmitters (USART1, USART2, USART3 and USART6) and two universal
asynchronous receiver transmitters (UART4 and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at
up to 5.25 Mbit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
DocID022152 Rev 8 35/202
STM32F405xx, STM32F407xx Description
2.2.24 Serial peripheral interface (SPI)
The STM32F40xxx feature up to three SPIs in slave and master modes in full-duplex and
simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3
can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
2.2.25 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and half-duplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Table 5. USART feature comparison
USART
name
Standard
features
Modem
(RTS/
CTS)
LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud rate
in Mbit/s
(oversampling
by 16)
Max. baud rate
in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 5.25 10.5
APB2
(max.
84 MHz)
USART2 X X X X X X 2.62 5.25
APB1
(max.
42 MHz)
USART3 X X X X X X 2.62 5.25
APB1
(max.
42 MHz)
UART4 X - X - X - 2.62 5.25
APB1
(max.
42 MHz)
UART5 X - X - X - 2.62 5.25
APB1
(max.
42 MHz)
USART6 X X X X X X 5.25 10.5
APB2
(max.
84 MHz)
Description STM32F405xx, STM32F407xx
36/202 DocID022152 Rev 8
2.2.26 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S application. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
2.2.27 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral available only on the STM32F407xx devices.
The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard medium-
independent interface (MII) or a reduced medium-independent interface (RMII). The
STM32F407xx requires an external physical interface device (PHY) to connect to the
physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII
port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz
(MII) from the STM32F407xx.
DocID022152 Rev 8 37/202
STM32F405xx, STM32F407xx Description
The STM32F407xx includes the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F40xxx/41xxx reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
2.2.29 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
2.2.30 Universal serial bus on-the-go full-speed (OTG_FS)
The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable
endpoint setting and supports suspend/resume. The USB OTG full-speed controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE
oscillator. The major features are:
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Description STM32F405xx, STM32F407xx
38/202 DocID022152 Rev 8
2.2.31 Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and
high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and
features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using
the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator.
The major features are:
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.2.32 Digital camera interface (DCMI)
The camera interface is not available in STM32F405xx devices.
STM32F407xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
2.2.33 Random number generator (RNG)
All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random
numbers generated by an integrated analog circuit.
2.2.34 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
DocID022152 Rev 8 39/202
STM32F405xx, STM32F407xx Description
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
2.2.35 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.2.36 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.2.37 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference VREF+
Description STM32F405xx, STM32F407xx
40/202 DocID022152 Rev 8
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.2.38 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.2.39 Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F40xxx through a small number of ETM pins to an external hardware trace port
analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID022152 Rev 8 41/202
STM32F405xx, STM32F407xx Pinouts and pin description
3 Pinouts and pin description
Figure 12. STM32F40xxx LQFP64 pinout
1. The above figure shows the package top view.
       
















       











6"!4
0#
0#
.234
0#
0#
0#
0#
633!
6$$!
0!?7+50
0! 
0! 
6$$

0"
0"
"//4
0"
0"
0"
0"
0"
0$
0#
0#
0#
0!   
0!   
6$$ 
6#!0?
0!   
0!   
0!   
0!   
0!  
0!  
0#
0#
0#
0#
0"
0"
0"
0"
0!
633
6$$
0!
0!
0!
0!
0#
0#
0"
0"
0"
0"
0"
6#!0?
6$$
,1&0
AIB
0#
0(
0(
633
Pinouts and pin description STM32F405xx, STM32F407xx
42/202 DocID022152 Rev 8
Figure 13. STM32F40xxx LQFP100 pinout
1. The above figure shows the package top view.


































































0%
0%
0%
0%
0%
6"!4
0#
0#
633
6$$
0(
.234
0#
0#
0#
0#
6$$
633!
62%&
6$$!
0! 
0! 
0! 
6$$
633
6#!0?
0! 
0! 
0! 
0! 
0! 
0!   
0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
0"
0"
0! 
633
6$$
0! 
0! 
0! 
0! 
0#
0#
0"
0"
0"
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
0"
6#!0?
6$$
6$$
633
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!

























AIC
,1&0
0#
0(
DocID022152 Rev 8 43/202
STM32F405xx, STM32F407xx Pinouts and pin description
Figure 14. STM32F40xxx LQFP144 pinout
1. The above figure shows the package top view.
6
$$
0$2?/.
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0'
6
$$
6
33
0'
0'
0'
0'
0'
0'
0$
0$
6
$$
6
33
0$
0$
0$
0$
0$
0$
0#
0#
0#
0! 
0! 
0% 6
$$
0% 6
33
0%
0% 0! 
0% 0! 
6"!4 0! 
0# 0! 
0# 0! 
0# 0! 
0& 0#
0& 0#
0& 0#
0& 0#
0& 6
$$
0& 6
33
6
33
0'
6
$$
0'
0& 0'
0& 0'
0& 0'
0& 0'
0& 0'
0( 0$
0( 0$
.234 6
$$
0# 6
33
0# 0$
0# 0$
0# 0$
6
33!
0$
6
$$
0$
6
2%&
0$
6
$$!
0"
0!  0"
0!  0"
0!  0"
0! 
6
33
6
$$
0! 
0! 
0! 
0! 
0#
0#
0"
0"
0"
0&
0&
6
$$
0&
0&
0&
0'
0'
0%
0%
0%
6
33
6
$$
0%
0%
0%
0%
0%
0%
0"
0"
6
#!0?
6
$$



























































































,1&0












































AIB
6
#!0?
6
33
Pinouts and pin description STM32F405xx, STM32F407xx
44/202 DocID022152 Rev 8
Figure 15. STM32F40xxx LQFP176 pinout
1. The above figure shows the package top view.
069
3'5B21
3(
3(
3%
3%
%227
3%
3%
3%
3%
3%
3*
3*
3*
3*
3*
3*
3*
3'
3'
3'
3'
3'
3'
3'
3'
3&
3&
3&
3,
3,
3(
3(
3(
3(
3$
3(
3$
9%$7
3$
3,
3$
3&
3$
3&
3$
3)
3&
3)
3&
3)
3&
3)
3&
3)
3) 3*
3*
3)
3*
3)
3*
3)
3*
3)
3*
3)
3*
3+
3'
3+
3'
1567
9
3&
9
3&
3'
3&
3'
3&
3'
3'
3'
95()
3'
3%
3$
3%
3$
3%
3$
3%
3$
3$
3$
3$
3$
3&
3&
3%
3%
3%
3)
3)
966
3)
3)
3)
3*
3*
3(
3(
3(
3(
3(
3(
3(
3(
3(
3%
3%



























































































/4)3












































3,
3$
3$
3,
3,
3,








3+
3+
3+
3+
3+
3+
3+
3+







3,
3,
3+
3+
3+
3+
















3&
3,
3,
3,
966
3+
3+
9''
966
9''
9''
966$
9''$
%<3$66B5(*
9''
9''
966
9''
9&$3B
9''
966
9''
9&$3B
966
9''
966
9''
966
9''
966
9''
9''
966
9''
966
9''
DocID022152 Rev 8 45/202
STM32F405xx, STM32F407xx Pinouts and pin description
Figure 16. STM32F40xxx UFBGA176 ballout
1. This figure shows the package top view.
AIB
     
! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0!
" 0% 0% 0% 0" 0" 0" 0'0'0'0' 0$ 0$ 0#0#0!
#6"!4 0) 0) 0) 0$2?/.
6$$ 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0!
$0# 0) 0) 0) "//4 633 633 633 0$ 0$ 0$ 0( 0) 0!
%0# 0& 0) 0) 0( 0( 0) 0!
& 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0? 0# 0!
'0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0#
(0( 0& 0& 0( 633 633 633 633 633 633 6$$ 0' 0#
* .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0'
+0& 0& 0&
6$$ 633 633 633 633 633 0( 0' 0' 0'
,0& 0& 0&
"90!33?
2%'
0( 0( 0$ 0'
- 633! 0# 0# 0# 0# 0" 0' 633 633 6#!0? 0( 0( 0( 0$ 0$
.62%& 0!
0!
0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$
0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$
2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0"
633

Pinouts and pin description STM32F405xx, STM32F407xx
46/202 DocID022152 Rev 8
Figure 17. STM32F40xxx WLCSP90 ballout
1. This figure shows the package bump view.
! 6"!4 0# 0$2?/. 0" 0$ 0$ 0#
"0# 6$$ 0" 0" 0$ 0$ 0!
#0! 633 0# 0)
0" 0$ 0$
$ 0# 0" 0!
%0# 633
&0( 0! 
'.234
(633!
*0!  0! 
0!  0" 0% 0" 0"
-36
0!
0)
0!
0! 0!
0# 0# 0#
0(
0"
0# 0$
0$
0% 0%
"90!33?
2%'
0$ 0$
0% 0"

6$$
0# 6#!0?
0!
0" 0$ 0# 0!
633 6$$ 633 6$$ 0#
6$$ 0% 0% 6#!0? 0$
0% 0% 0$ 0$
0! 0! 0" 0" 0"
0"
"//4
6$$! 0" 0%0! 
Table 6. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to ADC
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
DocID022152 Rev 8 47/202
STM32F405xx, STM32F407xx Pinouts and pin description
Table 7. STM32F40xxx pin and ball definitions
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
- - 1 1 A2 1 PE2 I/O FT -
TRACECLK/ FSMC_A23 /
ETH_MII_TXD3 /
EVENTOUT
-
- - 2 2 A1 2 PE3 I/O FT - TRACED0/FSMC_A19 /
EVENTOUT -
- - 3 3 B1 3 PE4 I/O FT - TRACED1/FSMC_A20 /
DCMI_D4/ EVENTOUT -
- - 4 4 B2 4 PE5 I/O FT -
TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6 /
EVENTOUT
-
- - 5 5 B3 5 PE6 I/O FT -
TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7 /
EVENTOUT
-
1A106 6 C1 6 V
BAT S- - - -
- - - - D2 7 PI8 I/O FT
(2)(
3) EVENTOUT
RTC_TAMP1,
RTC_TAMP2,
RTC_TS
2 A9 7 7 D1 8 PC13 I/O FT
(2)
(3) EVENTOUT
RTC_OUT,
RTC_TAMP1,
RTC_TS
3B108 8 E1 9 PC14/OSC32_IN
(PC14) I/O FT
(2)(
3) EVENTOUT OSC32_IN(4)
4B99 9 F110
PC15/
OSC32_OUT
(PC15)
I/O FT
(2)(
3) EVENTOUT OSC32_OUT(4)
- - - - D3 11 PI9 I/O FT - CAN1_RX / EVENTOUT -
- - - - E3 12 PI10 I/O FT - ETH_MII_RX_ER /
EVENTOUT -
- - - - E4 13 PI11 I/O FT - OTG_HS_ULPI_DIR /
EVENTOUT -
----F214 V
SS S- - - -
----F315 V
DD S- - - -
- - - 10 E2 16 PF0 I/O FT - FSMC_A0 / I2C2_SDA /
EVENTOUT -
Pinouts and pin description STM32F405xx, STM32F407xx
48/202 DocID022152 Rev 8
- - - 11 H3 17 PF1 I/O FT - FSMC_A1 / I2C2_SCL /
EVENTOUT -
- - - 12 H2 18 PF2 I/O FT - FSMC_A2 / I2C2_SMBA /
EVENTOUT -
- - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9
- - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14
- - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15
-C91016G222 V
SS S- - - -
-B81117G323 V
DD S- - - -
- - - 18 K2 24 PF6 I/O FT (4)
TIM10_CH1 /
FSMC_NIORD/
EVENTOUT
ADC3_IN4
- - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG/
EVENTOUT ADC3_IN5
- - - 20 L3 26 PF8 I/O FT (4)
TIM13_CH1 /
FSMC_NIOWR/
EVENTOUT
ADC3_IN6
- - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/
EVENTOUT ADC3_IN7
- - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8
5 F10 12 23 G1 29 PH0/OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN(4)
6F91324H130PH1/OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT(4)
7 G10 14 25 J1 31 NRST I/O RST - - -
8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/
EVENTOUT ADC123_IN10
9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11
10 D10 17 28 M4 34 PC2 I/O FT (4)
SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
/I2S2ext_SD/ EVENTOUT
ADC123_IN12
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 49/202
STM32F405xx, STM32F407xx Pinouts and pin description
11 E9 18 29 M5 35 PC3 I/O FT (4)
SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK/
EVENTOUT
ADC123_IN13
--1930-36 V
DD S- - - -
12 H10 20 31 M1 37 VSSA S- - - -
----N1- V
REF S- - - -
- - 21 32 P1 38 VREF+ S- - - -
13 G9 22 33 R1 39 VDDA S- - - -
14 C10 23 34 N3 40 PA0/WKUP
(PA0) I/O FT (5)
USART2_CTS/
UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR/
EVENTOUT
ADC123_IN0/WKU
P(4)
15 F8 24 35 N2 41 PA1 I/O FT (4)
USART2_RTS /
UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2/
EVENTOUT
ADC123_IN1
16 J10 25 36 P2 42 PA2 I/O FT (4)
USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO/ EVENTOUT
ADC123_IN2
- - - - F4 43 PH2 I/O FT - ETH_MII_CRS/EVENTOUT -
- - - - G4 44 PH3 I/O FT - ETH_MII_COL/EVENTOUT -
- - - - H4 45 PH4 I/O FT -
I2C2_SCL /
OTG_HS_ULPI_NXT/
EVENTOUT
-
- - - - J4 46 PH5 I/O FT - I2C2_SDA/ EVENTOUT -
17 H9 26 37 R2 47 PA3 I/O FT (4)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT
ADC123_IN3
18 E5 27 38 - - VSS S- - - -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Pinouts and pin description STM32F405xx, STM32F407xx
50/202 DocID022152 Rev 8
D9 L4 48 BYPASS_REG I FT - - -
19 E4 28 39 K4 49 VDD S- - - -
20 J9 29 40 N4 50 PA4 I/O TTa (4)
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
ADC12_IN4
/DAC_OUT1
21 G8 30 41 P4 51 PA5 I/O TTa (4)
SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CH1N/ EVENTOUT
ADC12_IN5/DAC_
OUT2
22 H8 31 42 P3 52 PA6 I/O FT (4)
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK / TIM3_CH1
/ TIM1_BKIN/ EVENTOUT
ADC12_IN6
23 J8 32 43 R3 53 PA7 I/O FT (4)
SPI1_MOSI/ TIM8_CH1N /
TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT
ADC12_IN7
24 - 33 44 N5 54 PC4 I/O FT (4)
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
ADC12_IN14
25 - 34 45 P5 55 PC5 I/O FT (4)
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
ADC12_IN15
26 G7 35 46 R5 56 PB0 I/O FT (4)
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
ADC12_IN8
27 H7 36 47 R4 57 PB1 I/O FT (4)
TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
TIM1_CH3N/ EVENTOUT
ADC12_IN9
28 J7 37 48 M6 58 PB2/BOOT1
(PB2) I/O FT - EVENTOUT -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 51/202
STM32F405xx, STM32F407xx Pinouts and pin description
- - - 49 R6 59 PF11 I/O FT - DCMI_D12/ EVENTOUT -
- - - 50 P6 60 PF12 I/O FT - FSMC_A6/ EVENTOUT -
---51M861 V
SS S- - - -
---52N862 V
DD S- - - -
- - - 53 N6 63 PF13 I/O FT - FSMC_A7/ EVENTOUT -
- - - 54 R7 64 PF14 I/O FT - FSMC_A8/ EVENTOUT -
- - - 55 P7 65 PF15 I/O FT - FSMC_A9/ EVENTOUT -
- - - 56 N7 66 PG0 I/O FT - FSMC_A10/ EVENTOUT -
- - - 57 M7 67 PG1 I/O FT - FSMC_A11/ EVENTOUT -
- G63858 R8 68 PE7 I/O FT - FSMC_D4/TIM1_ETR/
EVENTOUT -
- H6 39 59 P8 69 PE8 I/O FT - FSMC_D5/ TIM1_CH1N/
EVENTOUT -
- J6 40 60 P9 70 PE9 I/O FT - FSMC_D6/TIM1_CH1/
EVENTOUT -
---61M971 V
SS S- - - -
---62N972 V
DD S- - - -
- F6 41 63 R9 73 PE10 I/O FT - FSMC_D7/TIM1_CH2N/
EVENTOUT -
- J5 42 64 P10 74 PE11 I/O FT - FSMC_D8/TIM1_CH2/
EVENTOUT -
- H54365R1075 PE12 I/O FT - FSMC_D9/TIM1_CH3N/
EVENTOUT -
- G54466N11 76 PE13 I/O FT - FSMC_D10/TIM1_CH3/
EVENTOUT -
- F5 45 67 P11 77 PE14 I/O FT - FSMC_D11/TIM1_CH4/
EVENTOUT -
- G44668R11 78 PE15 I/O FT - FSMC_D12/TIM1_BKIN/
EVENTOUT -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Pinouts and pin description STM32F405xx, STM32F407xx
52/202 DocID022152 Rev 8
29 H4 47 69 R12 79 PB10 I/O FT -
SPI2_SCK / I2S2_CK /
I2C2_SCL/ USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
TIM2_CH3/ EVENTOUT
-
30 J4 48 70 R13 80 PB11 I/O FT -
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
TIM2_CH4/ EVENTOUT
-
31 F4 49 71 M10 81 VCAP_1 S- - -
32 - 50 72 N10 82 VDD S- - -
- - - - M11 83 PH6 I/O FT -
I2C2_SMBA / TIM12_CH1 /
ETH_MII_RXD2/
EVENTOUT
-
- - - - N12 84 PH7 I/O FT -
I2C3_SCL /
ETH_MII_RXD3/
EVENTOUT
-
- - - - M12 85 PH8 I/O FT -
I2C3_SDA /
DCMI_HSYNC/
EVENTOUT
-
- - - - M13 86 PH9 I/O FT - I2C3_SMBA / TIM12_CH2/
DCMI_D0/ EVENTOUT -
- - - - L13 87 PH10 I/O FT - TIM5_CH1 / DCMI_D1/
EVENTOUT -
- - - - L12 88 PH11 I/O FT - TIM5_CH2 / DCMI_D2/
EVENTOUT -
- - - - K12 89 PH12 I/O FT - TIM5_CH3 / DCMI_D3/
EVENTOUT -
----H1290 V
SS S- - - -
----J1291 V
DD S- - - -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 53/202
STM32F405xx, STM32F407xx Pinouts and pin description
33 J3 51 73 P12 92 PB12 I/O FT -
SPI2_NSS / I2S2_WS /
I2C2_SMBA/
USART3_CK/ TIM1_BKIN /
CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT
-
34 J1 52 74 P13 93 PB13 I/O FT -
SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT
OTG_HS_VBUS
35 J2 53 75 R14 94 PB14 I/O FT -
SPI2_MISO/ TIM1_CH2N /
TIM12_CH1 /
OTG_HS_DM/
USART3_RTS /
TIM8_CH2N/I2S2ext_SD/
EVENTOUT
-
36 H1 54 76 R15 95 PB15 I/O FT -
SPI2_MOSI / I2S2_SD/
TIM1_CH3N / TIM8_CH3N
/ TIM12_CH2 /
OTG_HS_DP/ EVENTOUT
RTC_REFIN
- H2 55 77 P15 96 PD8 I/O FT - FSMC_D13 / USART3_TX/
EVENTOUT -
- H3 56 78 P14 97 PD9 I/O FT - FSMC_D14 / USART3_RX/
EVENTOUT -
- G3 57 79 N15 98 PD10 I/O FT - FSMC_D15 / USART3_CK/
EVENTOUT -
- G15880N1499 PD11 I/O FT -
FSMC_CLE /
FSMC_A16/USART3_CTS/
EVENTOUT
-
- G2 59 81 N13 100 PD12 I/O FT -
FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/
EVENTOUT
-
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Pinouts and pin description STM32F405xx, STM32F407xx
54/202 DocID022152 Rev 8
- - 60 82 M15 101 PD13 I/O FT - FSMC_A18/TIM4_CH2/
EVENTOUT -
- - - 83 - 102 VSS S- - -
- - - 84 J13 103 VDD S- - -
- F2 61 85 M14 104 PD14 I/O FT - FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT -
- F1 62 86 L14 105 PD15 I/O FT - FSMC_D1/TIM4_CH4/
EVENTOUT -
- - - 87 L15 106 PG2 I/O FT - FSMC_A12/ EVENTOUT -
- - - 88 K15 107 PG3 I/O FT - FSMC_A13/ EVENTOUT -
- - - 89 K14 108 PG4 I/O FT - FSMC_A14/ EVENTOUT -
- - - 90 K13 109 PG5 I/O FT - FSMC_A15/ EVENTOUT -
- - - 91 J15 110 PG6 I/O FT - FSMC_INT2/ EVENTOUT -
- - - 92 J14 111 PG7 I/O FT - FSMC_INT3 /USART6_CK/
EVENTOUT -
- - - 93 H14 112 PG8 I/O FT -
USART6_RTS /
ETH_PPS_OUT/
EVENTOUT
-
---94G12113 V
SS S- - -
---95H13114 V
DD S- - -
37 F3 63 96 H15 115 PC6 I/O FT -
I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT
-
38 E1 64 97 G15 116 PC7 I/O FT -
I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT
-
39 E2 65 98 G14 117 PC8 I/O FT -
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK /
DCMI_D2/ EVENTOUT
-
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 55/202
STM32F405xx, STM32F407xx Pinouts and pin description
40 E3 66 99 F14 118 PC9 I/O FT -
I2S_CKIN/ MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4/ EVENTOUT
-
41 D1 67 100 F15 119 PA8 I/O FT -
MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF/
EVENTOUT
-
42 D2 68 101 E15 120 PA9 I/O FT -
USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0/
EVENTOUT
OTG_FS_VBUS
43 D3 69 102 D15 121 PA10 I/O FT -
USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT
-
44 C1 70 103 C15 122 PA11 I/O FT -
USART1_CTS / CAN1_RX
/ TIM1_CH4 /
OTG_FS_DM/ EVENTOUT
-
45 C2 71 104 B15 123 PA12 I/O FT -
USART1_RTS / CAN1_TX/
TIM1_ETR/ OTG_FS_DP/
EVENTOUT
-
46 D4 72 105 A15 124 PA13
(JTMS-SWDIO) I/O FT - JTMS-SWDIO/ EVENTOUT -
47 B1 73 106 F13 125 VCAP_2 S- - - -
- E7 74 107 F12 126 VSS S- - - -
48 E6 75 108 G13 127 VDD S- - - -
- - - - E12 128 PH13 I/O FT - TIM8_CH1N / CAN1_TX/
EVENTOUT -
- - - - E13 129 PH14 I/O FT - TIM8_CH2N / DCMI_D4/
EVENTOUT -
- - - - D13 130 PH15 I/O FT - TIM8_CH3N / DCMI_D11/
EVENTOUT -
- C3 - - E14 131 PI0 I/O FT -
TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13/
EVENTOUT
-
- B2 - - D14 132 PI1 I/O FT - SPI2_SCK / I2S2_CK /
DCMI_D8/ EVENTOUT -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Pinouts and pin description STM32F405xx, STM32F407xx
56/202 DocID022152 Rev 8
- - - - C14 133 PI2 I/O FT -
TIM8_CH4 /SPI2_MISO /
DCMI_D9 / I2S2ext_SD/
EVENTOUT
-
- - - - C13 134 PI3 I/O FT
TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10/
EVENTOUT
-
- - - - D9 135 VSS S- - - -
- - - - C9 136 VDD S- - - -
49 A2 76 109 A14 137 PA14
(JTCK/SWCLK) I/O FT - JTCK-SWCLK/ EVENTOUT -
50 B3 77 110 A13 138 PA15
(JTDI) I/O FT -
JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ETR
/ SPI1_NSS / EVENTOUT
-
51 D5 78 111 B14 139 PC10 I/O FT -
SPI3_SCK / I2S3_CK/
UART4_TX/SDIO_D2 /
DCMI_D8 / USART3_TX/
EVENTOUT
-
52 C4 79 112 B13 140 PC11 I/O FT -
UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX /
I2S3ext_SD/ EVENTOUT
-
53 A3 80 113 A12 141 PC12 I/O FT -
UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI
/I2S3_SD / USART3_CK/
EVENTOUT
-
- D6 81 114 B12 142 PD0 I/O FT - FSMC_D2/CAN1_RX/
EVENTOUT -
- C5 82 115 C12 143 PD1 I/O FT - FSMC_D3 / CAN1_TX/
EVENTOUT -
54 B4 83 116 D12 144 PD2 I/O FT -
TIM3_ETR/UART5_RX/
SDIO_CMD / DCMI_D11/
EVENTOUT
-
- - 84 117 D11 145 PD3 I/O FT -
FSMC_CLK/
USART2_CTS/
EVENTOUT
-
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 57/202
STM32F405xx, STM32F407xx Pinouts and pin description
- A4 85 118 D10 146 PD4 I/O FT -
FSMC_NOE/
USART2_RTS/
EVENTOUT
-
- C6 86 119 C11 147 PD5 I/O FT - FSMC_NWE/USART2_TX/
EVENTOUT -
- - - 120 D8 148 VSS S- - - -
- - - 121 C8 149 VDD S- - - -
- B5 87 122 B11 150 PD6 I/O FT - FSMC_NWAIT/
USART2_RX/ EVENTOUT -
- A5 88 123 A11 151 PD7 I/O FT - USART2_CK/FSMC_NE1/
FSMC_NCE2/ EVENTOUT -
- - - 124 C10 152 PG9 I/O FT -
USART6_RX /
FSMC_NE2/FSMC_NCE3/
EVENTOUT
-
- - - 125 B10 153 PG10 I/O FT - FSMC_NCE4_1/
FSMC_NE3/ EVENTOUT -
- - - 126 B9 154 PG11 I/O FT -
FSMC_NCE4_2 /
ETH_MII_TX_EN/
ETH _RMII_TX_EN/
EVENTOUT
-
- - - 127 B8 155 PG12 I/O FT -
FSMC_NE4 /
USART6_RTS/
EVENTOUT
-
- - - 128 A8 156 PG13 I/O FT -
FSMC_A24 /
USART6_CTS
/ETH_MII_TXD0/
ETH_RMII_TXD0/
EVENTOUT
-
- - - 129 A7 157 PG14 I/O FT -
FSMC_A25 / USART6_TX
/ETH_MII_TXD1/
ETH_RMII_TXD1/
EVENTOUT
-
- E8 - 130 D7 158 VSS S- - - -
- F7 - 131 C7 159 VDD S- - - -
- - - 132 B7 160 PG15 I/O FT - USART6_CTS /
DCMI_D13/ EVENTOUT -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Pinouts and pin description STM32F405xx, STM32F407xx
58/202 DocID022152 Rev 8
55 B6 89 133 A10 161
PB3
(JTDO/
TRACESWO)
I/O FT -
JTDO/ TRACESWO/
SPI3_SCK / I2S3_CK /
TIM2_CH2 / SPI1_SCK/
EVENTOUT
-
56 A6 90 134 A9 162 PB4
(NJTRST) I/O FT -
NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO /
I2S3ext_SD/ EVENTOUT
-
57 D7 91 135 A6 163 PB5 I/O FT -
I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH2
/ SPI1_MOSI/ SPI3_MOSI /
DCMI_D10 / I2S3_SD/
EVENTOUT
-
58 C7 92 136 B6 164 PB6 I/O FT -
I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
DCMI_D5/USART1_TX/
EVENTOUT
-
59 B7 93 137 B5 165 PB7 I/O FT -
I2C1_SDA / FSMC_NL /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2/
EVENTOUT
-
60 A7 94 138 D6 166 BOOT0 I B - - VPP
61 D8 95 139 A5 167 PB8 I/O FT -
TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
ETH_MII_TXD3 /
I2C1_SCL/ CAN1_RX/
EVENTOUT
-
62 C8 96 140 B4 168 PB9 I/O FT -
SPI2_NSS/ I2S2_WS /
TIM4_CH4/ TIM11_CH1/
SDIO_D5 / DCMI_D7 /
I2C1_SDA / CAN1_TX/
EVENTOUT
-
- - 97 141 A4 169 PE0 I/O FT - TIM4_ETR / FSMC_NBL0 /
DCMI_D2/ EVENTOUT -
- - 98 142 A3 170 PE1 I/O FT - FSMC_NBL1 / DCMI_D3/
EVENTOUT -
63 - 99 - D5 - VSS S- - - -
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
DocID022152 Rev 8 59/202
STM32F405xx, STM32F407xx Pinouts and pin description
- A8 - 143 C6 171 PDR_ON I FT - - -
64 A1 10
0144 C5 172 VDD S- - - -
- - - - D4 173 PI4 I/O FT - TIM8_BKIN / DCMI_D5/
EVENTOUT -
- - - - C4 174 PI5 I/O FT -
TIM8_CH1 /
DCMI_VSYNC/
EVENTOUT
-
- - - - C3 175 PI6 I/O FT - TIM8_CH2 / DCMI_D6/
EVENTOUT -
- - - - C2 176 PI7 I/O FT - TIM8_CH3 / DCMI_D7/
EVENTOUT -
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:
www.st.com.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset
ON mode), then PA0 is used as an internal Reset (active low).
Table 7. STM32F40xxx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin type
I / O structure
Notes
Alternate functions Additional
functions
LQFP64
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
Table 8. FSMC pin definition
Pins(1)
FSMC
LQFP100(2) WLCSP90
(2)
CF NOR/PSRAM/
SRAM NOR/PSRAM Mux NAND 16 bit
PE2 - A23 A23 - Yes -
PE3 - A19 A19 - Yes -
PE4 - A20 A20 - Yes -
PE5 - A21 A21 - Yes -
PE6 - A22 A22 - Yes -
PF0 A0 A0 - - - -
Pinouts and pin description STM32F405xx, STM32F407xx
60/202 DocID022152 Rev 8
PF1 A1 A1 - - - -
PF2 A2 A2 - - - -
PF3 A3 A3 - - - -
PF4 A4 A4 - - - -
PF5 A5 A5 - - - -
PF6 NIORD - - - - -
PF7 NREG - - - - -
PF8 NIOWR - - - - -
PF9 CD - - - - -
PF10 INTR - - - - -
PF12 A6 A6 - - - -
PF13 A7 A7 - - - -
PF14 A8 A8 - - - -
PF15 A9 A9 - - - -
PG0 A10 A10 - - - -
PG1 A11 - - - -
PE7 D4 D4 DA4 D4 Yes Yes
PE8 D5 D5 DA5 D5 Yes Yes
PE9 D6 D6 DA6 D6 Yes Yes
PE10 D7 D7 DA7 D7 Yes Yes
PE11 D8 D8 DA8 D8 Yes Yes
PE12 D9 D9 DA9 D9 Yes Yes
PE13 D10 D10 DA10 D10 Yes Yes
PE14 D11 D11 DA11 D11 Yes Yes
PE15 D12 D12 DA12 D12 Yes Yes
PD8 D13 D13 DA13 D13 Yes Yes
PD9 D14 D14 DA14 D14 Yes Yes
PD10 D15 D15 DA15 D15 Yes Yes
PD11 - A16 A16 CLE Yes Yes
PD12 - A17 A17 ALE Yes Yes
PD13 - A18 A18 - Yes -
PD14 D0 D0 DA0 D0 Yes Yes
PD15 D1 D1 DA1 D1 Yes Yes
Table 8. FSMC pin definition (continued)
Pins(1)
FSMC
LQFP100(2) WLCSP90
(2)
CF NOR/PSRAM/
SRAM NOR/PSRAM Mux NAND 16 bit
DocID022152 Rev 8 61/202
STM32F405xx, STM32F407xx Pinouts and pin description
PG2 - A12 - - - -
PG3 - A13 - - - -
PG4 - A14 - - - -
PG5 - A15 - - - -
PG6 - - - INT2 - -
PG7 - - - INT3 - -
PD0 D2 D2 DA2 D2 Yes Yes
PD1 D3 D3 DA3 D3 Yes Yes
PD3 - CLK CLK - Yes -
PD4 NOE NOE NOE NOE Yes Yes
PD5 NWE NWE NWE NWE Yes Yes
PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes
PD7 - NE1 NE1 NCE2 Yes Yes
PG9 - NE2 NE2 NCE3 - -
PG10 NCE4_1 NE3 NE3 - - -
PG11 NCE4_2 - - - - -
PG12 - NE4 NE4 - - -
PG13 - A24 A24 - - -
PG14 - A25 A25 - - -
PB7 - NADV NADV - Yes Yes
PE0 - NBL0 NBL0 - Yes -
PE1 - NBL1 NBL1 - Yes -
1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on
smaller packages are given in the dedicated package column.
2. Ports F and G are not available in devices delivered in 100-pin packages.
Table 8. FSMC pin definition (continued)
Pins(1)
FSMC
LQFP100(2) WLCSP90
(2)
CF NOR/PSRAM/
SRAM NOR/PSRAM Mux NAND 16 bit
STM32F405xx, STM32F407xx Pinouts and pin description
DocID022152 Rev 8 62/202
Table 9. Alternate function mapping
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
Port A
PA0 - TIM2_CH1_
ETR TIM 5_CH1 TIM8_ETR - - - USART2_CTS UART4_TX - - ETH_MII_CRS - - - EVENTOUT
PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS UART4_RX - -
ETH_MII
_RX_CLK
ETH_RMII__REF
_CLK
---EVENTOUT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX - - - ETH_MDIO - - - EVENTOUT
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - OTG_HS_ULPI_
D0 ETH _MII_COL - - - EVENTOUT
PA4 - - - - - SPI1_NSS SPI3_NSS
I2S3_WS USART2_CK - - - - OTG_HS_SOF DCMI_
HSYNC -EVENTOUT
PA5 - TIM2_CH1_
ETR - TIM8_CH1N - SPI1_SCK - - - - OTG_HS_ULPI_
CK - - - - EVENTOUT
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - - - TIM13_CH1 - - - DCMI_PIXCK - EVENTOUT
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - - - TIM14_CH1 -
ETH_MII _RX_DV
ETH_RMII
_CRS_DV
---EVENTOUT
PA8 MCO1 TIM1_CH1 - - I2C3_SCL - - USART1_CK - - OTG_FS_SOF - - - - EVENTOUT
PA9 - TIM1_CH2 - - I2C3_
SMBA - - USART1_TX - - - - - DCMI_D0 - EVENTOUT
PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_ID - - DCMI_D1 - EVENTOUT
PA11 - TIM1_CH4 - - - - - USART1_CTS - CAN1_RX OTG_FS_DM - - - - EVENTOUT
PA12 - TIM1_ETR - - - - - USART1_RTS - CAN1_TX OTG_FS_DP - - - - EVENTOUT
PA13 JTMS-
SWDIO - - - - - - - - - - - - - - EVENTOUT
PA14 JTCK-
SWCLK - - - - - - - - - - - - - - EVENTOUT
PA15 JT DI TIM 2_CH1
TIM 2_ETR - - - SPI1_NSS SPI3_NSS/
I2S3_WS - - - - - - - - EVENTOUT
Pinouts and pin description STM32F405xx, STM32F407xx
63/202 DocID022152 Rev 8
Port B
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - - - - OTG_HS_ULPI_
D1 ETH _MII_RXD2 - - - EVENTOUT
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - - - - OTG_HS_ULPI_
D2 ETH _MII_RXD3 - - - EVENTOUT
PB2 - - - - - - - - - - - - - - - EVENTOUT
PB3
JTDO/
TRACES
WO
TIM2_CH2 - - - SPI1_SCK
SPI3_SCK
I2S3_CK - - - - - - - - EVENTOUT
PB4 NJTRST - TIM3_CH1 - SPI1_MISO SPI3_MISO I2S3ext_SD - - - - - - - EVENTOUT
PB5 - - TIM3_CH2 I2C1_SMB
ASPI1_MOSI SPI3_MOSI
I2S3_SD - CAN2_RX OTG_HS_ULPI_
D7 ETH _PPS_OUT - DCMI_D10 - EVENTOUT
PB6 - - TIM4_CH1 I2C1_SCL - - USART1_TX - CAN2_TX - - - DCMI_D5 - EVENTOUT
PB7 - - TIM4_CH2 I2C1_SDA - - USART1_RX - - - - FSMC_NL
DCMI_VSYN
C -EVENTOUT
PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - CAN1_RX - ETH _MII_TXD3 SDIO_D4 DCMI_D6 - EVENTOUT
PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA
SPI2_NSS
I2S2_WS - - - CAN1_TX - - SDIO_D5 DCMI_D7 - EVENTOUT
PB10 - TIM2_CH3 - - I2C2_SCL
SPI2_SCK
I2S2_CK -USART3_TX - -
OTG_HS_ULPI_
D3 ETH_ MII_RX_ER - - - EVENTOUT
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - OTG_HS_ULPI_
D4
ETH _MII_TX_EN
ETH
_RMII_TX_EN
---EVENTOUT
PB12 - TIM1_BKIN - - I2C2_
SMBA
SPI2_NSS
I2S2_WS - USART3_CK - CAN2_RX
OTG_HS_ULPI_
D5
ETH _MII_TXD0
ETH _RMII_TXD0 OTG_HS_ID - - EVENTOUT
PB13 - TIM1_CH1N - - - SPI2_SCK
I2S2_CK - USART3_CTS - CAN2_TX
OTG_HS_ULPI_
D6
ETH _MII_TXD1
ETH _RMII_TXD1 ---EVENTOUT
PB14 - TIM1_CH2N - TIM8_CH2N - SPI2_MISO I2S2ext_SD USART3_RTS - TIM12_CH1 - - OTG_HS_DM - - EVENTOUT
PB15 RTC_
REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI
I2S2_SD - - - TIM12_CH2 - - OTG_HS_DP - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
STM32F405xx, STM32F407xx Pinouts and pin description
DocID022152 Rev 8 64/202
Port C
PC0 - - - - - - - - - - OTG_HS_ULPI_
STP - - - - EVENTOUT
PC1 - - - - - - - - - - - ETH_MDC - - - EVENTOUT
PC2 - - - - - SPI2_MISO I2S2ext_SD - - - OTG_HS_ULPI_
DIR ETH _MII_TXD2 - - - EVENTOUT
PC3 - - - - - SPI2_MOSI
I2S2_SD ----
OTG_HS_ULPI_
NXT
ETH
_MII_TX_CLK ---EVENTOUT
PC4 - - - - - - - - - - - ETH_MII_RXD0
ETH_RMII_RXD0 ---EVENTOUT
PC5 - - - - - - - - - - - ETH _MII_RXD1
ETH _RMII_RXD1 ---EVENTOUT
PC6 - - TIM3_CH1 TIM8_CH1 I2S2_MCK - USART6_TX - - - SDIO_D6 DCMI_D0 - EVENTOUT
PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - - - SDIO_D7 DCMI_D1 - EVENTOUT
PC8 - - TIM3_CH3 TIM8_CH3 - - - - USART6_CK - - - SDIO_D0 DCMI_D2 - EVENTOUT
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - - - - - SDIO_D1 DCMI_D3 - EVENTOUT
PC10 - - - - - - SPI3_SCK/
I2S3_CK USART3_TX/ UART4_TX - - - SDIO_D2 DCMI_D8 - EVENTOUT
PC11 - - - - - I2S3ext_SD SPI3_MISO/ USART3_RX UART4_RX - - - SDIO_D3 DCMI_D4 - EVENTOUT
PC12 - - - - - - SPI3_MOSI
I2S3_SD USART3_CK UART5_TX - - - SDIO_CK DCMI_D9 - EVENTOUT
PC13 - - - - - - - - - - - - - - - EVENTOUT
PC14 - - - - - - - - - - - - - - - EVENTOUT
PC15 - - - - - - - - - - - - - - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
Pinouts and pin description STM32F405xx, STM32F407xx
65/202 DocID022152 Rev 8
Port D
PD0 - - - - - - - - - CAN1_RX - - FSMC_D2 - - EVENTOUT
PD1 - - - - - - - - - CAN1_TX - - FSMC_D3 - - EVENTOUT
PD2 - - TIM3_ETR - - - - - UART5_RX - - - SDIO_CMD DCMI_D11 - EVENTOUT
PD3 - - - - - - - USART2_CTS - - - - FSMC_CLK - - EVENTOUT
PD4 - - - - - - - USART2_RTS - - - - FSMC_NOE - - EVENTOUT
PD5 - - - - - - - USART2_TX - - - - FSMC_NWE - - EVENTOUT
PD6 - - - - - - - USART2_RX - - - - FSMC_NWAIT - - EVENTOUT
PD7 - - - - - - - USART2_CK - - - - FSMC_NE1/
FSMC_NCE2 - - EVENTOUT
PD8 - - - - - - - USART3_TX - - - - FSMC_D13 - - EVENTOUT
PD9 - - - - - - - USART3_RX - - - - FSMC_D14 - - EVENTOUT
PD10 - - - - - - - USART3_CK - - - - FSMC_D15 - - EVENTOUT
PD11 - - - - - - - USART3_CTS - - - - FSMC_A16 - - EVENTOUT
PD12 - - TIM4_CH1 - - - - USART3_RTS - - - - FSMC_A17 - - EVENTOUT
PD13 - - TIM4_CH2 - - - - - - - - - FSMC_A18 - - EVENTOUT
PD14 - - TIM4_CH3 - - - - - - - - - FSMC_D0 - - EVENTOUT
PD15 - - TIM4_CH4 - - - - - - - - - FSMC_D1 - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
STM32F405xx, STM32F407xx Pinouts and pin description
DocID022152 Rev 8 66/202
Port E
PE0 - - TIM4_ETR - - - - - - - - - FSMC_NBL0 DCMI_D2 - EVENTOUT
PE1 - - - - - - - - - - - - FSMC_NBL1 DCMI_D3 - EVENTOUT
PE2 TRACECL
K - - - - - - - - - - ETH _MII_TXD3 FSMC_A23 - - EVENTOUT
PE3 TRACED0 - - - - - - - - - - - FSMC_A19 - - EVENTOUT
PE4 TRACED1 - - - - - - - - - - - FSMC_A20 DCMI_D4 - EVENTOUT
PE5 TRACED2 - - TIM9_CH1 - - - - - - - - FSMC_A21 DCMI_D6 - EVENTOUT
PE6 TRACED3 - - TIM9_CH2 - - - - - - - - FSMC_A22 DCMI_D7 - EVENTOUT
PE7 - TIM1_ETR - - - - - - - - - - FSMC_D4 - - EVENTOUT
PE8 - TIM1_CH1N - - - - - - - - - - FSMC_D5 - - EVENTOUT
PE9 - TIM1_CH1 - - - - - - - - - - FSMC_D6 - - EVENTOUT
PE10 - TIM1_CH2N - - - - - - - - - - FSMC_D7 - - EVENTOUT
PE11 - TIM1_CH2 - - - - - - - - - - FSMC_D8 - - EVENTOUT
PE12 - TIM1_CH3N - - - - - - - - - - FSMC_D9 - - EVENTOUT
PE13 - TIM1_CH3 - - - - - - - - - - FSMC_D10 - - EVENTOUT
PE14 - TIM1_CH4 - - - - - - - - - - FSMC_D11 - - EVENTOUT
PE15 - TIM1_BKIN - - - - - - - - - - FSMC_D12 - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
Pinouts and pin description STM32F405xx, STM32F407xx
67/202 DocID022152 Rev 8
Port F
PF0 - - - - I2C2_SDA - - - - - - - FSMC_A0 - - EVENTOUT
PF1 - - - - I2C2_SCL - - - - - - - FSMC_A1 - - EVENTOUT
PF2 - - - - I2C2_
SMBA - - - - - - - FSMC_A2 - - EVENTOUT
PF3 - - - - - - - - - - - - FSMC_A3 - - EVENTOUT
PF4 - - - - - - - - - - - - FSMC_A4 - - EVENTOUT
PF5 - - - - - - - - - - - - FSMC_A5 - - EVENTOUT
PF6 - - - TIM10_CH1 - - - - - - - - FSMC_NIORD - - EVENTOUT
PF7 - - - TIM11_CH1 - - - - - - - - FSMC_NREG - - EVENTOUT
PF8 - - - - - - - - - TIM13_CH1 - - FSMC_
NIOWR - - EVENTOUT
PF9 - - - - - - - - - TIM14_CH1 - - FSMC_CD - - EVENTOUT
PF10 - - - - - - - - - - - - FSMC_INTR - - EVENTOUT
PF11 - - - - - - - - - - - - DCMI_D12 - EVENTOUT
PF12 - - - - - - - - - - - - FSMC_A6 - - EVENTOUT
PF13 - - - - - - - - - - - - FSMC_A7 - - EVENTOUT
PF14 - - - - - - - - - - - - FSMC_A8 - - EVENTOUT
PF15 - - - - - - - - - - - - FSMC_A9 - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
STM32F405xx, STM32F407xx Pinouts and pin description
DocID022152 Rev 8 68/202
Port G
PG0 - - - - - - - - - - - - FSMC_A10 - - EVENTOUT
PG1 - - - - - - - - - - - - FSMC_A11 - - EVENTOUT
PG2 - - - - - - - - - - - - FSMC_A12 - - EVENTOUT
PG3 - - - - - - - - - - - - FSMC_A13 - - EVENTOUT
PG4 - - - - - - - - - - - - FSMC_A14 - - EVENTOUT
PG5 - - - - - - - - - - - - FSMC_A15 - - EVENTOUT
PG6 - - - - - - - - - - - - FSMC_INT2 - - EVENTOUT
PG7 - - - - - - - - USART6_CK - - - FSMC_INT3 - - EVENTOUT
PG8 - - - - - - - - USART6_
RTS - - ETH _PPS_OUT - - - EVENTOUT
PG9 - - - - - - - - USART6_RX - - - FSMC_NE2/
FSMC_NCE3 - - EVENTOUT
PG10 - - - - - - - - - - - -
FSMC_
NCE4_1/
FSMC_NE3
- - EVENTOUT
PG11 - - - - - - - - - - -
ETH _MII_TX_EN
ETH _RMII_
TX_EN
FSMC_NCE4_
2 - - EVENTOUT
PG12 - - - - - - - - USART6_
RTS - - - FSMC_NE4 - - EVENTOUT
PG13 - - - - - - - - UART6_CTS - - ETH _MII_TXD0
ETH _RMII_TXD0 FSMC_A24 - - EVENTOUT
PG14 - - - - - - - - USART6_TX - - ETH _MII_TXD1
ETH _RMII_TXD1 FSMC_A25 - - EVENTOUT
PG15 - - - - - - - - USART6_
CTS - - - - DCMI_D13 - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
Pinouts and pin description STM32F405xx, STM32F407xx
69/202 DocID022152 Rev 8
Port H
PH0 - - - - - - - - - - - - - - - EVENTOUT
PH1 - - - - - - - - - - - - - - - EVENTOUT
PH2 - - - - - - - - - - - ETH _MII_CRS - - - EVENTOUT
PH3 - - - - - - - - - - - ETH _MII_COL - - - EVENTOUT
PH4 - - - - I2C2_SCL - - - - - OTG_HS_ULPI_
NXT - - - - EVENTOUT
PH5 - - - - I2C2_SDA - - - - - - - - - - EVENTOUT
PH6 - - - - I2C2_
SMBA - - - - TIM12_CH1 - ETH _MII_RXD2 - - - EVENTOUT
PH7 - - - - I2C3_SCL - - - - - - ETH _MII_RXD3 - - - EVENTOUT
PH8 - - - - I2C3_SDA - - - - - - - - DCMI_
HSYNC -EVENTOUT
PH9 - - - - I2C3_
SMBA - - - - TIM12_CH2 - - - DCMI_D0 - EVENTOUT
PH10 - - TIM5_CH1 - - - - - - - - - - DCMI_D1 - EVENTOUT
PH11 - - TIM5_CH2 - - - - - - - - - - DCMI_D2 - EVENTOUT
PH12 - - TIM5_CH3 - - - - - - - - - - DCMI_D3 - EVENTOUT
PH13 - - - TIM8_CH1N - - - - - CAN1_TX - - - - - EVENTOUT
PH14 - - - TIM8_CH2N - - - - - - - - - DCMI_D4 - EVENTOUT
PH15 - - - TIM8_CH3N - - - - - - - - - DCMI_D11 - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
STM32F405xx, STM32F407xx Pinouts and pin description
DocID022152 Rev 8 70/202
Port I
PI0 - - TIM5_CH4 - - SPI2_NSS
I2S2_WS - - - - - - - DCMI_D13 - EVENTOUT
PI1 - - - - - SPI2_SCK
I2S2_CK - - - - - - - DCMI_D8 - EVENTOUT
PI2 - - - TIM8_CH4 - SPI2_MISO I2S2ext_SD - - - - - - DCMI_D9 - EVENTOUT
PI3 - - - TIM8_ETR - SPI2_MOSI
I2S2_SD - - - - - - - DCMI_D10 - EVENTOUT
PI4 - - - TIM8_BKIN - - - - - - - - - DCMI_D5 - EVENTOUT
PI5 - - - TIM8_CH1 - - - - - - - - - DCMI_
VSYNC -EVENTOUT
PI6 - - - TIM8_CH2 - - - - - - - - - DCMI_D6 - EVENTOUT
PI7 - - - TIM8_CH3 - - - - - - - - - DCMI_D7 - EVENTOUT
PI8 - - - - - - - - - - - - - - - EVENTOUT
PI9 - - - - - - - - - CAN1_RX - - - - - EVENTOUT
PI10 - - - - - - - - - - - ETH _MII_RX_ER - - - EVENTOUT
PI11 - - - - - - - - - - OTG_HS_ULPI_
DIR - - - - EVENTOUT
Table 9. Alternate function mapping (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
AF14 AF15
SYS TIM1/2 TIM3/4/5 TIM8/9/10
/11 I2C1/2/3
SPI1/SPI2/
I2S2/I2S2e
xt
SPI3/I2Sext
/I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/2
TIM12/13/
14
OTG_FS/
OTG_HS ETH FSMC/SDIO
/OTG_FS DCMI
DocID022152 Rev 8 71/202
STM32F405xx, STM32F407xx Memory mapping
4 Memory mapping
The memory map is shown in Figure 18.
Figure 18. STM32F40xxx memory map
-BYTE
BLOCK
#ORTEX-gS
INTERNAL
PERIPHERALS
-BYTE
BLOCK
.OTUSED
-BYTE
BLOCK
&3-#REGISTERS
-BYTE
BLOCK
&3-#BANK
BANK
-BYTE
BLOCK
&3-#BANK
BANK
-BYTE
BLOCK
0ERIPHERALS
-BYTE
BLOCK
32!-
X
X&&&&&&&
X
X&&&&&&&
X
X&&&&&&&
X
X&&&&&&&
X
X&&&&&&&
X!
X"&&&&&&&
X#
X$&&&&&&&
X%
X&&&&&&&&
-BYTE
BLOCK
#ODE
&LASH
XX&&&&&&&
X&&&X&&&!&
X&&&#X&&&#
XX&&&&&
XX&&&&&&
XX&&&&&
3YSTEMMEMORY/40
2ESERVED
2ESERVED
!LIASEDTO&LASHSYSTEM
MEMORYOR32!-DEPENDING
ONTHE"//4PINS
32!-+"ALIASED
BYBITBANDING
2ESERVED
XX"&&&
X#X&&&&
XX&&&&&&&
X
2ESERVED
X&&&
XX&&&&
X
X&&
X
2ESERVED X#X&&&&&&&
X
!(" X!&&&
X!X$&&&&&&&
AIF
/PTION"YTES
2ESERVED XX&&&&
X"&&
!("
X
XX&&&&&&&
2ESERVED
!("
32!-+"ALIASED
BYBITBANDING
2ESERVED X&&&#X&&&&&&&
X&&&!X&&&&&&2ESERVED
##-DATA2!-
+"DATA32!- XX&&&&
2ESERVED XX&&%&&&&
2ESERVED
!0"
X&&&&
!0"
#/24%8-INTERNALPERIPHERALS X%X%&&&&&
2ESERVED X%X&&&&&&&&
Memory mapping STM32F405xx, STM32F407xx
72/202 DocID022152 Rev 8
Table 10. register boundary addresses
Bus Boundary address Peripheral
0xE00F FFFF - 0xFFFF FFFF Reserved
Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals
0xA000 1000 - 0xDFFF FFFF Reserved
AHB3
0xA000 0000 - 0xA000 0FFF FSMC control register
0x9000 0000 - 0x9FFF FFFF FSMC bank 4
0x8000 0000 - 0x8FFF FFFF FSMC bank 3
0x7000 0000 - 0x7FFF FFFF FSMC bank 2
0x6000 0000 - 0x6FFF FFFF FSMC bank 1
0x5006 0C00- 0x5FFF FFFF Reserved
AHB2
0x5006 0800 - 0x5006 0BFF RNG
0x5005 0400 - 0x5006 07FF Reserved
0x5005 0000 - 0x5005 03FF DCMI
0x5004 0000- 0x5004 FFFF Reserved
0x5000 0000 - 0x5003 FFFF USB OTG FS
0x4008 0000- 0x4FFF FFFF Reserved
DocID022152 Rev 8 73/202
STM32F405xx, STM32F407xx Memory mapping
AHB1
0x4004 0000 - 0x4007 FFFF USB OTG HS
0x4002 9400 - 0x4003 FFFF Reserved
0x4002 9000 - 0x4002 93FF
ETHERNET MAC
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 5000 - 0x4002 5FFF Reserved
0x4002 4000 - 0x4002 4FFF BKPSRAM
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
0x4002 2400 - 0x4002 2FFF Reserved
0x4002 2000 - 0x4002 23FF GPIOI
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1800 - 0x4002 1BFF GPIOG
0x4002 1400 - 0x4002 17FF GPIOF
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA
0x4001 5800- 0x4001 FFFF Reserved
Table 10. register boundary addresses (continued)
Bus Boundary address Peripheral
Memory mapping STM32F405xx, STM32F407xx
74/202 DocID022152 Rev 8
APB2
0x4001 4C00 - 0x4001 57FF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF Reserved
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF SDIO
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
0x4000 7800- 0x4000 FFFF Reserved
Table 10. register boundary addresses (continued)
Bus Boundary address Peripheral
DocID022152 Rev 8 75/202
STM32F405xx, STM32F407xx Memory mapping
APB1
0x4000 7800 - 0x4000 7FFF Reserved
0x4000 7400 - 0x4000 77FF DAC
0x4000 7000 - 0x4000 73FF PWR
0x4000 6C00 - 0x4000 6FFF Reserved
0x4000 6800 - 0x4000 6BFF CAN2
0x4000 6400 - 0x4000 67FF CAN1
0x4000 6000 - 0x4000 63FF Reserved
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 5000 - 0x4000 53FF UART5
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF USART3
0x4000 4400 - 0x4000 47FF USART2
0x4000 4000 - 0x4000 43FF I2S3ext
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 2400 - 0x4000 27FF Reserved
0x4000 2000 - 0x4000 23FF TIM14
0x4000 1C00 - 0x4000 1FFF TIM13
0x4000 1800 - 0x4000 1BFF TIM12
0x4000 1400 - 0x4000 17FF TIM7
0x4000 1000 - 0x4000 13FF TIM6
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2
Table 10. register boundary addresses (continued)
Bus Boundary address Peripheral
Electrical characteristics STM32F405xx, STM32F407xx
76/202 DocID022152 Rev 8
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.8 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 19.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions Figure 20. Pin input voltage
-36
#P&
34-&PIN
/3#?/54(I:WHEN
USING(3%OR,3%
-36
34-&PIN
6).
/3#?/54(I:WHEN
USING(3%OR,3%
DocID022152 Rev 8 77/202
STM32F405xx, STM32F407xx Electrical characteristics
5.1.6 Power supply scheme
Figure 21. Power supply scheme
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be
placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality
of the device.
2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply
supervisor.
3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is
OFF.
4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
5. VDDA=VDD and VSSA=VSS.
069
%DFNXSFLUFXLWU\
26&.57&
:DNHXSORJLF
%DFNXSUHJLVWHUV
EDFNXS5$0
.HUQHOORJLF
&38GLJLWDO
5$0
$QDORJ
5&V
3//
3RZHU
VZLWFK
9%$7
*3,2V
287
,1
îQ)
î)
9%$7
WR9
9ROWDJH
UHJXODWRU
9''$
$'&
/HYHOVKLIWHU
,2
/RJLF
9''
Q)
)
)ODVKPHPRU\
9&$3B
9&$3B
î)
%<3$66B5(*
3'5B21 5HVHW
FRQWUROOHU
9''

966

9''
95()
95()
966$
95()
Q)
)
Electrical characteristics STM32F405xx, STM32F407xx
78/202 DocID022152 Rev 8
5.1.7 Current consumption measurement
Figure 22. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
DL
9%$7
9''
9''$
,''B9%$7
,''
Table 11. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage (including VDDA, VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN
Input voltage on five-volt tolerant pin(2)
2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.
VSS–0.3 VDD+4
Input voltage on any other pin VSS–0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX VSS|Variations between all the different ground pins
including VREF
-50
VESD(HBM) Electrostatic discharge voltage (human body model)
see Section 5.3.14:
Absolute maximum
ratings (electrical
sensitivity)
DocID022152 Rev 8 79/202
STM32F405xx, STM32F407xx Electrical characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 12. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
240
mA
IVSS Total current out of VSS ground lines (sink)(1) 240
IIO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin 25
IINJ(PIN) (2)
2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.21: 12-bit ADC
characteristics.
Injected current on five-volt tolerant I/O(3)
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
–5/+0
Injected current on any other pin(4)
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
±5
ΣIINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
±25
Table 13. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 125 °C
Table 14. General operating conditions
Symbol Parameter Conditions Min Typ Max Unit
fHCLK Internal AHB clock frequency
VOS bit in PWR_CR register = 0(1) 0 - 144
MHz
VOS bit in PWR_CR register= 1 0 - 168
fPCLK1 Internal APB1 clock frequency - 0 - 42
fPCLK2 Internal APB2 clock frequency - 0 - 84
VDD Standard operating voltage - 1.8(2) -3.6V
VDDA(3)(4)
Analog operating voltage
(ADC limited to 1.2 M samples) Must be the same potential as
VDD(5)
1.8(2) -2.4
V
Analog operating voltage
(ADC limited to 1.4 M samples) 2.4 - 3.6
VBAT Backup operating voltage - 1.65 - 3.6 V
Electrical characteristics STM32F405xx, STM32F407xx
80/202 DocID022152 Rev 8
V12
Regulator ON:
1.2 V internal voltage on
VCAP_1/VCAP_2 pins
VOS bit in PWR_CR register = 0(1)
Max frequency 144MHz 1.08 1.14 1.20 V
VOS bit in PWR_CR register= 1
Max frequency 168MHz 1.20 1.26 1.32 V
Regulator OFF:
1.2 V external voltage must be
supplied from external regulator
on VCAP_1/VCAP_2 pins
Max frequency 144MHz 1.10 1.14 1.20 V
Max frequency 168MHz 1.20 1.26 1.30 V
VIN
Input voltage on RST and FT
pins(6)
2 V VDD 3.6 V –0.3 - 5.5
V
VDD 2 V –0.3 - 5.2
Input voltage on TTa pins - –0.3 - VDDA+
0.3
Input voltage on B pin - - - 5.5
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(7)
LQFP64 - - 435
mW
LQFP100 - - 465
LQFP144 - - 500
LQFP176 - - 526
UFBGA176 - - 513
WLCSP90 - - 543
TA
Ambient temperature for 6 suffix
version
Maximum power dissipation –40 - 85
°C
Low-power dissipation(8) –40 - 105
Ambient temperature for 7 suffix
version
Maximum power dissipation –40 - 105
°C
Low-power dissipation(8) –40 - 125
TJ Junction temperature range
6 suffix version –40 - 105
°C
7 suffix version –40 - 125
1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole
temperature range, when the system clock frequency is between 30 and 144 MHz.
2. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
3. When the ADC is used, refer to Table 67: ADC characteristics.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. To sustain a voltage higher than VDD+0.3, the internal pull-up and pull-down resistors must be disabled.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
8. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 14. General operating conditions (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID022152 Rev 8 81/202
STM32F405xx, STM32F407xx Electrical characteristics
Table 15. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
state
(fFlashmax)
Maximum Flash
memory access
frequency
with wait
states(1) (2) I/O operation
Clock output
Frequency on
I/O pins
Possible
Flash
memory
operations
VDD =1.8 to
2.1 V(3)
Conversion
time up to
1.2 Msps
20 MHz(4) 160 MHz with 7
wait states
Degraded
speed
performance
No I/O
compensation
up to 30 MHz
8-bit erase
and program
operations
only
VDD = 2.1 to
2.4 V
Conversion
time up to
1.2 Msps
22 MHz 168 MHz with 7
wait states
Degraded
speed
performance
No I/O
compensation
up to 30 MHz
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
Conversion
time up to
2.4 Msps
24 MHz 168 MHz with 6
wait states
Degraded
speed
performance
–I/O
compensation
works
up to 48 MHz
16-bit erase
and program
operations
VDD = 2.7 to
3.6 V(5)
Conversion
time up to
2.4 Msps
30 MHz 168 MHz with 5
wait states
Full-speed
operation
–I/O
compensation
works
–up to
60 MHz
when VDD =
3.0 to 3.6 V
–up to
48 MHz
when VDD =
2.7 to 3.0 V
32-bit erase
and program
operations
1. It applies only when code executed from Flash memory access, when code executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use
of an external power supply supervisor (refer to Section : Internal reset OFF).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
Electrical characteristics STM32F405xx, STM32F407xx
82/202 DocID022152 Rev 8
5.3.2 VCAP_1/VCAP_2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP_1/VCAP_2 pins. CEXT is specified in Table 16.
Figure 23. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
5.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Table 16. VCAP_1/VCAP_2 operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF
ESR ESR of external capacitor < 2 Ω
069
(65
5
/HDN
&
Table 17. Operating conditions at power-up / power-down (regulator ON)
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 20
µs/V
VDD fall time rate 20
Table 18. Operating conditions at power-up / power-down (regulator OFF)(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
minimum value of V12.
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate Power-up 20
µs/V
VDD fall time rate Power-down 20
tVCAP
VCAP_1 and VCAP_2 rise time
rate Power-up 20
VCAP_1 and VCAP_2 fall time
rate Power-down 20
DocID022152 Rev 8 83/202
STM32F405xx, STM32F407xx Electrical characteristics
5.3.5 Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 14.
Table 19. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising
edge) 2.09 2.14 2.19 V
PLS[2:0]=000 (falling
edge) 1.98 2.04 2.08 V
PLS[2:0]=001 (rising
edge) 2.23 2.30 2.37 V
PLS[2:0]=001 (falling
edge) 2.13 2.19 2.25 V
PLS[2:0]=010 (rising
edge) 2.39 2.45 2.51 V
PLS[2:0]=010 (falling
edge) 2.29 2.35 2.39 V
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V
PLS[2:0]=011 (falling
edge) 2.44 2.51 2.56 V
PLS[2:0]=100 (rising
edge) 2.70 2.76 2.82 V
PLS[2:0]=100 (falling
edge) 2.59 2.66 2.71 V
PLS[2:0]=101 (rising
edge) 2.86 2.93 2.99 V
PLS[2:0]=101 (falling
edge) 2.65 2.84 2.92 V
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V
PLS[2:0]=110 (falling
edge) 2.85 2.93 2.99 V
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V
PLS[2:0]=111 (falling
edge) 2.95 3.03 3.09 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge 1.60 1.68 1.76 V
Rising edge 1.64 1.72 1.80 V
VPDRhyst(1) PDR hysteresis - - 40 - mV
VBOR1
Brownout level 1
threshold
Falling edge 2.13 2.19 2.24 V
Rising edge 2.23 2.29 2.33 V
Electrical characteristics STM32F405xx, STM32F407xx
84/202 DocID022152 Rev 8
5.3.6 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme.
All Run mode current consumption measurements given in this section are performed using
a CoreMark-compliant code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
At startup, all I/O pins are configured as analog inputs by firmware.
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states
from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2<