UC384(2,3)B, UC284(2,3)B Datasheet

ON Semiconductor

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Datasheet

© Semiconductor Components Industries, LLC, 2013
September, 2013 Rev. 17
1Publication Order Number:
UC3842B/D
UC3842B, UC3843B,
UC2842B, UC2843B
High Performance
Current Mode Controllers
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
OffLine and DCDC converter applications offering the designer a
costeffective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cyclebycycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8pin dualinline and surface
mount (SOIC8) plastic package as well as the 14pin plastic surface
mount (SOIC14). The SOIC14 package has separate power and
ground pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for offline converters. The UCX843B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
Trimmed Oscillator for Precise Frequency Control
Oscillator Frequency Guaranteed at 250 kHz
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Latching PWM for CycleByCycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
This is a PbFree and HalideFree Device
Figure 1. Simplified Block Diagram
5.0V
Reference
Latching
PWM
VCC
Undervoltage
Lockout
Oscillator
Error
Amplifier
7(12)
VC
7(11)
Output
6(10)
Power
Ground
5(8)
3(5)
Current
Sense
Input
Vref
8(14)
4(7)
2(3)
1(1) GND 5(9)
RT/CT
Voltage
Feedback
Input
R
R
+
-
Vref
Undervoltage
Lockout
Output
Compensation
Pin numbers in parenthesis are for the D suffix SOIC14 package.
VCC
14
SOIC14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 19 of this data sheet.
DEVICE MARKING INFORMATION
1
8
PDIP8
N SUFFIX
CASE 626
PIN CONNECTIONS
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
Compensation
Voltage Feedback
Current Sense
RT/CT
Vref
Vref
NC
VCC
VC
Output
GND
Power Ground
VCC
Output
GND
(Top View)
8
7
6
5
1
2
3
4
1
2
3
4
14
13
12
11
5
6
7
10
9
8
(Top View)
SOIC8
D1 SUFFIX
CASE 751
1
8
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MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC30 V
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink IO1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 mJ
Current Sense, Voltage Feedback, Vref and Rt/Ct Inputs Vin 0.3 to + 5.5 V
Compensation Vcomp 0.3 to + 7.2 V
Output Vo0.3 to VCC or
VC + 0.3
V
Error Amp Output Sink Current IO10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, JunctiontoAir
D1 Suffix, Plastic Package, SOIC8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, JunctiontoAir
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, JunctiontoAir
PD
RqJA
PD
RqJA
PD
RqJA
862
145
702
178
1.25
100
mW
°C/W
mW
°C/W
W
°C/W
Operating Junction Temperature TJ+150 °C
Operating Ambient Temperature
UC3842B, UC3843B
UC2842B, UC2843B
UC2843D
UC3842BV, UC3843BV
TA
0 to 70
25 to + 85
40 to +85
40 to +105
°C
Storage Temperature Range Tstg 65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC Standard JESD22-A114B
Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
UC3842B, UC3843B, UC2842B, UC2843B
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
UC284XB, UC2843D UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline 2.0 20 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload 3.0 25 3.0 25 mV
Temperature Stability TS0.2 0.2 mV/°C
Total Output Variation over Line, Load, and Temperature
UC284XB
UC2843D
Vref
4.9
4.82
5.1
5.18
4.82 5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn50 50 mV
Long Term Stability (TA = 125°C for 1000 Hours) S5.0 5.0 mV
Output Short Circuit Current ISC 30 85 180 30 85 180 mA
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
fOSC
49
48
225
52
250
55
56
275
49
48
225
52
250
55
56
275
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V) DfOSC/DV0.2 1.0 0.2 1.0 %
Frequency Change with Temperature, TA = Tlow to Thigh DfOSC/DT1.0 0.5 %
Oscillator Voltage Swing (PeaktoPeak) VOSC 1.6 1.6 V
Discharge Current (VOSC = 2.0 V)
TJ = 25°C, TA = Tlow to Thigh
UC284XB, UC384XB
UC2843D, UC384XBV
Idischg
7.8
7.5
8.3
8.8
8.8
7.8
7.6
7.2
8.3
8.8
8.8
8.8
mA
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) UC284XB
UC2843D
VFB 2.45
2.42
2.5
2.5
2.55
2.58
2.42 2.5 2.58 V
Input Bias Current (VFB = 5.0 V) IIB 0.1 1.0 0.1 2.0 mA
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 65 90 dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 0.7 1.0 MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 60 70 dB
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
ISink
ISource
2.0
0.5
12
1.0
2.0
0.5
12
1.0
mA
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
UC284XB, UC384XB
UC2843D, UC384XBV
VOH
VOL
5.0
6.2
0.8
1.1
5.0
6.2
0.8
0.8
1.1
1.2
V
3. Adjust VCC above the Startup threshold before setting to 15 V.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; 25°C for UC2842B, UC2843B; 40°C for UC3842BV, UC3843BV, UC2843D
Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV
UC3842B, UC3843B, UC2842B, UC2843B
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ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
UC284XB, UC2843D UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 5 and 6)
UC2843D, UC284XB, UC384XB
UC384XBV
AV
2.85
3.0
3.15
2.85
2.85
3.0
3.0
3.15
3.25
V/V
Maximum Current Sense Input Threshold (Note 5)
UC2843D, UC284XB, UC384XB
UC384XBV
Vth
0.9
1.0
1.1
0.9
0.85
1.0
1.0
1.1
1.1
V
Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5) PSRR 70 70 dB
Input Bias Current IIB 2.0 10 2.0 10 mA
Propagation Delay (Current Sense Input to Output) tPLH(In/Out) 150 300 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA) UC284XB, UC384XB
UC384XBV, UC2843D
High State (ISource = 20 mA) UC284XB, UC384XB
UC384XBV, UC2843D
(ISource = 200 mA)
VOL
VOH
13
12
0.1
1.6
13.5
13.4
0.4
2.2
13
12.9
12
0.1
1.6
1.6
13.5
13.5
13.4
0.4
2.2
2.3
V
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) 0.1 1.1 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr50 150 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf50 150 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC)
UCX842B, BV
UCX843B, BV, D
Vth
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
V
Minimum Operating Voltage After TurnOn (VCC)
UCX842B, BV
UCX843B, BV, D
VCC(min)
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
V
PWM SECTION
Duty Cycle
Maximum UC284XB, UC384XB, UC2843D
Maximum UC384XBV
Minimum
DC(max)
DC(min)
94
96
0
94
93
96
96
0
%
TOTAL DEVICE
Power Supply Current
Startup (VCC = 6.5 V for UCX843B, UC2843D
Startup VCC 14 V for UCX842B, BV)
(Note 7)
ICC + IC
0.3
12
0.5
17
0.3
12
0.5
17
mA
Power Supply Zener Voltage (ICC = 25 mA) VZ30 36 30 36 V
5. This parameter is measured at the latch trip point with VFB = 0 V.
6. Comparator gain is defined as: AVDV Output Compensation
DV Current Sense Input
7. Adjust VCC above the Startup threshold before setting to 15 V.
8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; 25°C for UC2842B, UC2843B; 40°C for UC3842BV, UC3843BV, UC2843D
Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV
UC3842B, UC3843B, UC2842B, UC2843B
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5
0.8
2.0
5.0
8.0
20
50
80
RT, TIMING RESISTOR (k )
Ω
1.0 M500 k200 k100 k50 k20 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
VCC = 15 V
TA = 25°C
Figure 2. Timing Resistor
versus Oscillator Frequency
Figure 3. Output Deadtime
versus Oscillator Frequency
1.0 M500 k200 k100 k50 k20 k10 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0
2.0
5.0
10
20
50
100
% DT, PERCENT OUTPUT DEADTIME
1
2
Figure 4. Oscillator Discharge Current
versus Temperature
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
, DISCHARGE CURRENT (mA)
7.0
-55
TA, AMBIENT TEMPERATURE (°C)
-25 0 25 50 75 100 125
dischg
I
7.5
8.0
8.5
9.0
VCC = 15 V
VOSC = 2.0 V
, MAXIMUM OUTPUT DUTY CYCLE (%)
max
D
400.8
RT, TIMING RESISTOR (kW)
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
50
60
70
80
90
100
VCC = 15 V
CT = 3.3 nF
TA = 25°C
1. CT = 10 nF
2. CT = 5.0 nF
3. CT = 2.0 nF
4. CT = 1.0 nF
5. CT = 500 pF
6. CT = 200 pF
7. CT = 100 pF
5
Idischg = 8.54 mA
7
3
6
4
VCC = 15 V
TA = 25°C
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
1.0 ms/DIV0.5 ms/DIV
20 mV/DIV
20 mV/DIV
2.55 V
2.50 V
2.45 V
3.0 V
2.5 V
2.0 V
VCC = 15 V
AV = -1.0
TA = 25°C
VCC = 15 V
AV = -1.0
TA = 25°C
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Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
-20
AVOL , OPEN LOOP VOLTAGE GAIN (dB)
10 M10
f, FREQUENCY (Hz)
Gain
Phase
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
0
30
60
90
120
150
180
100 1.0 k 10 k 100 k 1.0 M
0
20
40
60
80
100
, EXCESS PHASE (DEGREES)
φ
0
VO, ERROR AMP OUTPUT VOLTAGE (V)
0
, CURRENT SENSE INPUT THRESHOLD (V)
Vth
0.2
0.4
0.6
0.8
1.0
1.2
2.0 4.0 6.0 8.0
VCC = 15 V
TA = 25°C
TA = -55°C
TA = 125°C
VCC = 15 V
TA = -55°C
TA = 25°C
, REFERENCE VOLTAGE CHANGE (mV)
-16
0
Iref, REFERENCE SOURCE CURRENT (mA)
20 40 60 80 100 120
ref
V
-12
-8.0
-4.0
0
Δ
-20
-24
TA = 125°C
VCC = 15 V
RL 0.1 W
, REFERENCE SHORT CIRCUIT CURRENT (mA)
SC
I
50
-55
TA, AMBIENT TEMPERATURE (°C)
-25 0 25 50 75 100 125
70
90
110
Figure 12. Reference Load Regulation Figure 13. Reference Line Regulation
2.0 ms/DIV 2.0 ms/DIV
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
VCC = 12 V to 25
TA = 25°C
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VO
Δ
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VO
Δ
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Sink Saturation
(Load to VCC)
TA = -55°C
VCC
Source Saturation
(Load to Ground)
0
Vsat, OUTPUT SATURATION VOLTAGE (V)
8000
IO, OUTPUT LOAD CURRENT (mA)
200 400 600
1.0
2.0
3.0
-2.0
-1.0
0
TA = -55°C
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage
TA = 25°C
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
, SUPPLY CURRENT (mA)
CC
I
00
VCC, SUPPLY VOLTAGE (V)
10 20 30 40
5
10
15
20
25
UCX843B
UCX842B
TA = 25°C
GND
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
VCC = 30 V
CL = 15 pF
TA = 25°C
VCC = 15 V
CL = 1.0 nF
TA = 25°C
50 ns/DIV
100 ns/DIV
100 mA/DIV 20 V/DIV
90%
10%
, OUTPUT VOLTAGE
O
V, SUPPLY CURRENT
CC
I
PIN FUNCTION DESCRIPTION
8Pin 14Pin Function Description
1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 3 Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3 5 Current
Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CTThe Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5 GND This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT
.
8 Power
Ground
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
11 VCThe Output high state (VOH) is set by the voltage applied to this pin. With a separate power
source connection, it can reduce the effects of switching transient noise on the control circuitry.
9 GND This pin is the control circuitry ground return and is connected back to the power source ground.
2,4,6,1
3
NC No connection. These pins are not internally connected.
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OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for OffLine and DCtoDC
converter applications offering the designer a costeffective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Oscillator
The oscillator frequency is programmed by the values
chosen for the timing components RT and CT. It must also be
noted that the value of RT uniquely determines the
maximum duty ratio of UC384xx. The oscillator
configuration depicting the connection of the timing
components to the RT/CT pin of the controller is shown in
Figure 18. Capacitor CT gets charged from the Vref source,
through resistor RT to its peak threshold VRT/CT(peak),
typically 2.8 V. Upon reaching this peak threshold volage, an
internal 8.3 mA current source, Idischg, is enabled and the
voltage across CT begins to decrease. Once the voltage
across CT reaches its valley threshold, VRT/CT(valley),
typically 1.2 V, Idischg turns off. This allows capacitor CT to
charge up again from Vref. This entire cycle repeats, and the
resulting waveform on the RT/CT pin has a sawtooth shape.
Typical waveforms are shown in Figure 20.
The oscillator thresholds are temperature compensated to
within ±6% at 50 kHz. Considering the general industry
trend of operating switching controllers at higher
frequencies, the UC384xx is guaranteed to operate within
±10% at 250 kHz. These internal circuit refinements
minimize variations of oscillator frequency and maximum
duty ratio.
The charging and discharging times of the timing
capacitor CT are calculated using Equations 1 and 2. These
equations do not take into account the propagation delays of
the internal comparator. Hence, at higher frequencies, the
calculated value of the oscillator frequency differs from the
actual value.
tRTńCT(chg) +RTCTlnǒVRTńCT(valley) *Vref
VRTńCT(peak) *Vref Ǔ(eq. 1)
tRTńCT(dischg) +RTCTlnǒRTIdischg )VRTńCT(peak) *Vref
RTIdischg )VRTńCT(valley) *VrefǓ
(eq. 2)
The maximum duty ratio, Dmax is given by Equation 3.
Dmax +tRTńCT(chg)
tRTńCT(chg) )tRTńCT(dischg)
(eq. 3)
Substituting Equations 1 and 2 into Equation 3, and after
algebraic simplification, we obtain
Dmax +
lnǒVRTńCT(valley)*Vref
VRTńCT(peak)*Vref Ǔ
lnǒVRTńCT(valley)*Vref
VRTńCT(peak)*Vref @
RTIdischg)VRTńCT(peak)*Vref
RTIdischg)VRTńCT(valley)*VrefǓ
(eq. 4)
Clearly, the maximum duty ratio is determined by the
timing resistor RT. Therefore, RT is chosen such as to
achieve a desired maximum duty ratio. Once RT has been
selected, CT can now be chosen to obtain the desired
switching frequency as per Equation 5.
f+1
RTCTlnǒVRTńCT(valley)*Vref
VRTńCT(peak)*Vref @
RTIdischg)VRTńCT(peak)*Vref
RTIdischg)VRTńCT(valley)*VrefǓ
(eq. 5)
Figure 2 shows the frequency and maximum duty ratio
variation versus RT for given values of CT. Care should be
taken to ensure that the absolute minimum value of RT
should not be less than 542 W. However, considering a 10%
tolerance for the timing resistor, the nearest available
standard resistor of 680 W is the absolute minimum that can
be used to guarantee normal oscillator operation. If a timing
resistor smaller than this value is used, then the charging
current through the RT, CT path will exceed the pulldown
(discharge) current and the oscillator will get permanently
locked/latched to an undefined state.
In many noise-sensitive applications it may be desirable
to frequency-lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 22. For reliable synchronization, the
free-running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi-unit
synchronization is shown in Figure 23. By tailoring the
clock waveform, accurate Output duty ratio clamping can be
achieved.
Enable Idischg
Vref
RT/CT
RT
CT
2.8 V
1.2 V
Figure 18. Oscillator Configuration
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Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
DC voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is 2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 33). The output voltage is offset
by two diode drops (1.4 V) and divided by three before it
connects to the noninverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
is removed, or at the beginning of a softstart interval
(Figures 25, 26). The Error Amp minimum feedback
resistance is limited by the amplifiers source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparators 1.0 V clamp level:
Rf(min) 3.0 (1.0 V) + 1.4 V
0.5 mA = 8800 W
Current Sense Comparator and PWM Latch
The UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cyclebycycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
groundreferenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
Ipk = V(Pin 1) 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) = 1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 24. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 28).
UC3842B, UC3843B, UC2842B, UC2843B
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+
-
Reference
Regulator
VCC
UVLO
+
-Vref
UVLO
3.6V
36V
S
R
Q
Internal
Bias
+1.0mA
Oscillator
2.5V
R
R
R
2R
Error
Amplifier
Voltage
Feedback
Input
Output/
Compensation Current Sense
Comparator
1.0V
VCC 7(12)
GND 5(9)
VC
7(11)
Output
6(10)
Power Ground
5(8)
Current Sense Input
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
RT
CT
Vref
= Sink Only Positive True Logic
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package.
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
Figure 19. Representative Block Diagram
Figure 20. Timing Diagram
Large RT/Small CTSmall RT/Large CT
PWM
Latch
(See
Text)
Capacitor CT
Latch
“Set" Input
Output/
Compensation
Current Sense
Input
Latch
“Reset" Input
Output
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Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has builtin
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in offline converter applications where
efficient bootstrap startup techniques are required
(Figure 35). The UCX843B is intended for lower voltage
DCtoDC converter applications. A 36 V Zener is
connected as a shunt regulator from VCC to ground. Its
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (VCC) for the UCX842B is 11 V and 8.2 V for the
UCX843B.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pulldown resistor.
The SOIC14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 27 shows proper
power and control ground connections in a currentsensing
power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wirewrap or plugin prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulsewidth jitter. This is usually caused by excessive noise
pickup imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with lowcurrent signal and
highcurrent switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noisegenerating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 21A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turnon (t2) is increased
by DI + DI m2/m1. The minimum current at the next cycle
(t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation
is multiplied by m2/m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turnon. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 21B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 34).
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Figure 21. Continuous Current Waveforms
2(3) EA
Bias
+
Osc
R
R
R
2R
5(9)
1(1)
4(7)
8(14)
RT
CT
Vref
0.01
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of CT to go more than 300 mV below ground.
External
Sync
Input
47
+
R
R
R
2R
Bias
Osc
EA
5(9)
1(1)
2(3)
4(7)
8(14)
To Additional
UCX84XBs
R
S
Q
8 4
6
5
2
1
C
3
7
RA
RB5.0k
5.0k
5.0k MC1455
f +1.44
(RA)2R
B)C D(max) +RB
RA)2R
B
+
-
5.0V Ref
+
-
S
R
Q
Bias
+
Osc
R
R
R
2R
EA
1.0V
5(9)
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
R1
VClamp
R2
7(12)
Comp/Latch
1.0 mA
Ipk(max)[VClamp
RS
Where: 0 VClamp 1.0 V
VClamp
1.67
ǒR2
R1)1Ǔ+ 0.33x10-3 ǒR1R2
R1)R2Ǔ
Control Voltage
Inductor
Current
Oscillator Period
Control Voltage
Inductor
Current
Oscillator Period
(A)
(B)
m1m2
t0t1t2t3
m3
m2
t4t5t6
DI
m1
DI
Dl)Dlm2
m1Dl)Dlm2
m1 m2
m1
Figure 22. External Clock Synchronization
Figure 23. External Duty Cycle Clamp and
MultiUnit Synchronization
Figure 24. Adjustable Reduction of Clamp Level
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+
-
+
-
S
R
+
R
R
R
2R
VClamp [1.67
ǒR2
R1)1Ǔ
Ipk(max)[VClamp
RS
5.0V Ref
Q
Bias
Osc
EA
1.0V
5(9)
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
1(1)
2(3)
4(7)
8(14)
R1
VClamp
R2
Where: 0 VClamp 1.0 V
CMPSA63
tSoftStart +*Inƪ1*VC
3VClampƫC R1R2
R1)R
2
7(12)
1.0 mA
Comp/Latch
5.0V Ref
+
-
S
R
Q
Bias
+
1.0mA
Osc
R
R
R
2R
EA 1.0V
5(9)
1(1)
2(3)
4(7)
8(14)
C
1.0M
tSoft-Start 3600C in mF
Figure 25. SoftStart Circuit Figure 26. Adjustable Buffered Reduction of
Clamp Level with SoftStart
+
-
5.0V Ref
+
-
S
R
Q
(11)
(10)
(8)
Comp/Latch
(5) RS
1/4 W
VCC Vin
K
M
DSENSEFET
G
S
Power Ground:
To Input Source
Return
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 24 and 26.
VPin 5 [RSIpk rDS(on)
rDM(on) )RS
If: SENSEFET = MTP10N10M
RS = 200
Then : VPin5[ 0.075Ipk
(12)
Figure 27. Current Sensing Power MOSFET
+
-
5.0V Ref
+
-
S
R
Q
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC Vin
C
R
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
7(12)
Comp/Latch
Figure 28. Current Waveform Spike Suppression
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Figure 29. MOSFET Parasitic Oscillations
6(10)
5(8)
3(5) RS
Q1
Vin
C1
Base Charge
Removal
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C1.
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5)
RS
Q1
VCC
IB
+
-
0
Vin
Isolation
Boundary
VGS Waveforms
+
-
0
+
-
0
50% DC 25% DC
Ipk+V(Pin1) *1.4
3RSǒNS
NpǓ
Comp/Latch
7(12)
R
CNSNP
+
-
+
-
Bias
+
Osc
R
R
R
2R
EA
5(9)
1(1)
2(3)
4(7)
8(14)
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
MCR
101
2N
3905
2N
3903
1.0 mA
S
R
5.0V Ref
Q
7(11)
6(10)
5(8)
3(5) RS
Q1
VCC Vin
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
7(12)
Rg
Comp/Latch
+
-
+
-
Figure 30. Bipolar Transistor Drive
Figure 31. Isolated MOSFET Drive Figure 32. Latched Shutdown
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+
-
+
-
5.0V Ref
36V
S
RQ
Bias
+
1.0mA
Osc
R
R
R
2R
EA 1.0V
7(12)
7(11)
6(10)
5(8)
3(5) RS
VCC Vin
1(1)
2(3)
4(7)
8(14)
RT
CT
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
m
- 3.0m
-m
Rf
Cf
Ri
Rd
From VORSlope
MPS3904
5(9)
Comp/Latch
Figure 33. Error Amplifier Compensation
+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
Rf
Cf
Rd
Ri
From VO
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
Rf 8.8 k
+
R
2R
1.0mA
EA
2(3)
5(9)
2.5V
1(1)
Rf
Cf
Rd
Rp
From VO
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
Cp
Ri
Figure 34. Slope Compensation
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Figure 35. 27 W OffLine Flyback Regulator
MUR110
+
-
+
-
S
R
+
R
R
5.0V Ref
Q
Bias
EA
5(9)
7(11)
6(10)
5(8)
3(5) 0.5
MTP
4N50
1(1)
2(3)
4(7)
8(14)
10k
4700pF
470pF
150k
100
pF
18k
4.7k
0.01
100
+
1.0k
115 Vac
4.7WMDA
202
250
56k
4.7k 3300
pF
1N4935 1N4935
++
68
47
1N4937
1N4937
680pF
2.7k
L3
L2
L1
++
++
++
1000
1000
2200
10
10
1000
5.0V/4.0A
5.0V RTN
12V/0.3A
±12V RTN
-12V/0.3A
Primary: 45 Turns #26 AWG
Secondary ±12 V: 9 Turns #30 AWG
(2 Strands) Bifiliar Wound
Secondary 5.0 V: 4 Turns (six strands)
#26 Hexfiliar Wound
Secondary Feedback: 10 Turns
#30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin: Ferroxcube EC35PCB1
Gap: 0.10" for a primary inductance
of 1.0 mH
MUR110
MBR1635
T1
22
Osc
T1 -
7(12)
Comp/Latch
L1
L2, L3
- 15 mH at 5.0 A, Coilcraft Z7156
- 25 mH at 5.0 A, Coilcraft Z7157
1N5819
Test Conditions Results
Line Regulation: 5.0 V
±12 V
Vin = 95 to 130 Vac D = 50 mV or ±0.5%
D = 24 mV or ±0.1%
Load Regulation: 5.0 V
±12 V
Vin = 115 Vac,
Iout = 1.0 A to 4.0 A
Vin = 115 Vac,
Iout = 100 mA to 300 mA
D = 300 mV or ±3.0%
D = 60 mV or ±0.25%
Output Ripple: 5.0 V
±12 V
Vin = 115 Vac 40 mVpp
80 mVpp
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents, unless otherwise noted
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ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
UC2842BDG
TA = 25° to +85°C
SOIC14
(PbFree)
55 Units/Rail
UC2842BD1G SOIC8
(PbFree)
98 Units/Rail
UC2842BD1R2G SOIC8
(PbFree)
2500 Tape & Reel
UC2842BNG PDIP8
(PbFree) 1000 Units/Rail
UC3842BNG
TA = 0° to +70°C
PDIP8
(PbFree) 1000 Units/Rail
UC3842BDG SOIC14
(PbFree)
55 Units/Rail
UC3842BDR2G SOIC14
(PbFree)
2500 Tape & Reel
UC3842BD1G SOIC8
(PbFree)
98 Units/Rail
UC3842BD1R2G SOIC8
(PbFree) 2500 Tape & Reel
UC3842BVDR2G
TA = 40° to +105°C
SOIC14
(PbFree) 2500 Tape & Reel
UC3842BVD1G SOIC8
(PbFree)
98 Units/Rail
UC3842BVD1R2G SOIC8
(PbFree)
2500 Tape & Reel
UC2843BDG
TA = 25° to +85°C
SOIC14
(PbFree)
55 Units/Rail
UC2843BDR2G SOIC14
(PbFree)
2500 Tape & Reel
UC2843BD1G SOIC8
(PbFree)
98 Units/Rail
UC2843BD1R2G
TA = 25° to +85°C
SOIC8
(PbFree)
2500 Tape & Reel
UC2843BNG PDIP8
(PbFree)
1000 Units/Rail
UC2843DD1R2G
TA = 40° to +85°C
SOIC8
(PbFree)
2500 Tape & Reel
UC2843DDR2G SOIC8
(PbFree)
2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
UC3843BDG
TA = 0° to +70°C
SOIC14
(PbFree)
55 Units/Rail
UC3843BDR2G SOIC14
(PbFree)
2500 Tape & Reel
UC3843BD1G SOIC8
(PbFree)
98 Units/Rail
UC3843BD1R2G SOIC8
(PbFree) 2500 Tape & Reel
UC3843BDR2G SOIC14
(PbFree) 2500 Tape & Reel
UC3843BNG PDIP8
(PbFree)
1000 Units/Rail
UC3843BVDG
TA = 40° to +105°C
SOIC14
(PbFree)
55 Units/Rail
UC3843BVDR2G SOIC14
(PbFree)
2500 Tape & Reel
UC3843BVD1G SOIC8
(PbFree)
98 Units/Rail
UC3843BVD1R2G SOIC8
(PbFree)
2500 Tape & Reel
UC3843BVNG PDIP8
(PbFree)
1000 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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SOIC14
D SUFFIX
CASE 751A
SOIC8
D1 SUFFIX
CASE 751
MARKING DIAGRAMS
PDIP8
N SUFFIX
CASE 626
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= PbFree Package
UC3843BVN
AWL
YYWWG
1
8
UC384xBVDG
AWLYWW
1
14
384xB
ALYWV
G
1
8
UC384xBN
AWL
YYWWG
1
8
UC284xBN
AWL
YYWWG
1
8
UC384xBDG
AWLYWW
1
14
UC284xBDG
AWLYWW
1
14
384xB
ALYW
G
1
8
284xB
ALYW
G
1
8
UC2843DDG
AWLYWW
1
14
2843D
ALYW
G
1
8
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PACKAGE DIMENSIONS
PDIP8
N SUFFIX
CASE 62605
ISSUE N
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
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PACKAGE DIMENSIONS
SOIC8
D1 SUFFIX
CASE 75107
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
UC3842B, UC3843B, UC2842B, UC2843B
http://onsemi.com
22
PACKAGE DIMENSIONS
SOIC14
D SUFFIX
CASE 751A03
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
A
B
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
T
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
7X
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