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MT47Hxx(x)M4/8/16 Datasheet

Micron Technology Inc.

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Datasheet

DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
Features
•V
DD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
•4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Selectable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
• RoHS-compliant
Supports JEDEC clock jitter specification
Options1Marking
Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
FBGA package (Pb-free) – x16
84-ball FBGA (8mm x 12.5mm) Rev. G HR
84-ball FBGA (8mm x 12.5mm) Rev. H NF
FBGA package (Pb-free) – x4, x8
60-ball FBGA (8mm x 10mm) Rev. G CF
60-ball FBGA (8mm x 10mm) Rev. H SH
FBGA package (lead solder) – x16
84-ball FBGA (8mm x 12.5mm) Rev. G HW
FBGA package (lead solder) – x4, x8
60-ball FBGA (8mm x 10mm) Rev. G JN
Timing – cycle time
1.875ns @ CL = 7 (DDR2-1066) -187E
2.5ns @ CL = 5 (DDR2-800) -25E
3.0ns @ CL = 5 (DDR2-667) -3
Self refresh
– Standard None
– Low-power L
Operating temperature
Commercial (0°C TC +85°C)2None
Industrial (–40°C TC +95°C;
–40°C TA +85°C)
IT
• Revision :G/:H
Notes: 1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
2. For extended CT operating temperature,
see Table 11 (page 29), Note 7.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
tRC (ns)CL = 3 CL = 4 CL = 5 CL = 6 CL = 7
-187E 400 533 800 800 1066 54
-25E 400 533 800 800 n/a 55
-3 400 533 667 n/a n/a 55
512Mb: x4, x8, x16 DDR2 SDRAM
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2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing
Parameter 128 Meg x 4 64 Meg x 8 32 Meg x 16
Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh count 8K 8K 8K
Row address A[13:0] (16K) A[13:0] (16K) A[12:0] (8K)
Bank address BA[1:0] (4) BA[1:0] (4) BA[1:0] (4)
Column address A[11, 9:0] (2K) A[9:0] (1K) A[9:0] (1K)
Figure 1: 512Mb DDR2 Part Numbers
Example Part Number: MT47H128M4SH-25E:H
Configuration
128 Meg x 4
64 Meg x 8
32 Meg x 16
128M4
64M8
32M16
Speed Grade
tCK = 3ns, CL = 5
tCK = 2.5ns, CL = 5
-3
-25E
-
Configuration
MT47H Package Speed
Revision
:
^
Low power
Industrial temperature
L
IT
Revision
:G/:H
tCK = 1.875ns, CL = 7-187E
Package
Pb-free
84-ball 8mm x 12.5mm FBGA
60-ball 8mm x 10.0mm FBGA
60-ball 8mm x 10.0mm FBGA
Lead solder
84-ball 8mm x 12.5mm FBGA
60-ball 8mm x 10mm FBGA
HR
SH
CF
HW
JN
84-ball 8mm x 12.5mm FBGA
NF
Note: 1. Not all speeds and configurations are available in all packages.
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
512Mb: x4, x8, x16 DDR2 SDRAM
Features
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2004 Micron Technology, Inc. All rights reserved.
Contents
State Diagram .................................................................................................................................................. 8
Functional Description ..................................................................................................................................... 9
Industrial Temperature ................................................................................................................................. 9
General Notes ............................................................................................................................................ 10
Functional Block Diagrams ............................................................................................................................. 11
Ball Assignments and Descriptions ................................................................................................................. 13
Packaging ...................................................................................................................................................... 17
Package Dimensions ................................................................................................................................... 17
FBGA Package Capacitance ......................................................................................................................... 21
Electrical Specifications – Absolute Ratings ..................................................................................................... 22
Temperature and Thermal Impedance ........................................................................................................ 22
Electrical Specifications – IDD Parameters ........................................................................................................ 25
IDD Specifications and Conditions ............................................................................................................... 25
IDD7 Conditions .......................................................................................................................................... 25
AC Timing Operating Specifications ................................................................................................................ 32
AC and DC Operating Conditions .................................................................................................................... 44
ODT DC Electrical Characteristics ................................................................................................................... 44
Input Electrical Characteristics and Operating Conditions ............................................................................... 45
Output Electrical Characteristics and Operating Conditions ............................................................................. 48
Output Driver Characteristics ......................................................................................................................... 50
Power and Ground Clamp Characteristics ....................................................................................................... 54
AC Overshoot/Undershoot Specification ......................................................................................................... 55
Input Slew Rate Derating ................................................................................................................................ 57
Commands .................................................................................................................................................... 70
Truth Tables ............................................................................................................................................... 70
DESELECT ................................................................................................................................................. 74
NO OPERATION (NOP) ............................................................................................................................... 75
LOAD MODE (LM) ...................................................................................................................................... 75
ACTIVATE .................................................................................................................................................. 75
READ ......................................................................................................................................................... 75
WRITE ....................................................................................................................................................... 75
PRECHARGE .............................................................................................................................................. 76
REFRESH ................................................................................................................................................... 76
SELF REFRESH ........................................................................................................................................... 76
Mode Register (MR) ........................................................................................................................................ 76
Burst Length .............................................................................................................................................. 77
Burst Type .................................................................................................................................................. 78
Operating Mode ......................................................................................................................................... 78
DLL RESET ................................................................................................................................................. 78
Write Recovery ........................................................................................................................................... 79
Power-Down Mode ..................................................................................................................................... 79
CAS Latency (CL) ........................................................................................................................................ 80
Extended Mode Register (EMR) ....................................................................................................................... 81
DLL Enable/Disable ................................................................................................................................... 82
Output Drive Strength ................................................................................................................................ 82
DQS# Enable/Disable ................................................................................................................................. 82
RDQS Enable/Disable ................................................................................................................................. 82
Output Enable/Disable ............................................................................................................................... 82
On-Die Termination (ODT) ......................................................................................................................... 83
Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 83
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Posted CAS Additive Latency (AL) ................................................................................................................ 83
Extended Mode Register 2 (EMR2) ................................................................................................................... 85
Extended Mode Register 3 (EMR3) ................................................................................................................... 86
Initialization .................................................................................................................................................. 87
ACTIVATE ...................................................................................................................................................... 90
READ ............................................................................................................................................................. 92
READ with Precharge .................................................................................................................................. 96
READ with Auto Precharge .......................................................................................................................... 98
WRITE .......................................................................................................................................................... 103
PRECHARGE ................................................................................................................................................. 113
REFRESH ...................................................................................................................................................... 114
SELF REFRESH .............................................................................................................................................. 115
Power-Down Mode ........................................................................................................................................ 117
Precharge Power-Down Clock Frequency Change ........................................................................................... 124
Reset ............................................................................................................................................................. 125
CKE Low Anytime ...................................................................................................................................... 125
ODT Timing .................................................................................................................................................. 127
MRS Command to ODT Update Delay ........................................................................................................ 129
512Mb: x4, x8, x16 DDR2 SDRAM
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List of Figures
Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 11
Figure 4: 64 Meg x 8 Functional Block Diagram ............................................................................................... 12
Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 12
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 13
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 14
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16; Die Rev. :G .............................................................................. 17
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8; Die Rev. :G ............................................................................. 18
Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16; "NF" Die Rev. :H .................................................................... 19
Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev. :H ................................................................... 20
Figure 12: Example Temperature Test Point Location ...................................................................................... 23
Figure 13: Single-Ended Input Signal Levels ................................................................................................... 45
Figure 14: Differential Input Signal Levels ...................................................................................................... 46
Figure 15: Differential Output Signal Levels .................................................................................................... 48
Figure 16: Output Slew Rate Load .................................................................................................................. 49
Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 50
Figure 18: Full Strength Pull-Up Characteristics .............................................................................................. 51
Figure 19: Reduced Strength Pull-Down Characteristics .................................................................................. 52
Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 53
Figure 21: Input Clamp Characteristics .......................................................................................................... 54
Figure 22: Overshoot ..................................................................................................................................... 55
Figure 23: Undershoot ................................................................................................................................... 55
Figure 24: Nominal Slew Rate for tIS ............................................................................................................... 60
Figure 25: Tangent Line for tIS ........................................................................................................................ 60
Figure 26: Nominal Slew Rate for tIH .............................................................................................................. 61
Figure 27: Tangent Line for tIH ....................................................................................................................... 61
Figure 28: Nominal Slew Rate for tDS ............................................................................................................. 66
Figure 29: Tangent Line for tDS ...................................................................................................................... 66
Figure 30: Nominal Slew Rate for tDH ............................................................................................................. 67
Figure 31: Tangent Line for tDH ..................................................................................................................... 67
Figure 32: AC Input Test Signal Waveform Command/Address Balls ................................................................ 68
Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 68
Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 69
Figure 35: AC Input Test Signal Waveform (Differential) .................................................................................. 69
Figure 36: MR Definition ............................................................................................................................... 77
Figure 37: CL ................................................................................................................................................. 80
Figure 38: EMR Definition ............................................................................................................................. 81
Figure 39: READ Latency ............................................................................................................................... 84
Figure 40: WRITE Latency .............................................................................................................................. 84
Figure 41: EMR2 Definition ........................................................................................................................... 85
Figure 42: EMR3 Definition ........................................................................................................................... 86
Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 87
Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 90
Figure 45: Multibank Activate Restriction ....................................................................................................... 91
Figure 46: READ Latency ............................................................................................................................... 93
Figure 47: Consecutive READ Bursts .............................................................................................................. 94
Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 95
Figure 49: READ Interrupted by READ ............................................................................................................ 96
Figure 50: READ-to-WRITE ............................................................................................................................ 96
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Figure 51: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 97
Figure 52: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 97
Figure 53: Bank Read – Without Auto Precharge .............................................................................................. 99
Figure 54: Bank Read – with Auto Precharge .................................................................................................. 100
Figure 55: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window .................................................. 101
Figure 56: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 102
Figure 57: Data Output Timing – tAC and tDQSCK ......................................................................................... 103
Figure 58: Write Burst ................................................................................................................................... 105
Figure 59: Consecutive WRITE-to-WRITE ...................................................................................................... 106
Figure 60: Nonconsecutive WRITE-to-WRITE ................................................................................................ 106
Figure 61: WRITE Interrupted by WRITE ....................................................................................................... 107
Figure 62: WRITE-to-READ ........................................................................................................................... 108
Figure 63: WRITE-to-PRECHARGE ................................................................................................................ 109
Figure 64: Bank Write – Without Auto Precharge ............................................................................................ 110
Figure 65: Bank Write – with Auto Precharge .................................................................................................. 111
Figure 66: WRITE – DM Operation ................................................................................................................ 112
Figure 67: Data Input Timing ........................................................................................................................ 113
Figure 68: Refresh Mode ............................................................................................................................... 114
Figure 69: Self Refresh .................................................................................................................................. 116
Figure 70: Power-Down ................................................................................................................................ 118
Figure 71: READ-to-Power-Down or Self Refresh Entry .................................................................................. 120
Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 120
Figure 73: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 121
Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 121
Figure 75: REFRESH Command-to-Power-Down Entry .................................................................................. 122
Figure 76: ACTIVATE Command-to-Power-Down Entry ................................................................................. 122
Figure 77: PRECHARGE Command-to-Power-Down Entry ............................................................................. 123
Figure 78: LOAD MODE Command-to-Power-Down Entry ............................................................................. 123
Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 124
Figure 80: RESET Function ........................................................................................................................... 126
Figure 81: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 128
Figure 82: Timing for MRS Command to ODT Update Delay .......................................................................... 129
Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 129
Figure 84: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 130
Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 130
Figure 86: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 131
Figure 87: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 132
Figure 88: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 133
512Mb: x4, x8, x16 DDR2 SDRAM
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List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 15
Table 4: Input Capacitance ............................................................................................................................ 21
Table 5: Absolute Maximum DC Ratings ......................................................................................................... 22
Table 6: Temperature Limits .......................................................................................................................... 23
Table 7: Thermal Impedance ......................................................................................................................... 23
Table 8: General IDD Parameters ..................................................................................................................... 25
Table 9: IDD7 Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 25
Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) ................................................................ 26
Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) ................................................................ 29
Table 12: AC Operating Specifications and Conditions .................................................................................... 32
Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 44
Table 14: ODT DC Electrical Characteristics ................................................................................................... 44
Table 15: Input DC Logic Levels ..................................................................................................................... 45
Table 16: Input AC Logic Levels ...................................................................................................................... 45
Table 17: Differential Input Logic Levels ......................................................................................................... 46
Table 18: Differential AC Output Parameters ................................................................................................... 48
Table 19: Output DC Current Drive ................................................................................................................ 48
Table 20: Output Characteristics .................................................................................................................... 49
Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 50
Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 51
Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 52
Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 53
Table 25: Input Clamp Characteristics ............................................................................................................ 54
Table 26: Address and Control Balls ................................................................................................................ 55
Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 55
Table 28: AC Input Test Conditions ................................................................................................................ 55
Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) .................................................... 58
Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) ........................................... 59
Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ...................................................... 62
Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................. 63
Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb ................................................... 64
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ...................................... 64
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ...................................... 65
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ...................................... 65
Table 37: Truth Table – DDR2 Commands ...................................................................................................... 70
Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 71
Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 73
Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 74
Table 41: Burst Definition .............................................................................................................................. 78
Table 42: READ Using Concurrent Auto Precharge .......................................................................................... 98
Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 104
Table 44: Truth Table – CKE .......................................................................................................................... 119
512Mb: x4, x8, x16 DDR2 SDRAM
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State Diagram
Figure 2: Simplified State Diagram
Automatic Sequence
Command Sequence
PRE
Initialization
sequence
Self
refreshing
CKE_L
Refreshing
Precharge
power-
down
Setting
MRS
EMRS
SR
CKE_H
REFRESH
Idle
all banks
precharged
CKE_L
CKE_L
CKE_L
(E)MRS
OCD
default
Activating
ACT
Bank
active
Reading
READ
Writing
WRITE
Active
power-
down
CKE_L
CKE_L
CKE_H
CKE_L
Writing
with
auto
precharge
Reading
with
auto
precharge
READ A
WRITE A
PRE, PRE_A
WRITE A
WRITE A
READ A
PRE , PRE_A
READ A
READ
WRITE
Precharging
CKE_H
WRITE READ
PRE, PRE_A
ACT = ACTIVATE
CKE_H = CKE HIGH, exit power-down or self refresh
CKE_L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
PRE = PRECHARGE
PRE_A = PRECHARGE ALL
READ = READ
READ A = READ with auto precharge
REFRESH = REFRESH
SR = SELF REFRESH
WRITE = WRITE
WRITE A = WRITE with auto precharge
Note: 1. This diagram provides the basic command flow. It is not comprehensive and does not
identify all timing requirements or possible command restrictions such as multibank in-
teraction, power down, entry/exit, etc.
512Mb: x4, x8, x16 DDR2 SDRAM
State Diagram
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Functional Description
The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture, with an
interface designed to transfer two data words per clock cycle at the I/O balls. A single
READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bit-
wide, two-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,
UDQS#).
The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The ad-
dress bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be en-
abled to provide a self-timed row precharge that is initiated at the end of the burst ac-
cess.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM
enables concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Industrial Temperature
The industrial temperature (IT) option, if offered, has two simultaneous requirements:
ambient temperature surrounding the device cannot be less than –40°C or greater than
85°C, and the case temperature cannot be less than –40°C or greater than 95°C. JEDEC
specifications require the refresh rate to double when TC exceeds 85°C; this also requires
use of the high-temperature self refresh option. Additionally, ODT resistance, input/
output impedance and IDD values must be derated when TC is < 0°C or > 85°C.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
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General Notes
The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.
For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the up-
per byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.
A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
Connect UDQS to ground via 1kΩ* resistor
Connect UDQS# to VDD via 1kΩ* resistor
Connect UDM to VDD via 1kΩ* resistor
Connect DQ[15:8] individually to either VSS or VDD via 1kΩ* resistors, or float
DQ[15:8].
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
Complete functionality is described throughout the document, and any page or dia-
gram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
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Functional Block Diagrams
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
Figure 3: 128 Meg x 4 Functional Block Diagram
14
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode
registers
11
Command
decode
A0–A13,
BA0, BA1
14
Address
register
16
512
(x16)
8,192
I/O gating
DM mask logic
Column
decoder
Bank0
Memory
array
(16,384 x 512 x 16)
Bank0
row-
address
latch and
decoder
16,384
Sense amplifiers
Bank
control
logic
16
Bank1
Bank2
Bank3
14
9
2
2
Refresh
counter
4
44
2
RCVRS
16
16
16
CK out
Data
DQS, DQS#
internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK in
DRVRS
DLL
MUX
DQS
generator
4
4
4
4
4
DQ0–DQ3
DQS, DQS#
2
Read
latch
Write
FIFO
and
drivers
Data
4
4
4
4
16
1
1
1
1
Mask
1
1
1
11
4
4
4
2
Bank1
Bank2
Bank3
Input
registers
DM
RAS#
CAS#
CK
CS#
WE#
CK#
CKE
ODT
VddQ
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT control
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Figure 4: 64 Meg x 8 Functional Block Diagram
14
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode
registers
10
Command
decode
A0–A13,
BA0, BA1
14
Address
register
16
256
(x32)
8,192
I/O gating
DM mask logic
Column
decoder
Bank 0
Memory
array
(16,384 x 256 x 32)
Bank 0
row-
address
latch and
decoder
16,384
Sense amplifiers
Bank
control
logic
16
Bank 1
Bank 2
Bank 3
14
8
2
2
Refresh
counter
8
88
2
RCVRS
32
32
32
CK out
Data
DQS, DQS#
internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK in
DRVRS
DLL
MUX
DQS
generator
8
8
8
8
8
DQ0–DQ7
DQS, DQS#
2
Read
latch
Write
FIFO
and
drivers
Data
8
8
8
8
32
1
1
1
1
Mask
1
1
1
11
4
8
8
2
Bank 1
Bank 2
Bank 3
Input
registers
DM
RDQS#
RAS#
CAS#
CK
CS#
WE#
CK#
CKE
ODT
RDQS
VddQ
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT control
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
Figure 5: 32 Meg x 16 Functional Block Diagram
13
Row-
address
MUX
Control
Logic
Column-
address
counter/
latch
Mode
registers
10
A0–A12,
BA0, BA1
13
Address
register
15
256
(x64)
16,384
I/O gating
DM mask logic
Column
decoder
Bank 0
Memory
array
(8,192 x 256 x 64)
Bank 0
row-
Address
latch and
decoder
8,192
Sense amplifiers
Bank
control
logic
15
Bank 1
Bank 2
Bank 3
13
8
2
2
Refresh
counter
16
16
16
4
64
64
64
CK out
Data
UDQS, UDQS#
LDQS, LDQS#
Internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK in
DLL
MUX
DQS
generator
16
16
16
16
16
UDQS, UDQS#
LDQS, LDQS#
4
Read
latch
Write
FIFO
and
drivers
Data
16
16
16
16
64
2
2
2
2
Mask
2
2
2
2
2
8
16
16
2
Bank 1
Bank 2
Bank 3
Input
registers
UDM, LDM
DQ0–DQ15
RAS#
CAS#
CK
CS#
WE#
CK#
Command
decode
CKE
ODT
DRVRS
RCVRS
VddQ
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT control
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Block Diagrams
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View)
1234 67895
VDD
NF, DQ6
VDDQ
NF, DQ4
VDDL
RFU
VSS
VDD
NF, RDQS#/NU
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
DM, DM/RDQS
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
RFU
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
RFU
VDDQ
NF, DQ7
VDDQ
NF, DQ5
VDD
ODT
VDD
VSS
DQS#/NU
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
A13
A
B
C
D
E
F
G
H
J
K
L
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
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512MbDDR2.pdf - Rev. Y 06/17 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)
1234 67895
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
RFU
VSS
VDD
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
RFU
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
RFU
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
UDQS#/NU
VSSQ
DQ8
VSSQ
LDQS#/NU
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
RFU
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions
Symbol Type Description
A[12:0] (x16)
A[13:0] (x4, x8)
Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[1:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
BA0, BA1 Input Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[1:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-
er-down (row active in any bank). CKE is synchronous for power-down entry, power-
down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-
FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once VDD is applied during first pow-
er-up. After VREF has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, VREF must be maintained.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered high. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
LDM, UDM, DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for
upper byte DQ[15:8].
ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
DQ[15:0] (x16)
DQ[3:0] (x4)
DQ[7:0] (x8)
I/O Data input/output: Bidirectional data bus for 32 Meg x 16.
Bidirectional data bus for 128 Meg x 4.
Bidirectional data bus for 64 Meg x 8.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
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512MbDDR2.pdf - Rev. Y 06/17 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)
Symbol Type Description
DQS, DQS# I/O Data strobe: Output with read data, input with write data for source synchronous oper-
ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with write data.
LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned with write data.
UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
RDQS, RDQS# Output Redundant data strobe: For 64 Meg x 8 only. RDQS is enabled/disabled via the load
mode command to the extended mode register (EMR). When RDQS is enabled, RDQS is
output with read data only and is ignored during write data. When RDQS is disabled, ball
B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and dif-
ferential data strobe mode is enabled.
VDD Supply Power supply: 1.8V ±0.1V.
VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
VDDL Supply DLL power supply: 1.8V ±0.1V.
VREF Supply SSTL_18 reference voltage (VDDQ/2).
VSS Supply Ground.
VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
NC No connect: These balls should be left unconnected.
NF No function: x8: these balls are used as DQ[7:4]; x4: they are no function.
NU Not used: If EMR(E10) = 0: x16, A8 = UDQS# and E8 = LDQS#; x8, A2 = RDQS# and A8 =
DQS#; x4, A2 = NU and A8 = NU. If EMR(E10) = 1: x16, A8 = NU and E8 = NU; x8, A2 = NU
and A8 = NU; x4, A2 = NU and A8 = NU.
RFU Reserved for future use: Bank address BA2, row address bits A13 (x16 only), A14, and
A15.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignments and Descriptions
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Packaging
Package Dimensions
Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16; Die Rev. :G
Ball A1 ID
1.2 MAX
8 ±0.1
Ball A1 ID
84X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.35 SMD
ball pads.
0.8 TYP
11.2 CTR 12.5 ±0.1
0.8 ±0.05
0.12 A A
Seating
plane
6.4 CTR
0.8
TYP 0.25 MIN
1.8 CTR
Nonconductive overmold
0.155
9 8 7 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note: 1. All dimensions are in millimeters.
512Mb: x4, x8, x16 DDR2 SDRAM
Packaging
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8; Die Rev. :G
Ball A1 ID
1.2 MAX
0.25 MIN
8 ±0.1
Ball A1 ID
60X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.35 SMD ball
pads.
0.8 TYP
0.8 TYP
8 CTR 10 ±0.1
0.8 ±0.05
0.12 A A
Seating
Plane
6.4 CTR
9 8 7 3 2 1
A
B
C
D
E
F
G
H
J
K
L
1.8 CTR
Nonconductive overmold
0.155
Note: 1. All dimensions are in millimeters.
512Mb: x4, x8, x16 DDR2 SDRAM
Packaging
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Figure 10: 84-Ball FBGA (8mm x 12.5mm) – x16; "NF" Die Rev. :H
1.8 CTR
Nonconductive
overmold
0.155
Seating plane
0.12 A
123789
Ball A1 ID
(covered by SR)
Ball A1 ID
A
0.28 MIN
1.1 ±0.1
6.4 CTR
8 ±0.1
0.8 TYP
11.2 CTR
12.5 ±0.1
84X Ø0.47
Dimensions apply
to solder balls
post-reflow on
Ø0.42 SMD ball pads.
0.8 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
512Mb: x4, x8, x16 DDR2 SDRAM
Packaging
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Figure 11: 60-Ball FBGA (8mm x 10mm) – x4, x8; "SH" Die Rev. :H
1.8 CTR
Nonconductive
overmold
0.155
Seating plane
0.12 A
123789
Ball A1 ID
(covered by SR) Ball A1 ID
A
0.28 MIN
1.1 ±0.1
6.4 CTR
8 ±0.1
0.8 TYP
8 CTR
10 ±0.1
60X Ø0.47
Dimensions
apply to solder
balls post-reflow
on Ø0.42 SMD
ball pads.
0.8 TYP
A
B
C
D
E
F
G
H
J
K
L
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
512Mb: x4, x8, x16 DDR2 SDRAM
Packaging
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
FBGA Package Capacitance
Table 4: Input Capacitance
Parameter Symbol Min Max Units Notes
Input capacitance: CK, CK# CCK 1.0 2.0 pF 1
Delta input capacitance: CK, CK# CDCK 0.25 pF 2, 3
Input capacitance: Address balls, bank address
balls, CS#, RAS#, CAS#, WE#, CKE, ODT
CI1.0 2.0 pF 1, 4
Delta input capacitance: Address balls, bank ad-
dress balls, CS#, RAS#, CAS#, WE#, CKE, ODT
CDI 0.25 pF 2, 3
Input/output capacitance: DQ, DQS, DM, NF CIO 2.5 4.0 pF 1, 5
Delta input/output capacitance: DQ, DQS, DM, NF CDIO 0.5 pF 2, 3
Notes: 1. This parameter is sampled. VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V, VREF = VSS, f = 100 MHz,
TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O
balls, reflecting the fact that they are matched in loading.
2. The capacitance per ball group will not differ by more than this maximum amount for
any given device.
3. ΔC are not pass/fail parameters; they are targets.
4. Reduce MAX limit by 0.25pF for -25 and -25E speed devices.
5. Reduce MAX limit by 0.5pF for -3, -3E, -5E, -25, -25E, and -37E speed devices.
512Mb: x4, x8, x16 DDR2 SDRAM
Packaging
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2004 Micron Technology, Inc. All rights reserved.
Electrical Specifications – Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions oustide those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 5: Absolute Maximum DC Ratings
Parameter Symbol Min Max Units Notes
VDD supply voltage relative to VSS VDD –1.0 2.3 V 1
VDDQ supply voltage relative to VSSQ VDDQ –0.5 2.3 V 1, 2
VDDL supply voltage relative to VSSL VDDL –0.5 2.3 V 1
Voltage on any ball relative to VSS VIN, VOUT –0.5 2.3 V 3
Input leakage current; any input 0V VIN VDD;
all other balls not under test = 0V
II–5 5 μA
Output leakage current; 0V VOUT VDDQ; DQ
and ODT disabled
IOZ –5 5 μA
VREF leakage current; VREF = valid VREF level IVREF –2 2 μA
Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times; this is not re-
quired when power is ramping down.
2. VREF 0.6 x VDDQ; however, VREF may be VDDQ provided that VREF 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 6 (page 23), be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances cor-
rectly. The thermal impedances are listed in Table 7 (page 23) for the applicable and
available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedan-
ces listed in Table 7. For designs that are expected to last several years and require the
flexibility to use several DRAM die shrinks, consider using final target theta values (rath-
er than existing values) to account for increased thermal impedances from the die size
reduction.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the TC specification is not exceeded. In applications where the device’s ambient tem-
perature is too high, use of forced air and/or heat sinks may be required in order to sat-
isfy the case temperature specifications.
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings
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2004 Micron Technology, Inc. All rights reserved.
Table 6: Temperature Limits
Parameter Symbol Min Max Units Notes
Storage temperature TSTG –55 150 °C 1
Operating temperature: commercial TC0 85 °C 2, 3
Operating temperature: industrial TC–40 95 °C 2, 3 , 4
TA–40 85 °C 4, 5
Operating temperature: automotive TC–40 105 °C 2, 3, 4
TA–40 105 °C 4, 5
Notes: 1. MAX storage case temperature TSTG is measured in the center of the package, as shown
in Figure 12. This case temperature limit is allowed to be exceeded briefly during pack-
age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa-
rameters.”
2. MAX operating case temperature TC is measured in the center of the package, as shown
in Figure 12.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. Both temperature specifications must be satisfied.
5. Operating ambient temperature surrounding the package.
Figure 12: Example Temperature Test Point Location
Table 7: Thermal Impedance
Die Revision Package Substrate
Θ
Θ
JA (°C/W)
Airflow = 0m/s
Θ
JA (°C/W)
Airflow = 1m/s
Θ
JA (°C/W)
Airflow = 2m/s
Θ
JB (°C/W)
Θ
JC (°C/W)
G160-ball 2-layer 94.2 76.5 70.1 57.3 6.1
4-layer 76.4 66.9 63.1 56.5
84-ball 2-layer 88.8 71.3 65.6 52.5 6.0
4-layer 71.4 62.1 58.7 52.0
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings
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2004 Micron Technology, Inc. All rights reserved.
Table 7: Thermal Impedance (Continued)
Die Revision Package Substrate
Θ
Θ
JA (°C/W)
Airflow = 0m/s
Θ
JA (°C/W)
Airflow = 1m/s
Θ
JA (°C/W)
Airflow = 2m/s
Θ
JB (°C/W)
Θ
JC (°C/W)
H160-ball Low Conductivity 85.4 70.6 64.5 42.8 11.7
High Conductivity 63.2 56.1 52.8
84-ball Low Conductivity 80.8 67.0 61.6 44.7 11.7
High Conductivity 59.7 53.3 50.7
Note: 1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – Absolute Ratings
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Electrical Specifications – IDD Parameters
IDD Specifications and Conditions
Table 8: General IDD Parameters
IDD Parameters -187E -25E -25 -3E -3 -37E Units
CL (IDD) 756454
tCK
tRCD (IDD) 13.125 12.5 15 12 15 15 ns
tRC (IDD) 58.125 57.5 60 57 60 60 ns
tRRD (IDD) - x4/x8 (1KB) 7.5 7.5 7.5 7.5 7.5 7.5 ns
tRRD (IDD) - x16 (2KB) 10 10 10 10 10 10 ns
tCK (IDD) 1.875 2.5 2.5 3 3 3.75 ns
tRAS MIN (IDD) 454545454545ns
tRAS MAX (IDD) 70,000 70,000 70,000 70,000 70,000 70,000 ns
tRP (IDD) 13.125 12.5 15 12 15 15 ns
tRFC (IDD - 256Mb) 75 75 75 75 75 75 ns
tRFC (IDD - 512Mb) 105 105 105 105 105 105 ns
tRFC (IDD - 1Gb) 127.5 127.5 127.5 127.5 127.5 127.5 ns
tRFC (IDD - 2Gb) 197.5 197.5 197.5 197.5 197.5 197.5 ns
tFAW (IDD) - x4/x8 (1KB) Defined by pattern in Table 9 (page 25) ns
tFAW (IDD) - x16 (2KB) Defined by pattern in Table 9 (page 25) ns
IDD7 Conditions
The detailed timings are shown below for IDD7. Where general IDD parameters in the
General Parameters Table conflict with pattern requirements in the IDD7 Timing Pat-
terns Table, then the IDD7 timing patterns requirements take precedence.
Table 9: IDD7 Timing Patterns (4-Bank Interleave READ Operation)
Speed Grade IDD7 Timing Patterns
Timing patterns for 4-bank x4/x8/x16 devices
-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-3 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-3E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-25 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-25E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
-187E A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
Notes: 1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at tRC (IDD) without violating tRRD (IDD) using a BL = 4.
3. Control and address bus inputs are stable during DESELECTs.
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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Table 10: DDR2 IDD Specifications and Conditions (Die Revision G)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 -37E Units
Operating one bank active-precharge
current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is
HIGH between valid commands; address bus
inputs are switching; Data bus inputs are
switching
IDD0 x4, x8 75 65 60 55 mA
x16 90 80 75 70
Operating one bank active-read-pre-
charge current: IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid
commands; address bus inputs are switch-
ing; Data pattern is same as IDD4W
IDD1 x4, x8 85 75 70 65 mA
x16 100 95 90 85
Precharge power-down current: All
banks idle; tCK = tCK (IDD); CKE is LOW; Oth-
er control and address bus inputs are stable;
Data bus inputs are floating
IDD2P x4, x8, x16 7777mA
Precharge quiet standby current: All
banks idle; tCK = tCK (IDD); CKE is HIGH, CS#
is HIGH; Other control and address bus in-
puts are stable; Data bus inputs are floating
IDD2Q x4, x8 28 24 22 20 mA
x16 30 26 24 22
Precharge standby current: All banks
idle; tCK = tCK (IDD); CKE is HIGH, CS# is
HIGH; Other control and address bus inputs
are switching; Data bus inputs are switching
IDD2N x4, x8 34 28 25 23 mA
x16 36 30 27 25
Active power-down current: All banks
open; tCK = tCK (IDD); CKE is LOW; Other
control and address bus inputs are stable;
Data bus inputs are floating
IDD3Pf Fast PDN exit
MR12 = 0
23 18 15 14 mA
IDD3Ps Slow PDN exit
MR12 = 1
9999
Active standby current: All banks open;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address
bus inputs are switching; Data bus inputs
are switching
IDD3N x4, x8 40 33 30 27 mA
x16 42 35 32 29
Operating burst write current: All banks
open, continuous burst writes; BL = 4, CL =
CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS#
is HIGH between valid commands; address
bus inputs are switching; Data bus inputs
are switching
IDD4W x4, x8 145 125 115 99 mA
x16 185 160 135 120
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 -37E Units
Operating burst read current: All banks
open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid com-
mands; address bus inputs are switching;
Data bus inputs are switching
IDD4R x4, x8 140 120 110 95 mA
x16 180 150 125 110
Burst refresh current: tCK = tCK (IDD); re-
fresh command at every tRFC (IDD) interval;
CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus
inputs are switching; Data bus inputs are
switching
IDD5 x4, x8 105 95 90 90 mA
x16 110 100 90 90
Self refresh current: CK and CK# at 0V;
CKE 0.2V; Other control and address bus
inputs are floating; Data bus inputs are
floating
IDD6 x4, x8, x16 7777mA
IDD6L 3333
Operating bank interleave read cur-
rent: All bank interleaving reads, IOUT =
0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) -
1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, CS# is HIGH between valid com-
mands; address bus inputs are stable during
deselects; Data bus inputs are switching;
See IDD7 Conditions (page 25) for details
IDD7 x4, x8 160 150 140 135 mA
x16 225 215 200 195
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C TC +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
LOW VIN VIL(AC)max
HIGH VIN VIH(AC)min
Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT- or AT-option devices
when operated outside of the range 0°C TC 85°C:
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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When
TC
0°C
IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD4W must be derat-
ed by 2%; and IDD6 and IDD7 must be derated by 7%
When
TC
85°C
IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5 must be derat-
ed by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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2004 Micron Technology, Inc. All rights reserved.
Table 11: DDR2 IDD Specifications and Conditions (Die Revision H)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 Units
Operating one bank active-precharge cur-
rent: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH
between valid commands; address bus inputs
are switching; Data bus inputs are switching
IDD0 x4, x8 75 65 60 mA
x16 90 80 75
Operating one bank active-read-precharge
current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is
HIGH, CS# is HIGH between valid commands;
address bus inputs are switching; Data pattern
is same as IDD4W
IDD1 x4, x8 85 75 70 mA
x16 100 95 90
Precharge power-down current: All banks
idle; tCK = tCK (IDD); CKE is LOW; Other control
and address bus inputs are stable; Data bus in-
puts are floating
IDD2P x4, x8, x16 10 10 10 mA
Precharge quiet standby current: All banks
idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q x4, x8 28 24 22 mA
x16 30 26 24
Precharge standby current: All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are switching;
Data bus inputs are switching
IDD2N x4, x8 34 28 25 mA
x16 36 30 27
Active power-down current: All banks open;
tCK = tCK (IDD); CKE is LOW; Other control and
address bus inputs are stable; Data bus inputs
are floating
IDD3Pf Fast PDN exit
MR12 = 0
22 20 18 mA
IDD3Ps Slow PDN exit
MR12 = 1
15 15 15
Active standby current: All banks open; tCK
= tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus in-
puts are switching; Data bus inputs are switch-
ing
IDD3N x4, x8 40 33 30 mA
x16 42 35 32
Operating burst write current: All banks
open, continuous burst writes; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH
between valid commands; address bus inputs
are switching; Data bus inputs are switching
IDD4W x4, x8 145 125 115 mA
x16 185 160 135
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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2004 Micron Technology, Inc. All rights reserved.
Table 11: DDR2 IDD Specifications and Conditions (Die Revision H) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition Symbol Configuration -187E -25E -3 Units
Operating burst read current: All banks
open, continuous burst reads, IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid commands;
address bus inputs are switching; Data bus in-
puts are switching
IDD4R x4, x8 140 120 110 mA
x16 180 150 125
Burst refresh current: tCK = tCK (IDD); refresh
command at every tRFC (IDD) interval; CKE is
HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are
switching; Data bus inputs are switching
IDD5 x4, x8 105 95 90 mA
x16 110 100 90
Self refresh current: CK and CK# at 0V; CKE
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
IDD6 x4, x8, x16 7 7 7 mA
Operating bank interleave read current: All
bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK =
tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD
= tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; address bus inputs are stable
during deselects; Data bus inputs are switching;
See IDD7 Conditions (page 25) for details
IDD7 x4, x8 160 150 140 mA
x16 225 215 200
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C TC +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
LOW VIN VIL(AC)max
HIGH VIN VIH(AC)min
Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT- or AT-option devices
when operated outside of the range 0°C TC 85°C:
When
TC
0°C
IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD4W must be derat-
ed by 2%; and IDD6 and IDD7 must be derated by 7%
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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When
TC
85°C
IDD0 , IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5 must be derat-
ed by 2%; IDD2P must be derated by 20%; IDD3P slow must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
512Mb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
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AC Timing Operating Specifications
Table 12: AC Operating Specifications and Conditions
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Clock
Clock
cycle time
CL = 7 tCK (avg) 1.875 8.0 ns 6, 7, 8,
9
CL = 6 tCK (avg) 2.5 8.0 2.5 8.0 2.5 8.0
CL = 5 tCK (avg) 2.5 8.0 2.5 8.0 3.0 8.0 3.0 8.0 3.0 8.0
CL = 4 tCK (avg) 3.75 8.0 3.75 8.0 3.75 8.0 3.0 8.0 3.75 8.0 3.75 8.0 5.0 8.0
CL = 3 tCK (avg) 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0 5.0 8.0
CK high-level
width
tCH (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK 10
CK low-level width tCL (avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
Half clock period tHP MIN = lesser of tCH and tCL
MAX = n/a
ps 11
Absolute tCK tCK (abs) MIN = tCK (AVG) MIN + tJITper (MIN)
MAX = tCK (AVG) MAX + tJITper (MAX)
ps
Absolute CK
high-level width
tCH (abs) MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)
ps
Absolute CK
low-level width
tCL (abs) MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)
ps
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
PDF: 09005aef85651470
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Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Clock Jitter
Period jitter tJITper –90 90 –100 100 –100 100 –125 125 –125 125 –125 125 –125 125 ps 12
Half period tJITdty –75 75 –100 100 –100 100 –125 125 –125 125 –125 125 –150 150 ps 13
Cycle to cycle tJITcc 180 200 200 250 250 250 250 ps 14
Cumulative error,
2 cycles
tERR2per –132 132 –150 150 –150 150 –175 175 –175 175 –175 175 –175 175 ps 15
Cumulative error,
3 cycles
tERR3per –157 157 –175 175 –175 175 –225 225 –225 225 –225 225 –225 225 ps 15
Cumulative error,
4 cycles
tERR4per –175 175 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15
Cumulative error,
5 cycles
tERR5per –188 188 –200 200 –200 200 –250 250 –250 250 –250 250 –250 250 ps 15, 16
Cumulative error,
6–10 cycles
tERR6–
10per
–250 250 –300 300 –300 300 –350 350 –350 350 –350 350 –350 350 ps 15, 16
Cumulative error,
11–50 cycles
tERR11–
50per
–425 425 –450 450 –450 450 –450 450 –450 450 –450 450 –450 450 ps 15
Data Strobe-Out
DQS output access
time from CK/CK#
tDQSCK –300 300 –350 350 –350 350 –400 400 –400 400 –450 450 –500 500 ps 19
DQS read pream-
ble
tRPRE MIN = 0.9 × tCK
MAX = 1.1 × tCK
tCK 17, 18,
19
DQS read
postamble
tRPST MIN = 0.4 × tCK
MAX = 0.6 × tCK
tCK 17, 18,
19, 20
CK/CK# to DQS
Low-Z
tLZ1MIN = tAC (MIN)
MAX = tAC (MAX)
ps 19, 21,
22
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Data Strobe-In
DQS rising edge to
CK rising edge
tDQSS MIN = –0.25 × tCK
MAX = 0.25 × tCK
tCK 18
DQS input-high
pulse width
tDQSH MIN = 0.35 × tCK
MAX = n/a
tCK 18
DQS input-low
pulse width
tDQSL MIN = 0.35 × tCK
MAX = n/a
tCK 18
DQS falling to CK
rising: setup time
tDSS MIN = 0.2 × tCK
MAX = n/a
tCK 18
DQS falling from
CK rising:
hold time
tDSH MIN = 0.2 × tCK
MAX = n/a
tCK 18
Write preamble
setup time
tWPRES MIN = 0
MAX = n/a
ps 23, 24
DQS write
preamble
tWPRE MIN = 0.35 × tCK
MAX = n/a
tCK 18
DQS write
postamble
tWPST MIN = 0.4 × tCK
MAX = 0.6 × tCK
tCK 18, 25
WRITE command
to first DQS
transition
MIN = WL - tDQSS
MAX = WL + tDQSS
tCK
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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2004 Micron Technology, Inc. All rights reserved.
Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Data-Out
DQ output access
time from CK/CK#
tAC –350 350 –400 400 –400 400 –450 450 –450 450 –500 500 –600 600 ps 19
DQS–DQ skew,
DQS to last DQ
valid, per group,
per access
tDQSQ 175 200 200 240 240 300 350 ps 26, 27
DQ hold from next
DQS strobe
tQHS 250 – 300 – 300 – 340 – 340 – 400 – 450 ps 28
DQ–DQS hold, DQS
to first DQ not val-
id
tQH MIN = tHP - tQHS
MAX = n/a
ps 26, 27,
28
CK/CK# to DQ, DQS
High-Z
tHZ MIN = n/a
MAX = tAC (MAX)
ps 19, 21,
29
CK/CK# to DQ
Low-Z
tLZ2MIN = 2 × tAC (MIN)
MAX = tAC (MAX)
ps 19, 21,
22
Data valid output
window
DVW MIN = tQH - tDQSQ
MAX = n/a
ns 26, 27
Data-In
DQ and DM input
setup time to DQS
tDSb 0 50 50 100 100 100 150 ps 26, 30,
31
DQ and DM input
hold time to DQS
tDHb 75 125 125 175 175 225 275 ps 26, 30,
31
DQ and DM input
setup time to DQS
tDSa 200 250 250 300 300 350 400 ps 26, 30,
31
DQ and DM input
hold time to DQS
tDHa 200 250 250 300 300 350 400 ps 26, 30,
31
DQ and DM input
pulse width
tDIPW MIN = 0.35 × tCK
MAX = n/a
tCK 18, 32
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
PDF: 09005aef85651470
512MbDDR2.pdf - Rev. Y 06/17 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Command and Address
Input setup time tISb 125 175 175 200 200 250 350 ps 31, 33
Input hold time tIHb 200 250 250 275 275 375 475 ps 31, 33
Input setup time tISa 325 375 375 400 400 500 600 ps 31, 33
Input hold time tIHa 325 375 375 400 400 500 600 ps 31, 33
Input pulse width tIPW 0.6 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – tCK 18, 32
ACTIVATE-to-
ACTIVATE delay,
same bank
tRC 54 55 55 54 55 55 55 ns 18, 34,
51
ACTIVATE-to-READ
or WRITE delay
tRCD 13.125 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18
ACTIVATE-to-
PRECHARGE delay
tRAS 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K ns 18, 34,
35
PRECHARGE period tRP 13.125 12.5 15 12 15 15 15 ns 18, 36
PRE-
CHARGE
ALL period
<1Gb tRPA 13.125 12.5 15 12 15 15 15 ns 18, 36
1Gb tRPA 15 15 17.5 15 18 18.75 20 ns 18, 36
ACTIVATE
-to-
ACTIVATE
delay
different
bank
x4, x8 tRRD 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns 18, 37
x16 tRRD 10 10 10 10 10 10 10 ns 18, 37
4-bank
activate
period
(1Gb)
x4, x8 tFAW 35 35 35 37.5 37.5 37.5 37.5 ns 18, 38
x16 tFAW 45 45 45 50 50 50 50 ns 18, 38
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Command and Address
Internal READ-to-
PRECHARGE delay
tRTP 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns 18, 37,
39
CAS#-to-CAS#
delay
tCCD2 – 2–2–2–2–2–2–
tCK 18
Write recovery
time
tWR 15 15 15 15 15 15 15 ns 18, 37
Write AP recovery
+ precharge time
tDAL tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
–ns 40
Internal WRITE-to-
READ delay
tWTR 7.5 7.5 7.5 7.5 7.5 7.5 10 ns 18, 37
LOAD MODE cycle
time
tMRD2 – 2–2–2–2–2–2–
tCK 18
Refresh
REFRESH-
to-
ACTIVATE
or to
-REFRESH
interval
256Mb tRFC 75 75 75 75 75 75 75 ns 18, 41
512Mb 105 105 – 105 – 105 – 105 – 105 – 105 –
1Gb 127.5 127.5 – 127.5 – 127.5 – 127.5 – 127.5 – 127.5 –
2Gb 195 195 – 195 – 195 – 195 – 195 – 195 –
Average periodic
refresh
(commercial)
tREFI 7.8 7.8 7.8 7.8 7.8 7.8 7.8 μs 18, 41
Average periodic
refresh
(industrial)
tREFIIT 3.9 3.9 3.9 3.9 3.9 3.9 3.9 μs 18, 41
Average periodic
refresh
(automotive)
tREFIAT 3.9 3.9 3.9 3.9 3.9 3.9 3.9 μs 18, 41
CKE LOW to CK,
CK# uncertainty
tDELAY MIN limit = tIS + tCK + tIH
MAX limit = n/a
ns 42
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Self Refresh
Exit SELF REFRESH
to nonREAD
command
tXSNR MIN limit = tRFC (MIN) + 10
MAX limit = n/a
ns
Exit SELF REFRESH
to READ command
tXSRD MIN limit = 200
MAX limit = n/a
tCK 18
Exit SELF REFRESH
timing reference
tISXR MIN limit = tIS
MAX limit = n/a
ps 33, 43
Power-Down
Exit active
power-
down to
READ
command
MR12
= 0
tXARD 3 2 – 2 – 2 – 2 – 2 – 2 – tCK 18
MR12
= 1
10 -
AL
8 - AL 8 - AL 7 - AL 7 - AL 6 - AL 6 - AL tCK 18
Exit precharge
power-down and
active power-down
to any
nonREAD
command
tXP 3 – 2–2–2–2–2–2–
tCK 18
CKE MIN
HIGH/LOW time
tCKE MIN = 3
MAX = n/a
tCK 18, 44
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Table 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V
AC Characteristics -187E -25E -25 -3E -3 -37E -5E
Units NotesParameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max
ODT
ODT to power-
down entry latency
tANPD 4 3 – 3 – 3 – 3 – 3 – 3 – tCK 18
ODT power-down
exit latency
tAXPD 11 8 – 8 – 8 – 8 – 8 – 8 – tCK 18
ODT turn-on delay tAOND 2 tCK 18
ODT turn-off delay tAOFD 2.5 tCK 18, 45
ODT turn-on tAON tAC
(MIN)
tAC
(MAX)
+
2575
MIN = tAC (MIN)
MAX = tAC (MAX) + 600
MIN = tAC (MIN)
MAX = tAC (MAX) + 700
MIN = tAC (MIN)
MAX = tAC (MAX) + 1000
ps 19, 46
ODT turn-off tAOF MIN = tAC (MIN)
MAX = tAC (MAX) + 600
ps 47, 48
ODT turn-on
(power-down
mode)
tAONPD tAC
(MIN)
+ 2000
2 ×
tCK +
tAC
(MAX)
+
1000
MIN = tAC (MIN) + 2000
MAX = 2 × tCK + tAC (MAX) + 1000
ps 49
ODT turn-off
(power-down
mode)
tAOFPD MIN = tAC (MIN) + 2000
MAX = 2.5 × tCK + tAC (MAX) + 1000
ps
ODT enable from
MRS command
tMOD MIN = 12
MAX = n/a
ns 18, 50
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Notes: 1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply
voltage levels, but the related specifications and the operation of the device are warranted for the full voltage
range specified. ODT is disabled for all measurements that are not ODT-specific.
3. Outputs measured with equivalent load (see Figure 16 (page 49)).
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment, and parameter specifica-
tions are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input
signals used to test the device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates other than
1.0 V/ns may require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will effective-
ly switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal
does not ring back above [below] the DC input LOW [HIGH] level).
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 79 (page 124)), precharge
power-down mode, or system reset condition (see Reset (page 125)). SSC allows for small deviations in operating
frequency, provided the SSC guidelines are satisfied.
8. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock
rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed provided it does not
exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.
9. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate
spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent tCK (AVG); however, the
spread spectrum may not use a clock rate below tCK (AVG) MIN or above tCK (AVG) MAX.
10. MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the
device. The clock’s half period must also be of a Gaussian distribution; tCH (AVG) and tCL (AVG) must be met with
or without clock jitter and with or without duty cycle jitter. tCH (AVG) and tCL (AVG) are the average of any 200
consecutive CK falling edges. tCH limits may be exceeded if the duty cycle jitter is small enough that the absolute
half period limits (tCH [ABS], tCL [ABS]) are not violated.
11. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK# inputs; thus, tHP (MIN) the lesser
of tCL (ABS) MIN and tCH (ABS) MIN.
12. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock allowed
in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During
DLL lock time, the jitter values should be 20 percent less those than noted in the table (DLL locked).
13. The half-period jitter (tJITdty) applies to either the high pulse of clock or the low pulse of clock; however, the two
cumulatively can not exceed tJITper.
14. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next. JEDEC speci-
fies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent
less than those noted in the table (DLL locked).
15. The cumulative jitter error (tERRnper), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time allowed to
consecutively accumulate away from the average clock over any number of clock cycles.
16. JEDEC specifies using tERR6–10per when derating clock-related output timing (see notes 19 and 48). Micron requires
less derating by allowing tERR5per to be used.
17. This parameter is not referenced to a specific voltage level but is specified when the device output is no longer
driving (tRPST) or beginning to drive (tRPRE).
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AC Timing Operating Specifications
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18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-
er, the input timing (in ns) references to the tCK (AVG) when determining the required number of clocks. The fol-
lowing input parameters are determined by taking the specified percentage times the tCK (AVG) rather than tCK:
tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by
the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The
following parameters are required to be derated by subtracting tERR5per (MAX): tAC (MIN), tDQSCK (MIN), tLZDQS
(MIN), tLZDQ (MIN), tAON (MIN); while the following parameters are required to be derated by subtracting
tERR5per (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter
tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX), is derated by subtracting tJITper (MIN).
The parameter tRPST (MIN) is derated by subtracting tJITdty (MAX), while tRPST (MAX), is derated by subtracting
tJITdty (MIN). Output timings that require tERR5per derating can be observed to have offsets relative to the clock;
however, the total window will not degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driv-
ing (tLZ).
22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-
ded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-
ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either
be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above VIH[DC]min), then it must not transition LOW (below VIH[DC])
prior to tDQSH (MIN).
26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and
UDQS with DQ[15:8].
27. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS).
The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can
be derived.
28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or tCH (ABS) MAX times tCK (ABS) MIN
- tQHS. Minimizing the amount of tCH (AVG) offset and value of tJITdty will provide a larger tQH, which in turn
will provide a larger valid data out window.
29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns
for each signal). There are two sets of values listed: tDSa, tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference
only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The
baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb is referenced
from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tDHb is referenced from VIL(DC) for a rising sig-
nal and VIH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values
must be derated by adding the values from Table 31 (page 62) and Table 32 (page 63). If the DQS differential
strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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Table 33 (page 64). Single-ended DQS data timing is referenced at DQS crossing VREF. The correct timing values
for a single-ended DQS strobe are listed in Table 34 (page 64)–Table 36 (page 65) on Table 34 (page 64),
Table 35 (page 65), and Table 36 (page 65); listed values are already derated for slew rate variations and con-
verted from baseline values to VREF values.
31. VIL/VIH DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification (page 55).
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values (for reference
only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1 V/ns. The baseline values,
tISb, tIHb, are the JEDEC-defined values, referenced from the logic trip points. tISb is referenced from VIH(AC) for a
rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a
falling signal. If the command/address slew rate is not equal to 1 V/ns, then the baseline values must be derated
by adding the values from Table 29 (page 58) and Table 30 (page 59).
34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to tWR during auto pre-
charge.
35. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied because tRAS lock-
out feature is supported in DDR2 SDRAM.
36. When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing applies when the PRE-
CHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices (1Gb), tRPA (MIN)
= tRP (MIN) + tCK (AVG) (Table 12 (page 32) lists tRP [MIN] + tCK [AVG] MIN).
37. This parameter has a two clock minimum requirement at any tCK.
38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE commands may
be issued in a given tFAW (MIN) period. tRRD (MIN) restriction still applies.
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch begins to
when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the
READ so that data will output CL later. This parameter is only applicable when tRTP/(2 × tCK) > 1, such as frequen-
cies faster than 533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK) 1, then equation AL + BL/2 applies. tRAS (MIN) has
to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS
(MIN) has been satisfied.
40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next integer.
tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR9–MR11. For exam-
ple, -37E at tCK = 3.75ns with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 + (4)
clocks = 8 clocks.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average refresh
rate of 7.8125μs (commercial) or 3.9607μs (industrial and automotive). To ensure all rows of all banks are properly
refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial and automotive).
The JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.
42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being re-
moved in a system RESET condition (see Reset (page 125)).
43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in Figure 69 (page 116).
44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must re-
main at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any
CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 × tCK + tIH.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the
amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 -
0.03, or 2.47, for tAOF (MIN) and 2.5 + 0.03, or 2.53, for tAOF (MAX).
46. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-
on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND.
47. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX)
is when the bus is in High-Z. Both are measured from tAOFD.
48. Half-clock output parameters must be derated by the actual tERR5per and tJITdty when input clock jitter is present;
this will result in each parameter becoming larger. The parameter tAOF (MIN) is required to be derated by sub-
tracting both tERR5per (MAX) and tJITdty (MAX). The parameter tAOF (MAX) is required to be derated by subtract-
ing both tERR5per (MIN) and tJITdty (MIN).
49. The -187E maximum limit is 2 × tCK + tAC (MAX) + 1000 but it will likely be 3 x tCK + tAC (MAX) + 1000 in the
future.
50. Should use 8 tCK for backward compatibility.
51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
dress may result in reduction of the product lifetime.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
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AC and DC Operating Conditions
Table 13: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS
Parameter Symbol Min Nom Max Units Notes
Supply voltage VDD 1.7 1.8 1.9 V 1, 2
VDDL supply voltage VDDL 1.7 1.8 1.9 V 2, 3
I/O supply voltage VDDQ 1.7 1.8 1.9 V 2, 3
I/O reference voltage VREF(DC) 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V4
I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC) VREF(DC) + 40 mV 5
Notes: 1. VDD and VDDQ must track each other. VDDQ must be VDD.
2. VSSQ = VSSL = VSS.
3. VDDQ tracks with VDD; VDDL tracks with VDD.
4. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed
±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent
of VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination re-
sistors, is expected to be set equal to VREF, and must track variations in the DC level of
VREF.
ODT DC Electrical Characteristics
Table 14: ODT DC Electrical Characteristics
All voltages are referenced to VSS
Parameter Symbol Min Nom Max Units Notes
RTT effective impedance value for 75Ω setting
EMR (A6, A2) = 0, 1
RTT1(EFF) 60 75 90 Ω1, 2
RTT effective impedance value for 150Ω setting
EMR (A6, A2) = 1, 0
RTT2(EFF) 120 150 180 Ω1, 2
RTT effective impedance value for 50Ω setting
EMR (A6, A2) = 1, 1
RTT3(EFF) 40 50 60 Ω1, 2
Deviation of VM with respect to VDDQ/2 ΔVM –6 – 6 % 3
Notes: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(DC) to the ball
being tested, and then measuring current, I(VIH[AC]), and I(VIL[AC]), respectively.
RTT(EFF) = VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC))
2. Minimum IT and AT device values are derated by six percent less when the devices oper-
ate between –40°C and 0°C (TC ).
3. Measure voltage (VM) at tested ball with no load.
ǻVM = 2 × VM
VDDQ - 1 × 100
512Mb: x4, x8, x16 DDR2 SDRAM
AC and DC Operating Conditions
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Input Electrical Characteristics and Operating Conditions
Table 15: Input DC Logic Levels
All voltages are referenced to VSS
Parameter Symbol Min Max Units
Input high (logic 1) voltage VIH(DC) VREF(DC) + 125 VDDQ1mV
Input low (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV
Note: 1. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Table 16: Input AC Logic Levels
All voltages are referenced to VSS
Parameter Symbol Min Max Units
Input high (logic 1) voltage (-37E/-5E) VIH(AC) VREF(DC) + 250 VDDQ1mV
Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3) VIH(AC) VREF(DC) + 200 VDDQ1mV
Input low (logic 0) voltage (-37E/-5E) VIL(AC) –300 VREF(DC) - 250 mV
Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3) VIL(AC) –300 VREF(DC) - 200 mV
Note: 1. Refer to AC Overshoot/Undershoot Specification (page 55).
Figure 13: Single-Ended Input Signal Levels
650mV
775mV
864mV
882mV
900mV
918mV
936mV
1,025mV
1,150mV
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
Note: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
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Table 17: Differential Input Logic Levels
All voltages referenced to VSS
Parameter Symbol Min Max Units Notes
DC input signal voltage VIN(DC) –300 VDDQ mV 1, 6
DC differential input voltage VID(DC) 250 VDDQ mV 2, 6
AC differential input voltage VID(AC) 500 VDDQ mV 3, 6
AC differential cross-point voltage VIX(AC) 0.50 × VDDQ - 175 0.50 × VDDQ + 175 mV 4
Input midpoint voltage VMP(DC) 850 950 mV 5
Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage |VTR - VCP| required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to VIH(DC) -
VIL(DC). Differential input signal levels are shown in Figure 14.
3. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where
VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the comple-
mentary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is
equal to VIH(AC) - VIL(AC), as shown in Table 16 (page 45).
4. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 14.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC)
is expected to be approximately 0.5 × VDDQ.
6. VDDQ + 300mV allowed provided 1.9V is not exceeded.
Figure 14: Differential Input Signal Levels
TR2
CP2
2.1V
VDDQ = 1.8V
VIN(DC)max1
VIN(DC)min1
–0.30V
0.9V
1.075V
0.725V
VID(AC)6
VID(DC)5
X
VMP(DC)3VIX(AC)4
X
Notes: 1. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be
VDDQ/2.
4. TR and CP must cross in this region.
5. TR and CP must meet at least VID(DC)min when static and is centered around VMP(DC).
6. TR and CP must have a minimum 500mV peak-to-peak swing.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
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7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
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Output Electrical Characteristics and Operating Conditions
Table 18: Differential AC Output Parameters
Parameter Symbol Min Max Units Notes
AC differential cross-point voltage VOX(AC) 0.50 × VDDQ - 125 0.50 × VDDQ + 125 mV 1
Note: 1. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting de-
vice and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at
which differential output signals must cross.
Figure 15: Differential Output Signal Levels
Crossing point
VOX
VSSQ
Vswing
VDDQ
VTR
VCP
Table 19: Output DC Current Drive
Parameter Symbol Value Units Notes
Output MIN source DC current IOH –13.4 mA 1, 2, 4
Output MIN sink DC current IOL 13.4 mA 2, 3, 4
Notes: 1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for val-
ues of VOUT between VDDQ and VDDQ - 280mV.
2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21Ω for values of VOUT
between 0V and 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They
are used to test device drive current capability to ensure VIH,min plus a noise margin and
VIL,max minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-
ues are derived by shifting the desired driver operating point (see output IV curves)
along a 21Ω load line to define a convenient driver current for measurement.
512Mb: x4, x8, x16 DDR2 SDRAM
Output Electrical Characteristics and Operating Conditions
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Table 20: Output Characteristics
Parameter Min Nom Max Units Notes
Output impedance See Output Driver Characteristics (page 50) Ω1, 2
Pull-up and pull-down mismatch 0 4 Ω1, 2, 3
Output slew rate 1.5 5 V/ns 1, 4, 5, 6
Notes: 1. Absolute specifications: 0°C TC +85°C; VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V.
2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V; VOUT =
1420mV; (VOUT - VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and
VDDQ - 280mV. The impedance measurement condition for output sink DC current: VDDQ
= 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V
and 280mV.
3. Mismatch is an absolute value between pull-up and pull-down; both are measured at
the same temperature and voltage.
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT
+ 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew rate
is measured between DQS - DQS# = –500mV and DQS# - DQS = 500mV. Output slew rate
is guaranteed by design but is not necessarily tested on each device.
5. The absolute value of the slew rate as measured from VIL(DC)max to VIH(DC)min is equal to
or greater than the slew rate as measured from VIL(AC)max to VIH(AC)min. This is guaran-
teed by design and characterization.
6. IT and AT devices require an additional 0.4 V/ns in the MAX limit when TC is between –
40°C and 0°C.
Figure 16: Output Slew Rate Load
Output
(VOUT)
Reference
point
25ȍ
VTT = VDDQ/2
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Output Electrical Characteristics and Operating Conditions
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Output Driver Characteristics
Figure 17: Full Strength Pull-Down Characteristics
VOUT (V)
0.0 0.5 1.0 1.5
120
100
80
60
40
20
0
IOUT (mA)
Table 21: Full Strength Pull-Down Current (mA)
Voltage (V) Min Nom Max
0.0 0.00 0.00 0.00
0.1 4.30 5.63 7.95
0.2 8.60 11.30 15.90
0.3 12.90 16.52 23.85
0.4 16.90 22.19 31.80
0.5 20.40 27.59 39.75
0.6 23.28 32.39 47.70
0.7 25.44 36.45 55.55
0.8 26.79 40.38 62.95
0.9 27.67 44.01 69.55
1.0 28.38 47.01 75.35
1.1 28.96 49.63 80.35
1.2 29.46 51.71 84.55
1.3 29.90 53.32 87.95
1.4 30.29 54.9 90.70
1.5 30.65 56.03 93.00
1.6 30.98 57.07 95.05
1.7 31.31 58.16 97.05
1.8 31.64 59.27 99.05
1.9 31.96 60.35 101.05
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Output Driver Characteristics
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Figure 18: Full Strength Pull-Up Characteristics
VDDQ - VOUT (V)
0
–20
–40
–60
–80
–100
–120
0 0.5 1.0 1.5
IOUT (mA)
Table 22: Full Strength Pull-Up Current (mA)
Voltage (V) Min Nom Max
0.0 0.00 0.00 0.00
0.1 –4.30 –5.63 –7.95
0.2 –8.60 –11.30 –15.90
0.3 –12.90 –16.52 –23.85
0.4 –16.90 –22.19 –31.80
0.5 –20.40 –27.59 –39.75
0.6 –23.28 –32.39 –47.70
0.7 –25.44 –36.45 –55.55
0.8 –26.79 –40.38 –62.95
0.9 –27.67 –44.01 –69.55
1.0 –28.38 –47.01 –75.35
1.1 –28.96 –49.63 –80.35
1.2 –29.46 –51.71 –84.55
1.3 –29.90 –53.32 –87.95
1.4 –30.29 –54.90 –90.70
1.5 –30.65 –56.03 –93.00
1.6 –30.98 –57.07 –95.05
1.7 –31.31 –58.16 –97.05
1.8 –31.64 –59.27 –99.05
1.9 –31.96 –60.35 –101.05
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Output Driver Characteristics
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Figure 19: Reduced Strength Pull-Down Characteristics
70
60
50
40
30
20
10
0
0.0 0.5 1.0 1.5
VOUT (V)
IOUT (mV)
Table 23: Reduced Strength Pull-Down Current (mA)
Voltage (V) Min Nom Max
0.0 0.00 0.00 0.00
0.1 1.72 2.98 4.77
0.2 3.44 5.99 9.54
0.3 5.16 8.75 14.31
0.4 6.76 11.76 19.08
0.5 8.16 14.62 23.85
0.6 9.31 17.17 28.62
0.7 10.18 19.32 33.33
0.8 10.72 21.40 37.77
0.9 11.07 23.32 41.73
1.0 11.35 24.92 45.21
1.1 11.58 26.30 48.21
1.2 11.78 27.41 50.73
1.3 11.96 28.26 52.77
1.4 12.12 29.10 54.42
1.5 12.26 29.70 55.80
1.6 12.39 30.25 57.03
1.7 12.52 30.82 58.23
1.8 12.66 31.41 59.43
1.9 12.78 31.98 60.63
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Output Driver Characteristics
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Figure 20: Reduced Strength Pull-Up Characteristics
0
–10
–20
–30
–40
–50
–60
–70
0.0 0.5 1.0 1.5
VDDQ - VOUT (V)
IOUT (mV)
Table 24: Reduced Strength Pull-Up Current (mA)
Voltage (V) Min Nom Max
0.0 0.00 0.00 0.00
0.1 –1.72 –2.98 –4.77
0.2 –3.44 –5.99 –9.54
0.3 –5.16 –8.75 –14.31
0.4 –6.76 –11.76 –19.08
0.5 –8.16 –14.62 –23.85
0.6 –9.31 –17.17 –28.62
0.7 –10.18 –19.32 –33.33
0.8 –10.72 –21.40 –37.77
0.9 –11.07 –23.32 –41.73
1.0 –11.35 –24.92 –45.21
1.1 –11.58 –26.30 –48.21
1.2 –11.78 –27.41 –50.73
1.3 –11.96 –28.26 –52.77
1.4 –12.12 –29.10 –54.42
1.5 –12.26 –29.69 –55.8
1.6 –12.39 –30.25 –57.03
1.7 –12.52 –30.82 –58.23
1.8 –12.66 –31.42 –59.43
1.9 –12.78 –31.98 –60.63
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Output Driver Characteristics
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Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only balls: Address balls,
bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.
Table 25: Input Clamp Characteristics
Voltage Across Clamp (V)
Minimum Power Clamp Current
(mA)
Minimum Ground Clamp Current
(mA)
0.0 0.0 0.0
0.1 0.0 0.0
0.2 0.0 0.0
0.3 0.0 0.0
0.4 0.0 0.0
0.5 0.0 0.0
0.6 0.0 0.0
0.7 0.0 0.0
0.8 0.1 0.1
0.9 1.0 1.0
1.0 2.5 2.5
1.1 4.7 4.7
1.2 6.8 6.8
1.3 9.1 9.1
1.4 11.0 11.0
1.5 13.5 13.5
1.6 16.0 16.0
1.7 18.2 18.2
1.8 21.0 21.0
Figure 21: Input Clamp Characteristics
Voltage Across Clamp (V)
Minimum Clamp Current (mA)
25
20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
512Mb: x4, x8, x16 DDR2 SDRAM
Power and Ground Clamp Characteristics
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AC Overshoot/Undershoot Specification
Table 26: Address and Control Balls
Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, and ODT
Parameter
Specification
-187E -25/-25E -3/-3E -37E -5E
Maximum peak amplitude allowed for overshoot area
(see Figure 22) 0.50V 0.50V 0.50V 0.50V 0.50V
Maximum peak amplitude allowed for undershoot area
(see Figure 23) 0.50V 0.50V 0.50V 0.50V 0.50V
Maximum overshoot area above VDD (see Figure 22) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns
Maximum undershoot area below VSS (see Figure 23) 0.5 Vns 0.66 Vns 0.80 Vns 1.00 Vns 1.33 Vns
Table 27: Clock, Data, Strobe, and Mask Balls
Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, and LDM
Parameter
Specification
-187E -25/-25E -3/-3E -37E -5E
Maximum peak amplitude allowed for overshoot area
(see Figure 22)
0.50V 0.50V 0.50V 0.50V 0.50V
Maximum peak amplitude allowed for undershoot area
(see Figure 23)
0.50V 0.50V 0.50V 0.50V 0.50V
Maximum overshoot area above VDDQ (see Figure 22) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns
Maximum undershoot area below VSSQ (see Figure 23) 0.19 Vns 0.23 Vns 0.23 Vns 0.28 Vns 0.38 Vns
Figure 22: Overshoot
Maximum amplitude
Overshoot area
VDD/VDDQ
VSS/VSSQ
Volts (V)
Time (ns)
Figure 23: Undershoot
VSS/VSSQ
Maximum amplitude
Undershoot area
Time (ns)
Volts (V)
Table 28: AC Input Test Conditions
Parameter Symbol Min Max Units Notes
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
VRS See Note 2 1, 2, 3, 4
512Mb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
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Table 28: AC Input Test Conditions (Continued)
Parameter Symbol Min Max Units Notes
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
VRH See Note 5 1, 3, 4, 5
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
VREF(DC) VDDQ × 0.49 VDDQ × 0.51 V 1, 3, 4, 6
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
VRD VIX(AC) V 1, 3, 7, 8, 9
Notes: 1. All voltages referenced to VSS.
2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under
test, as shown in Figure 32 (page 68).
3. See Input Slew Rate Derating (page 57).
4. The slew rate for single-ended inputs is measured from DC level to AC level, VIL(DC) to
VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced
to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in
Figure 25 (page 60), Figure 27 (page 61), Figure 29 (page 66), and Figure 31
(page 67).
5. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under
test, as shown in Figure 32 (page 68).
6. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 34 (page 69).
7. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 33 (page 68).
8. Input waveform timing is referenced to the crossing point level (VIX) of two input signals
(VTR and VCP) applied to the device under test, where VTR is the true input signal and VCP
is the complementary input signal, as shown in Figure 35 (page 69).
9. The slew rate for differentially ended inputs is measured from twice the DC level to
twice the AC level: 2 × VIL(DC) to 2 × VIH(AC) on the rising edge and 2 × VIL(AC) to 2 ×
VIH(DC) on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK
rising edge and would be 250mV to –500mV for CK falling edge.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
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Input Slew Rate Derating
For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated
by adding the data sheet tIS (base) and tIH (base) value to the ΔtIS and ΔtIH derating
value, respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.
tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup nominal slew rate (tIS) for
a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the
first crossing of VIL(AC)max.
If the actual signal is always earlier than the nominal slew rate line between shaded
“VREF(DC) to AC region,” use the nominal slew rate for the derating value (Figure 24
(page 60)).
If the actual signal is later than the nominal slew rate line anywhere between the shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for the derating value (see Figure 25 (page 60)).
tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tIH, nominal slew rate for a fall-
ing signal, is defined as the slew rate between the last crossing of VIH(DC)min and the first
crossing of VREF(DC).
If the actual signal is always later than the nominal slew rate line between shaded “DC
to VREF(DC) region,” use the nominal slew rate for the derating value (Figure 26
(page 61)).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the DC
level to VREF(DC) level is used for the derating value (Figure 27 (page 61)).
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
For slew rates in between the values listed in Table 29 (page 58) and Table 30
(page 59), the derating values may obtained by linear interpolation.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
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Table 29: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)
Command/Address Slew Rate (V/ns)
CK, CK# Differential Slew Rate
Units
2.0 V/ns 1.5 V/ns 1.0 V/ns
Δ
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
4.0 187 94 217 124 247 154 ps
3.5 179 89 209 119 239 149 ps
3.0 167 83 197 113 227 143 ps
2.5 150 75 180 105 210 135 ps
2.0 125 45 155 75 185 105 ps
1.5 83 21 113 51 143 81 ps
1.0 0 0 30 30 60 60 ps
0.9 –11 –14 19 16 49 46 ps
0.8 –25 –31 5 –1 35 29 ps
0.7 –43 –54 –13 –24 17 6 ps
0.6 –67 –83 –37 –53 –7 –23 ps
0.5 –110 –125 –80 –95 –50 –65 ps
0.4 –175 –188 –145 –158 –115 –128 ps
0.3 –285 –292 –255 –262 –225 –232 ps
0.25 –350 –375 –320 –345 –290 –315 ps
0.2 –525 –500 –495 –470 –465 –440 ps
0.15 –800 –708 –770 –678 –740 –648 ps
0.1 –1450 –1125 –1420 –1095 –1390 –1065 ps
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
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Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH)
Command/
Address Slew
Rate (V/ns)
CK, CK# Differential Slew Rate
Units
2.0 V/ns 1.5 V/ns 1.0 V/ns
Δ
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
4.0 150 94 180 124 210 154 ps
3.5 143 89 173 119 203 149 ps
3.0 133 83 163 113 193 143 ps
2.5 120 75 150 105 180 135 ps
2.0 100 45 160 75 160 105 ps
1.5 67 21 97 51 127 81 ps
1.0 0 0 30 30 60 60 ps
0.9 –5 –14 25 16 55 46 ps
0.8 –13 –31 17 –1 47 29 ps
0.7 –22 –54 8 –24 38 6 ps
0.6 –34 –83 –4 –53 36 –23 ps
0.5 –60 –125 –30 –95 0 –65 ps
0.4 –100 –188 –70 –158 –40 –128 ps
0.3 –168 –292 –138 –262 –108 –232 ps
0.25 –200 –375 –170 –345 –140 –315 ps
0.2 –325 –500 –295 –470 –265 –440 ps
0.15 –517 –708 –487 –678 –457 –648 ps
0.1 –1000 –1125 –970 –1095 –940 –1065 ps
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
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Figure 24: Nominal Slew Rate for tIS
VSS
CK#
CK
tIH
tIS tIH
Setup slew rate
rising signal
Setup slew rate
falling signal
ǻTF ǻTR
ǻ
TF
=
VIH(AC)min -
V
REF
(DC)
ǻ
TR
=
VDDQ
tIS
Nominal
slew rate
V
REF
to AC
region
V
REF
to AC
region
V
REF
(DC)
- VIL(AC)max
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Nominal
slew rate
Figure 25: Tangent Line for tIS
Setup slew rate
rising signal
ǻ
TF
ǻ
TR
Tangent line (V
IH[AC]min
- V
REF[DC]
)
ǻTR
=
Tangent
line
Tangent
line
V
REF
to AC
region
Nominal
line
tIH
tIS tIH tIS
VSS
CK#
CK
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
V
REF
to AC
region
Nominal
line
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
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Figure 26: Nominal Slew Rate for tIH
ǻTR ǻTF
Nominal
slew rate DC to V
REF
region
tIH
tIS tIS
VSS
CK#
CK
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region
Nominal
slew rate
tIH
Figure 27: Tangent Line for tIH
Tangent
line DC to V
REF
region
tIH
tIS tIS
VSS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region Tangent
line
tIH
CK
CK#
Hold slew rate
falling signal
ǻTFǻTR
Tangent line (V
IH[DC]min
- V
REF[DC]
)
ǻ
TF
=
Nominal
line
Hold slew rate
rising signal
Tangent line (V
REF[DC]
- V
IL[DC]max
)
ǻ
TR
=
Nominal
line
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Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQ
Slew
Rate
(V/ns)
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
Δ
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
2.0 125 45 125 45 125 45 – – – – – – – – – – – –
1.5 83 21 83 21 83 21 95 33 – – – – – – – – – –
1.0 0 0 0 0 0 0 12 12 24 24 – – – – – – – –
0.9 – –11 –14 –11 –14 1 –2 13 10 25 22
0.8 –25 –31 –13 –19 –1 –7 11 5 23 17
0.7 –31 –42 –19 –30 –7 –18 5 –6 17 6
0.6 –43 –59 –31 –47 –19 –35 –7 –23 5 –11
0.5 –74 –89 –62 –77 –50 –65 –38 –53
0.4 – – – – – – – – – –127 –140 –115 –128 –103 –116
Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data
sheet value to the derating value listed in Table 31.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-
ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-
tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 28 (page 66)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “VREF(DC) to AC region,” the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 29 (page 66)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first
crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 30 (page 67)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to VREF(DC) region,” the slew rate of a tan-
gent line to the actual signal from the DC level to VREF(DC) level is used for the derating
value (see Figure 31 (page 67)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 33 (page 64) are the
DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to VREF is listed in Table 35 (page 65) and
Table 36 (page 65). Table 35 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-533. Table 36 provides the VREF-based fully derated values for
the DQ (tDSa and tDHa) for DDR2-400.
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Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQ
Slew
Rate
(V/ns)
DQS, DQS# Differential Slew Rate
2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
Δ
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135
1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114
1.0000000121224243636484860607272
0.9 –5 –14 –5 –14 –5 –14 7 –2 19 10 31 22 43 34 55 46 67 58
0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41
0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18
0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11
0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53
0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116
Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data
sheet value to the derating value listed in Table 32.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VREF(DC) and the first cross-
ing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-
tween the shaded “VREF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 28 (page 66)). If the actual signal is later than the nominal slew rate
line anywhere between shaded “VREF(DC) to AC region,” the slew rate of a tangent line
to the actual signal from the AC level to DC level is used for the derating value (see Fig-
ure 29 (page 66)).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC)min and the first
crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to VREF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 30 (page 67)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded “DC to VREF(DC) region,” the slew rate of a
tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat-
ing value (see Figure 31 (page 67)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH[AC]/VIL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 33 (page 64) are the
DQS single-ended slew rate derating with DQS referenced at VREF and DQ referenced at
the logic levels tDSb and tDHb. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to VREF is listed in Table 34 (page 64). Ta-
ble 34 provides the VREF-based fully derated values for the DQ (tDSa and tDHa) for
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DDR2-667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-
ended DQS; however, Table 33 would be used with the base values.
Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb
Reference points indicated in bold; Derating values are to be used with base tDSb- and tDHb--specified values
DQ (V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38
1.5 97 32 97 32 97 32 97 32 97 32 112 27 122 24 132 20 142 17
1.0 30 –10 30 –10 30 –10 30 –10 30 –10 45 –15 55 –18 65 –22 75 –25
0.9 25 –24 25 –24 25 –24 25 –24 25 –24 40 –29 50 –32 60 –36 70 –39
0.8 17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56
0.7 5 –64 5 –64 5 –64 5 –64 5 –64 20 –69 30 –72 40 –75 50 –79
0.6 –7 –93 –7 –93 –7 –93 –7 –93 –7 –93 8 –98 18 –102 28 –105 38 –108
0.5 –28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143 7 –147 17 –150
0.4 –78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667
Reference points indicated in bold
DQ (V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276
1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275
1.0 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275
0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275
0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275
0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275
0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275
0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275
0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274
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Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533
Reference points indicated in bold
DQ (V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326
1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325
1.0 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325
0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325
0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325
0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325
0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325
0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325
0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400
Reference points indicated in bold
DQ (V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2.0 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376
1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375
1.0 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375
0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375
0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375
0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375
0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375
0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375
0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374
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Figure 28: Nominal Slew Rate for tDS
VREF to AC
region
VREF to AC
region
Setup slew rate
rising signal
Setup slew rate
falling signal
ǻ
TF
ǻ
TR
VREF(DC)
- VIL(AC)max
ǻTF
=
VIH(AC)min
-
VREF(DC)
ǻTR
=
Nominal
slew rate
VSS
DQS#1
DQS1
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
tDH
tDS
Nominal
slew rate
tDH
tDS
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 29: Tangent Line for tDS
ǻ
TF
ǻ
TR
Setup slew rate
rising signal
Setup slew rate
falling signal
Tangent line (V
REF[DC]
- V
IL[AC]max
)
ǻTF
=
Tangent line (V
IH[AC]min
- V
REF[DC]
)
ǻTR
=
tDH
tDS
tDH
tDS
VSS
DQS#1
DQS1
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Nominal line
Tangent line
Nominal
line
Tangent line
V
REF
to AC
region
V
REF
to AC
region
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
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Figure 30: Nominal Slew Rate for tDH
Hold slew rate
falling signal
Hold slew rate
rising signal
VREF(DC) -
V
IL(DC)max
ǻ
TR
=
V
IH(DC)min
-
VREF(DC)
ǻ
TF
=
ǻTR ǻTF
Nominal
slew rate DC to V
REF
region
tIH
tIS tIS
VSS
DQS#1
DQS1
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region
Nominal
slew rate
tIH
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 31: Tangent Line for tDH
Tangent
line DC to V
REF
region
tIH
tIS tIS
VSS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region Tangent
line
tIH
DQS1
DQS#1
Hold slew rate
falling signal
ǻTF
ǻTR
Tangent line (V
IH[DC]min
- V
REF[DC]
)
ǻTF
=
Nominal
line
Hold slew rate
rising signal
Tangent line (V
REF[DC]
- V
IL[DC]max
)
ǻTR
=
Nominal
line
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
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Figure 32: AC Input Test Signal Waveform Command/Address Balls
tISa
Logic levels
VREF levels
tIHatISatIHa
tISbtIHbtISbtIHb
CK#
CK
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)min
VIL(AC)min
VSSQ
Vswing (MAX)
Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
DQS#
DQS
tDSatDHatDSatDHa
tDSbtDHbtDSbtDHb
Logic levels
VREF levels
VREF(DC)
VIL(DC)max
VIL(AC)max
VSSQ
VIH(DC)min
VIH(AC)min
VDDQ
Vswing (MAX)
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Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended)
DQS
VREF
V
REF(DC)
V
IL(DC)max
V
IL(AC)max
V
SSQ
V
IH(DC)min
V
IH(AC)min
V
DDQ
Vswing (MAX)
Logic levels
VREF levels
tDSatDHatDSatDHa
tDSbtDHbtDSbtDHb
Figure 35: AC Input Test Signal Waveform (Differential)
VTR
Vswing
VCP
VDDQ
VSSQ
VIX
Crossing point
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Commands
Truth Tables
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.
Table 37: Truth Table – DDR2 Commands
Notes: 1–3 apply to the entire table
Function
CKE
CS# RAS# CAS# WE#
BA2–
BA0 An–A11 A10 A9–A0 Notes
Previous
Cycle
Current
Cycle
LOAD MODE H H L L L L BA OP code 4, 6
REFRESH H H L L L H X X X X
SELF REFRESH entry H L L L L H X X X X
SELF REFRESH exit L H H X X X X X X X 4, 7
LHHH
Single bank
PRECHARGE
HHLLHLBAXLX6
All banks PRECHARGE H H L L H L X X H X
Bank ACTIVATE H H L L H H BA Row address 4
WRITE H H L H L L BA Column
address
L Column
address
4, 5, 6,
8
WRITE with auto
precharge
H H L H L L BA Column
address
H Column
address
4, 5, 6,
8
READ H H L H L H BA Column
address
L Column
address
4, 5, 6,
8
READ with auto
precharge
H H L H L H BA Column
address
H Column
address
4, 5, 6,
8
NO OPERATION H X L H H H X X X X
Device DESELECT H X H X X X X X X X
Power-down entry H L H X X X X X X X 9
LHHH
Power-down exit L H H X X X X X X X 9
LHHH
Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at
the rising edge of the clock.
2. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh. See ODT Timing (page 127) for details.
3. “X” means “H or L” (but a defined logic level) for valid IDD measurements.
4. BA2 is only applicable for densities 1Gb.
5. An n is the most significant address bit for a given density and configuration. Some larg-
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.
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6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
MODE command selects which mode register is programmed.
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 49
(page 96) and Figure 61 (page 107) for other restrictions and details.
9. The power-down mode does not perform any REFRESH operations. The duration of
power-down is limited by the refresh requirements outlined in the AC parametric sec-
tion.
Table 38: Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
Current
State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVATE (select and activate row)
L L L H REFRESH 7
L L L L LOAD MODE 7
Row active L H L H READ (select column and start READ burst) 8
L H L L WRITE (select column and start WRITE burst) 8
L L H L PRECHARGE (deactivate row in bank or banks) 9
Read (auto
precharge
disabled)
L H L H READ (select column and start new READ burst) 8
L H L L WRITE (select column and start WRITE burst) 8, 10
L L H L PRECHARGE (start PRECHARGE) 9
Write
(auto pre-
charge disa-
bled)
L H L H READ (select column and start READ burst) 8
L H L L WRITE (select column and start new WRITE burst) 8
L L H L PRECHARGE (start PRECHARGE) 9
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, tRP has been met, and any READ burst is com-
plete.
Row
active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled and has not yet
terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any
clock edge occurring during these states. Allowable commands to the other bank are
determined by its current state and this table, and according to Table 39 (page 73).
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Commands
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Precharge: Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Read with auto
precharge
enabled:
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when
tRCD is met. After tRCD is met, the bank will be in the row active
state.
Write with auto
precharge
enabled:
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
Refresh: Starts with registration of a REFRESH command and ends when tRFC is
met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle
state.
Accessing
mode
register:
Starts with registration of the LOAD MODE command and ends when
tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in the
all banks idle state.
Precharge
all:
Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
in a valid state for precharging.
10. A WRITE command may be applied after the completion of the READ burst.
512Mb: x4, x8, x16 DDR2 SDRAM
Commands
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2004 Micron Technology, Inc. All rights reserved.
Table 39: Truth Table – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise allowed to bank m
Row
active, active,
or precharge
L L H H ACTIVATE (select and activate row)
L H L H READ (select column and start READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read (auto
precharge
disabled)
L L H H ACTIVATE (select and activate row)
L H L H READ (select column and start new READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7, 8
L L H L PRECHARGE
Write (auto
precharge
disabled)
L L H H ACTIVATE (select and activate row)
L H L H READ (select column and start READ burst) 7, 9, 10
L H L L WRITE (select column and start new WRITE burst) 7
L L H L PRECHARGE
Read (with
auto
precharge)
L L H H ACTIVATE (select and activate row)
L H L H READ (select column and start new READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7, 8
L L H L PRECHARGE
Write (with
auto
precharge)
L L H H ACTIVATE (select and activate row)
L H L H READ (select column and start READ burst) 7, 10
L H L L WRITE (select column and start new WRITE burst) 7
L L H L PRECHARGE
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table describes an alternate bank operation, except where noted (the current state
is for bank n and the commands shown are those allowed to be issued to bank m, as-
suming that bank m is in such a state that the given command is allowable). Exceptions
are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, tRP has been met, and any READ
burst is complete.
Row active: A row in the bank has been activated and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled
and has not yet terminated.
Write: A WRITE burst has been initiated with auto precharge disabled
and has not yet terminated.
512Mb: x4, x8, x16 DDR2 SDRAM
Commands
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2004 Micron Technology, Inc. All rights reserved.
READ with auto
precharge enabled/
WRITE with auto
precharge enabled:
The READ with auto precharge enabled or WRITE with auto pre-
charge enabled states can each be broken into two parts: the ac-
cess period and the precharge period. For READ with auto pre-
charge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all
of the data in the burst. For WRITE with auto precharge, the pre-
charge period begins when tWR ends, with tWR measured as if
auto precharge was disabled. The access period starts with regis-
tration of the command and ends where the precharge period
(or tRP) begins. This device supports concurrent auto precharge
such that when a READ with auto precharge is enabled or a
WRITE with auto precharge is enabled, any command to other
banks is allowed, as long as that command does not interrupt
the read or write data transfer already in process. In either case,
all other related limitations apply (contention between read da-
ta and write data must be avoided).
The minimum delay from a READ or WRITE command with auto precharge enabled to
a command to a different bank is summarized in Table 40 (page 74).
4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
10. The number of clock cycles required to meet tWTR is either two or t</