iCE40 Ultra™ Family Datasheet

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Datasheet

iCE40 Ultra™ Family Data Sheet
DS1048 Version 2.0, June 2016
www.latticesemi.com 1-1 DS1048 Introduction_01.8
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
General Description
iCE40 Ultra family is an ultra-low power FPGA and sensor manager designed for ultra-low power mobile applica-
tions, such as smartphones, tablets and hand-held devices. The iCE40 Ultra family includes integrated SPI and I2C
blocks to interface with virtually all mobile sensors and application processors. The iCE40 Ultra family also features
two on-chip oscillators, 10 kHz and 48 MHz. The LFOSC (10 kHz) is ideal for low power function in always-on appli-
cations, while HFOSC (48 MHz) can be used for awaken activities.
The iCE40 Ultra family also features DSP functional block to off-load Application Processor to pre-process informa-
tion sent from the mobile sensors. The embedded RGB PWM IP, with the three 24 mA constant current RGB out-
puts on the iCE40 Ultra provides all the necessary logic to directly drive the service LED, without the need of
external MOSFET or buffer.
The 500 mA constant current IR driver output provides a direct interface to external LED for application such as
IrDA functions. Users simply implement the modulation logic that meets his needs, and connect the IR driver
directly to the LED, without the need of external MOSFET or buffer. This high current IR driver can also be used as
Barcode Emulation, sending barcode information to external Barcode Reader.
The iCE40 Ultra family of devices are targeting for mobile applications to perform functions such as IrDA, Service
LED, Barcode Emulation, GPIO Expander, SDIO Level Shift, and other custom functions.
The iCE40 Ultra family features three device densities, from 1100 to 3520 Look Up Tables (LUTs) of logic with pro-
grammable I/Os that can be used as either SPI/I2C interface ports or general purpose I/O’s. It also has up to 80
kbits of Block RAMs to work with user logic.
iCE40 Ultra Family Data Sheet
Introduction
Features
Flexible Logic Architecture
Three devices with 1100 to 3520 LUTs
Offered in WLCS, ucfBGA and QFN packages
Ultra-low Power Devices
Advanced 40 nm ultra-low power process
As low as 71 µA standby current typical
Embedded Memory
Up to 80 kbits sysMEM™ Embedded Block RAM
Two Hardened I2C Interfaces
Two Hardened SPI Interfaces
Two On-Chip Oscillators
Low Frequency Oscillator – 10 kHz
High Frequency Oscillator – 48 MHz
24 mA Current Drive RGB LED Outputs
Three drive outputs in each device
User selectable sink current up to 24 mA
500 mA Current Drive IR LED Output
One IR drive output in each device
User selectable sink current up to 500 mA
On-chip DSP
Signed and unsigned 8-bit or 16-bit functions
Functions include Multiplier, Accumulator, and
Multiply-Accumulate (MAC)
Flexible On-Chip Clocking
Eight low skew global signal resource, six can
be directly driven from external pins
One PLL with dynamic interface per device
Flexible Device Configuration
SRAM is configured through:
— Standard SPI Interface
— Internal Nonvolatile Configuration Memory
(NVCM)
Ultra-Small Form Factor
As small as 2.078 mm x 2.078 mm
Applications
• Smartphones
Tablets and Consumer Handheld Devices
Handheld Commercial and Industrial Devices
Multi Sensor Management Applications
Sensor Pre-processing and Sensor Fusion
Always-On Sensor Applications
USB 3.1 Type C Cable Detect / Power Delivery
Applications
1-2
Introduction
iCE40 Ultra Family Data Sheet
Table 1-1. iCE40 Ultra Family Selection Guide
Introduction
The iCE40 Ultra family of ultra-low power FPGAs has three devices with densities ranging from 1100 to 3520 Look-
Up Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programma-
ble logic, these devices also feature Embedded Block RAM (EBR), on-chip Oscillators (LFOSC, HFOSC), two
hardened I2C Controllers, two hardened SPI Controllers, three 24 mA RGB LED open-drain drivers, a 500 mA IR
LED open-drain drivers, and DSP blocks. These features allow the devices to be used in low-cost, high-volume
consumer and mobile applications.
The iCE40 Ultra FPGAs are available in very small form factor packages, as small as 2.078 mm x 2.078 mm. The
small form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 1-1
shows the LUT densities, package and I/O pin count.
The iCE40 Ultra devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per-pin”
basis.
The iCE40 Ultra devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices
can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40
Ultra family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 Ultra. Lattice
design tools use the synthesis tool output along with the user-specified preferences and constraints to place and
route the design in the iCE40 Ultra device. These tools extract the timing from the routing and back-annotate it into
the design for timing verification.
Lattice provides in the iCE40 Ultra 1K and 2K device the embedded RGB PWM IP at no extra cost of LUT available
to the user, to perform controlling the RGB LED function. This embedded IP allow users to control color, LED ON/
OFF time, and breathe rate of the LED. For more information, please refer to Usage Guide in Lattice Design Soft-
ware.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40 Ultra FPGA family. Lattice also can provide fully verified bitstream
for some of the widely used target functions in mobile device applications, such as ultra-low power sensor manage-
ment, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by Lat-
tice, or they can use the design to create their own unique required functions. For more information regarding
Lattice's reference designs or fully-verified bitstreams, please contact your local Lattice representative.
Part Number iCE5LP1K iCE5LP2K iCE5LP4K
Logic Cells (LUT + Flip-Flop) 1100 2048 3520
EBR Memory Blocks 16 20 20
EBR Memory Bits 64 k 80 k 80 k
PLL Block 1 1 1
NVCM Yes Yes Yes
DSP Blocks (MULT16 with 32-bit Accumulator) 2 4 4
Hardened I2C, SPI 1,1 2,2 2,2
HF Oscillator (48 MHz) 1 1 1
LF Oscillator (10 kHz) 1 1 1
24 mA LED Sink 3 3 3
500 mA LED Sink 1 1 1
Embedded PWM IP Yes Yes No
Packages, ball pitch, dimension Total User I/O Count
36-ball WLCSP, 0.35 mm, 2.078 mm x 2.078 mm 26 26 26
36-ball ucfBGA, 0.40 mm, 2.5 mm x 2.5 mm 26 26 26
48-ball QFN Package, 0.5 mm, 7.0 mm x 7.0 mm 39 39 39
www.latticesemi.com 2-1 DS1048 Architecture_01.7
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Architecture Overview
The iCE40 Ultra family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator Genera-
tors, two user configurable I2C controllers, two user configurable SPI controllers, and blocks of sysMEM™ Embed-
ded Block RAM (EBR) surrounded by Programmable I/O (PIO). Figure 2-1shows the block diagram of the iCE5LP-
4K device.
Figure 2-1. iCE5LP-4K Device, Top View
The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows
and columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the
device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The
PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface stan-
dards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route
software tool automatically allocates these routing resources.
In the iCE40 Ultra family, there are three sysIO banks, one on top and two at the bottom. User can connect some
VCCIOs together, if all the I/Os are using the same voltage standard. Refer to the details in later sections of this doc-
ument on Power Up Sequence. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks
can be configured as RAM, ROM or FIFO with user logic using PLBs.
Every device in the family has two user SPI ports, one of these (right side) SPI port also supports programming
and configuration of the device. The iCE40 Ultra also includes two user I2C ports, two Oscillators, and high current
RGB and IR LED sinks.
5 4 Kbit RAM
5 4 Kbit RAM
5 4 Kbit RAM
5 4 Kbit RAM
PLB
I/O Bank 0
I/O Bank 2
I
2
C
I
2
C
SPI
SPI
HFOSC LFOSC
config
I/O Bank 1
DSP
DSP
DSP
NVCM
IR Drv
RGB
Drv
Flip-flop with Enable
and Reset Controls
Carry Logic
4-Input Look-up
Table (LUT)
8 Logic Cells = Programmable Logic Block
DSP
iCE40 Ultra Family Data Sheet
Architecture
2-2
Architecture
iCE40 Ultra Family Data Sheet
PLB Blocks
The core of the iCE40 Ultra device consists of Programmable Logic Blocks (PLB) which can be programmed to
perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in
Figure 2-2. Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to
four inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade
multiple LUTs to create wider logic functions.
A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic func-
tions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
comparators, binary counters and some wide, cascaded logic functions.
Table 2-1. Logic Cell Signal Descriptions
Function Type Signal Names Description
Input Data signal I0, I1, I2, I3 Inputs to LUT
Input Control signal Enable Clock enable shared by all LCs in the PLB
Input Control signal Set/Reset1 Asynchronous or synchronous local set/reset shared by all LCs in
the PLB.
Input Control signal Clock Clock one of the eight Global Buffers, or from the general-purpose
interconnects fabric shared by all LCs in the PLB
Input Inter-PLB signal FCIN Fast carry in
Output Data signals O LUT or registered output
Output Inter-PFU signal FCOUT Fast carry out
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
= Statically defined by configuration program
LUT
Carry Logic
Logic Cell
SR
EN
DQ
DFF
Flip-flop with
optional enable and
set or reset controls
Four-input
Look-Up Table
(LUT)
Clock
Enable
FCOUT
FCIN
Set/Reset
Shared Block-Level Controls
Programmable Logic
Block (PLB)
8 Logic Cells (LCs)
I0
I1
I2
I3
O
1
0
2-3
Architecture
iCE40 Ultra Family Data Sheet
Routing
There are many resources provided in the iCE40 Ultra devices to route signals individually with related control sig-
nals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
Clock/Control Distribution Network
Each iCE40 Ultra device has six global inputs, two pins on the top bank and four pins on the bottom bank
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are
identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0].
These six inputs may be used as general purpose I/O if they are not used to drive the clock nets.
Table 2-2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally
connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered
global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the
PLB clock-enable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5
can connect to the two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC).
Table 2-2. Global Buffer (GBUF) Connections to Programmable Logic Blocks
The maximum frequency for the global buffers are shown in the iCE40 Ultra External Switching Characteristics
tables later in this document.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 Ultra device. This GHIZ sig-
nal is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-imped-
ance state.
Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 Ultra device. The global reset
signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up
state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the
application.
Global Buffer LUT Inputs Clock Clock Enable Reset
GBUF0
Yes, any 4 of 8
GBUF Inputs

GBUF1 
GBUF2 
GBUF3 
GBUF4 
GBUF5 
GBUF6 
GBUF7 
2-4
Architecture
iCE40 Ultra Family Data Sheet
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 Ultra devices have one sys-
CLOCK PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an exter-
nal I/O pin, the internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the
PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the refer-
ence frequency and thus synthesize a higher frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output.
The output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to
drive the iCE40 Ultra global clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock
which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be
either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock
after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has
been satisfied.
There is an additional feature in the iCE40 Ultra PLL. There are 2 FPGA controlled inputs, SCLK and SDI, that
allows the user logic to serially shift in data thru SDI, clocked by SCLK clock. The data shifted in would change the
configuration settings of the PLL. This feature allows the PLL to be time multiplexed for different functions, with dif-
ferent clock rates. After the data is shifted in, user would simply pulse the RESET input of the PLL block, and the
PLL will re-lock with the new settings. For more details, please refer to TN1251, iCE40 sysCLOCK PLL Design and
Usage Guide.
Figure 2-3. PLL Diagram
Table 2-3 provides signal descriptions of the PLL block.
2-5
Architecture
iCE40 Ultra Family Data Sheet
Table 2-3. PLL Signal Descriptions
sysMEM Embedded Block RAM Memory
Larger iCE40 Ultra device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs),
each 4 kbit in size. This memory can be used for a wide variety of purposes including data buffering, and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic
resources. Each block can be used in a variety of depths and widths as shown in Table 2-4.
Signal Name Direction Description
REFERENCECLK Input Input reference clock
BYPASS Input The BYPASS control selects which clock signal connects to the PLL-
OUT output.
0 = PLL generated signal
1 = REFERENCECLK
EXTFEEDBACK Input External feedback input to PLL. Enabled when the FEEDBACK_PATH
attribute is set to EXTERNAL.
DYNAMICDELAY[7:0] Input Fine delay adjustment control inputs. Enabled when
DELAY_ADJUSTMENT_MODE is set to DYNAMIC.
LATCHINPUTVALUE Input When enabled, puts the PLL into low-power mode; PLL output is held
static at the last input clock value. Set ENABLE ICEGATE_PORTA and
PORTB to ‘1’ to enable.
PLLOUTGLOBAL Output Output from the Phase-Locked Loop (PLL). Drives a global clock net-
work on the FPGA. The port has optimal connections to global clock
buffers GBUF4 and GBUF5.
PLLOUTCORE Output Output clock generated by the PLL, drives regular FPGA routing. The
frequency generated on this output is the same as the frequency of the
clock signal generated on the PLLOUTLGOBAL port.
LOCK Output When High, indicates that the PLL output is phase aligned or locked to
the input reference clock.
RESET Input Active low reset.
SCLK Input Input, Serial Clock used for re-programming PLL settings.
SDI Input Input, Serial Data used for re-programming PLL settings.
2-6
Architecture
iCE40 Ultra Family Data Sheet
Table 2-4. sysMEM Block Configurations1
Block RAM
Configuration
Block RAM
Configuration
and Size
WADDR Port
Size (Bits)
WDATA Port
Size (Bits)
RADDR Port
Size (Bits)
RDATA Port
Size (Bits)
MASK Port
Size (Bits)
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
256x16 (4 k) 8 [7:0] 16 [15:0] 8 [7:0] 16 [15:0] 16 [15:0]
SB_RAM512x8
SB_RAM512x8NR
SB_RAM512x8NW
SB_RAM512x8NRNW
512x8 (4 k) 9 [8:0] 8 [7:0] 9 [8:0] 8 [7:0] No Mask Port
SB_RAM1024x4
SB_RAM1024x4NR
SB_RAM1024x4NW
SB_RAM1024x4NRNW
1024x4 (4 k) 10 [9:0] 4 [3:0] 10 [9:0] 4 [3:0] No Mask Port
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
SB_RAM2048x2NRNW
2048x2 (4 k) 11 [10:0] 2 [1:0] 11 [10:0] 2 [1:0] No Mask Port
1. For iCE40 Ultra, the primitive name without "Nxx" uses rising-edge Read and Write clocks. "NR" uses rising-edge Write clock, falling-edge
Read clock. "NW" uses falling-edge Write clock and rising-edge Read clock. "NRNW" uses falling-edge clocks on both Read and Write.
2-7
Architecture
iCE40 Ultra Family Data Sheet
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
RAM4k Block
Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Figure 2-4. sysMEM Memory Primitives
Table 2-5. EBR Signal Descriptions
For further information on the sysMEM EBR block, please refer to TN1250, Memory Usage Guide for iCE40
Devices.
Signal Name Direction Description
WDATA[15:0] Input Write Data input.
MASK[15:0] Input
Masks write operations for individual data bit-lines.
0 = write bit
1 = do not write bit
WADDR[7:0] Input Write Address input. Selects one of 256 possible RAM locations.
WE Input Write Enable input.
WCLKE Input Write Clock Enable input.
WCLK Input Write Clock input. Default rising-edge, but with falling-edge option.
RDATA[15:0] Output Read Data output.
RADDR[7:0] Input Read Address input. Selects one of 256 possible RAM locations.
RE Input Read Enable input.
RCLKE Input Read Clock Enable input.
RCLK Input Read Clock input. Default rising-edge, but with falling-edge option.
WCLK
WERE
WCLKE RCLKE
RCLK
WDATA[15:0] RDATA[15:0]
MASK[15:0]
WADDR[7:0] RADDR[7:0]
Write Port Read Port
RAM4K
RAM Block
(256x16)
2-8
Architecture
iCE40 Ultra Family Data Sheet
sysDSP
The iCE40 Ultra family provides an efficient sysDSP architecture that is very suitable for low-cost Digital Signal
Processing (DSP) functions for mobile applications. Typical functions used in these applications are Multiply, Accu-
mulate, and Multiply-Accumulate. The block can also be used for simple Add and Subtract functions.
iCE40 Ultra sysDSP Architecture Features
The iCE40 Ultra sysDSP supports many functions that include the following:
Single 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit Multipliers
Optional independent pipeline control on Input Register, Output Register, and Intermediate Reg faster clock
performance
Single 32-bit Accumulator, or two independent 16-bit Accumulators
Single 32-bit, or two independent 16-bit Adder/Subtracter functions, registered or asynchronous
Cascadable to create wider Accumulator blocks
Figure 2-5 shows the block diagram of the sysDSP block. The block consists Multiplier section, with an bypassable
Output register. The Input Register, Intermediate register between Multiplier and AC timing to achieve the highest
performance.
Figure 2-5. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate)
HLD
R
DQ
0
1
A[15:0]
C1
HLD
R
DQ
0
1
B[15:0]
C2
R
DQ
0
1
C4
R
DQ
0
1
C6
A[15:8]
B[15:8]
A[7:0]
B[15:8]
A[15:8]
B[7:0]
A[7:0]
B[7:0]
+
+
+
P[7:0]
P[31:24]
P[15:8]
P[23:16]
R
DQ
0
1
C5
8x8
8x8
8x8
8x8
0
1
C7
R
DQ
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:0]
[7:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
HLD
R
DQ
0
1
C[15:0]
C0
HLD
R
DQ
0
1
D[15:0]
C3
0
1HLD
R
DQ
0
1
2
C10
C11
0
1
2
3
C8
C9
±
Q[31:16]
C12
0
1
O[31:16]
0
1HLD
R
DQ
0
1
2
C17
C18
0
1
2
3
C15
C16
±
Q[15:0
C19
0
1
O[15:0]
8x8=16
8x8=16
16x16=32
[31:16]
0
1
2
3
C14
C13
0
1
2
3
C20
C21
01
01
CICAS
CHLD
IHRST
C
O
OHHLD
OHRST
CI
OHLDA
OLLDA
OLHLD
OLRST
Multiplier Accumulator
Hi
Lo
Input Registers
16x16 Pipeline
Registers
16x16
Pipeline
Register
ILRST
AHLD
BHLD
DHLD
OHADS
OLADS
CLK
ENA
W
X
Y
Z
F
G
H
C22
8x8 PowerSave
R
DQ
0
1
C6
J
K
L
ASGND
BSGND
PQ
RS
C
A
B
D
COCAS
LCO
LCOCA
S
HLD
HLD
HLD
3
3
SIGNEXTIN
SIGNEXTOUT
X[15]
Z[15]
LCI
HCI
0
1
=C23
=C24
0
1
CSA CSA
[15:8]
[15:8]
2-9
Architecture
iCE40 Ultra Family Data Sheet
Table 2-6. sysDSP Input/Output List
Signal
Primitive Port
Name Width
Input /
Output Function Default
CLK CLK 1 Input Clock Input. Applies to all clocked elements in the
sysDSP block
ENA CE 1 Input Clock Enable Input. Applies to all clocked elements
in the sysDSP block.
0 = Not Enabled
1 = Enabled
0: Enabled
A[15:0] A[15:0] 16 Input Input to the A Register. Feeds the Multiplier or is a
direct input to the Adder Accumulator
16'b0
B[15:0] B[15:0] 16 Input Input to the B Register. Feeds the Multiplier or is a
direct input to the Adder Accumulator
16'b0
C[15:0] C[15:0] 16 Input Input to the C Register. It is a direct input to the
Adder Accumulator
16'b0
D[15:0] D[15:0] 16 Input Input to the D Register. It is a direct input to the
Adder Accumulator
16'b0
AHLD AHOLD 1 Input A Register Hold.
0 = Update
1 = Hold
0: Update
BHLD BHOLD 1 Input B Register Hold.
0 = Update
1 = Hold
0: Update
CHLD CHOLD 1 Input C Register Hold.
0 = Update
1 = Hold
0: Update
DHLD DHOLD 1 Input D Register Hold.
0 = Update
1 = Hold
0: Update
IHRST IRSTTOP 1 Input Reset input to A and C input registers, and the
pipeline registers in the upper half of the Multiplier
Section.
0 = No Reset
1 = Reset
0: No Reset
ILRST IRSTBOT 1 Input Reset input to B and D input registers, and the
pipeline registers in the lower half of the Multiplier
Section. It also resets the Multiplier result pipeline
register.
0 = No Reset
1 = Reset
0: No Reset
O[31:0] O[31:0] 32 Output Output of the sysDSP block. This output can be:
O[31:0] 32-bit result of 16x16 Multiplier or
MAC
O[31:16] 16-bit result of 8x8 upper half Multi-
plier or MAC
O[15:0] 16-bit result of 8x8 lower half Multi-
plier or MAC
OHHLD OHOLDTOP 1 Input High-order (upper half) Accumulator Register Hold.
0 = Update
1 = Hold
0: Update
OHRST ORSTTOP 1 Input Reset input to high-order (upper half) bits of the
Accumulator Register.
0 = No Reset
1 = Reset
0: No Reset
2-10
Architecture
iCE40 Ultra Family Data Sheet
The iCE40 Ultra sysDSP can support the following functions:
8-bit x 8-bit Multiplier
16-bit x 16-bit Multiplier
16-bit Adder/Subtracter
32-bit Adder/Subtracter
16-bit Accumulator
32-bit Accumulator
8-bit x 8-bit Multiply-Accumulate
16-bit x 16-bit Multiply-Accumulate
Figure 2-6 shows the path for an 8-bit x 8-bit Multiplier using the upper half of sysDSP block.
OHLDA OLOADTOP 1 Input High-order (upper half) Accumulator Register
Accumulate/Load control.
0 = Accumulate, register is loaded with Adder/Sub-
tracter results
1 = Load, register is loaded with Input C or C Reg-
ister
0: Accumu-
late
OHADS ADDSUBTOP 1 Input High-order (upper half) Accumulator Add or Sub-
tract select.
0 = Add
1 = Subtract
0: Add
OLHLD OHOLDBOT 1 Input Low-order (lower half) Accumulator Register Hold.
0 = Update
1 = Hold
0: Update
OLRST ORSTBOT 1 Input Reset input to Low-order (lower half) bits of the
Accumulator Register.
0 =No Reset
1 = Reset
0: No Reset
OLLDA OLOADBOT 1 Input Low-order (lower half) Accumulator Register Accu-
mulate/Load control.
0 = Accumulate, register is loaded with Adder/Sub-
tracter results
1 = Load, register is loaded with Input C or C Reg-
ister
0: Accumu-
late
OLADS ADDSUBBOT 1 Input Low-order (lower half) Accumulator Add or Sub-
tract select.
0 = Add
1 = Subtract
0: Add
CICAS ACCUMCI 1 Input Cascade Carry/Borrow input from previous sys-
DSP block
CI CI 1 Input Carry/Borrow input from lower logic tile
COCAS ACCUMCO 1 Output Cascade Carry/Borrow output to next sysDSP
block
CO CO 1 Output Carry/Borrow output to higher logic tile
SIGNEXTIN SIGNEXTIN 1 Input Sign extension input from previous sysDSP block
SIGNEXTOUT SIGNEXTOUT 1 Output Sing extension output to next sysDSP block
Signal
Primitive Port
Name Width
Input /
Output Function Default
2-11
Architecture
iCE40 Ultra Family Data Sheet
Figure 2-6. sysDSP 8-bit x 8-bit Multiplier
Figure 2-7 shows the path for an 16-bit x 16-bit Multiplier using the upper half of sysDSP block.
HLD
R
DQ
0
1
A
[15 :0]
C1
HLD
R
DQ
0
1
B[15 :0]
C2
R
DQ
0
1
C4
R
DQ
0
1
C6
A[ 15 :8]
B[ 15 :8]
A[ 7:0 ]
B[ 15 :8]
A[ 15 :8]
B[ 7:0 ]
A[ 7:0 ]
B[ 7:0 ]
+
+
+
P[ 7:0 ]
P[ 31: 24]
P[ 15: 8]
P[ 23: 16]
R
DQ
0
1
C5
8x8
8x8
8x8
8x8
0
1
C7
R
DQ
[15:8]
[15:8]
[15:8]
[15:0]
[15:0 ]
[15:0]
[15:0]
[15:0]
[15:0]
HLD
R
DQ
0
1
C[ 1 5 : 0 ]
C0
HLD
R
DQ
0
1
D[ 15 :0 ]
C3
0
1HLD
R
DQ
0
1
2
C10
C11
0
1
2
3
C8
C9
Q[31:16 ]
C1 2
0
1
O[ 31:16 ]
0
1HLD
R
DQ
0
1
2
C17
C18
0
1
2
3
C15
C16
Q[15:0
C1 9
0
1
O[ 15:0]
8x8=16
8x8=16
16 x16 =32
[31:16 ]
0
1
2
3
C14
C13
0
1
2
3
C2 0
C2 1
01
01
CICAS
CHLD
IHRST
CO
OHHLD
OHRST
CI
OHLDA
OLLDA
OLHLD
OLRST
Multiplier Accumulator
High
Low
Input Registers
16 x16 Pipeline
Registers
16 x 16
Pipeline
Register
( 25 - FEB- 2012 )
ILRST
AHLD
BHLD
DHLD
OHADS
OLADS
CLK
ENA
W
X
Y
Z
F
G
H
C22 8x8 PowerSave
R
DQ
0
1
C6
J
K
L
ASGND
BSGND
PQ
RS
C
A
B
D
COCAS
LCO
LCOCAS
HLD
HLD
HLD
3
3
SIGNEXTIN
SIGNEXTOUT
X[ 15]
Z[15 ]
LCI
HCI
0
1
=C23
=C24
0
1
CSA CSA
[7:0]
[7:0]
[7:0]
[15:8]
[7:0]
2-12
Architecture
iCE40 Ultra Family Data Sheet
Figure 2-7. DSP 16-bit x 16-bit Multiplier
HLD
R
D
Q
0
1
A
A
[15:
:
0]
C
C
C
C
1
HLD
R
D
Q
0
1
B
B
[15:
:
0]
C
C
C
C
2
R
D
Q
0
1
C
C
4
R
D
Q
0
1
C
C
6
A
A
[15:
:
:
8]
B
B
[15:
:
:
8]
A
A
A
[7:
:
:
0]
B
B
[15:
:
:
8]
A[15:
:
8
8
]
B[7:
:
0
0
]
A[7:
:
0
0
]
B[7:
:
0
0
]
+
+
+
P[7
7
7
:0]
P[31
1
:2
4
4
]
P[15
5
:8]
P[23
3
:16
6
]
R
D
Q
0
1
C5
8x
x
8
8x
x
8
8x
x
8
8x
x
8
0
1
C7
R
D
Q
[
[
7
7
:
7
:
0
0
0
]
[15:8]
[7:0
0
]
[15
5
:8]
[7:0
0
]
[15
5
:
:
0]
[15
5
:0
0
]
[15:
0
]
[15
5
:
0
]
[15
5
5
:0]
[15:
:
:
0]
HLD
R
D
Q
0
1
C
[15:
:
0]
C
C
C
C
0
HLD
R
D
Q
0
1
D
D
[15:
:
0]
C
C
3
0
1
HLD
R
D
Q
0
1
2
C10
C11
0
1
2
3
C
C
C
C
8
C9
±
Q
Q
[31
1
:
:
16]
C
C
C
12
0
1
O
O
[31
1
:
:
16]
0
1
HLD
R
D
Q
0
1
2
C17
C18
0
1
2
3
C15
C16
±
Q
Q
[15
5
:
:
0
C
C
19
0
1
O
O
[15
5
:
:
0]
8x
x
8=16
8x
x
x
8=
=
16
16x16=32
[31
1
1
:16]
0
1
2
3
C
C
C
14
C1
1
3
0
1
2
3
C
C
20
C
C
21
0 1
0 1
CICAS
CHLD
IHRS
T
CO
OHHLD
OHRS
T
CI
OHLD
A
OLLDA
OLHLD
OLRS
T
Mulplier Accumulator
High
Input Registers
16x16 Pipeline
Registers
16x16
Pipeline
Register
(25
5
-FEB
B
B
-2012
2
)
ILRS
T
H
L
D
D
D
AHLD
BHLD
DHLD
OHADS
OLADS
CL
K
ENA
W
X
Y
Z
F
1
1
1
5
5
:
0
]
G
1
6
H
C22 8x
x
8PowerSave
[
R
D
Q
0
1
C6
J
1
5
5
:
:
5
5
0
1
[
1
K
L
ASGND
BSGND
P
Q
RS
C
A
B
D
COCAS
LCO
LCOCAS
HLD
HLD
HLD
3
3
SIGNEXTIN
SIGNEXTOU
T
X
X
[15
5
]
Z[15]
LCI
HCI
0
1
=
=
C
C
23
=
=
C
C
24
0
1
Low
[7:0
0
]
[15
5
:8]
[15
5
:8]
CSACSA
2-13
Architecture
iCE40 Ultra Family Data Sheet
sysIO Buffer Banks
iCE40 Ultra devices have up to three I/O banks with independent VCCIO rails. The configuration SPI interface sig-
nals are powered by SPI_VCCIO1. Please refer to the Pin Information Summary table.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respec-
tive sysIO buffers and pads. The PIOs are placed on the top and bottom of the devices.
Figure 2-8. I/O Bank and Programmable I/O Cell
The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block.
To save power, the optional iCEGateTM latch can selectively freeze the state of individual, non-registered inputs
within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of
modes along with the necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed inter-
face signals before they are passed to the device core.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysIO buffers.
Figure 2-9 shows the input/output register block for the PIOs.
OUT
OE
VCCIO
I/O Bank 0 or 2
Voltage Supply
0 = Hi-Z
1 = Output
Enabled
PAD
HD
iCEGATE
HOLD
Disabled ‘0’
OUTCLK
OUTCLK
INCLK
Enabled ‘1’
Latch inhibits
switching for
power saving
Pull-up
Enable
Pull-up
Gxx pins optionally
connect directly to
an associated
GBUF global
buffer
IN
LPSG
5 4 Kbit RAM
5 4 Kbit RAM
5 4 Kbit RAM
5 4 Kbit RAM
PLB
I/O Bank 0
I/O Bank 2
I2C
I
2
C
SPI
SPI
HFOSC LFOSC
config
I/O Bank 1
DSP
DSP
DSP
NVCM
IR Drv
RGB
Drv
DSP
PIO
2-14
Architecture
iCE40 Ultra Family Data Sheet
Figure 2-9. iCE I/O Register Block Diagram
Table 2-7. PIO Signal List
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in today’s systems with LVCMOS interfaces.
Pin Name I/O Type Description
OUTPUT_CLK Input Output register clock
CLOCK_ENABLE Input Clock enable
INPUT_CLK Input Input register clock
OUTPUT_ENABLE Input Output enable
D_OUT_0/1 Input Data from the core
D_IN_0/1 Output Data to the core
LATCH_INPUT_VALUE Input Latches/holds the Input Value
(1,0)
(1,0)
(1,0)
0
1
(1,0)
Pad
Pad
CLOCK_ENABLE
OUTPUT_ENABLE
OUTPUT_ENABLE
OUTPUT_CLK
INPUT_CLK
LATCH_INPUT_VALUE
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
D_OUT_1
D_OUT_0
D_IN_1
D_IN_0
D_OUT_1
D_OUT_0
PIO Pair
0
1
= Statically defined by configuration program.
2-15
Architecture
iCE40 Ultra Family Data Sheet
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, SPI_VCCIO1, and VPP_2V5 reach the level
defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet.
After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all VCCIO banks
are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical
to the application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak
pull-up to VCCIO. The I/O pins maintain the pre-configuration state until VCC, SPI_VCCIO1, and VPP_2V5 reach the
defined levels. The I/Os take on the software user-configured settings only after POR signal is deactivated and the
device performs a proper download/configuration. Unused I/Os are automatically blocked and the pull-up termina-
tion is disabled.
Supported Standards
The iCE40 Ultra sysIO buffer supports both single-ended input/output standards, and used as differential compara-
tors. The buffer supports the LVCMOS 1.8, 2.5, and 3.3 V standards. The buffer has individually configurable
options for bus maintenance (weak pull-up or none).
Table 2-8 and Table 2-9 show the I/O standards (together with their supply and reference voltages) supported by
the iCE40 Ultra devices.
Differential Comparators
The iCE40 Ultra devices provide differential comparator on pairs of I/O pins. These comparators are useful in some
mobile applications. Please refer to the Pin Information Summary section to locate the corresponding paired I/Os
with differential comparators.
Table 2-8. Supported Input Standards
Table 2-9. Supported Output Standards
On-Chip Oscillator
The iCE40 Ultra devices feature two different frequency Oscillator. One is tailored for low-power operation that runs
at low frequency (LFOSC). Both Oscillators are controlled with internally generated current.
The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal fre-
quency of 48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all
always-on functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions
detect a condition that would need to wake up the system to perform higher frequency functions.
Input Standard VCCIO (Typical)
3.3 V 2.5 V 1.8 V
Single-Ended Interfaces
LVCMOS33
LVCMOS25
LVCMOS18
Output Standard VCCIO (Typical)
Single-Ended Interfaces
LVCMOS33 3.3 V
LVCMOS25 2.5 V
LVCMOS18 1.8 V
2-16
Architecture
iCE40 Ultra Family Data Sheet
User I2C IP
The iCE40 Ultra devices have two I2C IP cores. Either of the two cores can be configured either as an I2C master or
as an I2C slave. The pins for the I2C interface are not pre-assigned. User can use any General Purpose I/O pins.
In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal,
using dedicated on-chip delay elements. This provides an easier interface with any external I2C components.
When the IP core is configured as master, it will be able to control other devices on the I2C bus through the pre-
assigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to
an I2C Master. The I2C cores support the following functionality:
Master and Slave operation
7-bit and 10-bit addressing
Multi-master arbitration support
Clock stretching
Up to 400 kHz data transfer speed
General Call support
Optionally delaying input or output data, or both
For further information on the User I2C, please refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide.
User SPI IP
The iCE40 Ultra devices have two SPI IP cores. The pins for the SPI interface are not pre-assigned. User can use
any General Purpose I/O pins. Both SPI IP cores can be configured as a SPI master or as a slave. When the SPI
IP core is configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP
core is configured as a slave, the device will be able to interface to an external SPI master.
The SPI IP core supports the following functions:
Configurable Master and Slave modes
Full-Duplex data transfer
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
LSB First or MSB First Data Transfer
For further information on the User SPI, please refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide.
High Current LED Drive I/O Pins
The iCE40 Ultra family devices offer multiple high current LED drive outputs in each device in the family to allow the
iCE40 Ultra product to drive LED signals directly on mobile applications.
There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs,
and provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive
the RBG LEDs, such as the service LED found in a lot of mobile devices. An embedded RGB PWM IP is also
offered in the family. This RGB drive current is user programmable from 4 mA to 24 mA, in increments of 4 mA. This
output functions as General Purpose I/O with open-drain when the high current LED drive is not needed.
2-17
Architecture
iCE40 Ultra Family Data Sheet
There is one output on each device that can sink up to 500 mA current. This output is open-drain, and provides
sinking current to drive an external IR LED connecting to the positive supply. This IR drive current is user program-
mable from 50 mA to 500 mA in increments of 50 mA. This output functions as General Purpose I/O with open-
drain when the high current LED drive is not needed.
Embedded PWM IP
To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be
embedded into the user design. This PWM IP provides the flexibility for user to dynamically change the settings on
the ON-time duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set
breath-on and breath-off time.
For additional information on the embedded PWM IP, please refer to TN1288, iCE40 LED Driver Usage Guide.
Non-Volatile Configuration Memory
All iCE40 Ultra devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure
the device.
For more information on the NVCM, please refer to TN1248, iCE40 Programming and Configuration.
iCE40 Ultra Programming and Configuration
This section describes the programming and configuration of the iCE40 Ultra family.
Device Programming
The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using
SPI_VCCIO1 power supply.
Device Configuration
There are various ways to configure the Configuration RAM (CRAM), using SPI port, including:
From a SPI Flash (Master SPI mode)
System microprocessor to drive a Serial Slave SPI port (SSPI mode)
For more details on configuring the iCE40 Ultra, please see TN1248, iCE40 Programming and Configuration.
Power Saving Options
The iCE40 Ultra devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic
power requirements of their applications. Table 2-10 describes the function of these features.
Table 2-10. iCE40 Ultra Power Saving Features Description
Device Subsystem Feature Description
PLL When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at
last input clock value.
iCEGate
To save power, the optional iCEGate latch can selectively freeze the state of individual, non-regis-
tered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or
clock-enable control.
www.latticesemi.com 3-1 DS1048 DC and Switching_02.0
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Absolute Maximum Ratings1, 2, 3
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V
Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
NVCM Supply Voltage VPP_2V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
PLL Supply Voltage VCCPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V
I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 150 °C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 °C to 125 °C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
Recommended Operating Conditions1
Power Supply Ramp Rates1, 2
Symbol Parameter Min. Max. Units
VCC1Core Supply Voltage 1.14 1.26 V
VPP_2V5 VPP_2V5 NVCM Programming and
Operating Supply Voltage
Slave SPI Configuration 1.71 4 3.46 V
Master SPI Configuration 2.30 3.46 V
Configuration from NVCM 2.30 3.46 V
NVCM Programming 2.30 3.00 V
VCCIO1, 2, 3 I/O Driver Supply Voltage VCCIO_0, SPI_VCCIO1, VCCIO_2 1.71 3.46 V
VCCPLL PLL Supply Voltage 1.14 1.26 V
tJCOM Junction Temperature Commercial Operation 0 85 °C
tJIND Junction Temperature Industrial Operation 40 100 °C
tPROG Junction Temperature NVCM Programming 10.00 30.00 °C
1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. Please
refer to Power-Up Supply Sequencing section. VCC and VCCPLL are recommended to tie to same supply with an RC-based noise filter
between them. Please refer to TN1252, iCE40 Hardware Checklist.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration mode subject to the condition that none of
the HFOSC/LFOSC and RGB LED / IR LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a min-
imum 2.30 V level.
Symbol Parameter Min. Max. Units
tRAMP Power supply ramp rates for all power supplies. 0.6 10 V/ms
1. Assumes monotonic ramp rates.
2. Power up sequence must be followed. Please refer to Power-Up Supply Sequencing section.
iCE40 Ultra Family Data Sheet
DC and Switching Characteristics
3-2
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
Power-On Reset
All iCE40 Ultra devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device.
Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All
other supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must
be connected to power supplies for normal operation (including device configuration).
Power-Up Supply Sequencing
It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay
between the power supplies, however, there is a requirement for each supply to reach a level of 0.5V, or higher,
before any subsequent power supplies in the sequence are applied.
1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied
together subject to the recommendation to include a RC-based noise filter on the VCCPLL (Please refer to
TN1252, iCE40 Hardware Checklist.)
2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and
VCCPLL) have reached as level of 0.5 V or higher.
3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and
SPI_VCCIO1) have reached a level of 0.5 V or higher.
4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any
time after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater.
There is no power down sequence required. However, when partial power supplies are powered down, it is
required the above sequence to be followed when these supplies are repowered up again.
External Reset
When all power supplies have reached to their minimum operating voltage defined in Minimum Operation Condition
Table, it is required to either keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of
tCRESET_B, and release it to go HIGH, to start configuration download from either the internal NVCM or the external
Flash memory.
Figure 3-1 shows Power-Up sequence when SPI_VCCIO1 and VPP_2V5 are connected separately, and the
CRESET_B signal triggers configuration download. Figure 3-2 shows when SPI_VCCIO1 and VPP_2V5 connected
together.
All power supplies should be powered up during configuration. Before and during configuration, the I/Os are held in
tri-state. I/Os are released to user functionality once the device has finished configuration.
Figure 3-1. Power Up Sequence with SPI_VCCIO1 and VPP_2V5 Not Connected Together
VCC/VCC_PLL = 1.2 V
SPI_VCCIO1 = 1.8 V
VPP_2V5, VCCIO0 and VCCIO2= 2.5 V / 3.3 V
0.5 V
CRESET_B
tCRESET_B
VSUPPLY(MIN)
3-3
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
Figure 3-2. Power Up Sequence with All Supplies Connected Together
Power-On-Reset Voltage Levels1
ESD Performance
Please contact Lattice Semiconductor for additional information.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Min. Max. Units
VPORUP Power-On-Reset ramp-up trip point (circuit monitoring
VCC, SPI_VCCIO1, VPP_2V5)
VCC 0.62 0.92 V
SPI_VCCIO1 0.87 1.50 V
VPP_2V5 0.90 1.53 V
VPORDN Power-On-Reset ramp-down trip point (circuit monitor-
ing VCC, SPI_VCCIO1, VPP_2V5)
VCC —0.79 V
SPI_VCCIO1 —1.50 V
VPP_2V5 —1.53 V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under rec-
ommended operating conditions.
Symbol Parameter Condition Min. Typ. Max. Units
IIL, IIH1, 3, 4 Input or I/O Leakage 0V < VIN < VCCIO + 0.2 V +/10 µA
C1I/O Capacitance, excluding
LED Drivers2
VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V —6—pF
C2Global Input Buffer
Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V —6—pF
C3RGB Pin Capacitance2VCC = Typ., VIO = 0 to 3.5 V 15 pF
C4IRLED Pin Capacitance2VCC = Typ., VIO = 0 to 3.5 V 53 pF
VHYST Input Hysteresis VCCIO = 1.8 V, 2.5 V, 3.3 V 200 mV
IPU Internal PIO Pull-up
Current
VCCIO = 1.8 V, 0=<VIN<=0.65 VCCIO 3—31 µA
VCCIO = 2.5 V, 0=<VIN<=0.65 VCCIO 8—72 µA
VCCIO = 3.3 V, 0=<VIN<=0.65 VCCIO 11 128 µA
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25 °C, f = 1.0 MHz.
3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
4. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO or lower than GND, the Input Leakage current will be
higher than the IIL and IIH.
VCC/VCC_PLL = 1.2 V
SPI_VCCIO, VPP_2V5, VCCIO0 and VCCIO2= 1.8 V / 2.5 V / 3.3 V
0.5 V
VSUPPLY(MIN)
CRESET_B
tCRESET_B
3-4
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
Supply Current 1, 2, 3, 4, 5
User I2C Specifications
User SPI Specifications1, 2
Symbol Parameter
Typ. VCC =
1.2 V4Units
ICCSTDBY Core Power Supply Static Current 71 µA
IPP2V5STDBY VPP_2V5 Power Supply Static Current 0.55 µA
ISPI_VCCIO1STDBY SPI_VCCIO1 Power Supply Static Current 0.5 µA
ICCIOSTDBY VCCIO Power Supply Static Current 0.5 µA
ICCPEAK Core Power Supply Startup Peak Current 8.0 mA
IPP_2V5PEAK VPP_2V5 Power Supply Startup Peak Current 7.0 mA
ISPI_VCCIO1PEAK SPI_VCCIO1 Power Supply Startup Peak Current 9.0 mA
ICCIOPEAK VCCIO Power Supply Startup Peak Current 7.5 mA
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI config-
uration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 °C, power supplies at nominal voltage, on devices processed in nominal process conditions.
4. Does not include pull-up.
5. Startup Peak Currents are measured with decoupling capacitance of 0.1 uF, 10 nF, and 1 nF to the power supply. Higher decoupling capac-
itance causes higher current.
Parameter
Symbol Parameter Description
spec (STD Mode) spec (FAST Mode)
UnitsMin Typ Max Min Typ Max
fSCL Maximum SCL clock frequency 100 400 kHz
tHI SCL clock HIGH Time 4 0.6 µs
tLO SCL clock LOW Time 4.7 1.3 µs
tSU,DAT Setup time (DATA) 250 100 ns
tHD,DAT Hold time (DATA) 0 0 ns
tSU,STA Setup time (START condition) 4.7 0.6 µs
tHD,STA Hold time (START condition) 4 0.6 µs
tSU,STO Setup time (STOP condition) 4 — — 0.6 — — µs
tBUF Bus free time between STOP and START 4.7 1.3 µs
tCO,DAT SCL LOW to DATAOUT valid 3.4 0.9 µs
Parameter
Symbol Parameter Description Min Typ Max Units
fMAX Maximum SCK clock frequency 45 MHz
1. All setup and hold time parameters on external SPI interface are design-specific and, therefore, generated by the Lattice Design Software
tools. These parameters include the following:
tSUmaster master Setup time (master mode)
tHOLDmaster master Hold time (master mode)
tSUslave slave Setup time (slave mode)
tHOLDslave slave Hold time (slave mode)
tSCK2OUT SCK to out (slave mode)
2. The SCLK duty cycle needs to be specified in the Lattice Design Software as a timing constraint in order to ensure proper timing check on
SCLK HIGH and LOW (tHI, tLO) time.
3-5
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
Internal Oscillators (HFOSC, LFOSC)1
sysIO Recommended Operating Conditions
sysIO Single-Ended DC Electrical Characteristics
Differential Comparator Electrical Characteristics
Parameter Parameter Description Spec/Recommended Units
Symbol Conditions Min Typ Max
fCLKHF
Commercial Temp HFOSC clock frequency (tJ = 0 oC85 oC) 10% 48 10% MHz
Industrial Temp HFOSC clock frequency (tJ = 40 oC100 oC) 20% 48 20% MHz
fCLKLF LFOSC CLKK clock frequency 10% 10 10% kHz
DCHCLKHF
Commercial Temp HFOSC clock frequency (tJ = 0 oC85 oC) 45 50 55 %
Industrial Temp HFOSC clock frequency (tJ = 45 oC100 oC) 40 50 60 %
DCHCLKLF LFOSC Duty Cycle (Clock High Period) 45 50 55 %
Tsync_on Oscillator output synchronizer delay 5 Cycles
Tsync_off Oscillator output disable delay 5 Cycles
1. Glitchless enabling and disabling OSC clock outputs.
Standard
VCCIO (V)
Min. Typ. Max.
LVCMOS 3.3 3.14 3.3 3.46
LVCMOS 2.5 2.37 2.5 2.62
LVCMOS 1.8 1.71 1.8 1.89
Input/
Output
Standard
VIL VIH VOL Max.
(V)
VOH Min.
(V)
IOL Max.
(mA)
IOH Max.
(mA)Min. (V) Max. (V) Min. (V) Max. (V)
LVCMOS 3.3 0.3 0.8 2.0 VCCIO + 0.2V 0.4 VCCIO 0.4 8 8
0.2 VCCIO 0.2 0.1 0.1
LVCMOS 2.5 0.3 0.7 1.7 VCCIO + 0.2V 0.4 VCCIO 0.4 6 6
0.2 VCCIO 0.2 0.1 0.1
LVCMOS 1.8 0.3 0.35VCCIO 0.65VCCIO VCCIO + 0.2V 0.4 VCCIO 0.4 4 4
0.2 VCCIO 0.2 0.1 0.1
Parameter
Symbol Parameter Description
Test
Conditions Min. Max. Units
VREF Reference Voltage to compare, on VINM VCCIO = 2.5 V 0.25 VCCIO 0.25 V V
VDIFFIN_H Differential input HIGH (VINP - VINM)V
CCIO = 2.5 V 250 mV
VDIFFIN_L Differential input LOW (VINP - VINM)V
CCIO = 2.5 V 250 mV
IIN Input Current, VINP and VINM VCCIO = 2.5 V 10 10 µA
3-6
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
Typical Building Block Function Performance1, 2
Pin-to-Pin Performance (LVCMOS25)
Register-to-Register Performance
Derating Logic Timing
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num-
bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num-
bers at a particular temperature and voltage.
Maximum sysIO Buffer Performance1
Function Timing Units
Basic Functions
16-bit decoder 16.5 ns
4:1 MUX 18.0 ns
16:1 MUX 19.5 ns
Function Timing Units
Basic Functions
16:1 MUX 110 MHz
16-bit adder 100 MHz
16-bit counter 100 MHz
64-bit counter 40 MHz
Embedded Memory Functions
256x16 Pseudo-Dual Port RAM 150 MHz
1. The above timing numbers are generated using the Lattice Design Software tool. Exact performance may
vary with device and tool version. The tool uses internal parameters that have been characterized but are not
tested on every device.
2. Under worst case operating conditions.
I/O Standard Max. Speed Units
Inputs
LVCMOS33 250 MHz
LVCMOS25 250 MHz
LVCMOS18 250 MHz
Outputs
LVCMOS33 250 MHz
LVCMOS25 250 MHz
LVCMOS18 155 MHz
1. Measured with a toggling pattern
3-7
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
iCE40 Ultra Family Timing Adders
Over Recommended Commercial Operating Conditions1, 2, 3
iCE40 Ultra External Switching Characteristics
Over Recommended Commercial Operating Conditions
Buffer Type Description Timing (Typ.) Units
Input Adjusters
LVC M O S33 LVC M O S, V CCIO = 3.3 V 0.18 ns
LVC M O S25 LVC M O S, V CCIO = 2.5 V 0 ns
LVC M O S18 LVC M O S, V CCIO = 1.8 V 0.19 ns
Output Adjusters
LVC M O S33 LVC M O S, V CCIO = 3.3 V 0.12 ns
LVC M O S25 LVC M O S, V CCIO = 2.5 V 0 ns
LVC M O S18 LVC M O S, V CCIO = 1.8 V 1.32 ns
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. Commercial timing numbers are shown.
Parameter Description Device Min Max Units
Clocks
Global Clocks
fMAX_GBUF Frequency for Global Buffer Clock network All devices 185 MHz
tW_GBUF Clock Pulse Width for Global Buffer All devices 2 ns
tSKEW_GBUF Global Buffer Clock Skew Within a Device All devices 500 ps
Pin-LUT-Pin Propagation Delay
tPD Best case propagation delay through one
LUT logic All devices 9.0 ns
General I/O Pin Parameters (Using Global Buffer Clock without PLL)1
tSKEW_IO Data bus skew across a bank of IOs All devices 410 ps
tCO Clock to Output PIO Output Register All devices 9.0 ns
tSU Clock to Data Setup PIO Input Register All devices 0.5 — ns
tHClock to Data Hold PIO Input Register All devices 5.55 ns
General I/O Pin Parameters (Using Global Buffer Clock with PLL)
tCOPLL Clock to Output PIO Output Register All Devices 2.9 ns
tSUPLL Clock to Data Setup PIO Input Register All Devices 5.9 ns
tHPLL Clock to Data Hold PIO Input Register All Devices 0.6 — ns
1. All the data is from the worst case condition.
3-8
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
sysDSP Timing
Over Recommended Operating Conditions
Parameter Descriptions Conditions Min. Max. Units
fIN Input Clock Frequency
(REFERENCECLK, EXTFEEDBACK) 10 133 MHz
fOUT Output Clock Frequency (PLLOUT) 16 275 MHz
fVCO PLL VCO Frequency 533 1066 MHz
fPFD Phase Detector Input Frequency 10 133 MHz
AC Characteristics
tDT Output Clock Duty Cycle 40 60 %
tPH Output Phase Accuracy +/12 deg
tOPJIT1, 5, 6
Output Clock Period Jitter fOUT >= 100 MHz 450 ps p-p
fOUT < 100 MHz 0.05 UIPP
Output Clock Cycle-to-cycle Jitter fOUT >= 100 MHz 750 ps p-p
fOUT < 100 MHz 0.10 UIPP
Output Clock Phase Jitter fPFD >= 25 MHz 275 ps p-p
fPFD < 25 MHz 0.05 UIPP
tWOutput Clock Pulse Width At 90% or 10% 1.33 ns
tLOCK2, 3 PLL Lock-in Time 50 µs
tUNLOCK PLL Unlock Time 50 ns
tIPJIT4Input Clock Period Jitter fPFD 20 MHz 1000 ps p-p
fPFD < 20 MHz 0.02 UIPP
tSTABLE3LATCHINPUTVALUE LOW to PLL Stable 500 ns
tSTABLE_PW3LATCHINPUTVALUE Pulse Width 100 ns
tRST RESET Pulse Width 10 ns
tRSTREC RESET Recovery Time 10 µs
tDYNAMIC_WD DYNAMICDELAY Pulse Width 100 VCO
Cycles
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.
Parameter Description Min. Max. Units
fMAX8x8SMULT Max frequency signed MULT8x8 bypassing
pipeline register 50 — MHz
fMAX16x16SMULT Max frequency signed MULT16x16 bypass-
ing pipeline register 50 — MHz
3-9
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
SPI Master or NVCM Configuration Time1, 2
sysCONFIG Port Timing Specifications
Symbol Parameter Conditions Max. Units
tCONFIG POR/CRESET_B to Device I/O Active
All devices Low Frequency (Default) 95 ms
All devices Medium frequency 35 ms
All devices High frequency 18 ms
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
Symbol Parameter Conditions Min. Typ. Max. Units
All Configuration Modes
tCRESET_B
Minimum CRESET_B LOW pulse width
required to restart configuration, from
falling edge to rising edge
200 — ns
tDONE_IO
Number of configuration clock cycles
after CDONE goes HIGH before the
PIO pins are activated
49 Clock
Cycles
Slave SPI
tCR_SCK
Minimum time from a rising edge on
CRESET_B until the first SPI WRITE
operation, first SPI_XCK clock. During
this time, the iCE40 Ultra device is
clearing its internal configuration mem-
ory
1200 — µs
fMAX CCLK clock frequency Write 1 25 MHz
Read1—15—MHz
tCCLKH CCLK clock pulsewidth HIGH 20 ns
tCCLKL CCLK clock pulsewidth LOW 20 ns
tSTSU CCLK setup time 12 ns
tSTH CCLK hold time 12 ns
tSTCO CCLK falling edge to valid output 13 ns
Master SPI3
fMCLK MCLK clock frequency
Low Frequency
(Default)
7.0 12.0 17.0 MHz
Medium Frequency221.0 33.0 45.0 MHz
High Frequency233.0 53.0 71.0 MHz
tMCLK CRESET_B HIGH to first MCLK edge 1200 µs
tSU CCLK setup time49.9 — — ns
tHD CCLK hold time 1 ns
1. Supported with 1.2 V Vcc and at 25 oC.
2. Extended range fMAX Write operations support up to 53 MHz with 1.2 V Vcc and at 25 oC.
3. tSU and tHD timing must be met for all MCLK frequency choices.
4. For considerations of SPI Master Configuration Mode, please refer to TN1248, iCE40 Programming and Configuration.
3-10
DC and Switching Characteristics
iCE40 Ultra Family Data Sheet
RGB LED and IR LED Drive
Switching Test Conditions
Figure 3-3 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage,
and other test conditions are shown in Table 3-1.
Figure 3-3. Output Test Load, LVCMOS Standards
Table 3-1. Test Fixture Required Components, Non-Terminated Interfaces
Symbol Parameter Min. Max. Units
ILED_ACCURACY RGB0, RGB1, RGB2 Sink Current Accuracy to selected current @
VLEDOUT >= 0.5 V
12 +12 %
ILED_MATCH RGB0, RGB1, RGB2 Sink Current Matching among the 3 outputs @
VLEDOUT >= 0.5 V
5+5 %
IIR_ACCURACY IR LED Sink Current Accuracy to selected current @ VIROUT >= 0.8 V 14 +14 %
Test Condition R1CLTiming Reference VT
LVCMOS settings (L -> H, H -> L) 0 pF
LVCMOS 3.3 = 1.5 V
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 3.3 (Z -> H)
188 0 pF
1.5 V VOL
LVCMOS 3.3 (Z -> L) 1.5 V VOH
Other LVCMOS (Z -> H) VCCIO/2 VOL
Other LVCMOS (Z -> L) VCCIO/2 VOH
LVCMOS (H -> Z) VOH 0.15 V VOL
LVCMOS (L -> Z) VOL 0.15 V VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
V
T
R1
CL
Test Poi n t
www.latticesemi.com 4-1 DS1048 Pinout Information_01.7
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Signal Descriptions
Signal Name Function I/O Description
Power Supplies
VCC Power Core Power Supply
VCCIO_0, SPI_VCCIO1, VCCIO_2 Power Power for I/Os in Bank 0, 1 and 2.
VPP_2V5 Power Power for NVCM programming and operations.
VCCPLL Power Power for PLL
GND GROUND — Ground
GND_LED GROUND Ground for LED drivers. Should connect to GND on
board.
Configuration
CRESETB Configuration I Configuration Reset, active LOW. No internal pull-up
resistor. Either actively driven externally or connect
an 10 kOhm pull-up to VCCIO_1.
CDONE Configuration I/O Configuration Done. Includes a weak pull-up resistor
to SPI_VCCIO1.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function.
Config SPI
Primary Secondary
CRESETB Configuration I Configuration Reset, active LOW. No internal pull-up
resistor. Either actively driven externally or connect
an 10 kOhm pull-up to SPI_VCCIO1.
PIOB_xx CDONE Configuration I/O Configuration Done. Includes a weak pull-up resistor
to SPI_VCCIO1.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function.
Config SPI
Primary Secondary
PIOB_34a SPI_SCK Configuration I/O This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs the clock to
external SPI memory.
In Slave SPI mode, this pin inputs the clock from
external processor.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
PIOB_32a SPI_SDO Configuration Output This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs the command
data to external SPI memory.
In Slave SPI mode, this pin connects to the MISO pin
of the external processor.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function.
iCE40 Ultra Family Data Sheet
Pinout Information
4-2
Pinout Information
iCE40 Ultra Family Data Sheet
PIOB_33b SPI_SI Configuration Input This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin receives data from exter-
nal SPI memory.
In Slave SPI mode, this pin connects to the MOSI pin
of the external processor.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function.
PIOB_35b SPI_SS_B Configuration I/O This pin is shared with device configuration. During
configuration:
In Master SPI mode, this pin outputs to the external
SPI memory.
In Slave SPI mode, this pin inputs from the external
processor.
General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function.
Global Signals
Primary Secondary
PIOT_46b G0 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G0 pin drives the GBUF0 global buffer
PIOT_45a G1 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G1 pin drives the GBUF1 global buffer
PIOT_25b G3 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G3 pin drives the GBUF3 global buffer
PIOT_12a G4 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G4 pin drives the GBUF4 global buffer
PIOT_11b G5 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G5 pin drives the GBUF5 global buffer
PIOB_3b G6 General I/O I/O In user mode, after configuration, this pin can be pro-
grammed as general I/O in user function
Global Input Global input used for high fanout, or clock/reset net.
The G6 pin drives the GBUF6 global buffer
LED Signals
RGB0 General I/O Open-Drain I/O In user mode, with user's choice, this pin can be pro-
grammed as open drain I/O in user function
LED Open-Drain
Output
In user mode, with user's choice, this pin can be pro-
grammed as open drain 24mA output to drive exter-
nal LED
RGB1 General I/O Open-Drain I/O In user mode, with user's choice, this pin can be pro-
grammed as open drain I/O in user function
LED Open-Drain
Output
In user mode, with user's choice, this pin can be pro-
grammed as open drain 24mA output to drive exter-
nal LED
Signal Name Function I/O Description
4-3
Pinout Information
iCE40 Ultra Family Data Sheet
RGB2 General I/O Open-Drain I/O In user mode, with user's choice, this pin can be pro-
grammed as open drain I/O in user function
LED Open-Drain
Output
In user mode, with user's choice, this pin can be pro-
grammed as open drain 24mA output to drive exter-
nal LED
IRLED General I/O Open-Drain I/O In user mode, with user's choice, this pin can be pro-
grammed as open drain I/O in user function
LED Open-Drain
Output
In user mode, with user's choice, this pin can be pro-
grammed as open drain 500mA output to drive exter-
nal LED
PIOT_xx General I/O I/O In user mode, with user's choice, this pin can be pro-
grammed as I/O in user function in the top (xx = I/O
location)
PIOB_xx General I/O I/O In user mode, with user's choice, this pin can be pro-
grammed as I/O in user function in the bottom (xx = I/
O location)
Signal Name Function I/O Description
4-4
Pinout Information
iCE40 Ultra Family Data Sheet
Pin Information Summary
Pin Type iCE5LP1K iCE5LP2K iCE5LP4K
CM36 SWG36 SG481CM36 SWG36 SG481CM36 SWG36 SG481
General Purpose I/O
Per Bank
Bank 0125171251712517
Bank 1 4 15 14 4 15 14 4 15 14
Bank 2106 8106 8106 8
Total General Purpose I/Os 26 26 39 26 26 39 26 26 39
VCC 112112112
VCCIO Bank 0111111111
Bank 1111111111
Bank 2111111111
VCCPLL 111111111
VPP_2V5 111111111
Dedicated Config Pins 112112112
GND 220220220
GND_LED 110110110
Total Balls 363648363648363648
1. 48-pin QFN package (SG48) requires the package paddle to be connected to GND.
www.latticesemi.com 5-1 DS1048 Order Info_01.9
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
iCE5LP Part Number Description
Tape and Reel Quantity
Package TR Quantity
CM36 4,000
SWG36 5,000
SG48 2,000
Logic Cells
Package
CM36 = 36-Ball ucfBGA (0.40 mm Ball Pitch)
SWG36 = 36-Ball WLCSP (0.35 mm Ball Pitch)
SG48 = 48-Pin QFN (0.50 mm Pin Pitch)
Device Family
iCE5LP FPGA
iCE5LPXX-XXXXXITR
1K = 1,100 Logic Cells
2K = 2,048 Logic Cells
4K = 3,520 Logic Cells
All parts are shipped in tape-and-reel.
TR
TR = Tape and Reel (See quantity below)
TR50 = Tape and Reel, 50 units
TR1K = Tape and Reel, 1,000 units
Grade
I = Industrial
iCE40 Ultra Family Data Sheet
Ordering Information
5-2
Ordering Information
iCE40 Ultra Family Data Sheet
Ordering Part Numbers
Industrial
Part Number LUTs Supply Voltage Package Pins Temp.
iCE5LP1K-CM36ITR 1100 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP1K-CM36ITR50 1100 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP1K-CM36ITR1K 1100 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP1K-SWG36ITR 1100 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP1K-SWG36ITR50 1100 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP1K-SWG36ITR1K 1100 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP1K-SG48ITR 1100 1.2 V Halogen-Free QFN 48 IND
iCE5LP1K-SG48ITR50 1100 1.2 V Halogen-Free QFN 48 IND
iCE5LP2K-CM36ITR 2048 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP2K-CM36ITR50 2048 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP2K-CM36ITR1K 2048 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP2K-SWG36ITR 2048 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP2K-SWG36ITR50 2048 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP2K-SWG36ITR1K 2048 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP2K-SG48ITR 2048 1.2 V Halogen-Free QFN 48 IND
iCE5LP2K-SG48ITR50 2048 1.2 V Halogen-Free QFN 48 IND
iCE5LP4K-CM36ITR 3520 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP4K-CM36ITR50 3520 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP4K-CM36ITR1K 3520 1.2 V Halogen-Free ucfBGA 36 IND
iCE5LP4K-SWG36ITR 3520 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP4K-SWG36ITR50 3520 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP4K-SWG36ITR1K 3520 1.2 V Halogen-Free WLCSP 36 IND
iCE5LP4K-SG48ITR 3520 1.2 V Halogen-Free QFN 48 IND
iCE5LP4K-SG48ITR50 3520 1.2 V Halogen-Free QFN 48 IND
October 2014 Data Sheet DS1048
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 6-1 DS1048 Further Info_01.4
For Further Information
A variety of technical notes for the iCE40 Ultra family are available on the Lattice web site.
TN1248, iCE40 Programming and Configuration
TN1274, iCE40 SPI/I2C Hardened IP Usage Guide
TN1276, Advanced iCE40 SPI/I2C Hardened IP Usage Guide
TN1250, Memory Usage Guide for iCE40 Devices
TN1251, iCE40 sysCLOCK PLL Design and Usage Guide
TN1252, iCE40 Hardware Checklist
TN1288, iCE40 LED Driver Usage Guide
TN1295, DSP Function Usage Guide for iCE40 Devices
TN1296, iCE40 Oscillator Usage Guide
iCE40 Ultra Pinout Files
iCE40 Ultra Pin Migration Files
Thermal Management document
Lattice design tools
Schematic Symbols
iCE40 Ultra Family Data Sheet
Supplemental Information
June 2016 Data Sheet DS1048
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 7-1 DS1048 Revision History
Date Version Section Change Summary
June 2016 2.0 Introduction Updated General Description section. Changed “high current driver” to
“high current IR driver”.
Updated Features section. In Table 1-1, iCE40 Ultra Family Selection
Guide, corrected HF Oscillator (48 kHz) to (48 MHz).
Architecture Updated Architecture Overview section.
— Changed content to “The Programmable Logic Blocks (PLB) and
sysMEM EBR blocks, are arranged in a two-dimensional grid with rows
and columns. Each column has either PLB or EBR blocks."
— Changed “high current LED sink” to "high current RGB and IR LED
sinks".
Updated sysCLOCK Phase Locked Loops (PLLs) section. Corrected
VCCPLL character format in Figure 2-3, PLL Diagram.
Updated sysMEM Embedded Block RAM Memory section. Updated
footnote in Table 2-4, sysMEM Block Configurations.
Updated sysIO Buffer Banks section.
— Changed statement to “The configuration SPI interface signals are
powered by SPI_VCCIO1.”
— Corrected VCCIO character format in Figure 2-8, I/O Bank and Pro-
grammable I/O Cell.
Updated Typical I/O Behavior During Power-up section. Modified text
content.
Updated Supported Standards section. Changed statement to “The
iCE40 Ultra sysIO buffer supports both single-ended input/output stan-
dards, and used as differential comparators.
Updated On-Chip Oscillator section. Changed statement to “The high
frequency oscillator (HFOSC) runs at a nominal frequency of 48 MHz,
divisible to 24 MHz, 12 MHz, or 6 MHz by user option.
Updated section heading to High Current LED Drive I/O Pins.
Changed “high current drive” to “high current LED drive”.
Removed Power On Reset section.
DC and Switching
Characteristics
Updated Absolute Maximum Ratings section.
— Corrected symbol character format.
Updated Recommended Operating Conditions section.
— Corrected symbol character format.
— Revised footnote 1.
— Added footnote 4.
Updated Power Supply Ramp Rates section. Changed tRAMP Max.
value.
Added Power-On Reset section.
Updated section heading to Power-Up Supply Sequencing. Revised text
content.
Added External Reset section.
Updated DC Electrical Characteristics section. Revised footnote 4.
iCE40 Ultra Family Data Sheet
Revision History
7-2
Revision History
iCE40 Ultra Family Data Sheet
Updated Supply Current section.
— Corrected IPP2V5STDBY parameter.
— Added Typ. VCC = 1.2 V values for ICCPEAK, IPP_2V5PEAK,
ISPI_VCCIO1PEAK, and ICCIOPEAK.
— Added footnote 5.
— Corrected SPI_VCCIO1 character format.
Updated User SPI Specifications section. Removed parameters and
added footnotes.
Updated Internal Oscillators (HFOSC, LFOSC) section. Added Com-
mercial and Industrial Temp values for DCHCLKHF
.
Updated sysIO Single-Ended DC Electrical Characteristics section.
Removed footnote.
Updated Register-to-Register Performance section. Modified footnotes.
Updated iCE40 Ultra External Switching Characteristics section. Modi-
fied footnote.
Updated sysCLOCK PLL Timing section. Reversed tOPJIT conditions.
Updated sysCONFIG Port Timing Specifications section.
— Modified tCR_SCK Min. value.
— Added footnote 4 to tSU parameter.
— Modified tSU Min. value.
— Modified tHD parameter.
Updated section heading to RGB LED and IR LED Drive. Modified
ILED_ACCURACY and IIR_ACCURACY parameters, Min. and Max.
values.
Pinout Information Updated Signal Descriptions section. Changed VCCIO_1 to SPI_VCCIO1
in the CDONE, CRESETB and PIOB_xx descriptions.
Updated Pin Information Summary section.
— Corrected symbol character format.
— Corrected VCPP_2V5 to VPP_2V5.
1.9 Introduction Updated Features section. Updated BGA package to ucfBGA.
DC and Switching
Characteristics
Updated Differential Comparator Electrical Characteristics section. Cor-
rected typo in VREF Max. value.
Pinout Information Updated Signal Descriptions section.
— Changed PIOB_12a to PIOB_xx
— Changed SPI_CSN to SPI_SS_B and revised description when in
Slave SPI mode.
— Corrected minor typo errors.
Updated Pin Information Summary section. Added footnote to SG48.
Ordering Information Updated iCE5LP Part Number Description section. Updated BGA pack-
age to ucfBGA.
Updated Ordering Part Numbers section. Updated BGA package to ucf-
BGA.
June 2015 1.8 DC and Switching
Characteristics
Updated Internal Oscillators (HFOSC, LFOSC) section. Removed deci-
mals.
Ordering Information Updated iCE5LP Part Number Description section.
— Added TR items.
— Corrected formatting errors.
Updated Ordering Part Numbers section. Updated CM36 and SG48
packages.
Date Version Section Change Summary
7-3
Revision History
iCE40 Ultra Family Data Sheet
April 2015 1.7 Architecture Updated sysDSP section. Revised the following figures:
— Figure 2-5, sysDSP Functional Block Diagram
(16-bit x 16-bit Multiply-Accumulate)
— Figure 2-6, sysDSP 8-bit x 8-bit Multiplier
— Figure 2-7, DSP 16-bit x 16-bit Multiplier
Ordering Information Updated iCE5LP Part Number Description section. Added TR items.
Updated Ordering Part Numbers section. Added CM36, SW36 and
SG48 part numbers.
March 2015 1.6 Introduction Updated Features section.
— Added BGA and QFN packages in Flexible Logic Architecture.
— Added USB 3.1 Type C Cable Detect / Power Delivery Applications in
Applications.
— Updated Table 1-1, iCE40 Ultra Family Selection Guide. Added 36-
ball ucfBGA and 48-ball QFN packages. Changed subheading to Total
User I/O Count. Changed RBW IP to PWM IP. Deleted footnotes.
DC and Switching
Characteristics
Updated Power-up Sequence section. Indicated all devices in second
paragraph.
Updated sysIO Single-Ended DC Electrical Characteristics section.
Changed LVCMOS 3.3 and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.
Replaced the Differential Comparator Electrical Characteristics table.
Pinout Information Updated Pin Information Summary section.
— Added CM36 and SG48 values.
— Changed CRESET_B to Dedicated Config Pins.
Ordering Information Updated iCE5LP Part Number Description section.
— Added CM36 and SG48 package.
— Added TR items.
Updated Ordering Part Numbers section. Added CM36, SW36 and
SG48 part numbers.
October 2014 1.5 Introduction Updated Features section.
— Removed 26 I/O pins for 36-pin WLCSP under Flexible Logic Archi-
tecture.
— Changed form factor to 2.078 mm x 2.078 mm.
— Updated Table 1-1, iCE40 Ultra Family Selection Guide. Removed
20-Ball WLCSP.
Updated Introduction section.
Changed form factor to 2.078 mm x 2.078 mm.
Architecture Updated sysCLOCK Phase Locked Loops (PLLs) section. Removed
note in heading regarding sysCLOCK PLL support.
DC and Switching
Characteristics
Updated Recommended Operating Conditions section. Removed foot-
note on sysCLOCK PLL support.
Updated Power-up Sequence section. Removed information on 20-pin
WLCSP.
Pinout Information Updated Signal Descriptions section. Removed references 20-pin
WLCSP.
Updated Pin Information Summary section. Removed references to
UWG20 values.
Ordering Information Updated iCE5LP Part Number Description section. Removed 20-ball
WLCSP.
Updated Ordering Part Numbers section. Removed UWG20 part num-
bers.
Further Information Added technical note references.
Date Version Section Change Summary
7-4
Revision History
iCE40 Ultra Family Data Sheet
August 2014 1.4 All Removed Preliminary document status.
Introduction Updated General Description section. Added information on high cur-
rent driver.
Updated Features section.
— Changed standby current typical to as low as 71 µA.
— Changed feature to Embedded Memory.
— Updated Table 1-1, iCE40 Ultra Family Selection Guide. Added
NVCM and Embedded PWM IP rows. Added (MULT16 with 32-bit Accu-
mulator) to DSP Block. Added Total I/O (Dedicated I/O) Count data.
General update to Introduction section.
Architecture Updated Architecture Overview section.
— Revised and added information on sysIO banks.
— Updated reference for embedded PWM IP.
Updated iCE40 Ultra Programming and Configuration section.
— Changed SPI1 to SPI.
— Changed VCCIO_1 to SPI_VCCIO1.
DC and Switching
Characteristics
Updated Absolute Maximum Ratings section.
Changed PLL Supply Voltage VCCPLL value.
Updated Recommended Operating Conditions section.
Added footnote to VCCPLL.
Updated Power-up Sequence section. General update.
Updated Power-On-Reset Voltage Levels section.
Changed the VPORUP VCC Max.value.
Updated DC Electrical Characteristics section.
Added C3 and C4 information.
Updated Supply Current section.
— Completed Typ. VCC =1.2 V4 data.
— Changed symbols to ISPI_VCCIO1STDBY and ISPI_VCCIO1PEAK.
— Added information to footnote 3.
Updated Internal Oscillators (HFOSC, LFOSC) section. General
update.
Updated iCE40 Ultra External Switching Characteristics section.
Added Max. value for tCOPLL. Added Min. values for tSUPLL and tHPLL.
Updated sysCLOCK PLL Timing section.
Added Max. value for tOPJIT
.
Updated sysCONFIG Port Timing Specifications section.
— Added TSU and THD information.
— Added footnote 3 to Master SPI.
Updated High Current LED and IR LED Drive section.
Updated Min. value.
July 2014 1.3 All Changed document status from Advance to Preliminary.
Introduction Updated Features section. Adjusted Ultra-low Power Devices standby
current.
DC and Switching
Characteristics
Updated AC/DC specifications numbers.
Date Version Section Change Summary
7-5
Revision History
iCE40 Ultra Family Data Sheet
June 2014 1.2 All Product name changed to iCE40 Ultra.
Introduction Updated Table 1-1, iCE40 Ultra Family Selection Guide. Removed 30-
ball WLCSP.
DC and Switching
Characteristics
Updated values in the following sections:
— Supply Current
— Internal Oscillators (HFOSC, LFOSC)
— Power Supply Ramp Rates
— Power-On-Reset Voltage Levels
— SPI Master or NVCM Configuration Time
Indicated TBD for values to be determined.
Pinout Information Updated Signal Descriptions section. Removed 30-pin WLCSP.
Updated Pin Information Summary section. Removed SWG30 values.
Ordering Information Updated iCE5LP Part Number Description section. Removed 30-ball
WLCSP.
Updated Ordering Part Numbers section. Removed SWG30 and
UWG30 part numbers.
May 2014 01.1 Introduction Updated General Description, Features, and Introduction sections.
Removed hardened RGB PWM IP information.
Architecture Updated Architecture Overview section. Removed the RGB IP block in
Figure 2-1, iCE5LP-4K Device, Top View, Figure 2-8, I/O Bank and Pro-
grammable I/O, and in the text content.
Updated High Current Drive I/O Pins section. Removed hardened RGB
PWM IP information.
Updated Power On Reset section. Removed content on Vccio_2 power
down option.
Replaced RGB PWM Block section with Embedded PWM IP section.
DC and Switching
Characteristics
Removed RGB PWM Block Timing section.
April 2014 01.0 All Initial release.
Date Version Section Change Summary

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