Since the introduction of Power over Ethernet (PoE) in 2003, its power delivery capability has increased dramatically from its original 15.4 watts to 30 watts, but designers still need more for their applications. A new amendment to the PoE specification, IEEE 802.3bt, addresses that need by enabling up to 60 watts (and in some applications up to 90 watts) at the power source.
The amendment was ratified in late 2018. The first commercial integrated Power Sourcing Equipment (PSE) controllers and Powered Device (PD) interfaces are now available allowing design engineers to take advantage of what is now called “High-Power PoE”.
This article describes how IEEE 802.3bt differs from previous versions of PoE, before introducing integrated PSE controllers and PD interfaces from Microsemi, Texas Instruments (TI), Linear Technology, and Nexperia. It describes how to best apply these devices to build a system, covering important considerations such as circuit protection and design and layout requirements.
What is IEEE 802.3bt?
The original standard (IEEE 802.3af) specified up to 15.4 watts at the power source which was ample for applications such as IP phones and Wi-Fi access points, but not enough for later applications such as IP video phones or pan-tilt-zoom (PTZ) cameras. The 2009 amendment to the specification (IEEE 802.3at) solved that problem by specifying 30 watts at the power source. In recent years demand has increased for even more power to support Ethernet connected applications such as point of sale (POS) terminals, IEEE 802.11ac access points and networked LED lighting.
To address the need for more power, the new IEEE 802.3bt (High-Power PoE) amendment to the previous PoE and PoE+ specification increases PSE minimum output power and PD minimum input power. The major change is that power can be carried over all four twisted pairs in a Cat5e Ethernet cable. PoE and PoE+ used just two of the twisted pairs: either the data lines in “Alternative A” applications or spare lines in “Alternative B” applications. (See Digi-Key library article, “An Introduction to Power-over-Ethernet”.)
The new specification also prompted the introduction of “Type 3” and “Type 4” PSEs and PDs (which can handle 60 watts and 90 watts, respectively) and additional Classes (5-8) for output and input power (Table 1). The designer should note that the amendment is designed to comply with the limited power source and safety extra-low voltage (SELV) requirements of ISO/IEC 60950 which restricts power to a maximum of 100 watts per port.
Table 1: Comparison of High-Power PoE (IEEE 802.3bt) with PoE (IEEE 802.3af) and PoE+ (IEEE 802.3at). IEEE 802.3bt introduces increased power along with new Types of PSEs and PDs, as well as new Classes. (Table source: Microsemi)
Enhancements brought by IEEE 802.3bt
In addition to the higher power available with High-Power PoE, the specification introduces other functionality. Key enhancements include:
- Automatic Class functionality
- Low standby power support
- Extended power capability if channel (cable) length is known
Automatic Classification (or “Autoclass”) is a new (optional) classification mechanism unique to High-Power PoE that allows a PD to communicate its effective maximum power consumption to the PSE, thus enabling the PSE to set the power budget to precisely match that level (plus some reserve for channel losses and a ‘safety’ margin) for better system efficiency.
To power applications with stringent standby requirements, High-Power PoE includes a significant change to the minimum pulsed current duration that’s used to ensure the PSE maintains power. Previously, Type 1 and 2 PDs used a “Maintain Power Signature” (MPS) comprising a 10 milliamp (mA) pulsed current for at least 75 milliseconds (ms) every 325 ms, and an AC impedance lower than 26.3 kilo ohms (kΩ) in parallel with 0.05 microfarads (μF). The change brought by the IEEE 802.3bt specification (applying to Type 3 and 4 PSE) results in a pulse duration of around 10 percent of that for Type 1 and Type 2 PSEs.
The extended power feature is another important change. The PD measures the cable resistance and calculates power loss and hence the power reserve required to ensure the PD receives the minimum input power detailed by the specification. At worst, this will equal the power reserve specified by the previous amendments, but in practical applications it is likely to be lower, thus saving energy.
High-power PoE start-up
The introduction of an additional four Classes of PSE output power (Classes 5 to 8) and corresponding PD input power along with two new types (Types 3 and 4) of PSE and PD have made the start-up sequence for the technology more complex. This has implications for developers designing High-Power PoE systems and could influence the choice of PSE controller.
Generally, a device compliant to IEEE 802.3af or IEEE 802.3at is referred to as a Type 1 (Class 0-3) or Type 2 (Class 4) device. Devices compliant with IEEE 802.3bt are referred to as Type 3 (Class 5, 6) or Type 4 (Class 7, 8) devices. High-Power PoE defines a method of safely powering a PD over a cable by a PSE, and then switching off power if a PD is disconnected from the cable.
IEEE 802.3bt also features an inrush current and time limitation to ensure compatibility between PSEs and PDs of any Type or Class. The inrush limit is 400 to 450 mA for Class 0 to 4, 400 mA to 900 mA for Class 5 to 6, and 800 mA to 900 mA for Class 7 to 8. The PSE inrush limit applies for up to 75 ms after power up, after which the Type 2, 3 or 4 PSE supports a higher output current in accordance with the Classification.
The High-Power PoE start-up process commences with the PSE switching off power while it looks to see if something has been plugged onto the cable. The PSE then classifies the PD before supplying the power demanded by the PD, or the maximum power of the PSE if it doesn’t have adequate capacity to fully supply the PD. There is also a fourth operational state used by Type 3 and 4 PSEs to check if the PD has the same classification signature on each twisted pair.
Because it is an optional feature, not all High-Power PoE-compliant PSEs and PDs support Autoclass, so a check of the data sheet is required if the functionality forms part of the specification for the developer’s system. Microsemi’s PD70210ILD-TR front-end PD interface controller is one product that does via its “Enhanced Classification Block”. The PD70210ILD-TR also identifies which of the four pairs of the cable actually receive power and generates appropriate flags (Figure 1).
Figure 1: Microsemi’s PD70210ILD-TR front-end PD interface controller includes an Enhanced Classification Block to ease classification of new Classes and PD Types introduced in High-Power PoE. The chip can also identify which of the four twisted pairs of the cable actually receive power via its SUPP_S1 and SUPP_S2 pins. (Image source: Microsemi)
A PSE implementing Autoclass first checks if the PD supports the feature by checking for the Class current to fall to Class 0 current level after a short delay. If support is present, the PSE can proceed to the Autoclass measurement immediately after power up, with the PD required to draw its highest power throughout the following 1.35 to 3.65 seconds. Once started, the PD must present an MPS to assure the PSE that it is still connected. Loss of the MPS triggers the PSE to turn the power off (Figure 2).
Figure 2: High-Power PoE’s start up process is more complex than previous versions because of the introduction of new PSE and PD Classes and Types. Here the three main stages of the process (detection, classification and operation) and the input voltages at which they occur are shown. (Image source: Texas Instruments)
New controllers meet High-Power PoE specification
Since PoE’s ratification, developers have been well served by the availability of integrated PSE controllers and PD interfaces upon which to base their designs. The trend continues with IEEE 802.3bt. Courtesy of manufacturers that designed products to meet the draft version of the specification, there are already several PSE controllers and PD interfaces on the market, in addition to the Microsemi device described above.
For example, Linear Technology offers the LTC4291-1/LTC4292 chipset. The components are designed to work together to form Type 3 or 4 PSE controllers. Power management features include per-port 14-bit current monitoring, programmable current limit, and versatile shutdown of preselected ports. PD detection uses a proprietary multipoint detection mechanism to help prevent false PD identification. Autoclass is supported and the chipset is pin or I2C programmable to negotiate up to 71.3 watts at the PD.
The LTC4291-1/LTC4292 chipset is notable for its level of integration; virtually all necessary circuitry to implement an IEEE 802.3bt compliant PSE design is included with only a few additional peripherals required. The device is split into two chips (processor plus power supply) to simplify PSE isolation by allowing the LTC4291-1 to reside on the non-isolated side. There it can receive power from the main logic supply and connect directly to the I2C/SMBus bus. The chipset uses a proprietary isolation scheme for interchip communication, which replaces optoisolators and isolated power supplies with low-cost transformers. The transformers are 10BASE-T or 10/100BASE-T units with a 1:1 turns ratio and common-mode chokes (Figure 3).
Figure 3: Linear Technology’s LTC4291-1/LTC4292 four-port IEEE 802.3bt PoE PSE controller implements proprietary isolation that simplifies design by replacing opto-isolators and isolated power supplies with low-cost transformers. (Image source: Linear Technology)
To take full advantage of High-Power PoE, a PD needs a Type 3 or 4 interface, otherwise the PSE will only supply the maximum power defined by IEEE 802.3af of 15.4 watts (12.95 watts at the PD). One option for this interface is TI’s TPS2372-4RGWT which contains all the features needed to implement an IEEE 802.3bt Type 1 to Type 4 PD interface.
A low internal switch resistance allows the TPS2372-3 and TPS2372-4 to support High-Power PoE applications up to 60 watts and 90 watts respectively, and its Automatic MPS function enables applications requiring very low power standby modes. Note that the IEEE 802.3bt MPS requirement for the PD is applicable at the PSE end of the cable. That means that depending on the cable length and other parameters including the bulk capacitance, a longer MPS duration may be required to verify. For that purpose, the TPS2372 has three different selections of MPS pulse duration and duty cycle, selectable through its MPS_DUTY input pin.
The TPS2372 implements inrush current levels compatible with all PSE Types. The chip also implements a delay function to allow the PSE to complete its inrush phase before releasing the Power Good (PG) output, ensuring that the IEEE 802.3bt start-up requirements are met. The chip’s Autoclass enable input provides access to all the advanced system power optimization modes specified in the IEEE 802.3bt standard.
Getting started with High-Power PoE
When using a highly integrated chipset such as the LTC4291-1/LTC4292, much of the challenging design work has been done by the silicon vendor, but there is still some careful external component selection and pc board layout guidelines to consider. Much of this follows general design guidelines for PoE system design but with selection of components appropriate for the higher voltage and current levels introduced by High-Power PoE.
For example, a digital power supply and main PoE power supply are required for the VDD and VEE lines shown in Figure 3. VDD requires 3.3 volts and VEE requires a negative voltage of between –51 and –57 volts for Type 3 PSEs and –53 to –57 volts for Type 4 PSEs. A ceramic decoupling cap of at least 0.1 μF should be placed from VDD to DGND, as close as practical to each LTC4291-1. To maintain required isolation, LTC4292 AGNDP and LTC4291-1 DGND must not be connected.
VEE is the main isolated PoE supply that provides power to the PDs. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. For best system efficiency, VEE should be set to near maximum amplitude (57 volts) leaving just enough margin to account for transient over or under-shoot, temperature drift and line regulation. An electrolytic bulk capacitor of at least 47 μF is required between AGNDP and VEE to minimize spurious resets in the event of electrical transients.
Selection of an external MOSFET is another key design decision for the developer. This MOSFET forms the power switching device controlling the PSE output. The choice of component has a significant effect on system reliability and requires the designer to analyze and test MOSFET safe operational area (SOA) against the various PSE current limit conditions. Linear Technology recommends the Nexperia PSMN075-100MSEX for PSEs configured to deliver up to 51 watts at the PD, or the PSMN040-100MSEX for 71.3 watts at the PD because these MOSFETs have proven reliability in PoE applications.
The LTC4291-1/LTC4292 chipset is designed for a 0.15 Ω current sense resistance per channel. The developer must add two parallel 0.3 Ω resistors positioned as shown in Figure 4. The sense resistors must have ±1 percent tolerance or better, and no more than ±200 parts per million (ppm)/°Centigrade (C) temperature coefficient in order to meet the High-Power PoE specification.
Figure 4: Shown is the required top and bottom layer sense resistor block layout for the LTC4292. Sense resistor (RSTx) selection and placement is vital in order to meet the High-Power PoE specification. (Image source: Linear Technology)
Each port requires a 0.22 μF capacitor across OUTnA and OUTnB to AGNDP (see Figure 3, again) to keep the LTC4292 stable while in current limit during startup or overload. X7R ceramic capacitors rated for at least 100 volts are recommended and must be located close to the LTC4292.
Ethernet ports can be subject to significant electrical transients. Comprehensive surge protection for PoE systems is an involved subject requiring a separate article, but a minimum requirement is a bulk voltage suppressor such as a transient voltage suppression (TVS) diode (TVSBULK) and bulk capacitance (CBULK) to suppress surge current and voltages to safe levels for each port (Figure 5). A 10 Ω series resistor (R1) is also required from supply AGND to the LTC4292 AGNDP pin. Across the LTC4292 AGNDP pin and VEE pin should be a 58 volt TVS diode (D1) and a 1 μF, 100 volt bypass capacitor (C1) placed close to the LTC4292 pins. Finally, each port requires a pair of S1B clamp diodes: one from OUTnM to supply AGND and one from OUTnM to supply VEE. These direct any electrical transients into the supply rails where they are absorbed by the surge suppressors.
Figure 5: PSE controllers require protection from electrical transients. Shown here is Linear Technology’s LTC4292 with the required voltage/current suppressors and components to direct transients away from sensitive chips. (Image source: Linear Technology)
At the PD interface, the high level of integration for chips such as TI’s TPS2327 again makes life a little easier for the developer, but some external components are also required (Figure 6).
For example, diodes are required at the cable input to the PD interface. For the TPS2327, TI recommends 3 amp to 5 amp, 100 volt rated discrete or bridge Schottky diodes instead of conventional diodes in High-Power PoE applications because the power dissipation in the diodes is 30 percent lower. One thing for the developer to consider is that Schottky diodes often have a higher reverse leakage current than normal PN junction diodes, making it hard to meet the maximum backfeed voltage of 2.8 volts defined in the specification. To compensate, conservative diode operating temperature limits and low leakage devices should be used for this implementation. Schottky diodes are also more susceptible to electrical transients than conventional diodes so voltage/current protection in the form of ferrite beads and capacitors is advised.
The IEEE 802.3bt specification includes an input bypass capacitor of 0.05 to 0.12 μF (typically a 0.1 μF, 100 volt, ±10% ceramic) across VDD to VSS. The specification also requires a detection resistor, RDEN, classification resistors RCLSA and RCLSB, and MPS resistor RMPS. A resistor of 24.9 kΩ, ±1% is recommended for RDEN. The classification resistors are connected from CLSA and CLSB to VSS to program the classification current according to the IEEE 802.3bt standard. The value of these resistors and the class power assigned is determined by the maximum average power drawn by the PD during operation. RMPS sets the MPS duty cycle; for example, a 1.3 kΩ resistor sets the duty cycle to 26.4%. Shorting MPS_DUTY to RSS sets the duty cycle to 12.5%.
The High-Power PoE PD interface also requires TVS diode and bulk capacitor (D1, CBULK) voltage suppression across power lines to absorb electrical transients at this end of the cable.
Figure 6: The application diagram for TI’s TPS2372 High-Power PoE PD interface shows the peripheral components required to complete the design—primarily input diodes, suppression devices, and detection, classification and MPS resistors. (Image source: Texas Instruments)
There are many design guidelines to ensure that pc board layout, parts placement and routing requirements meet the requirements of the IEEE 802.3bt specification in terms of parametric measurement accuracy, system robustness and thermal dissipation. Both Linear Technology and TI offer reference designs for their PSE/PD interfaces that adhere to the specification and form a useful guide for the developer.
High-Power PoE extends PoE’s applications and improves efficiency. However, it has added complexity of implementation through the introduction of further PSE controller and PD interface Types and Classes, as well as additional operational and safety features.
For the designer, help comes in the form of integrated PSE controller and PD interface solutions that include these features as standard. These greatly simplify and accelerate the design process by reducing the number of peripheral components needed to complete the system.