Sensor and Internet of Things (IoT) technologies are rapidly extending their presence into industrial, commercial, and even consumer settings. Along with this expansion, there’s a growing need to ensure the integrity of the data coming from the associated sensors and their front-end interface circuitry.
The potential problem of data integrity becomes even more serious when a single interface IC supports multiple sensors, since a problem with that single IC could corrupt a cluster of readings. This, in turn, could lead to an incorrect assessment of the sensed situation, potentially resulting in inappropriate or even dangerous system actions.
This article will look at the various sources of both hard and soft (transient) faults and sensor reading inaccuracies in the sensor-to-processor signal chain. It will then introduce a highly integrated IC from Analog Devices, and show how it can be used to overcome these issues via diagnostics on the sensors, itself, and its digital I/O.
The sensor-to-processor signal path
The factors that ultimately affect the integrity of any sensor reading begin with the three main functional blocks of the signal chain shown in Figure 1. These blocks are:
- The sensor and its leads
- The analog front-end in the signal-conditioning IC, centered on the analog-to-digital converter (ADC)
- The digital I/O to the system processor
Figure 1: The basic sensor-to-processor signal path consists in principle of just a few basic functions, but a practical and useful interface IC offers many additional functions and features. (Image source: Digi-Key Electronics)
In a multichannel system, the sensors are often a mix of various types such as thermocouples, resistance temperature detectors (RTDs), and pressure sensors. A sensor can fail, of course, or its interconnection leads can open, or short to an adjacent lead, power rail, or ground.
Depending on the sensor type, a fault with its wire leads may be immediately apparent as the reading will go “off scale”. In contrast, some fault modes result in inaccurate but legitimate-looking signals. Also, some sensors, such as RTDs, need an external stimulus current, and this current must be within a set range for a valid reading. For these reasons, it is a good idea to test the continuity of the signal path between the sensor and analog front-end, and also check that the signal remains between the allowed minimum and maximum limits, preferably using analog circuitry that is independent of possible ADC issues.
This will not only provide accurate readings, but also readings in which the system decision making algorithms can be run with a very high level of confidence in the source data.
However, all these extra checks and balances add up to extra components, a larger footprint, and extra design time.
Self-interrogating IC ensures sensor data integrity
To address the need for high integrity data with minimal impact on design time and footprint, Analog Devices introduced the AD7124-8BCPZ-RL7, a sensor-focused ADC and interface that goes far beyond basic signal conditioning and conversion. It includes multiple signal and self-diagnostic functions to ensure data integrity.
Figure 2: The AD7124 sensor-focused ADC and interface goes far beyond basic signal conditioning and conversion to include multiple signal and self-diagnostic functions to ensure data integrity. (Image source: Analog Devices)
The AD7124 is a four-channel, low-noise, low-power, 24-bit, sigma-delta (Σ-Δ) device. Its sampling rate ranges from a little over 1 sample/sec, adequate for many sensor classes and their applications, to 19,200 samples/sec. At the lowest sample rate, it draws 255 microamperes (μA). The accuracy of the readings of this device is enhanced by the emphasis of the design on low noise, under 25 nanovolts (nV) rms, and the low drift of its internal voltage reference (10 ppm/°C).
The AD7124 itself is available in 32-lead LFCSP and 24-lead TSSOP packages. Its flexible digital I/O supports 3 and 4-wire SPI, QSPI, MICROWIRETM, and DSP-compatible interfaces.
The AD7124 addresses the sensor lead issues mentioned earlier using two techniques: signal limit alarms and burnout current detection. Signal limit alarms use an overvoltage/undervoltage alarm monitor to check the absolute voltage on each of the four pairs of analog input connections (Figure 3). This voltage must be within a defined window to meet the datasheet specifications.
Figure 3: A basic verification of the sensor leads using signal limit alarms uses hardware-based comparators with fixed minimum/maximum settings. (Image source: Analog Devices)
Burnout current detection uses a pair of complementary programmable current sinks and sources. By sourcing and sinking a predefined pair of currents into the sensor leads, the AD7124 can verify their integrity (Figure 4). The currents, which are either full-on or off, are switched to the selected analog input wire pair under test.
Figure 4: By sourcing and sinking a predefined pair of currents into the sensor leads, the AD7124 can verify their integrity. (Image source: Analog Devices)
A full-scale reading (or nearly so) can mean that the front-end sensor is open circuit. If the voltage measured is 0 volts, it may indicate that the transducer has short circuited. A corresponding flag bit is set in the error register to indicate the occurrence and type of error.
Finally, for applications where the user provides the reference externally instead of using the internal reference, often done with RTDs or strain gages, the AD7124 checks that any external conversion reference voltage is correct.
Verifying the front-end and ADC
Although the external sensors and their leads are the most likely source of difficulty, it’s essential to verify the performance of the front-end/conversion IC itself. Among the functions that may be out of spec or have malfunctioned entirely are:
- The internal ADC voltage reference
- The programmable gain amplifier (PGA) which amplifies the input signal to match the ADC span for highest resolution
- The low-dropout regulator (LDO) which provides the required sensor excitation
- The IC’s internal power rails
- The ADC itself
To test the analog section of the signal chain, the AD7124 invokes hardware and firmware based self-test. It generates a 20 millivolt (mV) signal that can be internally connected to any of its four differential input channels and then digitized. Doing this serves multiple objectives: it verifies basic operation of the input channel multiplexer and the ADC; it also enables assessment of the PGA by changing the PGA’s gain settings and checking the resultant ADC readings.
The ADC is also a source of possible problems. The AD7124 uses the well-established Σ-Δ converter architecture with its 1-bit modulator and requisite digital filters. Full testing of the ADC performance employs both analog and digital techniques.
In the AD7124, if the modulator output contains 20 consecutive 1s or 0s, it indicates that the modulator has saturated to one rail or the other, and an error flag bit is set. Similarly, the IC checks that the ADC offset coefficient is between 0x7FFFF and 0xF80000 after its self-initiated offset calibration. If it is outside this range, another error flag bit is set. Finally, during a full-scale calibration, any overflow of the digital filter sets another error flag bit.
Internal and external power sources and rails are also potential sources of problems. Many sensors require a small amount of excitation power, and this is often supplied by a small, low-noise LDO within the analog front-end IC.
The AD7124 checks its LDO outputs in two ways. First, the output of the LDO can be internally routed to the ADC and compared to its expected value. Second, a hardware comparator that is independent of the ADC continuously monitors the LDO versus the IC’s reference. If it falls below a preset threshold, an error flag bit is set. As a result, the LDO can be assessed during initialization, and this can also take place on a continuous basis without constantly consuming processor resources.
For further confidence, the test circuitry used for monitoring the supply can be checked (to some extent) by connecting its input to ground (nominal 0 volts), and then checking the digital reading. The AD7124 takes this assurance of data integrity one step further by checking that the required 0.1 microfarad (µF) decoupling capacitors are present and connected. It does this by directing the AD7124 to physically disconnect the decoupling capacitor via its internal switch and then checking the LDO output. If the LDO voltage falls, the decoupling capacitor is electrically absent. Again, this sets an error flag bit.
Of course, every IC has a maximum temperature rating beyond which it will go out of spec, or even fail outright. Therefore, a sensor is built into the AD7124 to provide die temperature readings at any time, with a typical accuracy of ±0.5°C.
What about digital errors?
So far, we have looked at ensuring performance and accuracy with respect to the analog sensor or conversion functions. However, in the electrically harsh industrial environments where many of these sensors are deployed, there are issues with noise, EMI/RFI, and transients affecting the digital electronics. Therefore, it is important to ensure the performance of the internal digital circuitry, as well as the interface link to the system processor to ensure robustness of the data as well as any read/write operations.
The AD7124 accomplishes this via a multipronged approach beginning with the following operations and features:
- The performance of the master clock is checked. The master clock is needed to set the output data rate, filter settling time, and the filter notch frequencies. It is checked by an independent count-up register that can be read back at any time.
- The number of SCLK pulses used in each SPI read or write operation is checked via a special clock counter. The number should be a multiple of eight (all SPI operations use 8, 16, 32, 40, or 48 clock pulses).
- The AD7124 checks that read and write operations address only valid register addresses.
These steps address internal operations, but do not ensure integrity of the processor interface and its data. To provide an extremely high level of confidence in the data, the user can direct the AD7124 to implement a cyclic redundancy check (CRC) polynomial checksum algorithm. The checksum ensures that only valid data is written to a register and allows data read from a register to be validated (Figure 5). Note that checksum is a high confidence technique for detecting even single-bit errors, but it cannot correct them.
Figure 5: A polynomial-based CRC checksum is added to the (left) SPI write and (right) SPI read transactions for detection of single-bit errors. (Image source: Analog Devices)
When enabled, this operation calculates a checksum on the data block and appends it to the end of each read and write transaction. To ensure that the register write was successful, the register needs to be read back to verify the stored checksum against the one calculated from the data.
In an electrically harsh setting, even memory may suffer bit errors. To provide a high-level check against such errors in the on-chip registers, the AD7124 calculates the checksum for a range of operations each time:
- There is a register write cycle
- There is an offset/full-scale calibration
- The device performs a single conversion cycle and the ADC goes into standby mode following the completion of the conversion
- It exits the continuous-read mode
For enhanced robustness. the internal read-only memory (ROM) is also evaluated. On power-up, all registers are initialized to default values which are stored in ROM. A CRC calculation is performed on the ROM contents on power-up. If it differs from the stored CRC result, it indicates the presence of at least a single-bit error.
The AD7124 also offers excitation for many types of sensors, as well as signal conditioning and scaling of the sensor output signal via amplifiers and a PGA. To provide the extreme robustness it offers, it has many internal registers for initialization, establishing desired functional modes and parameters, and for flagging various errors and faults.
Use the AD7124 eval board to kickstart AD7124 designs
The AD7124 is a complex system with many design possibilities and performance capabilities. It is not a simple “drop in and go” sensor interface IC. To facilitate learning and allow designers to quickly become familiar with its potential capabilities, Analog Devices also provides the EVAL-CN0376-SDPZ evaluation board (Figure 6).
Figure 6: The EVAL-CN0376-SDPZ evaluation board speeds design-in and allows for full exercise of the many functions and features of the AD7124. (Image source: Analog Devices)
The eval board contains the power supply and external components needed to connect the AD7124 with a variety of real-world sensors as well as a processor. It is supported by Windows PC-based CN-0376 Evaluation Software which communicates via a USB port to configure and capture data from the evaluation board.
Many critical decisions are being made by advanced algorithms embedded in system processors, now enhanced by artificial intelligence (AI) in many cases. It’s more essential than ever that the raw data on which these algorithms operate, develop conclusions and take action, be of high integrity. ICs such as the AD7124 add multiple layers of needed confidence in the data ensuring that every link in the signal chain, from the leads and the sensor interface to its own performance and functions, are operating as expected and are uncorrupted.