As digital systems increase in performance, designers need to pay increasingly meticulous attention to the design of the clock generation and distribution circuits to avoid differences or uncertainties in clock distribution timing. Such issues can degrade system performance, reduce timing margins, or cause functional errors. To avoid timing skew related issues, designers can use zero delay clock buffers.
The typical synchronous digital systems use a common clock to keep operations in sequence. This clock must be distributed to all the sequential elements in order to keep the system operating at the desired rate, often using closed-loop control to reduce timing skew. Zero delay clock buffers use phase-locked loops (PLLs) to guarantee that the buffered clock outputs are aligned with the reference clock input, ensuring near perfect clock timing.
This article will article describe zero delay clock buffers, explain how they work using sample solutions from Cypress Semiconductor, Integrated Device Technology Inc. (IDT), and ON Semiconductor, and detail how clock skew can be controlled. It will also investigate test methods to assure the stability of these devices.
In synchronous digital systems, the clocks may arrive at differing times to different parts of the circuit causing clock skew. Clock skew can reduce timing margins and cause the system to fail (Figure 1).
Figure 1: A simple example of how clock time skew can affect operations of a pipelined register. A skewed clock can violate setup and/or hold requirements resulting in an indeterminate output state. (Image source: IDT)
Consider a simple synchronous system consisting of two registers. Data is pipelined through the registers so that the output of register X, QX, is the input to register Y. Clocks are fed to the registers via independent buffers and designated CLK1 and CLK2. If there is no skew between the clocks as shown in diagram (a), the data state N, meeting the register setup (tSUx) and hold (tHx) time requirements, is clocked into the register X output, QX, on the first clock edge after the register’s propagation delay. The same clock edge on CLK2 causes the previous state of QX, N-1, to be read by the register and appear at the output QY after the register’s propagation delay.
If there is time skew between CLK1 and CLK2, as shown in diagram (b), then the state of QX may be in transition when CLK2 occurs. The input to register Y may not satisfy the register setup or hold time requirements, and the output may be indeterminate resulting in an error.
In order to ensure minimal clock skew, designers match the lengths of printed circuit traces, select buffers and other clock components with similar propagation delays, and balance the loading on the multiple clock sources. While these techniques help, it generally requires the use of zero delay clock buffers in order to obtain good control over clock skew.
Controlling clock skew
Clock skew arises from many possible sources. The most obvious is clock signals routed over printed circuit interconnects of varying lengths. Other skew sources include clocks passing through different active devices with differing propagation delays, clock buffers with different loading, or temperature differences in buffers. While some of these effects can be controlled, designers often use active devices to re-synchronize clocks to a reference clock using PLLs.
PLL circuits are used for frequency and phase control. They can be configured as frequency multipliers, demodulators, tracking generators, or clock recovery circuits. Each of these applications demands different characteristics, but they all use the same basic circuit concept shown in Figure 2.
Figure 2: Block diagram of a PLL configured as a frequency multiplier. It is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO). (Image source: Digi-Key Electronics)
Figure 2 shows a block diagram of a basic PLL configured as a frequency multiplier. The operation of this circuit is typical of all PLLs. It is basically a feedback control system that controls the phase of a VCO. The input signal is applied to one input of a phase detector. The other input is a feedback signal from the output of a divide by N counter. Normally the frequencies of both signals will be nearly the same.
The output of the phase detector is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter. It is the loop filter that determines the dynamic characteristics of the PLL. The filtered signal controls the VCO. Note that the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input (FIN). This output signal is sent back to the phase detector via the divide by N counter.
Normally the loop filter is designed to match the characteristics required by the application of the PLL. If the PLL is to acquire and track a signal, the bandwidth of the loop filter will be greater than if it were expecting a fixed input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies that the PLL will follow is called the tracking range. Generally, the tracking range is larger than the capture range. The PLL loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slew rate. The narrower the loop filter bandwidth, the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range. PLLs used in clock applications operate primarily at fixed frequencies.
Zero delay clock buffers
A zero delay buffer is a device that can buffer a clock signal, producing multiple clock outputs from a single reference clock input. The multiple, buffered clock outputs have little or no delay relative to the reference clock input and low skew between the outputs. The simplified block diagram of a Cypress Semiconductor CY2308SXC-3T zero delay buffer is shown in Figure 3.
Figure 3: The CY2308SXC-3T eight output zero delay buffer uses a PLL to synchronize all outputs to near zero time skew. (Image source: Cypress Semiconductor)
A zero delay buffer is built with an integral PLL that accepts a reference input (REF) and a feedback input (FBK) as the inputs to its phase detector. The feedback input is driven by one of the user selected outputs. The internal phase detector of the PLL adjusts the output phase of the VCO so that its two inputs have no phase or frequency difference. One of the buffered clock outputs and its load is selected to be the feedback signal to the PLL via the phase detector. Regardless of the load changes at that output, the PLL will dynamically compensate for those output load changes resulting in zero delay from the input to the output that drives feedback, regardless of its output loading.
The CY2308 family has two banks of four outputs, operating over a frequency range from 10 to 133 megahertz (MHz). Input to output time skew is less than 250 picoseconds (ps) and clock skew between outputs is less than 200 ps. The input to output time skew is adjustable by changing the load capacitance on the output used for the feedback input.
The product family offers several configurations of divide-by-two dividers. The component selected is the “-3” variant that has two such dividers as shown in the block diagram. This configuration allows the user to obtain outputs of two or four times the reference clock input frequency.
The most commonly used zero delay buffer is configured with five outputs and is available from several different manufacturers. The Cypress Semiconductor CY2305SXI-1HT, the IDT 2305-1DCGI8, and the ON Semiconductor NB2305AI1HDR2G are very similar devices. They all feature five buffered clock outputs, a single CLKOUT port, along with a quad bank of clock outputs. Unlike with the CY2308, the PLL feedback point is fixed at the single CLKOUT signal.
Zero delay buffer dynamics
The PLLs in the zero delay buffers are basically feedback control systems. The dynamics are controlled by the PLL loop filter. As with any control system, it is important to assess the feedback loop dynamics in response to a transient input. One way to do this is to apply an input with a step change to assess the step response (Figure 4).
Figure 4: Assessing the step response of the CY2305 zero delay buffer using a 1 radian phase step at 66.67 MHz. The top left grid is the input signal and the grid on the upper right is the output. (Source image: Digi-Key Electronics)
The input signal is a 66.67 MHz sine with a one radian step in the center of the acquired signal window. This waveform was generated by an arbitrary waveform generator (AWG). Both the input and output of the CY2305 zero delay buffer were acquired using an oscilloscope with a timebase setting of 10 microseconds (µs) per division.
The top left grid in Figure 4 is the input signal, and the grid on the upper right is the output. The time interval error (TIE) is the time difference of the measured clock edge to its ideal position and is measured for each waveform. In essence, it is the instantaneous phase of the signal referenced to a fixed clock rate, in this case 66.67 MHz. The value of TIE for each clock cycle of both the input and output are plotted as a waveform called a TIE track. The track for the input is the second grid from the top on the left. Here the step in the phase is visible with an amplitude of 2.4 nanoseconds (ns). This value represents a one radian phase shift for the 66.67 MHz clock frequency.
The second trace from the top on the right is the TIE track of the output. The track of the output shows some overshoot and settles to a new average value to match the input change. The third trace from the top shows a horizontally expanded zoom trace of the input on the left and of the output on the right. The details of the input step show a clean transition.
The zoom of the output exhibits some overshoot and then rapidly settles to the new average value in about one cycle of about a 500 ns duration. This is a well-behaved step response for such a large phase step. It settles quickly and there is no evidence of unstable oscillatory response.
The two bottom traces show horizontally expanded views of the input (left) and output (right). The large phase step is clearly visible in the input, but the slow output response is less visible at this time scale.
High-performance digital system designers need to continue to pay meticulous attention to the design of the clock generation and distribution circuits to avoid differences or uncertainties in clock distribution timing. Such issues can degrade system performance, reduce timing margins, or cause functional errors.
As described, the zero delay buffer is a good tool for active control when propagating multiple clock signals and maintaining synchronization with a master clock signal. They provide excellent tracking even with significant load changes on the sensed output. However, as shown, designers need to carefully assess the feedback loop dynamics of a zero delay buffer to ensure it meets the application requirements.