Achieve Optimal Wireless Communication Performance in IoT Circuit Board Designs

By Krisztián Kovács, Senior Director, Applications Engineering, Silicon Labs

Innovative technologies are accelerating development and uptake of the Internet of Things (IoT), not least the ‘system-on-chip’ (SoC) designs that combine microcontrollers (MCUs) with wireless connectivity. Modern SoCs are empowering designers to deliver high-performance networks and get new system designs to market faster and more cheaply than ever.

Product designers must maximize wireless communication performance – whichever protocol they use – by ensuring their radio frequency (RF) circuits and board layouts are fully optimized.

This is no easy task, because the RF signals you want to send and receive probably won’t be the only ones present: switching power supplies or the MCU clock, for example, can also generate RF signals. Bad design can hamper the device’s communication range, or require higher-power transmission to compensate. In battery-powered devices, the second option has the undesired effect of shortening battery life. Moreover, transmitting at higher power may create false signals, which can interfere with other devices or fall foul of regulatory requirements.

This is why product makers need to understand some key enablers of good wireless communication, as well as the way their circuit layouts can affect these enablers. This article will look at some best practices that will help designers deliver optimal RF performance from their products. Throughout the piece, we’ll make reference to a circuit board layout to house the EFR32 Wireless Gecko SoC from Silicon Labs.

What affects RF performance?

How you lay out the RF part of a printed circuit board (PCB) can have a huge bearing on the device’s RF performance. Firstly, there’s the question of where RF components are positioned and how far apart they are from other components. This can affect the coupling of unwanted signals.

Second, the routes and sizes of both RF and non-RF traces (particularly the supply lines) can have an impact.

Third is the type of antenna.

Other factors include ground metallization and the physical properties of the PCB, including its thickness, number of layers and its dielectric constant. Power converters, MCU clock circuits and other components on the PCB can also lead to excessive spurious signals in the RF spectrum, degrading sensitivity. Because of this, designers must implement filters to separate the desired signals from the unwanted ones, and stop the latter from reaching the RF path.

To help understand how to filter the signals, designers must understand the notion of RF circuit functions. The radio in the integrated circuit (IC) is made up of a transmitter (Tx) and receiver (Rx). The Tx aims to push the maximum amount of the desired signal to the antenna. Impedance transformation is used between the RF IC and load, seeking to ensure the maximum amount of power is radiated at the fundamental frequency, while reducing dissipated losses as much as possible. You do this using a combined matching and filtering network, made up of parallel capacitors and series inductors.

When you’re operating at 2.4 GHz, with Tx power levels over 13 dBm, it’s best to use a four-element ladder (see Figure 1). At lower powers, a two-element L-C network might be enough. In receiving mode, the Rx achieves maximum sensitivity by using the same impedance-matching network.

Diagram of 2.4 GHz four-element transmitter-matching network

Figure 1: This is a 2.4 GHz four-element transmitter-matching network.

Designing the RF section of the board: things to consider

Many SoC suppliers offer reference designs, which have been created to deliver optimal RF performance. However, there’s a dilemma: size and form-factor restrictions mean you can’t always copy the design straight into your product. On the other hand, tweaking it could affect RF performance: In the high-frequency ranges we’re talking about here, altering the distance between components and changing the PCB trace lengths risks introducing parasitic inductances. Different gaps between traces, or using a different thickness of substrate can bring in parasitic capacitances. Meanwhile, altering the relative orientations of components, or the spacing between them, can impact signal couplings. Swapping the type or size of component may introduce different component parasitics.

Bad designs can also detune the matching and filtering network and the load of the crystal. This could lead to a reduction in Tx output power and Rx sensitivity, alongside increased current consumption, spurious emissions and a frequency offset between different boards. You can observe these factors by measuring conducted and radiated signals.

Keep in mind that any problems you experience may not just be in the RF part of your PCB. When you’re thinking about RF radiation, you need to take the whole board design into account, because the ground plane and other factors will impact on the power of the transmitted signal, particularly if you use a monopole antenna. Both the ground plane’s shielding effect and non-RF PCB traces will impact the level of radiated spurs; make sure you keep these within EMC limits.

Lastly, remember that even if you’re using reference designs exactly as the SoC supplier recommends, you still need to design carefully for other elements on the PCB that fall outside the reference design, and consider how these may affect it.

How to design the RF part of your PCB in line with best practices

If you can’t use a reference design in its original form, following a set of best practice guidelines will increase your chances of success.

The first element of the matching network should sit as close to the RF IC’s Tx output pin as possible. The other components should also sit close together. You want the trace width that connects these elements to be equal to the pad width – for 0402-size surface-mount device components, this is usually 0.5 mm.

Image of Silicon Labs 2.4 GHz EFR32 board

Figure 2: This is a 2.4 GHz EFR32 board, with the important elements highlighted.

It’s essential you place the decoupling capacitors correctly on each supply pin. Place the lowest-value bypass capacitors nearest the IC pins, using good grounding and multiple vias to the ground plane. Using bypass capacitors with capacitance of around 100 nF can suppress clock signals (up to tens of MHz). If you don’t, these signals might get up-converted and cause undesired spurs around the carrier frequency.

The capacitors with the highest values (which filter out the interference from switching power supplies) can sit further away from the supply pins, and aren’t needed at all in a battery-powered kit.

Your crystal should sit as close as possible to the RF IC. Connect its casing to the ground with multiple vias. Use an isolating ground metal between the VDD traces and crystal.

Getting your ground connections right is essential. Thicken the traces that run near the capacitors’ ground pins and incorporate extra vias near these ground pins, linked to the bottom or inner layer ground plane.

Similarly, you should be using several vias to ground the exposed pad footprint for the RF IC’s paddle, which will also work as a heatsink. The example in Figure 2 has a 7 x 7 mm IC package with 25 vias, each with a diameter of 0.25 mm. Ideally, your paddle grounds should link to the top-layer ground metal, possibly using diagonal trace connections via the corners of the IC footprint. Sometimes, signals can couple between the ground connections of nearby filter capacitors; if you connect these to the ground on opposite sides of the transmission line, you can avert this issue.

In your matching network area, keep a minimum of 0.5 mm between your pads and the adjacent ground pours, as well as between traces. If you’re using a four-layer PCB, fill the first inner layer (below the top layer) of the area under your matching network and RF IC with continuous ground metal. It’s also best not to block the ground return paths between the Tx/Rx matching network ground vias and those of the RF IC paddle. You want a clear return path to the RF IC.

The last area to think about is the RF section itself. When you’re connecting to the on-board antenna, an antenna connector or any other RF components, use 50 Ohm grounded coplanar transmission lines. Among other things, this will cut down on undesired radiation, which you can lessen further by putting in multiple ground vias close to your coupler lines.

Figure 3 shows how you can use transmission lines.

Designing your overall PCB: Things to consider

Beyond the RF part of the PCB, you can improve performance in a number of ways. For starters, extend the continuous ground metallization from the RF area to the full PCB.

Keeping your RF voltage potentials equal across the full ground area will help achieve a good RF ground, by helping ensure correct VDD filtering. If you’re using monopole-type antennas, this will also give them a good ground plane. Fill any gaps with the ground metal and link resulting sections on the bottom and top layers with as many vias as you’re able to.

You also want to deploy multiple grounding vias at the edge of your ground metal area, particularly around supply traces (see Figure 3) and at the PCB edges. This will cut the harmonic radiation that fringing fields can cause.

If your board has three or more layers, place all your traces (particularly the supply ones) or wires in an inner layer. You can minimize radiation from these traces by using as much continuous ground metallization on both your top and bottom layers as possible.

Lastly, wherever possible, keep supply traces away from the edge of the PCB.

Image of Silicon Labs board layout transmission lines and ground vias

Figure 3: This board layout shows the transmission lines and the ground vias at the edges of the board.


Wireless connectivity plays a vital part in modern life – from the consumer electronics we use daily to the ever-growing IoT. The IoT is especially reliant on being able to send data to the internet efficiently (often via a local access point), using only a small battery as the power source.

To make this IoT-driven, interconnected world possible, product designers need robust, affordable methods of wireless communication. One of the best ways to achieve this is by using SoCs that can easily be built into larger products. But to get the overall design right, product makers must give careful thought to the make-up and layout of the RF circuit – an area that’s challenging at the best of times.

A good starting point is to use the SoC vendor’s reference designs, but this isn’t always viable. Designers therefore need to understand and implement RF design best practices. This will help ensure they achieve the communication performance they desire, while remaining within their power budgets and regulatory requirements.


Disclaimer: The opinions, beliefs, and viewpoints expressed by the various authors and/or forum participants on this website do not necessarily reflect the opinions, beliefs, and viewpoints of Digi-Key Electronics or official policies of Digi-Key Electronics.

About this author

Krisztián Kovács, Senior Director, Applications Engineering, Silicon Labs

Krisztián Kovács is the Senior Director of Applications Engineering, responsible for worldwide customer support and applications development of the wireless IoT products, and managing Silicon Labs’ R&D site in Budapest.