This introduction into the Efinix Trion T120 FPGA Evaluation Kit walks through implementing VexRiscv Ruby SoC RISC-V Soft CPU on Efinix Trion T120. Topics include connecting a JTAG, installing Efinity, building the RISC-V, programming the on-board configuration memory, and running example RISC-V projects.
Efinity® Integrated Development Environment
Zadig USB driver installation made easy
Download Zadig, which is a Windows application that installs generic USB driver
- Open the Zadig software.
- Choose Options > List All Devices.
- Turn off Options > Ignore Hubs or Composite Parents.
- Select the Trion T120F324 Development Board (Interface 0)
- Select libusbK (version) next to Driver.
- Click Replace Driver.
- Repeat with the Trion T120F324 Development Board (Interface 1)
Extract efx_ruby_riscv_soc-v1.1zip into C:/riscv/
Extract riscv_sdk_windows-v1.1zip into C:/riscv-sdk/
Programming the Development Board
On the F324 Board, make sure to set J10 to use the 10Mhz Oscillator option.
Open soc_rubySoc.xml project
|Start Efinity Software and select "Open Project..."|
Open Project from:
|Make sure Board is off|
|From Tools, Open Programmer|
|Turn Board on|
|Click Refresh USB Targets|
|Click Select Image File|
Fri September 11 20 14:35:55 - ftdi://0x0403:0x6010:FT4VR16K/1
Fri September 11 20 14:35:55 - Flash device: Winbond W25Q128 16 MiB @ SPI freq 6.0 MHz
Fri September 11 20 14:35:55 - Erasing 3468 KiB from flash @ 0x00000000 (may take a while...)
Fri September 11 20 14:36:50 - Finished erase in 54 seconds
Fri September 11 20 14:36:52 - Writing 3467 KiB to flash @ 0x00000000 ...
Fri September 11 20 14:40:33 - Finished write in 220 seconds
Fri September 11 20 14:40:33 - Reading 3467 KiB from flash @ 0x00000000 ...
Fri September 11 20 14:40:38 - Finished read in 5 seconds
Fri September 11 20 14:40:38 - Flash verify successful