This details a single port RAM circuit, written in VHDL. This memory component outputs data from the memory address specified and also writes input data to this address if a write enable is asserted. It was designed using Quartus Prime, version 17.0.0. Resource requirements depend on the implementation. Figure 1 illustrates a typical example of the RAM integrated into a system.
Figure 1. Example Implementation
This RAM uses a write-before-read architecture. During a write cycle, the RAM writes the data before reading it on the output port, so the data shown on the output port is the same as that being written, rather than the old data that is being overwritten.
The RAM is configured by setting the GENERIC parameters in the ENTITY. Table 1 describes the parameters.
Table 1. Generic Descriptions
|d_width||integer||8||The width of each data word|
The number of data words the memory can store
Table 2 describes the RAM’s ports.
Table 2. Port Descriptions
|clk||1||in||standard logic||user logic||System clock|
|wr_ena||1||in||standard logic||user logic||Write enable: synchronously writes data on data_in port to the memory location specified on addr port when ‘1’|
|addr||M^||in||integer||user logic||Address of memory location to access|
|data_in||N*||in||standard logic vector||user logic||Data to be written to memory location addr if wr_ena is asserted|
|data_out||N*||out||standard logic vector||user logic||Data currently stored in memory location addr|
* N is the specified width of a data word, set by the d_width generic in the entity
^ M is the required width for an integer equal to the memory size, set by the size generic in the entity
This programmable logic RAM is a simple, single port memory component that outputs data from the specified memory address and, if a write enable is asserted, writes input data to this address. The number of memory locations and the data width are both configurable.
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