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Code Download

DAC AD5628 Pmod Controller (top level file):  pmod_dac_ad5628.vhd

SPI Master (must be included in project):  spi_master.vhd

Features

  • VHDL source code of a streamlined interface to Digilent’s Pmod DA4 (Pmod for Analog Devices AD5628 digital-to-analog converter)
  • Configures the DAC to use its internal voltage reference
  • Accepts commands, addresses, and data to control the DAC using simple parallel interfaces
  • Handles all serial communication with the DAC Pmod
  • Configurable system clock rate

Introduction

This details a VHDL component that handles interfacing to the Digilent’s DAC AD5628 Pmod, shown in Figure 1.  Figure 2 illustrates a typical example of this DAC Pmod Controller integrated into a system.  As shown, the DAC Pmod Controller connects to the Pmod ports and executes transactions to set the DAC outputs (and other functions if desired).  Commands, addresses, and data are latched in on simple parallel interfaces which can be connected to user logic or to input ports on the FPGA.

Figure 1.  Digilent DAC AD5628 Pmod


Figure 2.  Example Implementation

Background

The DAC AD5628 Pmod provides an 8-channel, 12-bit digital-to-analog converter.  The channels can be updated individually or simultaneously.  An internal 1.25V reference is included.  It has a gain of 2 to provide a full-scale output range of 2.5V.  The 12-bit data resolution corresponds to approximately 0.6mV per bit.

Theory of Operation

The DAC Pmod Controller uses a simple state machine and the SPI Master component available on eewiki to control the DAC Pmod.

State Machine

The design uses the state machine depicted in Figure 3 to implement its operation.  Upon start-up the component immediately enters the start state.  It remains in this state for 100us to ensure the Pmod has ample time to power-up.  It then proceeds to the configure state, where it turns on the DAC’s internal voltage reference.  Once complete, it enters the pause state.  Here, it ensures at least 20ns elapse between transactions with DAC, as specified in the AD5628 datasheet.  It then deasserts the busy signal to indicate that the DAC Pmod Controller is ready for a new transaction with the DAC Pmod and proceeds to the ready state.  It waits in the ready state until the dac_tx_ena enable signal is asserted, when it latches in the command, address, and data for the new transaction and advances to the send_data state.  In this state, it executes the transaction with the Pmod and then returns to the pause state.  Although not shown, resetting the component at any time returns it to the start state.


Figure 3.  State Diagram

SPI Master

During the configure and send_data states, the state machine controls an SPI Master component to communicate with the DAC on the Pmod.  Documentation for the SPI Master is available here.

The SPI Master is configured with CPOL = 1 and CPHA = 0, to meet the requirements of the AD5628 converter.

Configuring the Clock

The clocking of this DAC Pmod Controller is configured by assigning values to the GENERIC parameters clk_freq and spi_clk_div, defined in the ENTITY.  The clk_freq parameter must be assigned the frequency of the system clock provided on the clk input port in MHz.  Equation 1 defines how the spi_clk_div value is calculated.

where fclk is the frequency of the provided system clock in MHz.

The default value specified in the code is spi_clk_div = 1.  This is arrived at because any clk_freq ≤ 100 MHz results in the default spi_clk_div = 1.  For instance, the component was developed and tested using a system clock of 50 MHz.  50/100 = 0.5, rounded up is 1. 

                 

Equation 2 defines the serial clock frequency fsclk that results.

This calculation keeps the serial clock below the DAC’s maximum specified communication frequency of 50 MHz.  The fastest communication occurs when the input clock frequency (in MHz) is an integer multiple of 100.

Transactions

Commands, Addresses, and Data

Transactions to the DAC Pmod require sending a 4-bit command (dac_cmd), 4-bit address (dac_addr), and 12-bit data (dac_data).  Table 1 lists the available commands.  In the most common case, sending a “0011” command will write and update the DAC of the chosen address.  The addresses of each DAC are tabulated in Table 2.  The data sent typically represents the analog voltage the DAC channel will output.  Each bit of data corresponds to approximately 0.6mV.

See the AD5628 datasheet for more information.

Table 1.  Command Codes

Command

Description

0000

Write to input register N

0001

Update DAC register N

0010

Write to input register N, update all (software nLDAC)

0011

Write to and update DAC channel N

0100

Power down / power up DAC

0101

Load clear code register

0110

Load nLDAC register

0111

Reset (power-on reset)

1000

Set up internal REF register

others

Reserved

Table 2. DAC Channel Addresses

Address

DAC Channel

0000

DAC A

0001

DAC B

0010

DAC C

0011

DAC D

0100

DAC E

0101

DAC F

0110

DAC G

0111

DAC H

1111

All DACs

Example Transaction

The DAC Pmod Controller indicates its availability on its busy output.  When the busy signal is ‘0’, the Controller is ready to accept transactions to send to the DAC Pmod.  Asserting the dac_tx_ena input latches in the current values of dac_cmd, dac_addr, and dac_data.  Once latched, the Controller asserts the busy signal to indicate that a transaction is in progress, so it is not currently available.  When the transaction is complete, it again deasserts the busy signal to indicate that it’s ready to accept another request.

Figure 4 illustrates an example transaction.  The busy signal is ‘0’.  The user logic then presents the command “0011” to write and update DAC G (address “0110”) with the data presented.  The Controller asserts the busy signal, indicating the request is latched in, at which point the user logic can deassert the dac_tx_ena signal.  The Controller sends the serial communication to the DAC Pmod, then deasserts busy when complete.  Later, the user logic initiates a new transaction to write and update DAC F (address “0101”).

If the dac_tx_ena signal is not deasserted, a new transaction request is latched in and begins immediately once the Controller is available.


Figure 4. Transaction Example

Port Descriptions

Table 3 describes the DAC Pmod Controller’s ports.

Table 3.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clock

1

in

standard logic

user logic

System clock

reset_n

1

in

standard logic

user logic

Asynchronous active low reset

dac_tx_en

1

in

standard logic

user logic

Transaction enable.  H: latches in command, address, and data, then performs a transaction with the DAC.  L: no transaction is initiated.

dac_cmd

4

in

standard logic vector

user logic

Command to transmit to DAC

dac_addr

4

in

standard logic vector

user logic

Address to transmit to DAC

dac_data

12

in

standard logic vector

user logic

Data to transmit to DAC

busy

1

out

standard logic

user logic

H: component is unavailable.  L: component is ready to accept a new transaction.

mosi

1

out

standard logic

DAC Pmod

Serial data output to DAC

sclk

1

buffer

standard logic

DAC Pmod

Serial clock

ss_n

1

buffer

standard logic vector

DAC Pmod

Chip select

Connections

This Pmod has a 6-pin connector, J1.  Table 4 provides the pinout for this connector.  The DAC Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.

Table 4.  DAC Pmod Pinout and Connections to DAC Pmod Controller

Pmod Connector

Pmod Pin Number

DAC Pmod Port

DAC Pmod Controller Port

J1

1

~SYNC

ss_n

J1

2

DIN

mosi

J1

3

NC

-

J1

4

SCLK

sclk

J1

5

GND

-

J1

6

VCC

-

Reset

The reset_n input port must have a logic high for the DAC Pmod Controller component to operate.  A low logic level on this port asynchronously resets the component.  During reset, the component aborts the current transaction with the DAC Pmod and sets the busy output high to indicate it is not available.  Once released from reset, the DAC Pmod Controller restarts operation.

Conclusion

This DAC Pmod Controller is a programmable logic component that interfaces to Digilent’s DAC AD5628 Pmod.  It activates the DAC’s internal reference and simplifies the communication to send it commands, addresses, and data.

Related Topics

Serial Peripheral Interface (SPI) Master (VHDL)

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.

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