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Code Download

I2S Playback Design Code

Top level file:  i2s_playback.vhd

I2S Transceiver (must also be included in the project):  i2s_transceiver.vhd

Complete Example Project

Archived Design for the Digilent Basys 3 development kit:

This design assumes the PmodI2S2 is plugged into the JA connector on the kit.


  • VHDL source code of an audio playback system for Digilent’s I2S Pmod (PmodI2S2)
  • Demonstrates an I2S transceiver interface to both receive and transmit audio using the Pmod


This details a VHDL design that handles interfacing to Digilent’s I2S Pmod to create an audio playback system, allowing the user to quickly get started using this Pmod with an FPGA.  The I2S Pmod is shown in Figure 1.  Figure 2 depicts a block diagram of the system.  The I2S Playback design inputs I2S formatted digital audio data from the I2S Pmod’s ADC and then transmits this audio data to the I2S Pmod’s DAC.  This component was designed using Vivado 2017.2.

Figure 1.  Digilent I2S Pmod

Figure 2.  System Block Diagram

Theory of Operation

Figure 3 is a block diagram of the I2S Playback design’s internal architecture.  It consists of an I2S Transceiver component and a PLL.

Figure 3.  I2S Playback Internal Architecture

I2S Transceiver

The I2S Transceiver depicted is a VHDL component that handles I2S reception and transmission per the I2S Bus Specification.  Complete documentation on this design is available here.  The I2S Playback design configures the I2S Transceiver component as follows.

The I2S Pmod uses a Cirrus Logic CS5343 Multi-Bit Audio A/D Converter and a Cirrus Logic CS4344 Stereo D/A Converter, which the I2S Transceiver component interfaces to directly.  Both the ADC and DAC support 24-bit data resolution, so the I2S Transceiver is configured for a 24-bit data width by setting its generic parameter d_width to 24.

This I2S Playback design uses the common 44.1 kHz sampling frequency.  From Figure 2 in Section 4.1.1 of the CS5343 Datasheet, it is appropriate to use an SCLK/LRCK ratio of 64 and a MCLK/LRCK ratio of 256.  Therefore, the I2S Transceiver’s generic parameter sclk_ws_ratio is set to 64.  (LRCK, e.g. left-right clock, and ws, e.g. word select, are synonymous.)  The generic parameter mclk_sclk_ratio is set to 4, since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.

As such, the word select (or left-right clock) frequency is 44.1 kHz, the serial clock frequency is 44.1 kHz * 64 = 2.82 MHz, and the master clock frequency is 2.82 MHz * 4 = 11.29 MHz.  Table 1, Section 4.1 of the CS4344 Datasheet confirms this selection, listing 11.29 MHz as a common frequency for the master clock when the LRCK is 44.1 kHz.

The I2S Playback design’s playback functionality results from routing the received data back into the I2S Transceiver component’s transmit ports, as shown in Figure 3 above.


The I2S Transceiver component requires a master clock to operate, from which it derives the serial clock and word select signals necessary for the I2S interface.  This master clock is generated using one of the FPGA’s PLLs.

As described above, the required master clock for this design is 11.29 MHz.

The archived design provided uses a PLL on the Artix-7 FPGA to produce an 11.29 MHz clock from the 100 MHz input clock on the Basys 3 board.  If using a different board, the user needs to modify the design to generate or provide this clock.

Port Descriptions

Table 1 describes the I2S Playback design’s ports.

Table 1.  Port Descriptions

PortWidthModeData TypeInterfaceDescription
clock1instandard logicuser logicSystem clock
reset_n1instandard logicuser logicAsynchronous active low reset
mclk2outstandard logic vectorI2S PmodMaster clock from which sclk and ws are derived
sclk2outstandard logic vectorI2S PmodSerial clock (i.e. bit clock)
ws2outstandard logic vectorI2S PmodWord select (i.e. left right clock)
sd_tx1outstandard logicI2S PmodSerial data transmit
sd_rx1instandard logicI2S PmodSerial data receive


This Pmod has a 12-pin connector.  Table 2 provides the pinout for this connector.  The I2S Playback design’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.

Table 2.  I2S Pmod Pinout and Connections to I2S Playback design ports

Pmod ConnectorPmod Pin NumberI2S Pmod PortI2S Playback Design Port
J11D/A MCLKmclk(1)
J12D/A LRCKws(1)
J13D/A SCLKsclk(1)
J14D/A SDINsd_tx
J17A/D MCLKmclk(0)
J18A/D LRCKws(0)
J19A/D SCLKsclk(0)
J110A/D SDOUTsd_rx


The reset_n input port must have a logic high for the I2S Playback system to operate.  A low signal on this port asynchronously resets the system.  During reset, the internal I2S Transceiver component holds the sclk, ws, and sd_tx ports low.  Any transmit currently underway is discontinued.  Any receive currently in progress is abandoned.  All internal data buffers are cleared.  Once released from reset, the I2S Transceiver restarts its operation, and playback resumes.


This I2S Playback design is an example programmable logic design that interfaces to Digilent’s I2S Pmod.  It handles all communication with the I2S Pmod to input the digital audio from the Pmod’s ADC and playback this audio through the Pmod’s DAC.

Related Topics

I2S Transceiver (VHDL)


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