7-Segment Displays Pmod Controller (top level file): pmod_seven_segments.vhd
7-Segment Display Driver for Multiple Digits (must be included in project): seven_segments.vhd
Binary to BCD Converter (must be included in the project): binary_to_bcd.vhd
Binary to BCD Digit Converter (must be included in the project): binary_to_bcd_digit.vhd
BCD to 7-Segment Mapping (must be included in the project): bcd_to_7seg_display.vhd
- VHDL source code of a streamlined interface to Digilent’s 7-Segment Displays Pmod (PmodSSD)
- Displays a 2-digit integer on the two 7-segment displays
- Does not display leading zeros
- Handles multiplexing between the two displays’ shared input pins on the Pmod
- Configurable system clock rate
This details a VHDL component that handles interfacing to the Digilent’s SSD Pmod, shown in Figure 1. Figure 2 illustrates a typical example of this SSD Pmod Controller integrated into a system. As shown, the SSD Pmod Controller connects directly to the SSD Pmod through the FPGA’s output ports. It inputs a number from user logic and outputs the necessary signals to display that number on the Pmod’s 7-segment displays. This component was designed using Vivado 2017.2.
Figure 1. Digilent SSD Pmod
Figure 2. Example Implementation
The SSD Pmod uses shared data lines to interface with two 7-segment displays, with one set of standard a-g data lines going directly to both SSDs. The SSDs are configured in a common cathode configuration. The common cathode connection acts as a “digit select.” This input is inverted between the SSDs, so that each digit has its cathode set high (effectively turning it off) when the other digit’s cathode is set low (enabling it).
Theory of Operation
The SSD Pmod Controller inputs a 2-digit integer, determines the SSD segment values required to represent it, and then multiplexes these values on the shared inputs of the SSD Pmod. Figure 2 illustrates the operations in this process.
Figure 2. Operations Performed
Determining SSD Segment Values
The SSD Pmod Controller uses the 7-Segment Display Driver for Multiple Digits component available on eewiki to take an input integer and determine the segment values required for each of the SSDs on the SSD Pmod. This component operates by first converting the integer input into a standard logic vector to get the binary representation of the integer. It converts this binary number to binary coded decimal (BCD) using the Binary to BCD Converter component. The resulting BCD digits are then disabled if they are leading zeros. Finally, it maps the BCD values to SSD segment values.
Three generic parameters configure the 7-Segment Display Driver for Multiple Digits component when it is instantiated. For this design, digits is set to 2, since the SSD Pmod has two SSDs to control. bits is set to 7, since 3.322 x digits = 6.644, rounds up to 7 (see calculation). Finally, ss_polarity is set to ‘1’, because the SSD Pmod’s 7-segment displays are configured in a common cathode arrangement.
Multiplexing the SSD Segment Values
Since the SSD Pmod has shared input pins for its two SSDs, the SSD Pmod Controller must multiplex the two SSD value sets. It alternates between which of the two SSD value sets it outputs every 5 ms. This corresponds to a 100 Hz refresh rate, which is fast enough to achieve persistence-of-vision, so it appears that both SSDs are lit simultaneously.
Configuring the Clock
The clocking of this SSD Pmod Controller is configured by assigning a value to the GENERIC clk, defined in the ENTITY. This is the frequency of the provided system clock in MHz.
Table 1 describes the SSD Pmod Controller’s ports.
Table 1. Port Descriptions
|clk||1||in||standard logic||user logic||System clock|
|reset_n||1||in||standard logic||user logic||Asynchronous active low reset|
|number||1||in||integer||user logic||Number to display on the 7-segment displays|
|digit_select||1||out||standard logic||SSD Pmod||Selects which SSD is active; ‘0’ is the lower digit, ‘1’ is the upper digit|
|segments||7||out||standard logic vector||SSD Pmod|
Outputs to drive the SSD segments
This Pmod has two 6-pin connectors. Table 2 provides the pinout for these connectors. The SSD Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to these connectors as listed.
Table 2. SSD Pmod Pinout and Connections to SSD Pmod Controller
|Pmod Connector||Pmod Pin Number||SSD Pmod Port||SSD Pmod Controller Port|
The reset_n input port must have a logic high for the SSD Pmod Controller component to operate. A low logic level on this port asynchronously resets the component. During reset, the component clears the digit_select and segments outputs. Once released from reset, the SSD Pmod Controller resumes operation.
This SSD Pmod Controller is a programmable logic component that interfaces to Digilent’s 7-Segment Displays (SSD) Pmod. It handles all process necessary to present a 2-digit integer on the Pmod’s SSDs.
Comments, feedback, and questions can be sent to firstname.lastname@example.org.