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Programmable Logic :: VHDL
LM4550 ac'97 Audio Codec
This is an example hardware driver used to interface a National Semiconductor LM4550 ac97 audio codec to an FPGA running at 100 MHz. The design can be scaled to other clock speeds by either scaling the internal counters or instantiating an onboard PLL to attain a 100 MHz clock. A Spartan 6 FPGA was used in developing the controller, but any FPGA can be used as long as the counters are scaled to provide correct timing with respect to the main system clock.
The inputs to the controller include the main FPGA oscillator, an active low reset, a serial data in line, a 12.288 MHz bit clock from the ac97, a 3 bit source selector (slide switches) and a 5 bit volume control (slide switches). The controller's outputs include a sync signal, serial data output, and an ac97 active low reset signal for initializing the ac97.
The controller has two main parts, the ac97 for generating signals, and converting 18 bit parallel data to serial data to interface the ac97 chip with the FPGA, and the command controller state machine used to configure the registers in the ac97 in a round robin fashion. The FSM can be changed to include user bus signal inputs, routed to each state corresponding to different register values, for on the fly configuration of the codec. The two parts of the ac97 hardware driver are synced with a one cycle, pulsed ready signal. The top of the hierarchy simply routes the parallel outputs of the controller to back into the parallel inputs of the controller on clock edges. This makes the ac97 talk through from input to output. This process in the top level file can be replaced by port mapping user components for various signal processing tasks.