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Code Downloads

Accelerometer ADXL362 Pmod Controller (top-level file):  pmod_accelerometer_adxl362.vhd

SPI Master (must also be included in the project):  spi_master.vhd

Features

  • VHDL source code of a streamlined interface to Digilent’s PmodACL2 (Pmod for Analog Devices ADXL362 Accelerometer)
  • Continually outputs latest 3-axis acceleration data on 3 parallel buses
  • Handles SPI communication to configure and retrieve data from the Accelerometer Pmod
  • Configurable accelerometer data range
  • Configurable accelerometer data rate
  • Configurable system clock rate

Introduction

This details a VHDL component that handles interfacing to Digilent’s Accelerometer ADXL362 Pmod, shown in Figure 1.  Figure 2 illustrates a typical example of this Accelerometer Pmod Controller integrated into a system.  As shown, the Accelerometer Pmod Controller connects to the Pmod ports and executes transactions to configure the accelerometer and gather data.  The data is continually updated and presented on 3 simple parallel buses (corresponding to the 3 axes), which can be connected to user logic or to output ports on the FPGA.

Figure 1.  Digilent Accelerometer ADXL362 Pmod


Figure 2.  Example Implementation

Theory of Operation

The Accelerometer Pmod Controller consists primarily of a state machine and an SPI Master component.

State Machine

The design uses the state machine depicted in Figure 3 to implement its operation.  Upon start-up the component immediately enters the start state, where it initializes parameters used in other states.  It then proceeds to the pause state.  Here, it pauses for 200ns between SPI transactions.  It then selects which of 3 transactions with the accelerometer to execute.  The first 2 transactions are carried out by the configure state (setting the accelerometer’s data range and data rate, and then enabling measurements).  At completion of each of these transactions, it returns to the pause state.  Once both configuration transactions are finished, the pause state repetitively selects the 3rd transaction, proceeding to the read_data state to execute it.  This state reads the accelerometer data for all 3 axes, then continues to the output_result state.  The output_result state writes the data to the acceleration_x, acceleration_y, and acceleration_z output buses, then returns to the pause state.  Resetting the component at any time returns it to the start state.

Figure 3.  State Diagram

SPI Master

During the configure and read_data states, the state machine controls an SPI Master component to communicate with the accelerometer on the Pmod.  Documentation for the SPI Master is available here

This design implements the SPI master in the CPOL = ‘0’ and CPHA = ‘0’ mode.  It sets the clk_div parameter based on the system clock frequency (specified with the clk_freq generic parameter, see below) to communicate with the accelerometer at the maximum SPI frequency specified in the ADXL362’s datasheet, i.e. 8 MHz.

This design also utilizes the Continuous Mode feature of the SPI Master to execute transactions of varying lengths.  The transactions in the configure state are 24 bits long, whereas the transactions in the read_data state are comprised of 64 bits.

Configuring the Accelerometer Pmod Controller

The Accelerometer Pmod Controller is configured by setting the generic parameters in the entity.

System Clock Frequency

The generic parameter clk_freq must be set to the frequency of the system clock provided to the Accelerometer Pmod Controller on its clk port.

Data Rate

The generic parameter data_rate defines the frequency at which the ADXL362 accelerometer takes measurements.  The parameter itself is the rate code that corresponds to the desired data rate, defined in Table 17 of the ADXL362’s datasheet.  Bandwidth and power consumption increase with higher data rates.  Table 1 describes the options and lists the rate codes.  The default rate code is “011” which configures the accelerometer to a 100 Hz output data rate.

Table 1.  Data Rate Options

Data Rate (Hz)

Bandwidth (Hz)

Rate Code

400

200

101…111

200

100

100

100

50

011

50

25

010

25

12.5

001

12.5

6.25

000

Data Range

The generic parameter data_range defines the range of acceleration values the accelerometer measures.  The parameter itself consists of the bits used to configure the accelerometer’s data format register, defined in Table 17 of the ADXL362’s datasheet.  Sensitivity scales with range.  Table 2 describes the options and lists the parameter settings.  The default setting is “00” which configures the accelerometer to a ±2g output data range.

Table 2.  Data Range Options

Data Range

Sensitivity (mg/LSB)

Setting

±2g

1

00

±4g

2

01

±8g

4

1X

Port Descriptions

Table 3 describes the Accelerometer Pmod Controller’s ports.

Table 3.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clk

1

in

standard logic

user logic

System clock

reset_n

1

in

standard logic

user logic

Asynchronous active low reset

miso

1

in

standard logic

Accelerometer Pmod

SPI master in, slave out data line

sclk

1

buffer

standard logic

Accelerometer Pmod

SPI serial clock

ss_n

1

buffer

standard logic vector

Accelerometer Pmod

SPI slave select signal

mosi

1

out

standard logic

Accelerometer Pmod

SPI master out, slave in data line

acceleration_x

12

out

standard logic vector

user logic

x-axis acceleration data

acceleration_y

12

out

standard logic vector

user logic

y-axis acceleration data

acceleration_z

12

out

standard logic vector

user logic

z-axis acceleration data

Connections

This Pmod has a 12-pin connector.  Table 4 provides the pinout for this connector.  The Accelerometer Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.

Table 4.  Accelerometer Pmod Pinout and Connections to Accelerometer Pmod Controller

Pmod Pin Number

Accelerometer Pmod Port

Accelerometer Pmod Controller Port

1

chip select (CS)

ss_n(0)

2

master out, slave in (MOSI)

mosi

3

master in, slave out (MISO)

miso

4

serial clock (SCLK)

sclk

5

GND

-

6

VCC

-

7

interrupt 2 (INT2)

-

8

interrupt 1 (INT1)

-

9

no connect (NC)

-

10

no connect (NC)

-

11

GND

-

12

VCC

-

Reset

The reset_n input port must have a logic high for the Accelerometer Pmod Controller component to operate.  A low logic level on this port asynchronously resets the component.  During reset, the component aborts the current transaction with the Pmod and clears the acceleration_x, acceleration_y, and acceleration_z data outputs.  Once released from reset, the Acceleration Pmod Controller restarts its operation.  It reconfigures the accelerometer and then resumes collecting and outputting acceleration data.

Conclusion

This Accelerometer Pmod Controller is a programmable logic component that interfaces to Digilent’s PmodACL2 (Accelerometer ADXL362 Pmod).  It handles all communication with this Pmod to configure the Pmod accelerometer’s data range and data rate, activate measurements, and provide a continual stream of updated acceleration data on 3 parallel output buses, one for each axis.

Additional Information

Analog Devices ADXL362 datasheet:  ADXL362.pdf

Related Topics

Serial Peripheral Interface (SPI) Master (VHDL)

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.

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