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Code Download

Real-Time Clock MCP9410 Pmod Controller (top level file):  pmod_real_time_clock.vhd

I2C Master (must be included in project):  i2c_master.vhd

Features

  • VHDL source code of a streamlined interface to Digilent’s Pmod RTCC (Pmod for Microchip’s MCP79410 real-time clock/calendar)
  • Continually outputs latest clock and calendar data on parallel interfaces
  • Simple interface for user to set the clock and calendar
  • Handles all I2C communication with the RTCC Pmod
  • Configurable system clock rate

Introduction

This details a VHDL component that handles interfacing an FPGA to Digilent’s Real-Time Clock/Calendar (RTCC) Pmod, shown in Figure 1.  Figure 2 illustrates a typical example of this RTCC Pmod Controller integrated into a system.  As shown, the RTCC Controller connects to the Pmod ports and executes transactions to both set the time and date on the Pmod and collect ongoing time and date values.  The time and date outputs are continually updated and presented on simple parallel interfaces.

Figure 1.  Digilent Real-Time Clock/Calendar Pmod


Figure 2.  Example Implementation

Theory of Operation

The RTCC Pmod Controller consists primarily of a state machine and an I2C Master component.

State Machine

The design uses the state machine depicted in Figure 3 to implement its operation.  Upon start-up, the component immediately enters the start state.  It remains in this state for 100ms to ensure the Pmod has ample time to power-up.  It then proceeds to the route state.  If the user logic has latched in new clock settings by toggling the set_clk_ena signal, it routes to the set_clock state.  Otherwise, it routes to the read_clock state.  The set_clock state writes the new user supplied clock settings to the RTCC on the pmod and then returns to the route state.  The read_clock state retrieves the current time and date from the RTCC, then progress to the output_result state, where it outputs the time and date to the corresponding output data ports.  Although not shown, resetting the component at any time returns it to the start state.

The RTCC Pmod Controller activates the RTCC’s on-board oscillator in the set_clock state.  This begins the time-keeping process.  Therefore, the output reads all zeros until the user sets the clock for the first time.


Figure 3.  State Diagram

I2C Master

During the set_clock and read_clock states, the state machine controls an I2C Master component to communicate with the MCP79410 RTCC on the Pmod.  Documentation for the I2C Master is available here.

System Clock Frequency

In the entity, the generic parameter sys_clk_freq must be set to the frequency (in Hz) of the system clock provided to the RTCC Pmod Controller on its clk port.

I2C Pull-Up Resistors

Unlike most of Digilent’s Pmod boards, the I2C pull-up resistors shown in Figure 2 above are not included on the Pmod RTCC.  The I2C bus will not operate correctly without them.

The user can solve this problem by wiring 2.2 kΩ resistors into the circuit as shown.

Several of Digilent’s other Pmods use I2C, include these resistors, and also include connectors to plug additional Pmods into the same I2C bus.  If this RTCC Pmod is used in conjunction with one those Pmods, the user can automatically take advantage of the pull-up resistors already included on those boards and no further action is needed.

Port Descriptions

Table 3 describes the RTCC Pmod Controller’s ports.

Table 3.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clk

1

In

standard logic

user logic

System clock

reset_n

1

In

standard logic

user logic

Asynchronous active low reset

scl

1

inout

standard logic

RTCC Pmod

Serial clock of I2C bus

sda

1

inout

standard logic

RTCC Pmod

Serial data of I2C bus

i2c_ack_err

1

out

standard logic

user logic

I2C communication error flag: '0' = no communication error, '1' = the RTCC Pmod did not properly acknowledge a transaction

set_clk_ena

1

In

standard logic

user logic

Set clock enable; toggling this bit to '1' for a system clock cycle latches in the input clock settings and initiates a transaction with the RTCC to set the time and date, and to start the RTCC onboard oscillator to begin timekeeping

set_seconds

7

In

standard logic vector

user logic

Seconds input clock setting; 2 digits in BCD format (00 to 59)

set_minutes

7

In

standard logic vector

user logic

Minutes input clock setting; 2 digits in BCD format (00 to 59)

set_hours

5

In

standard logic vector

user logic

Hours input clock setting; 2 digits in BCD format (00 to 12)

set_am_pm

1

In

standard logic

user logic

AM/PM input clock setting; AM = '0', PM = '1'

set_weekday

3

In

standard logic vector

user logic

Weekday input clock setting; 1 digit in BCD format (1 to 7)

set_day

6

In

standard logic vector

user logic

Day of month input clock setting; 2 digits in BCD format (01 to 31)

set_month

5

In

standard logic vector

user logic

Month input clock setting; 2 digits in BCD format (00 to 12)

set_year

8

In

standard logic vector

user logic

Year input clock setting; 2 digits in BCD format (00 to 99)

set_leapyear

1

In

standard logic

user logic

Set leapyear ('1') or not a leapyear ('0')

seconds

7

out

standard logic vector

user logic

Seconds clock output; 2 digits in BCD format (00 to 59)

minutes

7

out

standard logic vector

user logic

Minutes clock output; 2 digits in BCD format (00 to 59)

hours

5

out

standard logic vector

user logic

Hours clock output; 2 digits in BCD format (00 to 12)

am_pm

1

out

standard logic

user logic

AM/PM clock output; AM = '0', PM = '1'

weekday

3

out

standard logic vector

user logic

Weekday clock output; 1 digit in BCD format (1 to 7)

day

6

out

standard logic vector

user logic

Day of month clock output; 2 digits in BCD format (01 to 31)

month

5

out

standard logic vector

user logic

Month clock output; 2 digits in BCD format (00 to 12)

year

8

out

standard logic vector

user logic

Year clock output; 2 digits in BCD format (00 to 99)

Connections

This Pmod has an 8-pin connector.  Table 2 provides the pinout for this connector.  The RTCC Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.  The two rows of the J1 connector are tied together on the Pmod board, so only one side needs to be connected to the FPGA.

Table 2.  RTCC Pmod Pinout and Connections to RTCC Pmod Controller

Pmod Connector

Pmod Pin Number

RTCC Pmod Port

RTCC Pmod Controller Port

J1

1 & 5

Serial Clock (SCL)

scl

J1

2 & 6

Serial Data (SDA)

sda

J1

3 & 7

GND

-

J1

4 & 8

VCC

-

Reset

The reset_n input port must have a logic high for the RTCC Pmod Controller component to operate.  A low logic level on this port asynchronously resets the component.  During reset, the component aborts the current transaction with the Pmod and clears all of the time and date clock outputs, i.e., seconds, minutes, hours, am_pm, weekday, day, month, and year.  It also clears the i2c_ack_err output.  It does not reset the RTCC itself, so the RTCC will continue tracking the time and date from its last setting.  Once released from reset, the RTCC Pmod Controller restarts its operation.  It resumes collecting time and date data from the RTCC and outputting the result.

Conclusion

This RTCC Pmod Controller is a programmable logic component that interfaces to Digilent’s Pmod RTCC (Real-Time Clock/Calendar Pmod).  It handles all communication with this Pmod to allow the user to set the time and date, start the timekeeping, and continuously output the updated time and date back to the user.

Related Topics

I2C Master (VHDL)

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.

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