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Code Download

ADC AD7991 Pmod Controller (top level file):  pmod_adc_ad7991.vhd

I2C Master (must also be included in the project):  i2c_master.vhd

Features

  • VHDL source code of a streamlined interface to Digilent’s PmodAD2 (Pmod for Analog Device’s AD7991 Analog-to-Digital Converter)
  • Continually outputs latest data for each of the 4 converter channels on 4 corresponding parallel interfaces
  • Handles I2C communication and all data retrieval from the ADC Pmod
  • Configurable system clock rate

Introduction

This details a VHDL component that handles interfacing to Digilent’s ADC AD7991 Pmod, shown in Figure 1.  Figure 2 illustrates a typical example of this ADC Pmod Controller integrated into a system.  As shown, the ADC Pmod Controller connects to the Pmod’s I2C ports and executes transactions to gather data from each of the ADC’s 4 converter channels.  The data is continually updated and presented on simple parallel interfaces which can be connected to user logic or to output ports on the FPGA.

Figure 1.  Digilent ADC AD7991 Pmod


Figure 2.  Example Implementation

Theory of Operation

The ADC Pmod Controller consists primarily of a state machine and an I2C Master component.

State Machine

The design uses the state machine depicted in Figure 3 to implement its operation.  Upon start-up, the component immediately enters the start state.  It remains in this state for 100ms to ensure the Pmod has ample time to power-up.  In the following read_data state, it gathers the most recent ADC data from the Pmod’s ADC.  It completes this data transfer in a single I2C transaction and stores both the 4-bit header and 12-bit data from each ADC channel in a separate data buffer.  In the output_result state, it uses the header information to route each of the 12-bit data results to the correct parallel output.  It then continuously cycles between the read_data and output_result states to keep the ADC data constantly updated.  Resetting the component at any time returns it to the start state.


Figure 3.  State Diagram

I2C Master

During the read_data state, the state machine controls an I2C Master component to communicate with the ADC on the Pmod.  Documentation for the I2C Master is available here.

System Clock Frequency

In the entity, the generic parameter sys_clk_freq must be set to the frequency (in Hz) of the system clock provided to the ADC Pmod Controller on its clk port.

I2C Pull-Up Resistors

Unlike most of Digilent’s Pmod boards, the I2C pull-up resistors shown in Figure 2 above are not included on the PmodAD2.  The I2C bus will not operate correctly without them.

The user can solve this problem by wiring 2.2 kΩ resistors into the circuit as shown.

Several of Digilent’s other Pmods use I2C, include these resistors, and also include connectors to plug additional Pmods into the same I2C bus.  If this ADC Pmod is used in conjunction with one those Pmods, the user can automatically take advantage of the pull-up resistors already included on those boards and no further action is needed.

Port Descriptions

Table 1 describes the ADC Pmod Controller’s ports.

Table 1.  Port Descriptions

Port

Width

Mode

Data Type

Interface

Description

clk

1

in

standard logic

user logic

System clock

reset_n

1

in

standard logic

user logic

Asynchronous active low reset

scl

1

inout

standard logic

ADC Pmod

Serial clock of I2C bus

sda

1

inout

standard logic

ADC Pmod

Serial data of I2C bus

i2c_ack_err

1

out

standard logic

user logic

I2C communication error flag: '0' = no communication error, '1' = the ADC Pmod did not properly acknowledge a transaction

adc_ch0_data

12

out

standard logic vector

user logic

ADC channel 0 data retrieved

adc_ch1_data

12

out

standard logic vector

user logic

ADC channel 1 data retrieved

adc_ch2_data

12

out

standard logic vector

user logic

ADC channel 2 data retrieved

adc_ch3_data

12

out

standard logic vector

user logic

ADC channel 3 data retrieved

Connections

This Pmod has an 8-pin connector.  Table 2 provides the pinout for this connector.  The ADC Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.  The two rows of the J1 connector are tied together on the Pmod board, so only one side needs to be connected to the FPGA.

Table 2.  ADC 7991 Pmod Pinout and Connections to ADC Pmod Controller

Pmod Connector

Pmod Pin Number

ADC Pmod Port

ADC Pmod Controller Port

J1

1 & 5

Serial Clock (SCL)

scl

J1

2 & 6

Serial Data (SDA)

sda

J1

3 & 7

GND

-

J1

4 & 8

VCC

-

The Pmod also has a jumper.  JP1 must connect the middle pin to the pin labeled V4.  This connects the 4th channel on the ADC to its input pin on the J2 connector, thus enabling its use.

Reset

The reset_n input port must have a logic high for the ADC Pmod Controller component to operate.  A low logic level on this port asynchronously resets the component.  During reset, the component aborts the current transaction with the Pmod.  It clears the parallel data outputs and the i2c_ack_err output.  Once released from reset, the ADC Pmod Controller restarts its operation and resumes collecting and outputting ADC data.

Conclusion

This ADC AD7991 Pmod Controller is a programmable logic component that interfaces to Digilent’s PmodAD2 (ADC AD7991 Pmod).  It handles all communication with this Pmod to gather data from the Pmod ADC’s 4 channels and provide a continual stream of updated data on 4 corresponding parallel outputs.

Related Topics

I2C Master (VHDL)

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.

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